A method for manufacturing a semiconductor device of a micro gate field plate for radio frequency

Abstract

The application discloses a preparation method of a semiconductor device of a micro gate field plate for radio frequency, and comprises the following steps: providing a heterojunction wafer; depositing a passivation layer on the surface of the heterojunction wafer, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer; etching the hard mask layer, the dielectric layer and the passivation layer to form a gate recess; etching the dielectric layer formed with the gate recess to expand the gate recess in part of the area; the size of the gate recess in the dielectric layer is the length of the micro field plate; etching away the hard mask layer; performing photolithography on the surface of the dielectric layer and in the gate recess to form a gate area, depositing a gate metal in the gate area, stripping the gate metal after evaporation to form a gate; and etching away the dielectric layer to form a micro field plate gate. The application can simplify the preparation process of the micro field plate gate.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a preparation method of a semiconductor device with a micro gate field plate for radio frequency. BACKGROUND

[0002] In recent years, with the radio frequency of the 5G and 6G wireless communication system entering the millimeter wave frequency band and expanding to a higher frequency range of the terahertz frequency band, the comprehensive characteristics such as the frequency characteristics and the power density of the device are challenged. In order to realize a higher application frequency of the device, the frequency characteristics of the device can be improved by reducing the gate length of the HEMT device, using N+GaN regrowth to reduce parasitic resistance, shortening the source-drain spacing and the like; however, the non-ideal factors related to the peak electric field between the gate and the drain, such as current collapse and breakdown voltage, limit the improvement of the power density.

[0003] The GaN HEMT device can use a field plate structure connected with the gate to improve the power density characteristics. Through the gate field plate structure, the peak electric field distribution from the gate to the drain can be optimized, and the current collapse and knee voltage drift phenomenon can be effectively reduced. However, the longer gate field plate leads to an increase in the gate-drain capacitance, although the characteristic frequency fT is mainly limited by the gate-source capacitance, but the larger gate-drain capacitance also makes fT decrease, resulting in inhibition of the improvement of high-frequency performance. In order to improve the breakdown characteristics and the output power density of the device, while as far as possible reducing the influence on the frequency performance, the micro gate field plate structure with a T-shaped gate combined with a micro gate field plate under the gate is currently adopted, and this structure is usually completed by multiple electron beam lithography. For example: the first lithography groove, the second lithography groove uses three layers of photoresist, and the field plate and the gate cap are lithographed in layers, which requires high-precision lithography overlay technology, the number of photoresist layers is large, the exposure and development are complex, the process is difficult and time-consuming, and there are problems of high cost and difficulty in large-scale application.

[0004] Therefore, it is urgent to provide a preparation method of a semiconductor device with a micro gate field plate to solve the defects of the prior art. SUMMARY

[0005] In order to solve the above-mentioned problems in the prior art, the application provides a preparation method of a semiconductor device with a micro gate field plate for radio frequency. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] In the first aspect, the application provides a preparation method of a semiconductor device with a micro gate field plate for radio frequency, comprising:

[0007] providing a heterojunction wafer;

[0008] depositing a passivation layer on the surface of the heterojunction wafer, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer;

[0009] Etching the hard mask layer, the dielectric layer and the passivation layer to form a gate recess;

[0010] Etching the dielectric layer to form the gate recess, so that part of the gate recess extends in the dielectric layer; the size of the gate recess in the dielectric layer is the length of the micro field plate;

[0011] Etching away the hard mask layer;

[0012] Photolithographing a gate region on the surface of the dielectric layer and in the gate recess, depositing a gate metal in the gate region, and stripping the gate metal after evaporation to form a gate;

[0013] Etching away the dielectric layer to form a micro field plate gate.

[0014] The present application has the following advantages:

[0015] The present application provides a preparation method of a semiconductor device with a micro gate field plate for radio frequency, which utilizes the different properties of dry etching and wet etching of the three-layer materials of the hard mask layer, the dielectric layer and the passivation layer, and realizes the formation of a micro field plate structure through etching of different materials by one-time photolithography, thereby simplifying the manufacturing steps of the micro field plate gate and reducing the process difficulty. In addition, the process is compatible with the mainstream production line capacity of GaN and ternary compound semiconductors, and can effectively realize the combination of high frequency characteristics and power characteristics of GaN HEMT devices.

[0016] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a schematic diagram of the preparation process of a micro field plate gate provided by the prior art;

[0018] Figure 2 is another schematic diagram of the preparation process of a micro field plate gate provided by the prior art;

[0019] Figure 3 is a flowchart of the preparation method of a semiconductor device with a micro gate field plate for radio frequency provided by an embodiment of the present application;

[0020] Figures 4a to 4f is a schematic diagram of the preparation method of a semiconductor device with a micro gate field plate for radio frequency provided by an embodiment of the present application;

[0021] Figures 5a to 5g is a schematic diagram of the preparation method of a semiconductor device with a micro gate field plate for radio frequency provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0023] In the prior art, such as Figure 1 As shown, first prepare a wafer with an AlGaN / GaN heterojunction on the surface, deposit a dielectric passivation layer on the surface, and apply a special electron beam resist; then use electron beam lithography to develop the gate groove, and etch the dielectric to remove the resist to make a gate groove structure on the dielectric layer; then apply three layers of electron beam resist on the wafer surface, and use electron beam lithography to make the three layers of electron beam resist present three different sizes of windows: medium, large, and small, and finally deposit metal to form a micro field plate gate structure. The size of the micro field plate depends on the size of the minimum window. Use as Figure 1 The preparation method requires two electron beam lithography processes, which is costly and time-consuming, making it unsuitable for large-scale use. Precise alignment is required between the two lithography processes. For example, for a 50nm micro-field plate width, it is necessary to ensure that the position of the second electron beam lithography process is no more than 50nm relative to the position of the first lithography pattern. This places high demands on the overlay accuracy of the lithography process and also leads to a decrease in the yield rate. When using electron beam lithography gate caps and micro-field plates, three layers of photoresist need to be used simultaneously. Such multiple layers of photoresist result in a total stacked photoresist thickness that is too thick, often reaching about 1um. During the exposure process, the electron beam current will scatter in the photoresist, and excessively thick photoresist thickness will also lead to greater scattering, causing the pattern to expand to a certain extent. In order to fully develop the photoresist at the bottom layer, overdevelopment is often serious, and the pattern expansion is even more serious, further increasing the difficulty of the process.

[0024] like Figure 2 As shown, first prepare a wafer with an AlGaN / GaN heterojunction on the surface, deposit a dielectric passivation layer, a sacrificial layer and an etch stop layer on the surface in sequence, use photolithography technology to make a photoresist groove on the surface, and etch the gate groove to the dielectric passivation layer; then use PECVD to deposit a dielectric layer on the surface, which can adhere to the sidewall of the gate groove; then use ICP dry etching to etch the wafer surface, first etch away the surface deposited in the previous step and the dielectric layer at the bottom of the groove, and then etch away the dielectric passivation layer at the bottom of the groove. Since the sidewall is relatively thick, the dielectric layer attached to the sidewall is retained; finally, etch away the dielectric layer and the etch stop layer attached to the sidewall to form a micro field plate structure, then photolithography the gate cap, evaporate the metal, make a micro field plate gate, and etch away the sacrificial layer. Use as Figure 2The preparation method of the micro field plate is as follows: four layers of dielectric layers are deposited in total, and the dry and wet etching selectivities of the four layers of dielectric layers are different from each other, for example, the passivation dielectric layer needs to have etching selectivity with respect to the sacrifice layer and the etching stop layer; the dielectric layer needs to have etching selectivity with respect to the etching stop layer; and the etching stop layer and the dielectric layer need to have etching selectivity with respect to the sacrifice layer, which greatly increases the complexity of the etching process. In addition, the length of the final gate is equal to the length of the first gate slot minus the width of the fourth side wall; and the length of the micro field plate is equal to the width of the fourth side wall plus the width of the final gate. If it is necessary to fix the length of the final gate and optimize the length of the micro field plate, the first gate slot length and the thickness of the side wall (i.e., the thickness of the deposited dielectric layer and the lateral etching width) need to be changed simultaneously, which does not utilize parameter optimization.

[0025] Therefore, the present application provides a preparation method of a semiconductor device of a micro gate field plate for radio frequency, which deposits passivation, dielectric and hard mask layers on a heterojunction, and then performs wet etching on the intermediate layer material after photolithography and etching to manufacture the micro gate field plate, so that the micro field plate structure is formed by one-time photolithography, the manufacturing steps of the micro field plate are simplified, the process difficulty is reduced, and the combination of high frequency characteristics and power characteristics of the GaN HEMT device can be effectively realized.

[0026] Please refer to Figure 3 and Figures 4a to 4f , Figure 3 is a flow chart of the preparation method of the semiconductor device of the micro gate field plate for radio frequency provided by the embodiment of the present application, Figures 4a to 4f is a schematic diagram of the preparation method of the semiconductor device of the micro gate field plate for radio frequency provided by the embodiment of the present application, and the preparation method of the semiconductor device of the micro gate field plate for radio frequency comprises the following steps:

[0027] S101, providing a heterojunction wafer.

[0028] Specifically, in the embodiment, the heterojunction wafer comprises a substrate, a gallium nitride layer and a barrier layer which are arranged in layers.

[0029] S102, depositing a passivation layer on the surface of the heterojunction wafer, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer, as shown in Figure 4a .

[0030] Specifically, please refer to Figure 4a , in the embodiment, the passivation layer, the dielectric layer and the hard mask layer are sequentially deposited on the surface of the AlGaN / GaN heterojunction wafer, the hard mask layer can use one or more of aluminum, nickel, titanium, tungsten and the like, the passivation layer can be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer can be a silicon dioxide layer.

[0031] S103, etching the hard mask layer, the dielectric layer and the passivation layer to form a gate recess, as shown in Figure 4b .

[0032] Specifically, please refer to Figure 4b In this embodiment, the photolithography etching technology is used to etch the gate recess on the wafer surface.

[0033] An alternative way, considering the depth of etching, the photoresist is coated on the surface of the hard mask layer, and the hard mask layer, the dielectric layer and the passivation layer are etched in turn using the photolithography etching process to form the gate recess.

[0034] Another alternative way, the photoresist is coated on the surface of the hard mask layer, and the hard mask layer is etched using the photolithography etching process;

[0035] The photoresist coated on the surface of the hard mask layer is removed, and the dielectric layer and the passivation layer are etched using the hard mask layer by the photolithography etching process to form the gate recess.

[0036] An alternative embodiment, the dielectric layer and the passivation layer are etched using F-based plasma.

[0037] It should be noted that when the dielectric layer and the passivation layer are etched using F-based plasma, the barrier layer will not be etched.

[0038] S104, etching the dielectric layer of the gate recess to make part of the gate recess area expand in the dielectric layer; the size of the gate recess in the dielectric layer is the length of the micro field plate, as shown in Figure 4c .

[0039] Specifically, please refer to Figure 4c In this embodiment, the BOE etching solution is used to etch the intermediate dielectric layer from the gate recess to make it expand laterally, and the concentration of the etching solution and the etching time are controlled to control the length of the lateral expansion, which is the length of the micro field plate.

[0040] It should be noted that the BOE etching solution has selectivity to the passivation layer and the hard mask layer, and has relatively weak etching property to the passivation layer and the hard mask layer material; in this embodiment, the BOE etching solution is a buffer oxide etchant (Boe 6:1 concentration), which is actually used according to the demand.

[0041] This embodiment ingeniously uses the selectivity of wet etching to the dielectric and passivation and hard mask, and makes the micro field plate structure on the wafer through photolithography and etching and etching, which is easier to control the length of the micro field plate than the existing technology which uses three layers of photoresist to expose the gate cap and the micro field plate.

[0042] It should be noted that according to the material selection of the dielectric layer and the passivation layer, the dielectric layer is etched away a lot when the boe wet etching is used, and the passivation layer is basically unchanged or changes a little, for example, the etching selection ratio (rate ratio) is 1:10.

[0043] S105, etching away the hard mask layer, as shown in Figure 4d .

[0044] Specifically, referring to Figure 4d , in the embodiment, other etching liquid is used to etch away the hard mask layer, and the etching liquid is selected according to the material of the hard mask layer; for example, if nickel metal is used as the hard mask layer, FeCl3 solution can be used as the etching liquid.

[0045] S106, photoetching the gate region on the surface of the dielectric layer and in the gate groove, depositing gate metal in the gate region, and stripping after evaporation of the gate metal to form a gate, as shown in Figure 4e .

[0046] Specifically, referring to Figure 4e , in the embodiment, the gate is first photoetched, and the gate metal is evaporated and stripped.

[0047] After the micro field plate structure is prepared in the embodiment, the hard mask layer is etched away, and the gate is directly photoetched and evaporated to make a micro field plate gate; that is, the micro field plate structure is etched on the basis of the gate groove, and the micro field plate gate is directly formed subsequently, without the need of high-precision photoetching and etching of the micro field plate structure on the gate groove, so that the process difficulty is reduced, the cost is saved, and the yield is increased.

[0048] S107, etching away the dielectric layer to form a micro field plate gate, as shown in Figure 4f .

[0049] Specifically, referring to Figure 4f , in the embodiment, the dielectric layer is etched away by using the BOE etching liquid to reduce the parasitic capacitance and form the micro field plate gate.

[0050] In summary, the preparation method of the semiconductor device of the micro gate field plate for radio frequency provided by the application utilizes the different properties of the dry and wet etching of the three-layer materials of the hard mask layer, the dielectric layer and the passivation layer, and realizes the formation of the micro field plate structure by one-time photoetching, so that the manufacturing steps of the micro field plate gate are simplified, and the process difficulty is reduced. In addition, the process is consistent with the mainstream production line capability of GaN and three-five compound semiconductors at present, and can effectively realize the combination of high frequency characteristics and power characteristics of GaN HEMT devices.

[0051] In an alternative embodiment of the present application, the micro field plate semiconductor device is prepared by the following steps, specifically:

[0052] S101, providing a heterojunction wafer.

[0053] Specifically, in this embodiment, the heterojunction wafer includes a substrate, a gallium nitride layer and a barrier layer arranged in layers.

[0054] S102, depositing a passivation layer on the surface of the heterojunction wafer, and depositing a dielectric layer on the surface of the passivation layer.

[0055] Specifically, in this embodiment, the passivation layer can be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer can be a silicon dioxide layer.

[0056] S103, photoetching the dielectric layer and the passivation layer to form a gate recess,

[0057] Specifically, in this embodiment, photoresist is coated on the surface of the dielectric layer, a pattern of the gate recess is defined on the photoresist, and the dielectric layer and the passivation layer are etched to form the gate recess; at this time, the photoresist remaining on the surface of the dielectric layer is not removed.

[0058] S104, etching the dielectric layer in which the gate recess is formed, so that part of the gate recess extends in the dielectric layer; the size of the gate recess in the dielectric layer is the length of the micro field plate.

[0059] S105, removing the photoresist on the surface of the dielectric layer.

[0060] S106, photoetching a gate region on the surface of the dielectric layer and in the gate recess, depositing a gate metal in the gate region, and peeling off after evaporation of the gate metal to form a gate.

[0061] S107, etching away the dielectric layer to form a micro field plate gate.

[0062] In an alternative embodiment of the present application, Figures 5a to 5g is a schematic diagram of a preparation method of a micro gate field plate semiconductor device for radio frequency provided by an embodiment of the present application, and the micro field plate Fin gate is prepared by the following steps, specifically:

[0063] S101, providing a heterojunction wafer.

[0064] Specifically, in this embodiment, the heterojunction wafer includes a substrate, a gallium nitride layer and a barrier layer arranged in layers.

[0065] S102, depositing a passivation layer on the surface of the heterojunction wafer, and depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer.

[0066] Specifically, in this embodiment, a passivation layer, a dielectric layer and a hard mask layer are sequentially deposited on the surface of the AlGaN / GaN heterojunction wafer, the hard mask layer can use one or more of aluminum, nickel, titanium, tungsten and the like, the passivation layer can be a silicon nitride layer or an aluminum oxide layer, and the dielectric layer can be a silicon dioxide layer.

[0067] S103, etching the hard mask layer, the dielectric layer and the passivation layer to form a gate recess, as shown in Figure 5a .

[0068] Specifically, please refer to Figure 5a , in this embodiment, a gate recess is etched on the surface of the wafer by using photolithography etching technology.

[0069] An alternative way is to consider the depth of etching, coat photoresist on the surface of the hard mask layer, and sequentially etch the hard mask layer, the dielectric layer and the passivation layer by using photolithography etching process to form a gate recess.

[0070] Another alternative way is to coat photoresist on the surface of the hard mask layer, and etch the hard mask layer by using photolithography etching process.

[0071] Remove the photoresist coated on the surface of the hard mask layer, and etch the dielectric layer and the passivation layer by using the hard mask layer by using photolithography etching process to form a gate recess.

[0072] An alternative embodiment is to etch the dielectric layer and the passivation layer by using F-based plasma.

[0073] It should be noted that when etching the dielectric layer and the passivation layer by using F-based plasma, the barrier layer will not be etched.

[0074] S104, coat photoresist on the surface of the hard mask layer and on part of the bottom and side of the gate recess, etch part of the barrier layer to form a Fin slot, as shown in Figure 5b .

[0075] S105, remove the photoresist, as shown in Figure 5c .

[0076] S106, etch the dielectric layer in which the gate recess is formed, so that part of the area of the gate recess is expanded in the dielectric layer; the size of the gate recess in the dielectric layer is the length of a micro field plate, as shown in Figure 5d .

[0077] S107, etch away the hard mask layer, as shown in Figure 5e .

[0078] Specifically, please refer to Figure 5eIn the embodiment, other etching solution is used to etch away the hard mask layer, and the etching solution is selected according to the material of the hard mask layer; for example, if nickel metal is used as the hard mask layer, FeCl3 solution can be used as the etching solution.

[0079] S108, the gate region is photoetched on the surface of the medium layer, in the gate groove, and in the Fin groove, the gate metal is deposited in the gate region, and the gate is formed after evaporation and stripping of the gate metal, as shown in Figure 5f .

[0080] Specifically, please refer to Figure 5f In the embodiment, the gate is first photoetched, and the gate metal is evaporated and stripped.

[0081] S109, the medium layer is etched away to form a micro field plate gate, as shown in Figure 5g .

[0082] It should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the article or device including the element. The terms "connected" or "connected" and the like are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. The directions or positional relationships indicated by "up", "down", "left", "right", and the like are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0083] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0084] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all should be deemed as falling within the protection scope of the present application.

Claims

1. A method for preparing a semiconductor device with a micro gate field plate for radio frequency, characterized in that: include: Providing a heterogeneous crystal circle; Depositing a passivation layer on the surface of the heterogeneous crystal circle, depositing a dielectric layer on the surface of the passivation layer, and depositing a hard mask layer on the surface of the dielectric layer; Etching the hard mask layer, the dielectric layer, and the passivation layer to form a gate groove; The dielectric layer forming the gate groove is corroded so that a partial area of ​​the gate groove extends in the dielectric layer; the size of the gate groove in the dielectric layer is the length of the micro field plate; etching away the hard mask layer; Photolithography of a gate region on the surface of the dielectric layer and in the gate groove, depositing a gate metal in the gate region, evaporating the gate metal and then peeling it off to form a gate; The dielectric layer is etched away to form a micro field plate gate.

2. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 1, characterized in that: The heterogeneous crystal circle includes a substrate, a gallium nitride layer and a barrier layer which are stacked.

3. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 1, characterized in that: The material of the hard mask layer includes one or more of aluminum, nickel, titanium, and tungsten.

4. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the hard mask layer, the dielectric layer, and the passivation layer to form a gate groove includes: A photoresist is coated on the surface of the hard mask layer, and the hard mask layer, the dielectric layer and the passivation layer are sequentially etched using a photolithography and etching process to form the gate groove.

5. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the hard mask layer, the dielectric layer, and the passivation layer to form a gate groove includes: Coating a photoresist on the surface of the hard mask layer, and etching the hard mask layer using a photolithography etching process; The photoresist coated on the surface of the hard mask layer is removed, and the dielectric layer and the passivation layer are etched using the hard mask layer by using a photolithography and etching process to form the gate groove.

6. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 4 or 5, characterized in that: Etching the dielectric layer and the passivation layer, comprising: The dielectric layer and the passivation layer are etched using F-based plasma.

7. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 1, characterized in that: The etching of the dielectric layer forming the gate groove so that a portion of the gate groove extends into the dielectric layer includes: The dielectric layer forming the gate groove is etched using a BOE etchant, and the concentration of the BOE etchant and the etching time are controlled to control the size of the gate groove extending in the dielectric layer.

8. The method for preparing a semiconductor device with a radio frequency micro-gate field plate according to claim 7, characterized in that: The etching time of the BOE etching solution is 5 to 30 seconds.

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