MOS device and preparation method thereof

Abstract

The invention discloses an MOS device and a preparation method thereof, and the MOS device comprises at least one source trench structure which is located between two adjacent first side surfaces and is in contact with a source region structure, the source trench structure comprises a first grid electrode, a second grid electrode, a first dielectric layer and a second dielectric layer, the first dielectric layer is located between the first grid electrode and the second grid electrode, and the second dielectric layer is located between the first grid electrode and the second grid electrode; the first grid electrode, the second grid electrode and the first dielectric layer form a first structure, the second dielectric layer is located on the side face and the bottom face of the first structure respectively and makes contact with the source region structure and the drift layer, and the first dielectric layer at least comprises a first material layer and a second material layer which are stacked in the second direction; the dielectric constant of the material of the first material layer is greater than that of the material of the second material layer, and the second direction is the direction from the substrate to the source region structure. The problems that reverse leakage current between a source and a drain in an MOS device damages the device and the coupling area between the source and the drain is large so that power consumption is large in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOS device and a method for preparing the MOS device. Background Art

[0002] Silicon-based IGBTs dominate high-voltage and high-current scenarios, but they cannot withstand high-frequency conditions and have high power consumption. SiC's high-voltage and high-temperature resistance allows it to cover the voltage resistance level of silicon-based IGBTs with only simpler MOSFET devices, while avoiding its high energy consumption disadvantages. Under the same environment, silicon carbide-based MOSFETs reduce energy losses by 66% compared to silicon-based IGBTs of the same specifications, mainly due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used to drive and control inverters, on-board chargers, and fast charging piles for motors. In photovoltaic power generation, leading photovoltaic inverter companies have currently adopted SiC power devices to replace silicon devices.

[0003] SiC MOSFET mainly acts as an electronic switch in power electronic systems. When MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not added in reverse parallel, this leakage current may cause damage to other devices in the circuit. In addition, when SiC MOSFET is used for rectification of AC circuits, since MOSFET can only be turned on under forward voltage, an anti-parallel diode is required to provide a conduction channel under reverse voltage to achieve current rectification. Therefore, it is usually necessary to anti-parallel or integrate a diode in the body of SiC MOSFET to improve the performance of the SiC MOSFET body diode, thereby improving the working efficiency of SiC MOSFET. However, the external anti-parallel diode will increase the circuit space occupied, increase the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance, resulting in slow response speed of the reverse diode, poor reliability and other problems. The internal integrated heterojunction Schottky diode (Schottky Barrier Diode, referred to as SBD) has a too high turn-on voltage (2.7-3.0V), and it is difficult to play the role of freewheeling protection MOSFET under reverse bias. Both methods will take up extra area. The reverse leakage of the integrated Schottky diode device is large, and even the reverse breakdown voltage of the MOSFET will be affected when the SBD area is too large. In addition, the Schottky diode's own voltage drop is too large at high currents, which will cause the voltage drop loss on the Schottky diode to be very large when the freewheeling current is large. When the SiC MOS device is in the off state, there will be a reverse leakage current between the drain and the source. If the freewheeling channel is not added, this leakage current may cause damage to other devices in the circuit. Summary of the invention

[0004] The present application provides a MOS device and a method for preparing the MOS device, so as to solve the problems in the related art that the reverse leakage current between the source and the drain in the MOS device damages the device and the large coupling area between the source and the drain leads to large power consumption.

[0005] According to one aspect of the present application, a MOS device is provided, comprising a plurality of cells, wherein the cells comprise a substrate and a drift layer located on one side of the substrate, wherein the drift layer has a first surface facing away from the substrate, and the cells further comprise: a plurality of source region structures, wherein the plurality of source region structures are spaced apart along a first direction, wherein two adjacent source region structures have first sides close to each other and two second sides facing away from each other in the first direction, wherein an area between two adjacent second sides is a drift region, wherein the drift region is a partial area in the drift layer, and the first direction is parallel to the first surface; a plurality of gate structures, wherein the gate structures are located on a side of the drift region facing away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region, respectively; and at least one source trench structure, wherein the source A first gate electrode and a second gate electrode are provided between the first and second gate electrodes, and the first gate electrode and the second gate electrode are provided between the first and second gate electrodes, and the first gate electrode, the second gate electrode and the first dielectric layer constitute a first structure, and the second dielectric layer is provided on the side and the bottom of the first structure and contacts the source region structure and the drift layer, wherein the second dielectric layer at least comprises a first material layer and a second material layer stacked in sequence from a second direction, the dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer, and the second direction is a direction from the substrate to the source region structure.

[0006] Optionally, the material of the first material layer includes a high-K material, and the material of the second material layer includes a low-K material.

[0007] Optionally, the first dielectric layer further includes a third material layer, the third material layer is located on a side of the second material layer away from the first material layer, and the material of the third material layer includes an insulating material with waterproof performance.

[0008] Optionally, the first material layer has a first thickness in the second direction, the second material layer has a second thickness in the second direction, and the first thickness is smaller than the second thickness.

[0009] Optionally, the second dielectric layer includes a first gate oxide layer and a fourth material layer which are stacked, wherein the first gate oxide layer is respectively located on the side and bottom surfaces of the first structure in contact with the drift layer, and the fourth material layer is located above and inside the first gate oxide layer, wherein the material of the fourth material layer includes a high-K material.

[0010] Optionally, the MOS device further includes: a shielding region, the shielding region is located on a side of the source trench structure close to the substrate, the shielding region and the drift layer have different doping types, wherein the shielding region has a plurality of sub-shielding regions spaced apart along the first direction.

[0011] Optionally, there is a first spacing between any two adjacent sub-shielding areas in the first direction, and there are m sub-shielding areas along the first direction, wherein: m is an even number, and the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacings; m is an odd number, and the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area in the first direction is greater than the remaining first spacings, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2th sub-shielding area is greater than the remaining first spacings.

[0012] Optionally, the MOS device further includes: a first conductive layer, which is located on a side of the source trench structure away from the substrate and is respectively in contact with the first gate, the second gate, the first dielectric layer and the second dielectric layer, and the first conductive layer is connected to the source region structure.

[0013] According to another aspect of the present application, a method for preparing a MOS device is provided, the MOS device includes a plurality of cells, and the steps of forming the cells include: providing a substrate; forming a drift layer on one side of the substrate, the drift layer having a first surface facing away from the substrate, the cell further including: forming a plurality of source region structures in the drift layer, the plurality of source region structures being spaced apart along a first direction, two adjacent source region structures having a first side surface close to each other and a second side surface facing away from each other, wherein the region between two adjacent second side surfaces is a drift region, the drift region is a partial region in the drift layer, and the first direction is parallel to the first surface; forming a first trench between two adjacent source region structures, the sidewall of the first trench exposing the first side surface of the source region structure, forming a source trench structure in the first trench, the source trench structure The structure includes a first gate, a second gate, a first dielectric layer and a second dielectric layer, the first gate and the second gate are arranged at intervals along the first direction, the first dielectric layer is located between the first gate and the second gate, the first gate, the second gate and the first dielectric layer constitute a first structure, the second dielectric layer is respectively located on the side and bottom of the first structure and is in contact with the source region structure and the drift layer, wherein the second dielectric layer at least includes a first material layer and a second material layer stacked in sequence along a second direction, the dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer, and the second direction is a direction from the substrate to the source region structure; a plurality of gate structures are formed on a side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region, respectively.

[0014] Optionally, the steps of forming the source trench structure include: forming the second dielectric layer on the sidewall of the first trench, and the remaining first trench constitutes the second trench; forming a gate material region in the second trench using a deposition process; etching to form a third trench in the gate material region, and the opposite sidewalls of the third trench in the first direction respectively expose the gate material region, and the remaining gate material region respectively constitutes the first gate and the second gate; using multiple deposition processes to form the first material layer and the second material layer in the third trench, and the first material layer and the second material layer constitute the first dielectric layer.

[0015] By applying the technical solution of the present application, a MOS device is provided. A source trench structure is formed between first side surfaces of two source regions of the MOS device. A first gate and a second gate in the source trench structure are arranged at intervals, and a first dielectric layer is provided between the first gate and the second gate, so that the source trench structure has a structure similar to a split gate. When the MOS device is in a forward state, the source trench structure and the source structure work together to reduce lateral leakage. When the MOS device is in a reverse state, the first gate and the second gate will respectively induce an annular inversion layer around the source trench structure with the nearby source structure, thereby forming a freewheeling channel for current to flow from the source to the drain. The source trench structure will result in a large coupling area between the source and the drain, greatly increasing the feedback capacitance and source charge of the device and reducing the switching speed of the device. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than the dielectric constant of the second material layer. The second material layer can shield the coupling area between the source and the drain, reducing the feedback capacitance and source charge of the device, increasing the switching speed of the device and reducing the power consumption of the device. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increase the breakdown resistance at the bottom of the source trench structure, and thereby improve the overall performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a schematic cross-sectional structure diagram of a MOS device according to an embodiment of the present application;

[0018] Figure 2 is a schematic cross-sectional structure diagram of another MOS device according to an embodiment of the present application;

[0019] Figure 3 is a schematic cross-sectional structure diagram of another MOS device according to an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of current flow direction of a MOS device in a reverse conduction state according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of current flow direction of a MOS device in a forward conduction state according to an embodiment of the present application;

[0022] Figure 6 A flow chart of a method for preparing a MOS device provided according to an embodiment of the present application is shown;

[0023] Figure 7 A schematic diagram of the cross-sectional structure of a substrate obtained in steps 1 to 4 in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0024] Figure 8 A schematic cross-sectional structure diagram of a rear substrate after forming a shielding area in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0025] Fig. 9 A schematic cross-sectional structure diagram of a substrate obtained in steps 5 to 9 in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0026] Fig.10 A schematic cross-sectional structure diagram of a substrate obtained in steps 10 to 13 in a method for preparing a MOS device provided in an embodiment of the present application is shown.

[0027] The above drawings include the following reference numerals:

[0028] 1. Cell; 10. Substrate; 20. Drift layer; 201. First surface; 202. Drift region; 30. Source region structure; 301. First side; 302. Second side; 31. Body region; 32. First doping region; 40. Gate structure; 41. Third gate; 42. Second gate oxide layer; 50. Source trench structure; 51. First gate; 511. Gate material region; 52. Second gate; 53. First dielectric layer; 531. First material layer; 532. Second material layer; 533. Third material layer; 54. Second dielectric layer; 541. Fourth material layer; 542. First gate oxide layer; 61. Gate electrode; 62. Gate dielectric layer; 70. Shielding region; 71. Sub-shielding region; 81. First conductive layer; 811. Ohmic metal layer; 82. Second conductive layer; 91. First trench; 92. Second trench; 93. Third trench. DETAILED DESCRIPTION

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] As described in the background technology, in the prior art, when the SiC MOS device is in the cut-off state, there will be a reverse leakage current between the drain and the source. If a freewheeling channel is not added, this leakage current may cause damage to other devices in the circuit. The present application provides a MOS device and a method for preparing a MOS device.

[0033] According to one aspect of the present application, a MOS device is provided, such as Figures 1 to 5As shown, it includes a plurality of cells 1, the cell 1 includes a substrate 10 and a drift layer 20 located on one side of the substrate 10, the drift layer 20 has a first surface 201 away from the substrate 10, and the cell 1 also includes: a plurality of source region structures 30, the plurality of source region structures 30 are arranged at intervals along a first direction A, two adjacent source region structures 30 have a first side surface 301 close to each other and two second side surfaces 302 away from each other in the first direction A, wherein the area between the two adjacent second side surfaces 302 is a drift region 202, the drift region 202 is a partial area in the drift layer 20, and the first direction A is parallel to the first surface 201; a plurality of gate structures 40, the gate structure 40 is located on the side of the drift region 202 away from the substrate 10, and the gate structure 40 is in contact with the source region structures 30 located on both sides of the drift region 202 respectively; at least one source trench structure 50, the source trench structure 5 0 is located between two adjacent first side surfaces 301 and is in contact with the source region structure 30. The source trench structure 50 includes a first gate 51, a second gate 52, a first dielectric layer 53 and a second dielectric layer 54. The first gate 51 and the second gate 52 are spaced apart along a first direction A. The first dielectric layer 53 is located between the first gate 51 and the second gate 52. The first gate 51, the second gate 52 and the first dielectric layer 53 constitute a first structure. The second dielectric layer 54 is respectively located on the side and bottom of the first structure and is in contact with the source region structure 30 and the drift layer 20. The first dielectric layer 53 at least includes a first material layer 531 and a second material layer 532 which are stacked in sequence along a second direction B. The dielectric constant of the material of the first material layer 531 is greater than the dielectric constant of the material of the second material layer 532. The second direction B is a direction from the substrate 10 to the source region structure 30.

[0034] In the above MOS device, a source trench structure is formed between the first side surfaces of the two source regions, a first gate and a second gate in the source trench structure are arranged at intervals, and a first dielectric layer is provided between the first gate and the second gate, so that the source trench structure has a structure similar to a split gate. When the MOS device is in a forward state, the source trench structure and the source structure work together to reduce lateral leakage; when the MOS device is in a reverse state, the first gate and the second gate will respectively induce an annular inversion layer with the nearby source structure around the source trench structure, thereby forming a freewheeling channel for current to flow from the source to the drain. However, the source trench structure will result in a large coupling area between the source and the drain, increase the feedback capacitance and source charge of the device, and reduce the switching speed of the device. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than the dielectric constant of the second material layer. The smaller the dielectric constant, the smaller the polarization charge, and the weaker the ability of the material to affect the electric field. The second material layer has a smaller dielectric constant, which can shield the coupling area between the source and the drain, reduce the feedback capacitance and source charge of the device, increase the switching speed of the device and reduce the power consumption of the device. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increase the breakdown resistance at the bottom of the source trench structure, and thereby improve the overall performance of the device.

[0035] Among them, the depth of the source trench structure is 0.8μm~1.5μm, the width is 0.15μm~1.3μm, and the thickness of the second dielectric layer is 0.03μm~0.08μm. Those skilled in the art can make reasonable selections according to actual needs, and this application does not make specific limitations.

[0036] In the above embodiment, the substrate and the drift layer have the same doping type, and the resistivity of the substrate is 0.016-0.24Ωcm; the drift layer is the main breakdown layer of the device, and its doping concentration is 1.0×10 15 cm -3 ~1.0×10 16 cm -3 The thickness of the drift layer can be selected according to product requirements. For example, the thickness of the drift layer of a 1200V MOS device is 9 μm to 11 μm, and the thickness of the drift layer of a 650V MOS device is 5 μm to 7 μm.

[0037] In the above embodiment, if Figures 1 to 5As shown, the source region structure 30 includes a body region 31 and a first doping region 32, the side of the first doping region 32 away from the drift region 202 is located in the first side 301, the body region 31 is located on the side of the first doping region 32 close to the substrate 10 and the body region 31 is located on the side of the first doping region 32 close to the drift region 202, and the gate structure 40 is in contact with the body region 31, wherein the doping type of the body region 31 is different from that of the first doping region 32, the first doping region 32 has the same doping type as the drift layer 20, and the doping concentration of the first doping region 32 is greater than the doping concentration of the body region 31. The magnitude of the gate voltage applied to the gate structure 40 can control the formation of a current channel in the body region 31 region in contact with the gate structure 40, and when the MOS device works normally, that is, when a current is applied to the source, a current channel is formed in the body region 31 region in contact with the source trench structure 50, thereby forming a freewheeling channel for current to flow from the source to the drain.

[0038] Specifically, the depth of the body region is 0.7 μm to 0.8 μm, and its doping concentration is 5.0×10 16 cm -3 ~1.5×10 17 cm -3 The depth of the first doping layer is 0.2 μm to 0.3 μm, and its doping concentration is 1.0×10 19 cm -3 ~1.0×10 20 cm -3 , technical personnel in this field can make adjustments according to actual needs, and this application does not make specific limitations.

[0039] In the above embodiment, if Figures 1 to 5 As shown, the gate structure 40 includes a third gate 41 and a second gate oxide layer 42 . The second gate oxide layer 42 is located on a side of the third gate 41 close to the substrate 10 . The third gate 41 contacts the gate electrode 61 . Furthermore, the third gate 41 and the gate electrode 61 are covered by the gate dielectric layer 62 .

[0040] Specifically, by applying a gate voltage to the third electrode, a current channel is controlled to be formed in the body region in contact with the gate structure. When the gate voltage is greater than a threshold value, the current channel in the body region is opened to form a current channel. When the gate voltage is less than the threshold value, no current is formed in the body region. At this time, no current is formed in the body region, and the gate structure forms a planar MOS structure, wherein the thickness of the gate dielectric layer is 600nm to 1000nm.

[0041] In some optional embodiments, the material of the first material layer includes a high-K material, and the material of the second material layer includes a low-K material.

[0042] Specifically, high-K material, i.e., high dielectric constant material, refers to a material with a higher dielectric constant than silicon dioxide. The dielectric constant of silicon dioxide is about 3.9, so a material with a dielectric constant greater than 3.9 is a high-K material. High-K material has a higher charge storage capacity, which means that under the same electric field, high-K material can store more charge, and high-K material has a lower leakage current and a higher breakdown voltage, which helps to improve the performance of the device. Low-K material, i.e., low dielectric constant material, refers to a material with a smaller dielectric constant, and the dielectric constant of low-K material is usually less than 3.0. Low-K material has a lower capacitance effect and leakage current, which can reduce the power consumption and heat generation of the circuit. The second material layer is a low-K material, which has a lower capacitance effect, can effectively reduce the feedback capacitance and source charge of the device, increase the switching speed of the device and reduce the power consumption of the device. The first material layer is a high-K material, which reduces the leakage current while improving the breakdown resistance. In addition, the low-K material has a multi-void structure, and the first gate and the second gate materials are mostly made of doped polysilicon materials. The doping elements in the polysilicon material are easy to diffuse, and the diffusion into the void structure of the low-K material causes the second material layer to have the layer degeneration of the capacitor dielectric. The first material layer composed of high-K material is located at the bottom of the first dielectric layer, which can play a good blocking role.

[0043] Among them, low-K materials include fluorosilicate glass FSG, porous organosilicate glass P-OSG, fluorinated polyimide, benzocyclobutene BCB, etc., and high-K materials can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, La2O3, Y2O3, SrTiO3 and BaSrTiO. Those skilled in the art can make reasonable selections according to actual needs, and this application does not make specific limitations.

[0044] In some optional embodiments, such as Figure 1 and Figures 3 to 5 As shown, the first dielectric layer 53 further includes a third material layer 533 . The third material layer 533 is located on a side of the second material layer 532 away from the first material layer 531 . The material of the third material layer 533 includes an insulating material with waterproof performance.

[0045] Specifically, when the second material layer has a lower dielectric constant, the material with a lower dielectric constant, especially the low-K material, has a void structure or has a hydrophilic group in the chemical cost, which makes it easy to absorb water, and will cause the second material layer to absorb water and deform during the subsequent manufacturing process. When the second material layer absorbs water and deforms, it will affect the strength and adhesion of the second material layer, reduce the stability and reliability of the device, and the low-K material after absorbing water will reduce its capacitance effect and durability, affecting the overall performance of the device. A layer of insulating material with waterproof properties, such as Si3N4, is formed above the second material layer to effectively protect the second material layer and prevent the second material layer from being affected by water in subsequent processes and causing water absorption and deformation. The thickness of the third material layer is 0.1μm to 0.6μm, and the specific thickness is not limited in this application.

[0046] Among them, in addition to the above-mentioned Si3N4, the materials of the third material layer also include one or more materials of metal oxides (such as aluminum oxide), polymer materials (such as polyimide, polyparaxylene and epoxy resin), hydrophobic materials (such as fluorinated polymers), carbon-based materials (such as graphene), and inorganic films (such as tantalum nitride, titanium nitride and silicon nitride oxide). This application does not limit this. These materials mainly have low moisture permeability and good chemical stability, and can also effectively prevent material performance changes or corrosion caused by moisture.

[0047] In some optional embodiments, the first material layer has a first thickness in the second direction, the second material layer has a second thickness in the second direction, and the first thickness is less than the second thickness.

[0048] Specifically, in the first dielectric layer, the first material layer located on the upper layer has the function of reducing the feedback capacitance and source charge of the device, improving the switching speed of the device and reducing the power consumption of the device. The second material layer located on the lower layer plays a role in protecting the second material layer from breakdown and increasing the breakdown resistance of the bottom of the source trench structure. Therefore, by increasing the thickness of the first material layer and reducing the thickness of the second material layer, while not affecting the forward operation of the source trench structure to reduce lateral leakage and reverse operation to form a freewheeling channel for current flowing from the source to the drain, the function of the second material layer in shielding the coupling area of ​​the source and the drain is enhanced, thereby further reducing the feedback capacitance and source charge of the device, improving the switching speed of the device and reducing the power consumption of the device.

[0049] The thickness of the first material layer is 0.02 μm to 0.1 μm, and the thickness of the second material layer is 0.7 μm to 1 μm. The specific thickness is not limited in this application.

[0050] In some optional embodiments, such as Figure 2 and Figure 3As shown, the second dielectric layer 54 includes a fourth material layer 541 and a first gate oxide layer 542 which are stacked, the first gate oxide layer 542 is respectively located on the side and bottom of the first structure in contact with the drift layer 20, and the fourth material layer 541 is located above and inside the first gate oxide layer 542, wherein the material of the fourth material layer 541 includes a high-K material.

[0051] Specifically, the high-K material has a higher dielectric constant. If the first dielectric layer of the source trench structure adopts a high-K material, the control of the channel charge can be enhanced, the control accuracy of the gate voltage on the channel current can be improved, and the gate voltage requirement can be reduced to achieve the same electric field strength. At the same time, the high-K material can help to more evenly distribute the electric field around the trench, reduce the electric field concentration, and thus improve the voltage resistance of the device. However, the interface state density between the high-K material and the drift layer material is relatively large. If the first dielectric layer only adopts a high-K material, while the high-K material can enhance the voltage resistance of the device, it will also weaken the carrier mobility in the MOS device and affect the forward conduction characteristics of the device. In the above embodiment, there is a first gate oxide layer and a fourth material layer in the second dielectric layer, and the material of the fourth material layer is a high-K material. There is a first gate oxide layer between the fourth material layer formed by the high-K material and the drift layer, wherein the interface state density between the first gate oxide layer and the drift layer is relatively small, and will not affect the carrier mobility in the MOS device. Therefore, the inner high-K material constituting the fourth material layer can improve the voltage resistance of the device, while the outer first gate oxide layer will not affect the carrier mobility in the MOS device, thereby improving the voltage resistance performance at the bottom of the source trench structure.

[0052] In some optional embodiments, such as Figures 1 to 5 As shown, the MOS device further includes: a shielding region 70, which is located on a side of the source trench structure 50 close to the substrate 10, and the shielding region 70 and the drift layer 20 have different doping types, wherein the shielding region 70 has a plurality of sub-shielding regions 71 arranged at intervals along the first direction A.

[0053] Specifically, the electric field concentration at the corners of the source trench structure causes the second dielectric layer to be broken down, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. By implanting a shielding area at the bottom of the source trench structure, the electric field distribution at the bottom of the source trench can be effectively improved, and the electric field concentration can be reduced, especially at the corners. This can significantly enhance the device's ability to resist breakdown, allowing the device to operate normally at a higher voltage without early breakdown, and also improves the long-term operating reliability of the device. When the MOS device is in a reverse biased state, the shielding area can act as a freewheeling channel by inducing a ring-shaped inversion layer in the body region, allowing current to flow from the source to the drain under control, thereby avoiding unnecessary leakage current and reducing the power consumption of the device.

[0054] In some specific implementations, the shielding region is composed of a plurality of sub-shielding regions, and the sub-shielding regions are floating, that is, they are not in contact with the source trench structure.

[0055] Specifically, multiple sub-shielding areas help improve device thermal management. Multiple sub-shielding areas can serve as multiple thermal barriers to reduce heat transfer between the source and drain, reduce heat accumulation in the device in high-frequency, high-current applications, and improve thermal stability. The floating sub-shielding area is electrically isolated from the source trench structure, which can reduce the concentration of the electric field in the source trench structure, especially avoid the high electric field strength at the bottom of the source trench, and reduce the risk of oxide layer breakdown. When the MOS device is under forward or reverse bias conditions, the floating sub-shielding area can dynamically sense and control the distribution of charges, thereby forming a more uniform electric field, reducing the loss of charge carriers, and reducing the power consumption of the device. If the sub-shielding area is in contact with the source trench structure, it will cause the device to form an additional charge dissipation path in the forward blocking state, thereby forming unnecessary leakage current. The floating sub-shielding area can avoid the above situation and ensure good charge control in the cut-off state. Even if the device is under non-ideal working conditions (such as extreme temperature, high-voltage environment), it can have good anti-interference and self-protection capabilities, thereby improving the robustness and adaptability of the device.

[0056] In some optional embodiments, there is a first spacing between any two adjacent sub-shielding areas in the first direction, and there are m sub-shielding areas along the first direction, wherein: m is an even number, and the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacings; m is an odd number, and the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area in the first direction is greater than the remaining first spacings, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2th sub-shielding area is greater than the remaining first spacings.

[0057] In the above embodiment, in the first direction, the first spacing between the sub-shielding areas in the middle is greater than the first spacing between the sub-shielding areas on both sides. Exemplarily, the first direction has an even number m of sub-shielding areas, m is 4, then the first spacing between the 2nd sub-shielding area and the 3rd sub-shielding area is greater than the first spacing between the 1st sub-shielding area and the 2nd sub-shielding area, and at the same time, the first spacing between the 2nd sub-shielding area and the 3rd sub-shielding area is greater than the first spacing between the 3rd sub-shielding area and the 4th sub-shielding area. In another example, the first direction has an odd number m of sub-shielding areas, m is 5, then the first spacing between the 2nd sub-shielding area and the 3rd sub-shielding area is greater than the first spacing between the other sub-shielding areas, or the first spacing between the 3rd sub-shielding area and the 4th sub-shielding area is greater than the first spacing between the other sub-shielding areas, or the first spacing between the 2nd sub-shielding area and the 3rd sub-shielding area is equal to the first spacing between the 3rd sub-shielding area and the 4th sub-shielding area, and is greater than the first spacing between the other sub-shielding areas.

[0058] Specifically, the denser the sub-shielding areas are, the better the improvement effect on the electric field distribution is. By adjusting the spacing of multiple sub-shielding areas, the spacing of the sub-shielding areas on both sides is smaller than the spacing of the sub-shielding areas in the middle. The dense sub-shielding areas on both sides more effectively disperse the electric field strength at the corners of the source trench structure, reduce the concentration of the electric field, and thus significantly improve the breakdown voltage of the device, enhance the forward blocking characteristics and long-term reliability of the device. In addition, the dense sub-shielding areas located below the corners of the source trench structure help to form a more effective heat dissipation path at the edge of the trench, help to quickly dissipate heat energy, reduce hot spots, and improve the thermal stability of the device, especially under high current and high frequency working conditions, which can significantly improve the durability and reliability of the device.

[0059] The doping concentration of the sub-shielding region is greater than the doping concentration of the drift layer. Specifically, the doping concentration of the sub-shielding region is 5.0×10 18 cm -3 ~1.5×10 19 cm -3 , the injection depth of the sub-shielding area is 0.9μm to 1.8μm, the length of the sub-shielding area along the first direction is 0.3μm to 0.6μm, the width of the sub-shielding area along the second direction is 0.3μm to 0.6μm, the adjacent first spacing is 0.2μm to 0.5μm, and the distance between the sub-shielding area and the bottom surface of the upper source trench structure is 0.2μm to 1μm. Those skilled in the art can make appropriate selections according to the performance of the product, and this application does not make specific limitations.

[0060] In some optional embodiments, such as Figures 1 to 5As shown, the MOS device also includes: a first conductive layer 81, which is located at least on the side of the source trench structure 50 away from the substrate and contacts the first gate 51, the second gate 52, the first dielectric layer 53 and the second dielectric layer 54 respectively, and is connected to the source region structure 30.

[0061] Specifically, the first conductive layer is the source electrode of the MOS device, the first conductive layer contacts the first gate and the second gate in the source trench structure, and forms a connection with the source region. When the MOS device is reversely conducted, the first gate and the second gate in contact with the first conductive layer respectively induce an inversion layer with the body region in the source region structure on both sides, forming a conductive channel from the drift layer to the body region and the first doped region in the source region structure and then to the first conductive layer, that is, forming a freewheeling channel for current to flow from the source to the drain, playing a role of reverse freewheeling, and the current channel is as follows: Figure 4 When the MOS device is forward-conducting, a freewheeling channel for current to flow from the source to the drain is formed in the body region in contact with the gate structure. The current channel is as shown in FIG. Figure 5 In the direction of the arrow shown in the figure, the first conductive layer is connected to a negative potential, and the first gate and the second gate can adjust the electric field of the source trench structure, so that the electric field becomes stronger in the vertical direction, while the electric field in the lateral direction is weakened, and the charge carriers are restricted to move in the vertical direction, thereby reducing lateral leakage.

[0062] In addition, the electric field concentration at the corners of the source trench structure causes the thin oxide dielectric layer to break down, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. A floating sub-shielding area is implanted at the bottom of the source trench. The floating sub-shielding area is designed to have a small edge spacing and a large middle spacing, which can better reduce the electric field concentration at the bottom of the source trench, enhance the anti-breakdown property, and thus improve the reliability of the device. In addition, the use of a trench split-gate structure under the source can also shield the coupling area between the source and the drain, greatly reducing the feedback capacitance and source charge of the device, and improving the switching speed of the device.

[0063] In some optional embodiments, such as Figures 1 to 5 As shown, the MOS device further includes: a second conductive layer 82, which is located on a side of the substrate 10 away from the drift layer 20, so as to serve as a drain electrode of the device.

[0064] In order to reduce the on-resistance of the device, in some embodiments, as Figures 1 to 5 As shown, an ohmic metal layer 811 is formed between the source region structure 30 and the first conductive layer 81. The ohmic metal layer 811 forms an ohmic contact with the first doped region 32. The ohmic contact has a lower on-resistance to reduce the on-resistance of the MOS device. The material of the ohmic metal layer 811 includes Ni, Ti and other materials.

[0065] According to another aspect of the present application, a method for preparing a MOS device is provided, which is used to prepare any MOS device, such as Figure 6 As shown, the MOS device includes a plurality of cells, and the preparation method includes:

[0066] Step S101: providing a substrate;

[0067] Step S102: forming a drift layer on one side of the substrate, wherein the drift layer has a first surface facing away from the substrate;

[0068] Step S103: forming a plurality of source region structures in the drift layer, wherein the plurality of source region structures are spaced apart along a first direction, wherein two adjacent source region structures have first side surfaces close to each other and second side surfaces away from each other, wherein an area between two adjacent second side surfaces is a drift region, and the drift region is a partial area in the drift layer, and the first direction is parallel to the first surface;

[0069] Step S104: forming a first trench between two adjacent source region structures, wherein the sidewall of the first trench exposes the first side surface of the source region structure, and forming a source trench structure in the first trench, wherein the source trench structure comprises a first gate, a second gate, a first dielectric layer, and a second dielectric layer, wherein the first gate and the second gate are spaced apart along a first direction, the first dielectric layer is located between the first gate and the second gate, the first gate, the second gate, and the first dielectric layer constitute a first structure, and the second dielectric layer is respectively located on the side surface and the bottom surface of the first structure and contacts the source region structure and the drift layer, wherein the second dielectric layer comprises at least a first material layer and a second material layer stacked in sequence along a second direction, the dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer, and the second direction is a direction from the substrate to the source region structure;

[0070] Step S105: forming a plurality of gate structures on a side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region respectively.

[0071] By adopting the above-mentioned preparation method of the embodiment of the present application, a first groove is formed between the first side surfaces of the two source regions, and a source groove structure is formed in the first groove. The first gate and the second gate in the source groove structure are arranged at intervals, and a first dielectric layer is provided between the first gate and the second gate, so that the source groove structure has a structure similar to a split gate. When the MOS device is in the forward state, the source groove structure and the source structure work together to reduce lateral leakage; when the MOS device is in the reverse state, the first gate and the second gate will respectively induce an annular inversion layer with the nearby source structure around the source groove structure, thereby forming a freewheeling channel for current to flow from the source to the drain. However, the source trench structure will result in a large coupling area between the source and the drain, increase the feedback capacitance and source charge of the device, and reduce the switching speed of the device. The first dielectric layer between the first gate and the second gate has a first material layer and a second material layer. The dielectric constant of the first material layer is greater than the dielectric constant of the second material layer. The smaller the dielectric constant, the smaller the polarization charge, and the weaker the ability of the material to affect the electric field. The second material layer has a smaller dielectric constant, which can shield the coupling area between the source and the drain, reduce the feedback capacitance and source charge of the device, increase the switching speed of the device and reduce the power consumption of the device. The first material layer is located at the bottom of the first dielectric layer, which can protect the second material layer from breakdown, increase the breakdown resistance at the bottom of the source trench structure, and thereby improve the overall performance of the device.

[0072] The following will describe in more detail the exemplary embodiments of the method for preparing a power device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0073] First, proceed to step S101: Figure 7 As shown in (a), a substrate 10 is provided.

[0074] Specifically, the substrate material includes but is not limited to silicon, silicon nitride, silicon carbide, gallium nitride, gallium oxide, aluminum oxide and aluminum nitride and other materials. Personnel in this field can make reasonable selections based on actual needs and no specific limitation is made without application.

[0075] After the step of providing the substrate, step S102 is performed; Figure 7 As shown in (b), a drift layer 20 is formed on the substrate 10.

[0076] Specifically, the drift layer material may include silicon, silicon nitride, silicon carbide, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and other materials. Personnel in the art may make reasonable selections according to actual needs, and no specific limitation is made without application. Exemplarily, the drift layer material is silicon carbide material to solve the problem that the performance advantage of SiC diode devices is not obvious in some parameters.

[0077] In some optional embodiments, the process of forming the drift layer includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of the impurities is relatively easy to control, and the activation rate is relatively fixed, and the target doping distribution is easy to achieve. It is not only applicable to silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate, and has a low cost. Among them, the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Among them, physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal organic compound chemical vapor deposition (MOCVD), laser induced chemical vapor deposition (LCVD), and those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0078] After the step of forming the drift layer, step S103 is performed: Figure 7 As shown in (c), a plurality of source region structures 30 are formed.

[0079] Specifically, the steps of forming the source region structure include: Figure 7 As shown in (c), first, a plurality of spaced-apart body regions 31 are formed in the drift layer 20, wherein the body regions 31 and the drift layer 20 have different doping types; then, a first doping region 32 is formed on the side close to each other of any two adjacent body regions 31, wherein the first doping region 32 and the body region 31 have different doping types, and the doping concentration of the first doping region 32 is greater than the doping concentration of the body region 31.

[0080] Among them, the process of forming the body region and the first doping region includes an ion implantation process. The ion implantation process does not require high temperature treatment, that is, it can achieve precise control of the concentration and depth of the implanted ions. While achieving precise doping, it can avoid damage and deformation of the material structure. In addition, the doping concentration of the first doping region is greater than the doping concentration of the body region, and the depth of the first doping region is less than the depth of the body region. The ion implantation process can accurately control the doping concentration and depth of the first doping region and the body region. In addition, the carbon-silicon bond energy in the silicon carbide material is relatively high, and impurity atoms are difficult to diffuse in the silicon carbide material. The ion implantation process is a method of adding a certain amount and type of impurities to the semiconductor material to change the electrical properties. The ion implantation process has the advantages of low injection temperature, and the doping distribution can be flexibly and accurately controlled, which can reduce the damage of high temperature to the silicon carbide material and improve the doping efficiency.

[0081] In some optional embodiments, the above preparation method further comprises: Figure 7 As shown in (d), a first trench 91 is formed between two adjacent source region structures 30, and the sidewall of the first trench 91 exposes the first side surface of the source region structure 30; then, as shown in Figure 8 As shown, after forming the first trench 91, a shielding area 70 is formed at the bottom of the first trench 91, wherein the shielding area 70 has a plurality of sub-shielding areas 71, which can effectively improve the electric field distribution at the bottom of the source trench and reduce the electric field concentration, especially at the corners, which can significantly enhance the device's ability to resist breakdown, so that the device can operate normally at a higher voltage without early breakdown, and also improve the long-term operation reliability of the device. When the MOS device is in a reverse bias state, by inducing a ring-shaped inversion layer in the body region, the shielding area can act as a freewheeling channel, allowing the current to flow from the source to the drain under control, thereby avoiding unnecessary leakage current and reducing the power consumption of the device. Among them, the sub-shielding area is floating, that is, it is non-contact with the source trench structure; the doping type of the sub-shielding area is different from the doping type of the drift layer, and the doping concentration of the sub-shielding area is greater than the doping concentration of the drift layer; the process of forming the sub-shielding area 71 includes an ion implantation process.

[0082] Specifically, the etching process includes but is not limited to dry etching (Dry Etching), wet etching (Wet Etching), deep etching (Deep Etching), ion beam etching (IBE) and electrolytic etching, among which dry etching includes physical etching, chemical vapor etching and plasma etching, and deep etching includes deep reactive ion etching and laser etching. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0083] After the source region structure is formed, step S104 is performed: forming a source trench structure.

[0084] Specifically, the steps of forming the source trench structure include: first, Fig. 9 As shown in (a), a second dielectric layer 54 is formed on the sidewall of the first trench 91, and the remaining first trench 91 constitutes a second trench 92; then, as shown in Fig. 9 As shown in (b), a gate material region 511 is formed in the second trench 92 by a deposition process; then, as shown in Fig. 9 As shown in (c), a third trench 93 is formed by etching in the gate material region 511, and the sidewalls of the third trench 93 opposite to each other in the first direction respectively expose the gate material region, and the remaining gate material region respectively constitutes the first gate 51 and the second gate 52; then, as shown in Fig. 9 As shown in (d), a first material layer 531, a second material layer 532 and a third material layer 533 are respectively formed in the third groove 93 by multiple deposition processes, the first material layer 531, the second material layer 532 and the third material layer 533 constitute a first dielectric layer 53, and the first gate 51, the second gate 52, the first dielectric layer 53 and the second dielectric layer 54 constitute a source trench structure 50, wherein the dielectric constant of the material of the first material layer 531 is greater than the dielectric constant of the material of the second material layer 532, specifically, the material of the first material layer 531 includes a high-K material, the material of the second material layer 532 includes a low-K material, and the material of the third material layer 533 includes a waterproof material.

[0085] Specifically, the process of forming the first gate, the second gate, the first material layer and the second material layer includes but is not limited to a deposition process and an epitaxial growth process, wherein the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD), wherein physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal organic compound chemical vapor deposition (MOCVD), laser induced chemical vapor deposition (LCVD), and technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0086] After the source trench structure is formed, step S105 is performed: forming a gate structure.

[0087] Specifically, the steps of forming the gate structure include: first, Fig.10 As shown in (a), Fig. 9 In the structure shown in (d), a second gate oxide layer 42 is formed on the drift region 202 formed by the drift layer 20 where the source region structure 30 is away from the source trench structure 50, and the second gate oxide layer 42 is in contact with the body region 31 and a portion of the first doped region 32; then, as shown in Fig.10As shown in FIG. 5( b ), a third gate electrode 41 is formed on the second gate oxide layer 42 , and the second gate oxide layer 42 and the third gate electrode 41 constitute a gate structure 40 .

[0088] In some optional implementations, after forming the gate structure, the method further includes: Fig.10 As shown in (c), first, a gate electrode 61 is formed on the third gate 41 ; then, a gate dielectric layer 62 is formed on the gate electrode 61 , the third gate 41 and the sidewall of the gate structure 40 .

[0089] In some optional embodiments, the above preparation method further includes: step S106: Figure 1 As shown, a first conductive layer 81 is formed on the substrate including the source trench structure 50 and the gate structure 40 ; and a second conductive layer 82 is formed on a side of the substrate away from the drift layer.

[0090] In a specific embodiment, Fig.10 As shown in (d), before forming the first conductive layer 81 , an ohmic metal layer 811 is formed. The ohmic metal layer 811 is located on a side of the first doping region 32 away from the substrate 10 and in contact with the first doping region 32 .

[0091] The MOS device formed by the MOS device preparation method of the present application will be described below in conjunction with an embodiment.

[0092] Example

[0093] Provide an N-type silicon carbide substrate 10, such as Figure 7 (a)

[0094] An N-type silicon carbide drift layer 20 is formed on the silicon carbide substrate 10 by using an epitaxial growth process. Figure 7 (b)

[0095] An ion implantation process is used to form a plurality of P-type body regions 31 spaced apart from each other in the drift layer 20 ;

[0096] An N-type first doping region 32 is formed in the body region 31 by an ion implantation process, wherein the body region 31 and the first doping region 32 constitute a source region structure 30, such as Figure 7 (c)

[0097] A first trench 91 is formed between two adjacent source region structures 30 by an etching process, and the sidewall of the first trench 91 exposes the first side surface of the source region structure 30. Figure 7 (d)

[0098] Four P-type sub-shielding regions 71 are formed on the bottom surface of the first trench 91 by an ion implantation process. The four P-type sub-shielding regions 71 constitute a P-type shielding region 70. Figure 8 As shown;

[0099] A silicon oxide layer is formed on the sidewall and bottom of the first trench 91 by a high temperature thermal oxidation process to form a second dielectric layer 54. The remaining first trench 91 constitutes a second trench 92. Fig. 9 (a)

[0100] A deposition process is used to form an N-type polysilicon region in the second trench 92 to form a gate material region 511. Fig. 9 (b)

[0101] A third trench 93 is formed by etching in the gate material region 511. Two sidewalls of the third trench 93 opposite to each other in the first direction expose the polysilicon region respectively. The remaining polysilicon region constitutes the first gate 51 and the second gate 52 respectively. Fig. 9 (c)

[0102] A HfO2 layer, a fluorosilicic acid glass layer and a Si3N4 layer are deposited in the third trench 93 to form a first material layer 531, a second material layer 532 and a third material layer 533. The first material layer 531, the second material layer 532 and the third material layer 533 constitute a first dielectric layer 53. Fig. 9 (d)

[0103] A silicon oxide layer is deposited on the drift region 202 to form a second gate oxide layer 42. Fig.10 (a)

[0104] An N-type polysilicon layer is deposited on the second gate oxide layer 42 to form a third gate 41. Fig.10 (b)

[0105] Metal copper is deposited on the third gate 41 to form a gate electrode 61, and silicon dioxide is formed on the gate electrode 61, the third gate 41 and the sidewall of the gate structure 40 by a deposition process to form a gate dielectric layer 62. Fig.10 (c)

[0106] A Ni layer is formed on the first doping region 32 to form an ohmic metal layer 811, such as Fig.10 (d)

[0107] A first conductive layer 81 is formed on the substrate including the source trench structure 50 and the gate structure 40 by a deposition process, and a second conductive layer 82 is formed by deposition on the side of the substrate away from the drift layer. Figure 1 shown.

[0108] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0109] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A MOS device, characterized in that: The invention comprises a plurality of cells, wherein the cells comprise a substrate and a drift layer located on one side of the substrate, wherein the drift layer has a first surface facing away from the substrate, and the cells further comprise: A plurality of source region structures, wherein the plurality of source region structures are arranged at intervals along a first direction, wherein two adjacent source region structures have first side surfaces close to each other and two second side surfaces away from each other in the first direction, wherein a region between two adjacent second side surfaces is a drift region, and the drift region is a partial region in the drift layer, and the first direction is parallel to the first surface; A plurality of gate structures, wherein the gate structures are located on a side of the drift region away from the substrate, and the gate structures are in contact with the source region structures located on both sides of the drift region respectively; At least one source trench structure, the source trench structure is located between two adjacent first side surfaces and is in contact with the source region structure, the source trench structure includes a first gate, a second gate, a first dielectric layer and a second dielectric layer, the first gate and the second gate are spaced apart along the first direction, the first dielectric layer is located between the first gate and the second gate, the first gate, the second gate and the first dielectric layer constitute a first structure, the second dielectric layer is respectively located on the side and bottom of the first structure and is in contact with the source region structure and the drift layer, wherein the first dielectric layer at least includes a first material layer and a second material layer stacked in sequence from a second direction, the dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer, and the second direction is a direction from the substrate to the source region structure.

2. The MOS device according to claim 1, characterized in that: The material of the first material layer includes a high-K material, and the material of the second material layer includes a low-K material.

3. The MOS device according to claim 2, characterized in that: The first dielectric layer further includes a third material layer, the third material layer is located on a side of the second material layer away from the first material layer, and the material of the third material layer includes an insulating material with waterproof performance.

4. The MOS device according to claim 1, characterized in that: The first material layer has a first thickness in the second direction, the second material layer has a second thickness in the second direction, and the first thickness is smaller than the second thickness.

5. The MOS device according to claim 1, characterized in that: The second dielectric layer includes a first gate oxide layer and a fourth material layer which are stacked, wherein the first gate oxide layer is respectively located on the side and bottom of the first structure in contact with the drift layer, and the fourth material layer is located above and inside the first gate oxide layer, wherein the material of the fourth material layer includes a high-K material.

6. The MOS device according to any one of claims 1 to 5, characterized in that: The MOS device further comprises: A shielding region, the shielding region is located on a side of the source trench structure close to the substrate, the shielding region and the drift layer have different doping types, wherein the shielding region has a plurality of sub-shielding regions spaced apart along the first direction.

7. The MOS device according to claim 6, characterized in that: There is a first spacing between any two adjacent sub-shielding areas in the first direction, and there are m sub-shielding areas along the first direction, wherein: m is an even number, and the first spacing between the m / 2th sub-shielding area and the (m / 2)+1th sub-shielding area in the first direction is greater than the remaining first spacings; m is an odd number, and in the first direction, the first spacing between the (m-1) / 2th sub-shielding area and the (m+1) / 2th sub-shielding area is greater than the remaining first spacings, and / or the first spacing between the (m+1) / 2th sub-shielding area and the (m+3) / 2th sub-shielding area is greater than the remaining first spacings.

8. The MOS device according to claim 1, characterized in that: The MOS device further includes: a first conductive layer, which is located on a side of the source trench structure away from the substrate and contacts the first gate, the second gate, the first dielectric layer and the second dielectric layer respectively, and is connected to the source region structure.

9. A method for preparing a MOS device, characterized in that: The MOS device includes a plurality of cells, and the steps of forming the cells include: Provide substrate A drift layer is formed on one side of the substrate, wherein the drift layer has a first surface facing away from the substrate, and the cell further comprises: A plurality of source region structures are formed in the drift layer, wherein the plurality of source region structures are spaced apart along a first direction, and two adjacent source region structures have first side surfaces close to each other and second side surfaces away from each other, wherein a region between two adjacent second side surfaces is a drift region, and the drift region is a partial region in the drift layer, and the first direction is parallel to the first surface; A first trench is formed between two adjacent source region structures, the sidewall of the first trench exposes the first side of the source region structure, a source trench structure is formed in the first trench, the source trench structure comprises a first gate, a second gate, a first dielectric layer and a second dielectric layer, the first gate and the second gate are arranged with spacing along the first direction, the first dielectric layer is located between the first gate and the second gate, the first gate, the second gate and the first dielectric layer constitute a first structure, the second dielectric layer is respectively located on the side and bottom of the first structure and contacts the source region structure and the drift layer, wherein the second dielectric layer comprises at least a first material layer and a second material layer stacked in sequence from a second direction, the dielectric constant of the material of the first material layer is greater than the dielectric constant of the material of the second material layer, and the second direction is a direction from the substrate to the source region structure; A plurality of gate structures are formed on a side of the drift region away from the substrate, and the gate structures are respectively in contact with the source region structures located on both sides of the drift region.

10. The preparation method according to claim 9, characterized in that: The steps of forming the source trench structure include: forming the second dielectric layer on the sidewall of the first trench, and the remaining first trench constitutes a second trench; forming a gate material region in the second trench by a deposition process; Etching a third trench in the gate material region, wherein opposite sidewalls of the third trench in the first direction respectively expose the gate material region, and the remaining gate material region respectively constitutes the first gate and the second gate; The first material layer and the second material layer are respectively formed in the third trench by using multiple deposition processes, and the first material layer and the second material layer constitute the first dielectric layer.

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