Electronic device

Abstract

An electronic device according to an embodiment of the present invention may include: a display panel including: a pixel including a pixel driving circuit and a light emitting element; the sensor comprises a sensor driving circuit and a sensing element, and the display panel defines a display area and works in a sensing mode; the pixels comprise a first pixel, a second pixel and a third pixel, the sensors comprise a first sensor, a second sensor and a third sensor, the display area comprises a first area, a second area and a third area, and the readout circuit is electrically connected with the pixels in the sensing mode. The first pixel disposed in the first region emits light at a first brightness, the second pixel disposed in the second region emits light at a second brightness, and the readout circuit receives a readout signal from the first sensor disposed in the first region.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device capable of sensing blood pressure. Background Art

[0002] As the information society develops, the demand for electronic devices for displaying images increases in various forms. Electronic devices are applicable to various electronic devices such as smart phones, digital cameras, notebook computers, tablet PCs, navigation devices, and smart TVs. In the case of portable electronic devices such as smart phones and tablet PCs, various functions such as image capture, fingerprint recognition, and facial recognition are provided.

[0003] As the healthcare industry has recently received attention, methods for easily obtaining biological information about health have been developed. For example, attempts have been made to manufacture a portable blood pressure measuring device from a conventional oscillometric blood pressure measuring device.

[0004] However, the portable blood pressure measurement device requires its own independent light source, sensor, and display, and has the inconvenience of needing to be carried separately in addition to the portable smartphone or tablet PC. Summary of the invention

[0005] An object of the present invention is to provide an electronic device capable of sensing blood pressure.

[0006] An electronic device according to an embodiment of the present invention may include: a display panel including: pixels including a pixel driving circuit and a light-emitting element; and a sensor including a sensor driving circuit and a sensing element, wherein the display panel defines a display area and operates in a sensing mode; and a readout circuit electrically connected to the sensor, wherein the pixels include a first pixel, a second pixel and a third pixel, and the sensor includes a first sensor, a second sensor and a third sensor. The display area includes a first area, a second area adjacent to the first area and a third area surrounding the first area and the second area. In the sensing mode, the first pixel arranged in the first area emits a first light with a first brightness, the second pixel arranged in the second area emits a second light with a second brightness different from the first brightness, and the third pixel arranged in the third area does not emit light, and the readout circuit receives a readout signal from the first sensor arranged in the first area.

[0007] The sensor disposed in the display area may sense blood pressure in the sensing mode.

[0008] It may be that the first sensor is configured in the first area, and the third sensor is configured in the third area.

[0009] It may be that, in the sensing mode, the first pixel and the first sensor are turned on, the second pixel is turned on, the second sensor is turned off, and the third pixel and the third sensor are turned off.

[0010] It may be that the first brightness is lower than the second brightness.

[0011] It may be that the sensor driving circuit includes: a reset transistor, electrically connected to the sensing element, including a gate electrode receiving a reset control signal, a first electrode receiving a reset voltage, and a second electrode connected to a first sensing node; an amplification transistor, including: a first electrode receiving a sensor driving voltage, a second electrode connected to a second sensing node, and a gate electrode connected to the first sensing node; and an output transistor, including: a first electrode connected to the second sensing node, a second electrode connected to a readout line, and a gate electrode receiving an output control signal.

[0012] It may be that the readout circuit also includes: an amplifier circuit, which receives the transmission of the readout signal from the sensor drive circuit through the readout line and amplifies it; a sampling and holding unit, which samples and holds the signal provided from the amplifier circuit; and an analog-to-digital converter, which digitizes the analog signal provided from the sampling and holding unit, and the sampling and holding unit includes: a reset unit, including a first switch and a first capacitor; and a holding unit, including a second switch and a second capacitor.

[0013] It may be that the first region has a circular shape, and the second region has a ring shape and surrounds the first region.

[0014] It may be that the first region has a polygonal shape, and the second region surrounds the first region.

[0015] The second region may include a 2-1 region and a 2-2 region separated from the 2-1 region, and the first region may be arranged between the 2-1 region and the 2-2 region.

[0016] It may be that the second light includes: 2-1 light having a first wavelength; and 2-2 light having a second wavelength different from the first wavelength, the second region also includes: 2-3 region, arranged on the first region, emitting the 2-1 light in the 2-1 region and the 2-2 region, emitting the 2-2 light in the 2-3 region, the first region includes the 1-1 region and the 1-2 region, the 1-1 region receives light from the 2-1 region to the 2-3 region, and the 1-2 region receives light from the 2-1 region and the 2-2 region.

[0017] It may be that the first brightness gradually decreases along a first direction from a center of the first area.

[0018] It may be that the first light has a first wavelength, and the second light has a second wavelength different from the first wavelength.

[0019] It may be that the first wavelength is shorter than the second wavelength.

[0020] An electronic device according to an embodiment of the present invention may include: a display panel including: a plurality of pixels, each including a pixel driving circuit and a light-emitting element; a plurality of sensors, each including a sensor driving circuit and a sensing element; and a readout line, wherein the display panel defines a display area, the plurality of sensors are electrically connected to the readout circuit via one of the readout lines, the display area includes a first area, a second area adjacent to the first area, and a third area surrounding the first area and the second area, pixels among the plurality of pixels arranged in the first area emit light with a first brightness, pixels among the plurality of pixels arranged in the second area emit second light with a second brightness different from the first brightness, pixels among the plurality of pixels arranged in the third area do not emit light, and the readout circuit receives a readout signal from a sensor among the plurality of sensors arranged in the second area.

[0021] The plurality of sensors disposed in the display area may sense blood pressure.

[0022] It may be that the first brightness is lower than the second brightness.

[0023] It may be that the first region has a circular shape, and the second region has a ring shape and surrounds the first region.

[0024] It may be that the first region has a polygonal shape, and the second region surrounds the first region.

[0025] The second region may include a 2-1 region and a 2-2 region separated from the 2-1 region, and the first region may be arranged between the 2-1 region and the 2-2 region.

[0026] According to the above, the electronic device can easily sense blood pressure by making not only the light emitting area but also the light receiving area emit light for sensing. Therefore, an electronic device with improved reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a three-dimensional diagram of an electronic device according to an embodiment of the present invention.

[0028] Figure 2is a cross-sectional view of an electronic device according to an embodiment of the present invention.

[0029] Figure 3 is a block diagram of an electronic device according to an embodiment of the present invention.

[0030] Figure 4a is an equivalent circuit diagram of a pixel and a sensor according to an embodiment of the present invention.

[0031] Figure 4b is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0032] Figure 5 FIG. 1 is a diagram specifically showing a connection structure between a writing scanning line and a sensor of a display panel according to an embodiment of the present invention.

[0033] Figure 6 is an enlarged view showing an embodiment of the present invention Figure 3 Floor plan of the AA area.

[0034] Figure 7 is a block diagram showing first to fourth rows of sensors and a readout circuit.

[0035] Figure 8 is a circuit diagram showing in detail a first row of sensors and a readout circuit according to an embodiment of the present invention.

[0036] Fig. 9 is a graph showing the Figure 7 Waveform diagram of the read circuit signal and the write scan signal.

[0037] Fig.10 It is shown that according to the configuration Figure 6 A graph of a sensing signal voltage of brightness of pixels in a first area.

[0038] Figures 11a to 11d FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA region corresponds to the plan view of the area.

[0039] Figures 12a to 12e FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA region corresponds to the plan view of the area.

[0040] Fig.13 FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA region corresponds to the plan view of the area.

[0041] Fig.14 FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA region corresponds to the plan view of the area.

[0042] (Explanation of Reference Numerals)

[0043] DD: electronic device DP: display panel

[0044] PX: Pixel FX: Sensor

[0045] PDC: Pixel drive circuit ED: Light emitting element

[0046] O_SD: sensor drive circuit OPD: sensing element DETAILED DESCRIPTION

[0047] In this specification, when any constituent element (or region, layer, part, etc.) is mentioned as being "on" other constituent elements, "connected" or "combined with" other constituent elements, it means that it can be directly configured / connected / combined with other constituent elements or a third constituent element can be configured between them.

[0048] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations of more than one possible definition of the associated structure.

[0049] The terms "first", "second", etc. may be used to describe various constituent elements, but the constituent elements may not be limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly the second constituent element may also be named as the first constituent element. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0050] In addition, terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between the structures shown in the drawings. The above terms are relative concepts and are explained based on the directions shown in the drawings.

[0051] The terms "including" or "having" etc. should be understood as specifying the presence of the features, numbers, steps, tasks, constituent elements, accessories or combinations thereof recorded in the specification, and do not preclude the existence or additional possibility of one or more other features or numbers, steps, tasks, constituent elements, accessories or combinations thereof.

[0052] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms that may be the same as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and not interpreted as highly idealized or overly formal meanings, unless explicitly defined herein.

[0053] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of an electronic device DD according to an embodiment of the present invention. Figure 2 is a cross-sectional view of an electronic device DD according to an embodiment of the present invention.

[0055] Reference Figure 1 as well as Figure 2 The electronic device DD may be a mobile phone, a tablet, a car, a navigation system, a game console, or a wearable device, but is not limited thereto. Figure 1 It is exemplarily shown in FIG. 1 that the electronic device DD is a mobile phone.

[0056] In addition, Figure 1 exemplarily shows a rigid type electronic device DD in the form of a bar, but is not particularly limited thereto. For example, the electronic device DD may be a foldable, rollable, or slidable type electronic device DD.

[0057] The upper surface of the electronic device DD may be defined as a display surface IS, and the display surface IS may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated in the electronic device DD may be provided to a user through the display surface IS.

[0058] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the meaning of "when viewed on a plane" may refer to a state viewed in the third direction DR3. That is, the plane may be parallel to a surface defined by the first direction DR1 and the second direction DR2.

[0059] The display surface IS may be divided into a transmissive area TA and a frame area BZA. The transmissive area TA may be an area where an image IM is displayed. A user recognizes the image IM through the transmissive area TA. In the present embodiment, the transmissive area TA is shown as a quadrilateral with circular vertices. However, this is shown by way of example, and the transmissive area TA may have various shapes such as a rectangle, a circle, or a square, and is not limited to any one embodiment.

[0060] The frame area BZA is adjacent to the transmission area TA. The frame area BZA may have a predetermined color. The frame area BZA may surround the transmission area TA. Thus, the shape of the transmission area TA may be substantially defined by the frame area BZA. However, this is shown as an example, and the frame area BZA may also be configured adjacent to only one side of the transmission area TA, or may be omitted.

[0061] The electronic device DD can sense external input applied from the outside. The external input may include various forms of input provided from the outside of the electronic device DD. For example, the external input may include contact through a part of the user's body such as the hand US_F, and external input applied close to or adjacent to the electronic device DD at a predetermined distance (e.g., hovering). In addition, the external input may have various forms such as force, pressure, temperature, light, etc. The external input may also be provided by a separate device, such as an active pen or a digital pen. In addition, the electronic device DD can sense the user's biological information provided from the outside, or measure the surrounding brightness.

[0062] The appearance of the electronic device DD can be formed by the window WM and the housing EDC. For example, the window WM and the housing EDC can be combined with each other, and other components of the electronic device DD, such as the display module DM, can be accommodated therein.

[0063] The front of the window WM defines the display surface IS of the electronic device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multi-layer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded by an adhesive, or include a glass substrate and a plastic film bonded by an adhesive.

[0064] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the structure of the electronic device DD accommodated in the internal space from external impacts. Although not shown in the figure, a battery module or the like that supplies power required for the overall operation of the electronic device DD may be configured between the display module DM and the housing EDC.

[0065] Reference Figure 2 The electronic device DD may include a display module DM, an adhesive layer AL, and a window WM. The display module DM may include a display panel DP and an upper functional layer UFL.

[0066] The display panel DP may be a display panel that substantially generates an image IM (see Figure 1) structure. The display panel DP may be a light-emitting display panel, for example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro LED display panel or a nano LED display panel. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0067] The display panel DP includes a base layer BL, a pixel layer PXL, and an encapsulation layer TFE. The display panel DP according to the present invention may be a flexible display panel or a rigid display panel. For example, the display panel DP may be a foldable display panel folded with a folding axis as a reference, a rollable display panel with at least a portion wound with a rotation axis as a reference, or a slidable display panel.

[0068] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0069] The pixel layer PXL is disposed on the base layer BL. The pixel layer PXL may include a circuit layer DP_CL and a device layer DP_ED.

[0070] The circuit layer DP_CL is disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film.

[0071] The circuit element may include a plurality of pixels PX (refer to Figure 3 ) in each of the pixel drive circuits PDC (refer to Figure 4a ) and includes a plurality of sensors FX (refer to Figure 3 ) in each of the sensor drive circuits O_SD (refer to Figure 4a ) etc. The circuit layer DP_CL may also include a circuit connected to the pixel driving circuit PDC (refer to Figure 4a ) and / or sensor drive circuit O_SD (refer to Figure 4a ) signal line.

[0072] The element layer DP_ED may include a light emitting element ED included in each of the plurality of pixels PX (refer to Figure 4a ) and a light sensing element OPD (refer to Figure 4aAs an example of the present invention, the optical sensing element OPD may be a photodiode, for example, an organic photodiode. The optical sensing element OPD may be a sensor that senses light reflected by a user's fingerprint or reacts to light. Figure 4b The following will be described in detail.

[0073] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may contain an inorganic substance and protect the element layer DP_ED from moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not particularly limited thereto. The organic layer may contain an organic substance and protect the element layer DP_ED from foreign matter such as dust particles.

[0074] The upper functional layer UFL may be disposed on the display panel DP. The upper functional layer UFL may be formed on the display panel DP through a continuous process, but the present invention is not limited thereto.

[0075] The upper functional layer UFL may include a sensor layer for detecting coordinates input from the outside and an anti-reflection layer for reducing the reflectivity of external light incident from the outside. The sensor layer may be configured on the display panel DP, and the anti-reflection layer may be configured on the sensor layer. However, it is not limited thereto, and the upper functional layer UFL may also include only the sensor layer, or only the anti-reflection layer.

[0076] The anti-reflection layer may include a color filter, a black matrix, and a planarization layer. The color filter may have a predetermined arrangement. For example, the color filter may be arranged in consideration of the luminous color of the pixels included in the display panel DP. In other embodiments, the anti-reflection layer may include a black matrix and a reflection adjustment layer. The reflection adjustment layer may selectively absorb light of a portion of the wavelength band of light reflected from the display panel DP and / or the inside of the electronic device or light incident from the outside of the display panel DP and / or the electronic device. In another embodiment, the anti-reflection layer may be a polarizing film.

[0077] The electronic device DD according to an embodiment of the present invention may further include an adhesive layer AL. The window WM may be attached to the upper functional layer UFL through the adhesive layer AL. The adhesive layer AL may include an optically clear adhesive (Optical Clear Adhesive), an optically clear adhesive resin (Optically Clear Adhesive Resin) or a pressure sensitive adhesive (PSA, Pressure Sensitive Adhesive).

[0078] Figure 3is a block diagram of an electronic device DD according to an embodiment of the present invention.

[0079] Reference Figure 3 The electronic device DD includes a display panel DP, a panel driver (or referred to as a driving circuit) and a driving controller 100. As an example of the present invention, the panel driver includes a data driver 200, a scan driver 300, a light emitting driver 350, a voltage generator 400 and a readout circuit 500.

[0080] The display panel DP may include a transmissive area TA (refer to Figure 1 ) corresponding to the display area DA and the frame area BZA (refer to Figure 1 ) corresponds to the non-display area NDA.

[0081] The display panel DP may include a plurality of pixels PX arranged in the display area DA and a plurality of sensors FX arranged in the display area DA. As an example of the present invention, each of the plurality of sensors FX may be arranged between two pixels PX adjacent to each other. The plurality of pixels PX and the plurality of sensors FX may be arranged alternately in the first and second directions DR1 and DR2. However, the present invention is not limited thereto. That is, two or more pixels PX may be arranged between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be arranged between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0082] The display panel DP further includes initialization scan lines SIL1-SILn, compensation scan lines SCL1-SCLn, write scan lines SWL1-SWLn, black scan lines SBL1-SBLn, emission control lines EML1-EMLn, data lines DL1-DLm, and readout lines RL1-RLh.

[0083] The initialization scan lines SIL1-SILn, the compensation scan lines SCL1-SCLn, the write scan lines SWL1-SWLn, the black scan lines SBL1-SBLn, and the emission control lines EML1-EMLn extend in the second direction DR2. The initialization scan lines SIL1-SILn, the compensation scan lines SCL1-SCLn, the write scan lines SWL1-SWLn, the black scan lines SBL1-SBLn, and the emission control lines EML1-EMLn are arranged to be spaced apart from each other in the first direction DR1. The data lines DL1-DLm and the readout lines RL1-RLh extend in the first direction DR1 and are spaced apart from each other in the second direction DR2.

[0084] The plurality of pixels PX are electrically connected to the initialization scan lines SIL1-SILn, the compensation scan lines SCL1-SCLn, the write scan lines SWL1-SWLn, the black scan lines SBL1-SBLn, the emission control lines EML1-EMLn, and the data lines DL1-DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, the number of scan lines connected to each pixel PX is not limited thereto and may be changed.

[0085] The plurality of sensors FX are electrically connected to the readout lines RL1-RLh, respectively. One sensor FX may be electrically connected to one scan line, for example, one write scan line among the write scan lines SWL1-SWLn. However, the present invention is not limited thereto. The number of scan lines connected to each sensor FX may vary.

[0086] As an example of the present invention, the number of readout lines RL1-RLh may correspond to 1 / 2 of the number of data lines DL1-DLm. However, the present invention is not limited thereto. Alternatively, the number of readout lines RL1-RLh may correspond to 1 / 4 or 1 / 8 of the number of data lines DL1-DLm.

[0087] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data signal DATA by converting the data format of the image signal RGB into an image data signal matching the interface specification of the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0088] In addition, the driving controller 100 may receive a mode control signal MCS. The mode control signal MCS may be provided by a processor. However, this is only an example, and the mode control signal MCS provided by the processor may also be provided to the readout circuit 500.

[0089] The driving controller 100 may operate in a first mode for sensing fingerprints or a second mode for sensing blood pressure according to information included in the mode control signal MCS. The second mode for sensing blood pressure may be referred to as a sensing mode. That is, the pixel PX and the sensor FX may be controlled by the driving controller 100 to operate in a first mode for sensing fingerprints or a second mode for sensing blood pressure.

[0090] The data driver 200 receives the third control signal DCS and the image data signal DATA from the driving controller 100. The data driver 200 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1-DLm described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0091] The scan driver 300 receives a first control signal SCS from the drive controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS. For example, the scan driver 300 outputs an initialization scan signal to the initialization scan lines SIL1-SILn in response to the first control signal SCS, and outputs a compensation scan signal to the compensation scan lines SCL1-SCLn. In addition, the scan driver 300 may output a write scan signal to the write scan lines SWL1-SWLn in response to the first control signal SCS, and output a black scan signal to the black scan lines SBL1-SBLn.

[0092] The scan driver 300 may be disposed in the non-display area NDA of the display panel DP, but is not particularly limited thereto. For example, at least a portion of the scan driver 300 may also be disposed in the display area DA.

[0093] The light emitting driver 350 may be disposed in the non-display area NDA of the display panel DP. The light emitting driver 350 receives the second control signal ECS from the driving controller 100. The light emitting driver 350 may output the light emitting control signal to the light emitting control lines EML1-EMLn in response to the second control signal ECS. Alternatively, the scan driver 300 may be connected to the light emitting control lines EML1-EMLn. In this case, the light emitting driver 350 may be omitted, and the scan driver 300 outputs the light emitting control signal to the light emitting control lines EML1-EMLn.

[0094] The voltage generator 400 generates voltages required for the operation of the display panel DP. In one embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, and a reset voltage Vrst.

[0095] The readout circuit 500 receives the fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive the sensing signal from the sensing lines RL1-RLh in response to the fourth control signal RCS. The readout circuit 500 may process the sensing signal received from the sensing lines RL1-RLh and provide the processed sensing signal S_FS to the driving controller 100.

[0096] The readout circuit 500 can provide a reset control signal RST to the sensor FX via a reset control line RCL. More specifically, the reset control signal RST is provided to a reset transistor ST1 (see Figure 4a ) and reset transistor ST1 (refer to Figure 4a ) is turned on.

[0097] Figure 4ais an equivalent circuit diagram of a pixel PXij and a sensor FXdj according to an embodiment of the present invention.

[0098] exist Figure 4a A plurality of pixels PX (see Figure 3 ) is an equivalent circuit diagram of a pixel PXij in FIG. Each of the plurality of pixels PX has the same circuit structure, so the circuit structure of the pixel PXij is described below, and the detailed description of the remaining pixels PX is omitted. Figure 4a By way of example Figure 3 The equivalent circuit diagram of one sensor FXdj among the plurality of sensors FX is shown. Each of the plurality of sensors FX has the same circuit structure, and therefore, the circuit structure of the sensor FXdj will be described, and the detailed description of the remaining sensors FX will be omitted.

[0099] Reference Figure 3 as well as Figure 4a The pixel PXij is electrically connected to the i-th data line DLi among the data lines DL1-DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1-SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1-SCLn, the j-th write scan line SWLj among the write scan lines SWL1-SWLn, the j-th black scan line SBLj among the black scan lines SBL1-SCLn, and the j-th emission control line EMLj among the emission control lines EML1-EMLn.

[0100] The pixel PXij includes a light emitting element ED and a pixel driving circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto.

[0101] The pixel driving circuit PDC includes first to fifth transistors T1, T2, T3, T4, T5, first and second light emission control transistors ET1, ET2, and a capacitor Cst.

[0102] At least one of the first to fifth transistors T1, T2, T3, T4, T5, and the first and second light emission control transistors ET1 and ET2 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to fifth transistors T1, T2, T3, T4, T5, and the first and second light emission control transistors ET1 and ET2 may be a transistor having an oxide semiconductor layer. For example, the third and fourth transistors T3 and T4 may be oxide semiconductor transistors, and the first, second, and fifth transistors T1, T2, T5 and the first and second light emission control transistors ET1 and ET2 may be LTPS transistors.

[0103] Specifically, in the case of the first transistor T1 that directly affects the brightness of the electronic device DD, it can be configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby realizing a high-resolution display device. On the other hand, oxide semiconductors have high carrier mobility and low leakage current, so even if the driving time is long, the voltage drop is not large. That is, when driven at a low frequency, the color change of the image according to the voltage drop is not large, so low-frequency driving is possible. In this way, in the case of oxide semiconductors, there is an advantage of small leakage current, so at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be adopted as an oxide semiconductor to reduce power consumption while preventing leakage current that can flow to the gate electrode.

[0104] A portion of the first to fifth transistors T1, T2, T3, T4, T5, and the first and second light emission control transistors ET1 and ET2 may be P-type transistors, and the rest may be N-type transistors. For example, the first, second, and fifth transistors T1, T2, T5, and the first and second light emission control transistors ET1 and ET2 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors.

[0105] The structure of the pixel driving circuit PDC according to the present invention is not limited to Figure 4a The embodiment shown. Figure 4a The pixel driving circuit PDC shown is only an example, and the structure of the pixel driving circuit PDC can be modified. For example, the first to fifth transistors T1, T2, T3, T4, T5, the first and second light emitting control transistors ET1, ET2 can all be P-type transistors or N-type transistors.

[0106] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can respectively transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWSj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have a voltage level corresponding to the image signal RGB input to the electronic device DD.

[0107] The first and second driving voltage lines VL1 and VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 can transmit the first initialization voltage VINT1 and the second initialization voltage VINT2 to the pixel PXij, respectively.

[0108] The first transistor T1 is electrically connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via the first emission control transistor ET1, and a first electrode connected to the anode AE ​​of the light emitting element ED via the second emission control transistor ET2 (see Figure 4b ) and a third electrode (e.g., a gate electrode) connected to one end of the capacitor Cst (e.g., the first node N1). The first transistor T1 can receive the transmission of the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2 and supply the driving current Id to the light emitting element ED.

[0109] The second transistor T2 is electrically connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 can be turned on according to the write scan signal SWSj transmitted through the j-th write scan line SWLj to transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0110] The third transistor T3 is electrically connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 can be turned on according to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and the third electrode and the second electrode of the first transistor T1 are connected to each other to make the first transistor T1 diode-connected.

[0111] The fourth transistor T4 is electrically connected between the first initialization voltage line VL3 to which the first initialization voltage VINT1 is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 transmitting the first initialization voltage VINT1, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line SILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal SIj transmitted through the j-th initialization scan line SILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT1 to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0112] The first light emission control transistor ET1 includes a first electrode connected to the first driving voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a third electrode (eg, a gate electrode) connected to the j-th light emission control line EMLj.

[0113] The second light emission control transistor ET2 includes a first electrode connected to the second electrode of the first transistor T1, an anode AE ​​connected to the light emitting element ED (see Figure 4b ) and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0114] The first and second emission control transistors ET1 and ET2 are simultaneously turned on according to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied by the turned-on first emission control transistor ET1 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED.

[0115] The fifth transistor T5 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VINT2, a second electrode connected to a second electrode of the second light emission control transistor ET2, and a third electrode (e.g., a gate electrode) connected to the black scan line SBLj. The second initialization voltage VINT2 may have a voltage level lower than or equal to the first initialization voltage VINT1.

[0116] As described above, one end of the capacitor Cst is connected to the third electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. Figure 4b ) may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0117] The sensor FX is electrically connected to the d-th readout line RLd among the readout lines RL1 to RLh, the j-th write scanning line SWLj (or referred to as an output control line), and the reset control line RCL.

[0118] The sensor FX includes a light sensing element OPD (or referred to as a sensing element) and a sensor driving circuit O_SD.

[0119] The light sensing element OPD may be a photodiode. As an example of the present invention, the light sensing element OPD may be an organic photodiode including an organic substance as a photoelectric conversion layer. The anode AE1 (refer to Figure 4b ) is connected to the first sensing node SN1, the cathode CE of the light sensing element OPD (refer to Figure 4b ) is connected to a second driving voltage line VL2 that transmits a second driving voltage ELVSS. Figure 4a 2 shows that the sensor FXdj includes one light sensing element OPD, but the invention is not particularly limited thereto. For example, the sensor FX may include z light sensing elements connected in parallel to each other. z may be an integer greater than 2.

[0120] The sensor driving circuit O_SD includes three transistors ST1, ST2, and ST3. The three transistors ST1, ST2, and ST3 may be a reset transistor ST1, an amplifier transistor ST2, and an output transistor ST3, respectively. At least one of the reset transistor ST1, the amplifier transistor ST2, and the output transistor ST3 may be an oxide semiconductor transistor. As an example of the present invention, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifier transistor ST2 and the output transistor ST3 may be LTPS transistors. However, it is not limited thereto, and at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifier transistor ST2 may be an LTPS transistor.

[0121] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and some may be N-type transistors. As an example of the present invention, the amplifying transistor ST2 and the output transistor ST3 may be P-type transistors, and the reset transistor ST1 may be an N-type transistor. However, it is not limited thereto, and the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors, or all be P-type transistors.

[0122] The circuit structure of the sensor driving circuit O_SD according to the present invention is not limited to Figure 4a . Figure 4a The sensor driving circuit O_SD shown is only an example, and the structure of the sensor driving circuit O_SD may be modified.

[0123] The reset transistor ST1 includes a first electrode connected to the third initialization voltage line VL5 and receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal RST. The reset transistor ST1 can reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal RST. The reset control signal RST can be a signal provided by the reset control line RCL.

[0124] The amplifier transistor ST2 includes a first electrode for receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 can be turned on according to the potential of the first sensing node SN1 and apply the sensing drive voltage SLVD to the second sensing node SN2. As an example of the present invention, the sensing drive voltage SLVD can be one of the first driving voltage ELVDD, the first and second initialization voltages VINT1, and VINT2. When the sensing drive voltage SLVD is the first driving voltage ELVDD, the first electrode of the amplifier transistor ST2 can be electrically connected to the first driving voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage VINT1, the first electrode of the amplifier transistor ST2 can be electrically connected to the first initialization voltage line VL3, and when the sensing drive voltage SLVD is the second initialization voltage VINT2, the first electrode of the amplifier transistor ST2 can be electrically connected to the second initialization voltage line VL4.

[0125] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the d-th readout line RLd, and a third electrode receiving an output control signal. The output transistor ST3 can transmit the sensing signal FSd to the d-th readout line RLd in response to the output control signal. The output control signal can be the j-th write scan signal SWSj (or referred to as the j-th output control signal) supplied through the j-th write scan line SWLj. That is, the output transistor ST3 can receive the j-th write scan signal SWSj supplied from the j-th write scan line SWLj as the output control signal.

[0126] The reset period can be defined as an activation interval (i.e., a high level period) of the reset control line RCL. If a high level reset control signal RST is supplied through the reset control line RCL, the reset transistor ST1 is turned on. Alternatively, when the reset transistor ST1 is composed of a PMOS transistor, a low level reset control signal RST can be supplied to the reset control line RCL during the reset period. During the reset period, the first sensing node SN1 can be reset to a potential corresponding to the reset voltage Vrst. As an example of the present invention, the reset voltage Vrst can have a voltage level lower than the second drive voltage ELVSS.

[0127] The light sensing element OPD of the sensor FX can be exposed to light during the light emitting period of the light emitting element ED. The light emitting period can be referred to as the light receiving period EIT of the sensor FX (refer to Fig. 9). The voltage of the first sensing node SN1 maintains the reset voltage Vrst in the reset period, and as the light sensing element OPD is exposed to light, the voltage of the first sensing node SN1 may gradually shift toward the second driving voltage ELVSS. The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current in proportion to the amount of charge of the first sensing node SN1 input to the third electrode.

[0128] In the output period, the j-th write scan signal SWSj of low level is supplied to the output transistor ST3 through the j-th write scan line SWLj. If the output transistor ST3 is turned on in response to the j-th write scan signal SWSj of low level, the sensing signal FSd corresponding to the current flowing through the amplifying transistor ST2 can be output to the d-th readout line RLd.

[0129] Figure 4b According to one embodiment of the present invention, Figure 3 A cross-sectional view of the display panel DP taken along line II'.

[0130] Reference Figure 4a as well as Figure 4b The display panel DP may include a base layer BL, a circuit layer DP_CL configured on the base layer BL, a device layer DP_ED, and a packaging layer TFE.

[0131] At least one inorganic layer is formed on the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. The multiple inorganic layers may constitute the barrier layers BR1, BR2 and / or the buffer layer BFL described later. The barrier layers BR1, BR2 and the buffer layer BFL may be selectively configured.

[0132] The barrier layers BR1 and BR2 prevent foreign matter from flowing in from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Each of these may be provided in plurality, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0133] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. A first back metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2. In one embodiment of the present invention, the first back metal layer BMC1 may also be omitted.

[0134] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL enhances the bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0135] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0136] Figure 4b Only a portion of the first semiconductor pattern configured on the buffer layer BFL is shown, and another portion of the first semiconductor pattern may be configured in other regions. The first semiconductor pattern may be arranged in a specific rule across pixels. The first semiconductor pattern may have different electrical properties depending on whether it is doped or not. The first semiconductor pattern may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. It may be that a P-type transistor includes a doped region doped with a P-type dopant, and an N-type transistor includes a doped region doped with an N-type dopant. The second region may be a non-doped region, or a region doped at a lower concentration than the first region.

[0137] The conductivity of the first region may be greater than that of the second region, and the first region may substantially function as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and yet another portion may be a connecting electrode or a connecting signal line.

[0138] The first electrode S1 , the channel portion A1 , and the second electrode D1 of the first transistor T1 are formed from the first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions to each other.

[0139] exist Figure 4b A portion of a connection signal line CSL formed from the first semiconductor pattern is shown. Although not shown separately, the connection signal line CSL may be connected to the fifth transistor T5 (refer to FIG. 1 ) on a plane. Figure 4a )'s second electrode.

[0140] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels and cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit layer DP_CL described later may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above substances, but is not limited thereto.

[0141] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a part of the metal pattern. The third electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may act as a mask in the process of doping the first semiconductor pattern. The third electrode G1 may include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0142] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the present embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0143] The upper electrode UE and the second back metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping therewith may define a capacitor Cst (refer to Figure 4a In one embodiment of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may function as a mask for forming the insulating pattern from the second insulating layer 20.

[0144] The second back metal layer BMC2 may be disposed corresponding to the oxide thin film transistor, for example, below the third transistor T3 . The second back metal layer BMC2 may receive application of a constant voltage or signal.

[0145] The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the upper electrode UE and the second back metal layer BMC2. The third insulating layer 30 may have a single layer or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0146] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions divided according to whether the metal oxide is reduced or not. The region where the metal oxide is reduced (hereinafter referred to as the "reduction region") has greater conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the "non-reduction region"). The reduction region substantially has the function of the source / drain or signal line of the transistor. The non-reduction region substantially corresponds to the active region (or semiconductor region, channel) of the transistor. In other words, a portion of the second semiconductor pattern may be the active region of the transistor, another portion may be the source / drain region of the transistor, and another portion may be the signal transmission region.

[0147] The first electrode S3, the channel portion A3 and the second electrode D3 of the third transistor T3 are formed from the second semiconductor pattern. The first electrode S3 and the second electrode D3 include metal reduced from the metal oxide semiconductor. The first electrode S3 and the second electrode D3 may extend from the channel portion A3 in opposite directions in cross section.

[0148] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap with the plurality of pixels and cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0149] The third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be a part of the metal pattern. The third electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. The third electrode G3 may serve as a mask in the process of doping the second semiconductor pattern. In one embodiment of the present invention, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0150] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0151] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be electrically connected to the connection signal line CSL through a first contact hole CH1 penetrating the first to fifth insulating layers 10, 20, 30, 40, and 50.

[0152] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include general polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof, but is not particularly limited thereto.

[0153] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be electrically connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0154] A first electrode layer is disposed on the circuit layer DP_CL. A pixel definition layer PDL is formed on the first electrode layer. The first electrode layer may include an anode AE ​​of the light emitting element ED and an anode AE1 of the light sensing element OPD. The anode AE ​​of the light emitting element ED and the anode AE1 of the light sensing element OPD are disposed on the seventh insulating layer 70. The anode AE ​​of the light emitting element ED may be connected to the second connection electrode CNE20 through a third contact hole CH3 penetrating the seventh insulating layer 70.

[0155] The pixel definition film PDL is provided with first and second film openings PDL-OP1 and PDL-OP2. The first film opening PDL-OP1 exposes at least a portion of the anode AE ​​of the light emitting element ED. The second film opening PDL-OP2 exposes at least a portion of the anode AE1 of the light sensing element OPD.

[0156] In one embodiment of the present invention, the pixel definition film PDL may further include a black substance. The pixel definition film PDL may further include a black organic dye / pigment such as carbon black or aniline black. The pixel definition film PDL may be formed by mixing a blue organic substance and a black organic substance. The pixel definition film PDL may further include a liquid-repellent organic substance.

[0157] like Figure 4bAs shown, the display panel DP may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. In this embodiment, the light emitting region PXA is defined corresponding to a portion of the anode AE ​​exposed through the first film opening PDL-OP1.

[0158] A light-emitting layer EL may be arranged on the anode AE ​​of the light-emitting element ED. The light-emitting layer EL may be arranged in an area corresponding to the first film opening PDL-OP1. The light-emitting layer EL may generate predetermined colored light. In this embodiment, a patterned light-emitting layer EL is exemplarily described, but one light-emitting layer may be arranged in common in a plurality of light-emitting areas. In this case, the light-emitting layer may also generate white light or blue light. In addition, the light-emitting layer may have a multilayer structure referred to as a tandem.

[0159] The light-emitting layer EL may include low molecular weight organic matter or high molecular weight organic matter as the light-emitting substance. In addition, the light-emitting layer EL may include quantum dot material as the light-emitting substance. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, IV-VI group compounds, IV group elements, IV group elements and combinations thereof.

[0160] The cathode CE is disposed on the light emitting layer EL. As an example of the present invention, the cathode CE may be disposed in the light emitting region PXA, the non-light emitting region NPXA, and the non-pixel region NPA. No pixel PX may be disposed in the non-pixel region NPA.

[0161] The circuit layer DP_CL may further include a sensor driving circuit O_SD (see Figure 4a ). For ease of explanation, a reset transistor ST1 in a sensor driving circuit O_SD is shown. A first electrode STS1, a channel portion STA1, and a second electrode STD1 of the reset transistor ST1 are formed from a second semiconductor pattern. The first electrode STS1 and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. The fourth insulating layer 40 is configured to cover the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. A third electrode STG1 of the reset transistor ST1 is configured on the fourth insulating layer 40. In the present embodiment, the third electrode STG1 may be a part of a metal pattern. The third electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1.

[0162] As an example of the present invention, the reset transistor ST1 can be configured on the same layer as the third transistor T3. That is, the first electrode STS1, the channel portion STA1 and the second electrode STD1 of the reset transistor ST1 can be formed by the same process as the first electrode S3, the channel portion A3 and the second electrode D3 of the third transistor T3. The third electrode STG1 of the reset transistor ST1 can be formed simultaneously by the same process as the third electrode G3 of the third transistor T3. Although not shown separately, the amplifying transistor ST2 (refer to Figure 4a ) and output transistor ST3 (refer to Figure 4a ) can be formed by the same process as the first electrode S1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 can be formed on the same layer by the same process, and no additional process is required for forming the reset transistor ST1, thereby improving process efficiency and reducing costs.

[0163] The element layer DP_ED may further include a light sensing element OPD. The light sensing element OPD may include an anode AE1, a photoelectric conversion layer RL, and a cathode CE. The anode AE1 of the light sensing element OPD may be configured on the same layer as the anode AE ​​of the light emitting element ED. That is, the anode AE1 may be configured on the circuit layer DP_CL and formed simultaneously with the anode AE ​​of the light emitting element ED through the same process.

[0164] The second film opening PDL-OP2 of the pixel defining film PDL exposes at least a portion of the anode AE1. The photoelectric conversion layer RL is disposed on the anode AE1 exposed by the second film opening PDL-OP2. The photoelectric conversion layer RL may include an organic light sensing material. The cathode CE may be disposed on the photoelectric conversion layer RL. Each of the anode AE1 and the cathode CE may receive an electrical signal. The anode AE1 and the cathode CE may receive different signals. Therefore, a predetermined electric field may be formed between the anode AE1 and the cathode CE. The photoelectric conversion layer RL generates an electrical signal corresponding to the light incident on the sensor.

[0165] The charges generated in the photoelectric conversion layer RL cause the electric field between the anode AE1 and the cathode CE to change. The amount of charges generated in the photoelectric conversion layer RL may be different depending on whether light is incident on the light sensing element OPD, the amount of light incident on the light sensing element OPD, and the intensity. Thus, the electric field formed between the anode AE1 and the cathode CE may be different. The light sensing element OPD according to the present invention may obtain fingerprint information or illumination information about the user through the change of the electric field between the anode AE1 and the cathode CE.

[0166] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers stacked alternately.

[0167] The encapsulation inorganic layer protects the light emitting element ED and the light sensing element OPD from moisture / oxygen, and the encapsulation organic layer protects the light emitting element ED and the light sensing element OPD from foreign matter such as dust particles. The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not particularly limited thereto. The encapsulation organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0168] Figure 5 FIG. 1 is a diagram specifically showing a connection structure between a writing scanning line and a sensor of a display panel according to an embodiment of the present invention.

[0169] Reference Figure 3 as well as Figure 5 , the display area DA alternately arranges red, green, and blue pixels PX and sensors FX in a matrix form. The sensor FX receives the supply of the write scan signal SWSj through one of the write scan lines SWL1-SWLn. For example, the sensors FX arranged in the 4k-3 to 4k rows (here, k is a natural number) are electrically connected to the 4k-3 to 4k write scan lines, respectively. The sensor FX may include a first row sensor FX1, a second row sensor FX2, a third row sensor FX3, and a fourth row sensor FX4.

[0170] In the following, for the sake of convenience, the 4k-3rd write scan line is referred to as the first write scan line SWL1, the 4k-2nd write scan line is referred to as the second write scan line SWL2, the 4k-1th write scan line is referred to as the third write scan line SWL3, and the 4kth write scan line is referred to as the fourth write scan line SWL4. In addition, the sensor FX electrically connected to the first write scan line SWL1 is referred to as a plurality of first row sensors FX1, the sensor FX electrically connected to the second write scan line SWL2 is referred to as a plurality of second row sensors FX2, the sensor FX electrically connected to the third write scan line SWL3 is referred to as a plurality of third row sensors FX3, and the sensor FX electrically connected to the fourth write scan line SWL4 is referred to as a plurality of fourth row sensors FX4.

[0171] Readout lines RL1-RLh (refer to Figure 4a) may include a first readout line RL1, a second readout line RL2, a third readout line RL3, and a fourth readout line RL4. For example, the first to fourth row sensors FX1-FX4 arranged in the first column may be connected to the first readout line RL1. The first to fourth row sensors FX1-FX4 arranged in the second column may be connected to the second readout line RL2. The first to fourth row sensors FX1-FX4 arranged in the third column may be connected to the third readout line RL3. The first to fourth row sensors FX1-FX4 arranged in the fourth column may be connected to the fourth readout line RL4.

[0172] The pixels PX and the sensors FX are arranged in a matrix. The first row of sensors FX1 is electrically connected to the first write scan line SWL1, the second row of sensors FX2 is electrically connected to the second write scan line SWL2, the third row of sensors FX3 is electrically connected to the third write scan line SWL3, and the fourth row of sensors FX4 is electrically connected to the fourth write scan line SWL4. The first to fourth row sensors FX1-FX4 may be arranged repeatedly.

[0173] Figure 6 is an enlarged view showing an embodiment of the present invention Figure 3 Floor plan of the AA area.

[0174] Reference Figure 2 , Figure 3 , Figure 4a as well as Figure 6 , the display area DA may include a first area XA1, a second area XA2, and a third area XA3. The first area XA1 may be located at the center of the AA area. For example, the first area XA1 may have a circular shape. The second area XA2 may be adjacent to the first area XA1 and surround the first area XA1. For example, the second area XA2 may have a ring shape. The third area XA3 may surround the first area XA1 and the second area XA2.

[0175] exist Figure 6 exemplarily shows that the second area XA2 surrounds the first area XA1, but as the shape of the first area XA1 changes, the second area XA2 may not surround the first area XA1. For example, a detailed description of this will be described later.

[0176] The pixel PX may include a first pixel APX1, a second pixel APX2, and a third pixel APX3. The sensor FX may include a first sensor AFX1, a second sensor AFX2, and a third sensor AFX3. The first pixel APX1 and the first sensor AFX1 may be configured in a first area XA1. The second pixel APX2 and the second sensor AFX2 may be configured in a second area XA2. The third pixel APX3 and the third sensor AFX3 may be configured in a third area XA3.

[0177] The driving controller 100 can make the display panel DP operate in the sensing mode through the mode control signal MCS. In the sensing mode, the first pixel APX1 and the first sensor AFX1 can be turned on. The light-emitting element ED of the first pixel APX1 can emit the first light at the first brightness. It can be that the second pixel APX2 is turned on and the second sensor AFX2 is turned off. The light-emitting element ED of the second pixel APX2 can emit the second light at the second brightness. The first brightness can be lower than the second brightness. For example, the first brightness can be 150 to 200 grayscales, and the second brightness can be 255 grayscales, but is not limited to this. The third pixel APX3 and the third sensor AFX3 can be turned off. The light-emitting element ED of the third pixel APX3 may not emit light.

[0178] In the sensing mode, the user's hand US_F (refer to Figure 1 ) can be in contact with the form WM. The second light can be in contact with the user's hand US_F (refer to Figure 1 ). The reflected second light can be sensed by the first sensor AFX1. The first light can be reflected at the upper functional layer UFL. The reflected first light can be sensed by the first sensor AFX1. That is, the first sensor AFX1 can sense the first light and the second light to sense the blood pressure. The first sensor AFX1 can send a readout signal FSd containing information of the sensed blood pressure to the readout circuit 500.

[0179] According to the present invention, the first sensor AFX1 can sense not only the second light of the second pixel APX2 for sensing the blood vessel required for blood pressure sensing, but also the first light of the first pixel APX1. Due to this, the absolute amount of the sensed light can be increased. The DC component of the readout signal FSd received by the first sensor AFX1 can be increased. Therefore, an electronic device DD (refer to Figure 1 ).

[0180] Figure 7 is a block diagram showing first to fourth rows of sensors and a readout circuit. Figure 8 is a circuit diagram showing in detail a first row of sensors and a readout circuit according to an embodiment of the present invention.

[0181] Reference Figure 3 , Figure 7 as well as Figure 8 The readout circuit 500 can read out the Figure 4a ) is connected to sensor FX.

[0182] The sensor FX may include a first row of sensors FX1, a second row of sensors FX2, a third row of sensors FX3, and a fourth row of sensors FX4. For example, the first to fourth row sensors FX1-FX4 may be arranged in the first area XA1 (refer to Figure 6 ) of the first sensor AFX1 (refer to Figure 6 )correspond.

[0183] For example, the readout circuit 500 may be connected to the first to fourth row sensors FX1-FX4 through a first readout line RL1. The first to fourth row sensors FX1-FX4 may transmit readout signals FS1-FS4 to the readout circuit 500 through the first readout line RL1. Figure 7 The readout lines RL1-RLh are exemplarily described in Figure 4a ) in the first readout line RL1, but can also be applied to other readout lines RL1-RLh (refer to Figure 4a ).

[0184] The readout circuit 500 may include an amplification circuit 510 , a sample and hold section 520 , and an analog-to-digital converter 530 .

[0185] The amplifier circuit 510 may include an operational amplifier 511, a capacitor Cf, and a switch SW. The operational amplifier 511 may include an inverting input terminal -, a non-inverting input terminal +, and an output terminal Out. The inverting input terminal may be connected to the first readout line RL1, the non-inverting input terminal may be input with a reference voltage VREF, and the output terminal Out may be connected to the sampling and holding unit 520.

[0186] The capacitor Cf may be connected between the inverting input terminal - and the output terminal Out, and the switch SW may be connected in parallel to the capacitor Cf. The gain of the operational amplifier 511 may correspond to the capacitance of the capacitor Cf. The capacitor Cf may accumulate a voltage applied through the first readout line RL1 during a frame period. The applied voltage may be a noise signal voltage or a sensing signal voltage VC (refer to Fig. 9 ). The switch SW plays a role in controlling the operation of the capacitor Cf. For example, when the switch SW is turned on, the capacitor Cf can be reset.

[0187] The sampling and holding section 520 may include a holding section 521 and a reset section 522. The holding section 521 may include a first switch SW1 and a first capacitor Csh1. The reset section 522 may include a second switch SW2 and a second capacitor Csh2. The sampling and holding section 520 may sample the output voltage Vout of the operational amplifier 511 at the first capacitor Csh1 and the second capacitor Csh2 and store the sampled output voltage.

[0188] The first capacitor Csh1 can be connected to the output terminal Out of the operational amplifier 511 through the first switch SW1. If the first switch SW1 is turned on, the output voltage Vout is charged to the first capacitor Csh1. For example, the first switch SW1 can be turned on at the timing when the readout signal FS1-FS4 flows through the first readout line RL1. Therefore, the output voltage Vout charged to the first capacitor Csh1 can be the noise signal voltage and the sensing signal voltage VC (refer to Fig. 9 ).

[0189] The second capacitor Csh2 can be connected to the output terminal Out of the operational amplifier 511 through the second switch SW2. If the second switch SW2 is turned on, the output voltage Vout is charged to the second capacitor Csh2. For example, the second switch SW2 can be turned on at a timing when the readout signal FS1-FS4 does not flow through the first readout line RL1. Therefore, the output voltage Vout charged to the second capacitor Csh2 can be a noise signal voltage.

[0190] The analog-to-digital converter 530 may convert the difference between the voltage provided from the holding unit 521 and the voltage provided from the reset unit 522 into a digital value or a digital code. The voltage stored in the first capacitor Csh1 and the second capacitor Csh2 may be differentiated to obtain the sense signal voltage VC (refer to Fig. 9 ) is converted into light sensing data as digital data and outputted. That is, the analog-to-digital converter 530 can generate a digital value or a digital code according to the sensing voltage from which noise is removed.

[0191] Fig. 9 is a graph showing the sensing period Figure 7 Waveform diagram of the read circuit signal and the write scan signal.

[0192] Reference Figures 6 to 9 , shows the operation process of the switch SW, the first switch SW1, and the second switch SW2 of the readout circuit 500 according to the sensing period SP and the operation process of the write scan signal SWSj of the first to fourth row sensors FX1-FX4. The write scan signal SWSj can be sequentially provided to the first to fourth row sensors FX1-FX4 as the first to fourth write scan signals SWS1-SWS4.

[0193] Each of the first to fourth row sensors FX1 - FX4 may receive the reset control signal RST to reset the potential of the first sensing node SN1 .

[0194] Afterwards, each of the first to fourth row sensors FX1 - FX4 may receive light from the first pixel APX1 and the second pixel APX2 during the light receiving period EIT. For example, the light receiving period EIT may be 8.3 ms (millisecond).

[0195] According to the present invention, each of the first to fourth row sensors FX1-FX4 can sense not only the second light of the second pixel APX2 but also the first light of the first pixel APX1 during the light receiving period EIT. Due to this, the absolute amount of sensed light can be increased. The voltage of the first sensing node SN1 can be shifted approximately toward the second drive voltage ELVSS. For example, the second drive voltage ELVSS can be referred to as a ground voltage. The DC component of the readout signal FSd received by the first sensor AFX1 can be increased. Therefore, an electronic device DD (refer to Figure 1 ).

[0196] The readout circuit 500 may receive the input of the feedback reset signal IRST, the first sampling signal SHS, the second sampling signal SHR, and the first to fourth readout signals FS1-FS4 during the sensing period SP. The readout circuit 500 may sense the sensing signal voltage VC according to the first to fourth readout signals FS1-FS4 during the sensing period SP.

[0197] The sensing period SP may include a first read period st1 in which the capacitor Cf is reset according to a feedback reset signal IRST, a second read period st2 in which a voltage is stored in the second capacitor Csh2 according to a second sampling signal SHR, fifth to eighth read periods st5 to st8 in which the readout signals FS1 to FS4 generated according to light exposure are output to the readout circuit 500 based on the write scan signal SWSj, a third read period st3 in which a sensing signal voltage VC according to the readout signals FS1 to FS4 is stored in the first capacitor Csh1 according to the first sampling signal SHS, and a fourth read period st4 in which the first sampling signal SHS has a cut-off voltage.

[0198] The feedback reset signal IRST may control the switch SW. For example, the feedback reset signal IRST has a first horizontal period HT1. That is, the interval between the pulses of the feedback reset signal IRST may have a first horizontal period HT1. The feedback reset signal IRST may have a turn-on signal during the first reading period st1 in the first horizontal period HT1. Thus, the feedback reset signal IRST may repeatedly turn on the signal in each first horizontal period HT1.

[0199] The feedback reset signal IRST may include a first reading period st1 in which the switch SW is turned on. During the first reading period st1, the switch SW is turned on. Thus, the two ends of the capacitor Cf may be connected to reset the capacitor Cf. In the first reading period st1, the output voltage Vout of the operational amplifier 511 may be the same as the initial voltage VREF of the inverting input terminal -.

[0200] The second sampling signal SHR may control the second switch SW2. For example, the second sampling signal SHR has a first horizontal period HT1. That is, the interval between the pulses of the second sampling signal SHR may have the first horizontal period HT1. That is, the feedback reset signal IRST and the second sampling signal SHR may have the same period. The second sampling signal SHR may have a turn-on signal during the second reading period st2 in the first horizontal period HT1. Thus, the second sampling signal SHR may repeatedly turn on the signal in each first horizontal period HT1.

[0201] The second sampling signal SHR may include a second read period st2 in which the second switch SW2 is turned on. During the second read period st2, the switch SW is turned on, and the second switch SW2 is turned on. Thus, the output terminal Out of the operational amplifier 511 may be electrically connected to the second capacitor Csh2. The second read period st2 is before the second transistor T2 is turned on, so no valid signal can be output through the first readout line RL1. Thus, the noise signal voltage may be stored in the second capacitor Csh2. That is, the voltage of the initial voltage VREF plus the noise signal voltage may be stored in the second capacitor Csh2.

[0202] During the fifth reading period st5, the first writing scanning signal SWS1 having the gate-on voltage Von is supplied to the first writing scanning line SWL1. During the fifth reading period st5, the output transistor ST3 of the first row sensor FX1 is turned on by the first writing scanning signal SWS1. Due to this, it can be that the amplifying transistor ST2 is connected to the first readout line RL1, and the first readout signal FS1 proportional to the voltage charged in the first sensing node SN1 is output to the readout circuit 500 through the first readout line RL1. The first readout signal FS1 can be stored as the first sensing signal voltage V1 in the output terminal Out of the operational amplifier 511. That is, the first reading signal FS1 sensed by the first row sensor FX1 can be stored as the first sensing signal voltage V1 in the amplifying circuit 510.

[0203] During the sixth reading period st6, the second writing scanning signal SWS2 having the gate-on voltage Von is supplied to the second writing scanning line SWL2. During the sixth reading period st6, the output transistor ST3 of the second row sensor FX2 is turned on by the second writing scanning signal SWS2. Due to this, it can be that the amplifying transistor ST2 is connected to the first sensing line RL1, and the second sensing signal FS2 proportional to the voltage charged in the first sensing node SN1 is output to the sensing circuit 500 through the first sensing line RL1. The second sensing signal FS2 can be stored as the second sensing signal voltage V2 in the output terminal Out of the operational amplifier 511. That is, the second sensing signal FS2 sensed by the second row sensor FX2 can be stored as the second sensing signal voltage V2 in the amplifying circuit 510. The second sensing signal voltage V2 can be accumulated in the first sensing signal voltage V1 and stored.

[0204] During the seventh read period st7, the third write scan signal SWS3 having the gate-on voltage Von is supplied to the third write scan line SWL3. During the seventh read period st7, the output transistor ST3 of the third row sensor FX3 is turned on by the third write scan signal SWS3. Due to this, it can be that the amplifier transistor ST2 is connected to the first readout line RL1, and the third readout signal FS3 proportional to the voltage charged in the first sensing node SN1 is output to the readout circuit 500 through the first readout line RL1. The third readout signal FS3 can be stored as the third sensing signal voltage V3 in the output terminal Out of the operational amplifier 511. That is, the third readout signal FS3 sensed by the third row sensor FX3 can be stored as the third sensing signal voltage V3 in the amplifier circuit 510. The third sensing signal voltage V3 can increase in the opposite direction to the first sensing signal voltage V1. The third sensing signal voltage V3 can be accumulated in the first sensing signal voltage V1 and the second sensing signal voltage V2 and stored.

[0205] During the eighth reading period st8, the fourth writing scanning signal SWS4 having the gate-on voltage Von is supplied to the fourth writing scanning line SWL4. During the eighth reading period st8, the output transistor ST3 of the fourth row sensor FX4 is turned on by the fourth writing scanning signal SWS4. Due to this, it can be that the amplifying transistor ST2 is connected to the first reading line RL1, and the fourth reading signal FS4 proportional to the voltage charged in the first sensing node SN1 is output to the reading circuit 500 through the first reading line RL1. The fourth reading signal FS4 can be stored as the fourth sensing signal voltage V4 in the output terminal Out of the operational amplifier 511. That is, the fourth reading signal FS4 sensed by the fourth row sensor FX4 can be stored as the fourth sensing signal voltage V4 in the amplifying circuit 510. The fourth sensing signal voltage V4 can increase in the opposite direction to the first sensing signal voltage V1. The fourth sensing signal voltage V4 can be accumulated in the first to third sensing signal voltages V1-V3 and stored.

[0206] exist Fig. 9 exemplarily shows that the sensing signal voltage VC is received from four sensors during one sensing period SP, but the number of sensors received during the sensing period SP according to an embodiment of the present invention is not limited thereto. For example, during the sensing period SP, the readout circuit 500 may receive the sensing signal voltage VC from more than two sensors.

[0207] The write scan signal SWSj has a second horizontal period HT2. The write scan signal SWSj may have a turn-on signal in each second horizontal period HT2. That is, the write scan signal SWSj may repeatedly turn on the signal in each second horizontal period HT2. For example, the interval between the pulses of the first write scan signal SWS1 and the second write scan signal SWS2 may have a second horizontal period HT2. In addition, the interval between the pulses of each of the second to fourth write scan signals SWS2-SWS4 may have a second horizontal period HT2.

[0208] The first sampling signal SHS may control the first switch SW1. For example, the first sampling signal SHS has a first horizontal period HT1. That is, the interval between pulses of the first sampling signal SHS may have a first horizontal period HT1. The first sampling signal SHS may have a turn-on signal during the third reading period st3 in the first horizontal period HT1. Thus, the first sampling signal SHS may repeatedly turn on the signal in each first horizontal period HT1.

[0209] The first sampling signal SHS may include a third reading period st3 in which the first switch SW1 is turned on. The first switch SW1 is turned on during the third reading period st3. Thus, the output terminal Out of the operational amplifier 511 may be electrically connected to the first capacitor Csh1. First, in the third reading period st3, the output terminal Out of the operational amplifier 511 sensed in the fifth reading period st5 corresponds to the first sensing signal voltage V1, so the first capacitor Csh1 may store the first sensing signal voltage V1. Next, in the third reading period st3, the output terminal Out of the operational amplifier 511 sensed in the sixth to eighth reading periods st6-st8 respectively corresponds to the second to fourth sensing signal voltages V2-V4, so the first capacitor Csh1 may also accumulate and store the second to fourth sensing signal voltages V2-V4.

[0210] Thus, the first capacitor Csh1 may sequentially accumulate and store the first to fourth sensing signal voltages V1-V4 during the third reading period st3. Therefore, the voltage sequentially accumulated by the first to fourth sensing signal voltages V1-V4 may be stored as the accumulated sensing signal voltage VF. The accumulated sensing signal voltage VF may have a voltage level lower than the saturation voltage VS. Therefore, the accumulated sensing signal voltage VF may not become a saturated state.

[0211] Unlike the present invention, when the signals received from a plurality of sensors are accumulated and output, the accumulated sensing signal voltage has the possibility of becoming a saturated state. However, according to the present invention, each of the first to fourth row sensors FX1-FX4 can sense not only the second light of the second pixel APX2, but also the first light of the first pixel APX1 during the light receiving period EIT. Due to this, the DC component of the signal can be increased, and if the DC component increases, the voltage level of the sensing signal voltage VC can be reduced. The voltage of the first sensing node SN1 can be shifted approximately toward the second drive voltage ELVSS. That is, after the fifth reading period st5, the sensing signal voltage VC can have a level equivalent to the first sensing signal voltage V1 lower than the saturation voltage VS, and have a voltage level close to the second drive voltage ELVSS. Thereafter, even if the sensing signal voltages V2, V3, and V4 received from a plurality of sensors FX2-FX4 are accumulated, the voltage level of the accumulated sensing signal voltage VF can have a voltage level lower than the saturation voltage VS. That is, signal integration for improving accuracy and sensitivity can be easy. Therefore, an electronic device DD (refer to Figure 1 ).

[0212] In addition, according to the present invention, the sensing signal voltage VC can accumulate an AC component equivalent to the accumulated sensing signal voltage VF. This can easily obtain a signal for sensing blood pressure, and reduce or remove noise components. Therefore, an electronic device DD with improved sensing reliability can be provided (see Figure 1 ).

[0213] In addition, the first sampling signal SHS includes a fourth read period st4 having a cut-off voltage. During the fourth read period st4, the capacitor Cf is reset according to the feedback reset signal IRST, and a voltage is stored in the second capacitor Csh2 according to the second sampling signal SHR.

[0214] In summary, the first capacitor Csh1 can accumulate and store the first to fourth sensing signal voltages V1-V4. That is, the first capacitor Csh1 can store the accumulated sensing signal voltage VF from the first to fourth row sensors FX1-FX4 during the third reading period st3. Therefore, the first capacitor Csh1 can store a voltage obtained by adding the initial voltage VREF, the noise signal voltage, and the accumulated sensing signal voltage VF.

[0215] The analog-to-digital converter 530 can convert the sensing signal voltage VC into a data value by differentiating the voltage stored in the second capacitor Csh2 from the voltage stored in the first capacitor Csh1, and can provide the data value to the driving controller 100. The sensing signal S_FS (refer to Figure 3 ) may include the data value.

[0216] When the first horizontal period HT1 as the conduction period of the switch SW, the first switch SW1 and the second switch SW2 of the readout circuit 500 and the second horizontal period HT2 as the conduction period of the output transistor ST3 of the sensor FX are as shown in FIG. Fig. 9 When performed sequentially, the first horizontal period HT1 may be greater than the second horizontal period.

[0217] In addition, the third reading period st3 in which the first sampling signal SHS has the on voltage may be greater than the second horizontal period HT2. For example, the first to fourth row sensors FX1-FX4 may sequentially output the first to fourth readout signals FS1-FS4 through the first readout line RL1 in response to the first to fourth write scan signals SWS1-SWS4. According to the second horizontal period HT2 (e.g., about 3.2 μs (microseconds)) of the write scan signal SWSj, the first to fourth readout signals FS1-FS4 may be sequentially output to the readout circuit 500.

[0218] On the other hand, the readout circuit 500 may output the sensing signal voltage VC every time during the first horizontal period HT1 (e.g., about 12.8 μs). For example, the sensing signal voltage VC may be generated every first horizontal period HT1 which is a conduction period of the switch SW, the first switch SW1, and the second switch SW2 of the readout circuit 500. That is, the readout circuit 500 may generate a sensing signal data value according to the sensing signal voltage VC every first horizontal period HT1, and calculate a pulse signal therefrom.

[0219] In summary, the third reading period st3 in which the first sampling signal SHS has a turn-on voltage is greater than the first horizontal period HT1 of the write scanning signal SWSj, so that the plurality of readout signals FSd of the plurality of sensors FX can be stored in the first capacitor Csh1. Therefore, the readout circuit 500 can receive the input of the plurality of readout signals FSd and store the accumulated sensing signal voltage VF. Thus, the readout circuit 500 can output a pulse wave signal according to the accumulated sensing signal voltage VF, and sense blood pressure according to the pulse wave signal.

[0220] Fig.10 It is shown that according to the configuration Figure 6 A graph of a sensing signal voltage of brightness of pixels in a first area.

[0221] Reference Figure 6 , Figure 7 , Fig. 9 as well as Fig.10 , the x-axis of the graph may show time. The y-axis of the graph may show data values ​​converted from the sensing signal voltage VC. For example, the data values ​​may be defined as a first data value SV1 to a second data value SV2. For example, the first data value SV1 may be 0. The second data value SV2 may be 65535.

[0222] An area adjacent to the first data value SV1 may be defined as a first signal saturation area SA1. An area adjacent to the second data value SV2 may be defined as a second signal saturation area SA2. When a signal belongs to the first signal saturation area SA1 and the second signal saturation area SA2, the signal may be saturated and the reliability of the signal may be reduced.

[0223] In the graph, a first embodiment LO, a second embodiment LL and a third embodiment LH may be defined according to the embodiment.

[0224] The first embodiment LO can be defined as an embodiment in which the first pixel APX1 disposed in the first area XA1 is turned off and does not emit light, and the second pixel APX2 disposed in the second area XA2 is turned on and emits light. For example, the first embodiment LO can be an embodiment for describing a conventional blood pressure sensing method.

[0225] The second embodiment LL and the third embodiment LH can be defined as embodiments in which the first pixel APX1 configured in the first area XA1 and the second pixel APX2 configured in the second area XA2 are turned on and emit light. For example, the second embodiment LL can be an embodiment for comparison, and the third embodiment LH can be an embodiment for explaining the blood pressure sensing method of the present invention.

[0226] At this time, the brightness of the first pixel APX1 in the second embodiment LL may be lower than that of the first pixel APX1 in the third embodiment LH. For example, the first pixel APX1 in the second embodiment LL may emit light at 150 grayscale, and the first pixel APX1 in the third embodiment LH may emit light at 185 grayscale or 200 grayscale, but is not limited thereto.

[0227] Each of the first to eighth signals SG1 - SG8 shows a pulse signal output from the readout circuit 500 according to an embodiment.

[0228] In the first embodiment LO, a first signal SG1 and a second signal SG2 can be output.

[0229] The first signal SG1 may be a first readout signal FS1 sensed by the first row sensor FX1. That is, the first signal SG1 may be a pulse signal output by the readout circuit 500 receiving a signal from a sensor. For example, the DC component of the first signal SG1 may have a data value of 28906, and the AC component may have a data value having a width of 157.

[0230] The second signal SG2 may be a signal accumulated from the first readout signal FS1 sensed by the first row sensor FX1 and the second readout signal FS2 sensed by the second row sensor FX2. That is, the second signal SG2 may be a pulse signal outputted by the readout circuit 500 receiving signals from the two sensors and integrating the signals. For example, the DC component of the second signal SG2 may have a data value of 69, and the AC component may have a data value having a width of 17.

[0231] The second signal SG2 may correspond to the first signal saturation region SA1. That is, the second signal SG2 may correspond to the first signal saturation region SA1 without acquiring the width of the AC component. Therefore, the second signal SG2 is not suitable as a signal for sensing a pulse wave signal, and thus the maximum signal that can be obtained in the first embodiment LO may be the first signal SG1.

[0232] In the second embodiment LL, a third signal SG3, a fourth signal SG4 and a fifth signal SG5 can be output.

[0233] The third signal SG3 may be the first readout signal FS1 sensed by the first row sensor FX1. That is, the third signal SG3 may be a pulse signal output by the readout circuit 500 receiving a signal from a sensor. For example, the DC component of the third signal SG3 may have a data value of 41033, and the AC component may have a data value having a width of 232.

[0234] In the second embodiment LL, the first sensor AFX1 can sense not only the second light of the second pixel APX2 sensing the blood vessel required for blood pressure sensing, but also the first light of the first pixel APX1. Due to this, the DC component of the signal output by the readout circuit 500 can be increased. When the first signal SG1 output in the first embodiment LO and the third signal SG3 output in the second embodiment LL, which receive signals from the same number of sensors, are compared, the DC component of the third signal SG3 can be increased over the DC component of the first signal SG1. For example, the DC component of the third signal SG3 can be increased by 42.0% over the DC component of the first signal SG1.

[0235] The fourth signal SG4 may be a signal accumulated from the first readout signal FS1 sensed by the first row sensor FX1 and the second readout signal FS2 sensed by the second row sensor FX2. That is, the fourth signal SG4 may be a pulse signal output by the readout circuit 500 receiving signals from the two sensors and integrating the signals. For example, the DC component of the fourth signal SG4 may have a data value of 19212, and the AC component may have a data value having a width of 392.

[0236] The fifth signal SG5 may be a signal accumulated from the first readout signal FS1 sensed by the first row sensor FX1, the second readout signal FS2 sensed by the second row sensor FX2, and the third readout signal FS3 sensed by the third row sensor FX3. That is, the fifth signal SG5 may be a pulse signal output by the readout circuit 500 receiving signals from the three sensors and integrating the signals. For example, the DC component of the fifth signal SG5 may have a data value of 311, and the AC component may have a data value having a width of 18.

[0237] The fifth signal SG5 may correspond to the first signal saturation region SA1. That is, the fifth signal SG5 may correspond to the first signal saturation region SA1 without acquiring the width of the AC component. Therefore, the fifth signal SG5 is not suitable as a signal for sensing a pulse wave signal, and thus the maximum signal that can be obtained in the second embodiment LL may be the fourth signal SG4.

[0238] In the third embodiment LH, a sixth signal SG6, a seventh signal SG7, and an eighth signal SG8 can be output.

[0239] The sixth signal SG6 may be the first readout signal FS1 sensed by the first row sensor FX1. That is, the sixth signal SG6 may be a pulse signal output by the readout circuit 500 receiving a signal from a sensor. For example, the DC component of the sixth signal SG6 may have a data value of 46150, and the AC component may have a data value having a width of 196. The sixth signal SG6 may correspond to the second signal saturation area SA2. Therefore, the sixth signal SG6 may not be suitable as a signal for sensing a pulse signal.

[0240] The seventh signal SG7 may be a signal accumulated from the first readout signal FS1 sensed by the first row sensor FX1 and the second readout signal FS2 sensed by the second row sensor FX2. That is, the seventh signal SG7 may be a pulse signal output by the readout circuit 500 receiving signals from the two sensors and integrating the signals. For example, the DC component of the seventh signal SG7 may have a data value of 29767, and the AC component may have a data value having a width of 364.

[0241] According to the present invention, in the third embodiment LH, the first sensor AFX1 can sense not only the second light of the second pixel APX2 sensing the blood vessel required for blood pressure sensing, but also the first light of the first pixel APX1. Due to this, the DC component of the signal output by the readout circuit 500 can be increased. When the fourth signal SG4 output in the second embodiment LL and the seventh signal SG7 output in the third embodiment LH, which receive signals from the same number of sensors, are compared, the DC component of the seventh signal SG7 can be increased over the DC component of the fourth signal SG4. For example, the DC component of the seventh signal SG7 can be increased by 54.9% over the DC component of the fourth signal SG4.

[0242] In addition, according to the present invention, the third embodiment LH has an increased DC component compared to the first embodiment LO, so that signal integration can be easy. When the first signal SG1 having a DC component having data values ​​similar to each other is compared with the seventh signal SG7, the AC component of the seventh signal SG7 can be increased compared to the AC component of the first signal SG1. For example, the AC component of the seventh signal SG7 can be increased by 131.8% compared to the AC component of the first signal SG1.

[0243] The eighth signal SG8 may be a signal accumulated from the first readout signal FS1 sensed by the first row sensor FX1, the second readout signal FS2 sensed by the second row sensor FX2, and the third readout signal FS3 sensed by the third row sensor FX3. That is, the eighth signal SG8 may be a pulse signal output by the readout circuit 500 receiving signals from the three sensors. For example, the DC component of the eighth signal SG8 may have a data value of 19506, and the AC component may have a data value having a width of 493.

[0244] According to the present invention, the third embodiment LH has an increased DC component compared to the second embodiment LL, so that signal integration can be easy. When the fourth signal SG4 and the eighth signal SG8 having DC components with data values ​​similar to each other are compared, the AC component of the eighth signal SG8 can be increased compared to the AC component of the fourth signal SG4. For example, the AC component of the eighth signal SG8 can be increased by 25.8% compared to the AC component of the fourth signal SG4.

[0245] The eighth signal SG8 may not correspond to the first signal saturation area SA1. Therefore, the eighth signal SG8 is suitable as a signal for sensing a pulse wave signal, and thus the maximum signal that can be obtained in the third embodiment LH may be the eighth signal SG8.

[0246] When comparing the first signal SG1, the fourth signal SG4, and the eighth signal SG8, ​​which are the maximum signals that can be obtained in each embodiment LO, LL, and LH, the eighth signal SG8 may have a large AC component. It may be that the larger the AC component, the easier it is to sense the pulse wave signal. That is, the pulse wave signal can be most easily sensed in the third embodiment LH.

[0247] Figures 11a to 11d FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA area corresponds to the plan view of the area. Figures 11a to 11d When Figure 6 The constituent elements described above are denoted by the same reference numerals, and description thereof will be omitted.

[0248] Reference Fig.11a , display area DA (refer to Figure 3 ) may include a first area XB1, a second area XB2 and a third area XB3.

[0249] The first region XB1 may have a polygonal shape. The first region XB1 may have a hexagonal shape. The second region XB2 may have a shape corresponding to the shape of the first region XB1 and surrounding the first region XB1. The third region XB3 may surround the first region XB1 and the second region XB2.

[0250] Reference Fig.11b , display area DA (refer to Figure 3 ) may include a first region XC1, a second region XC2 and a third region XC3.

[0251] The first region XC1 may have a polygonal shape. The first region XC1 may have a quadrilateral shape. The second region XC2 may have a shape corresponding to the shape of the first region XC1 and surrounding the first region XC1. The third region XC3 may surround the first region XC1 and the second region XC2.

[0252] Reference Fig.11c , display area DA (refer to Figure 3 ) may include a first region XD1, a second region XD2 and a third region XD3.

[0253] The second region XD2 may include a 2-1 region XD2-1 and a 2-2 region XD2-2. The 2-1 region XD2-1 may be disposed apart from the 2-2 region XD2-2. The first region XD1 may be disposed between the 2-1 region XD2-1 and the 2-2 region XD2-2. The third region XD3 may surround the first region XD1 and the second region XD2.

[0254] Reference Fig.11d , display area DA (refer to Figure 3 ) may include a first area XE1, a second area XE2 and a third area XE3.

[0255] The second region XE2 may have a polygonal shape. The second region XE2 may have a quadrilateral shape. The first region XE1 may have a shape corresponding to the shape of the second region XE2 and surrounding the second region XE2. The third region XE3 may surround the first region XE1 and the second region XE2.

[0256] Reference Figures 11a to 11d According to the shapes of the first regions XB1, XC1, XD1, and XE1, the shapes of the second regions XB2, XC2, XE2, the 2-1st region XD2-1, and the 2-2nd region may be changed.

[0257] According to the present invention, a conductive first sensor AFX1 (see Figure 6 The shape of each of the first regions XA1-XE1 of the embodiment of the present invention may be provided differently. According to the shape, the first sensor AFX1 (refer to Figure 6 ) The integration degree of the light received by the sensor can be improved. Therefore, an electronic device DD with improved sensing reliability can be provided (refer to Figure 1 ).

[0258] Figures 12a to 12e FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA area corresponds to the plan view of the area. Figures 12a to 12e When Figure 6 , Figures 11a to 11d The constituent elements described above are denoted by the same reference numerals, and description thereof will be omitted.

[0259] Reference Figure 6 as well as Fig.12a , display area DA (refer to Figure 3) may include a 1-1th area XA1-1, a second area XA2, and a third area XA3.

[0260] A plurality of first pixels APX1 may be arranged in the 1-1 region XA1-1. The brightness of the first pixel APX1 arranged in the center of the 1-1 region XA1-1 may be the highest. As the first pixel APX1 is arranged at a position away from the center of the 1-1 region XA1-1, the brightness of the first pixel APX1 may gradually decrease.

[0261] Reference Figure 6 as well as Figure 12b , display area DA (refer to Figure 3 ) may include a 1-1th area XB1-1, a second area XB2, and a third area XB3.

[0262] A plurality of first pixels APX1 may be arranged in the 1-1 region XB1-1. The brightness of the first pixel APX1 arranged in the center of the 1-1 region XB1-1 may be the highest among the brightness of the first pixels APX1 arranged in the 1-1 region XB1-1. As the first pixel APX1 is arranged at a position away from the center of the 1-1 region XB1-1, the brightness of the first pixel APX1 may gradually decrease.

[0263] Reference Figure 6 as well as Fig.12c , display area DA (refer to Figure 3 ) may include a 1-1th region XC1-1, a second region XC2, and a third region XC3.

[0264] A plurality of first pixels APX1 may be arranged in the 1-1 region XC1-1. The brightness of the first pixel APX1 arranged in the center of the 1-1 region XC1-1 may be the highest among the brightness of the first pixels APX1 arranged in the 1-1 region XC1-1. As the first pixel APX1 is arranged at a position away from the center of the 1-1 region XC1-1, the brightness of the first pixel APX1 may gradually decrease.

[0265] Reference Figure 6 as well as Fig.12d , display area DA (refer to Figure 3 ) may include a 1-1st region XD1-1, a second region XD2, and a third region XD3. The second region XD2 may include a 2-1st region XD2-1 and a 2-2nd region XD2-2.

[0266] A plurality of first pixels APX1 may be arranged in the 1-1 region XD1-1. The brightness of the first pixel APX1 arranged on the first center line CL1 of the 1-1 region XD1-1 may be the highest among the brightness of the first pixels APX1 arranged in the 1-1 region XD1-1. As the first pixel APX1 is arranged at a position away from the first center line CL1, the brightness of the first pixel APX1 may gradually decrease.

[0267] Reference Figure 6 as well as Fig.12e , display area DA (refer to Figure 3 ) may include a 1-1th region XE1-1 region, a second region XE2 and a third region XE3.

[0268] The brightness of the first pixel APX1 arranged on the second center line CL2 of the 1-1 region XE1-1 may be the highest among the first pixels APX1 arranged in the 1-1 region XE1-1. The brightness of the first pixel APX1 may gradually decrease as it is arranged farther from the second center line CL2.

[0269] According to the present invention, the shape of each of the first regions XA1-1-XE1-1 configured with the first sensor AFX1 turned on can be provided differently. According to the shape, the integration of the light received by the first sensor AFX1 can be improved. Thus, the DC component of the signal received by the first sensor AFX1 can be increased. In addition, the light emitted from each of the first regions XA1-1-XE1-1 configured with the first sensor AFX1 turned on can have a radial gradation. Thus, the AC component of the signal received by the first sensor AFX1 can be increased. Therefore, an electronic device DD with improved sensing reliability can be provided (refer to Figure 1 ).

[0270] Fig.13 FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA area corresponds to the plan view of the area. Fig.13 When Figure 6 The constituent elements described above are denoted by the same reference numerals, and description thereof will be omitted.

[0271] Reference Figure 2 , Figure 3 , Figure 6 as well as Fig.13 , the display area DA may include a 1-2nd area XA1-2, a second area XA2, and a third area XA3.

[0272] The first pixel APX1 and the first sensor AFX1 may be disposed in the 1-2 region XA1-2. Figure 4a ) can emit a first light with a first brightness. At this time, the first light can have a first wavelength.

[0273] The second pixel APX2 may be disposed in the second area XA2. The light emitting element ED of the second pixel APX2 may emit the second light at the second brightness. The first sensor AFX1 may receive the first light and the second light.

[0274] The second light may have a second wavelength different from the first wavelength. The first wavelength may be shorter than the second wavelength. For example, the first wavelength may be 545nm (nanometer) to 600nm, and the second wavelength may be 600nm to 650nm. For example, the first wavelength may be identified as blue light or green light, and the second wavelength may be identified as red light, but is not limited thereto.

[0275] The first wavelength may have a smaller penetration depth of light into the skin than the second wavelength. The larger the wavelength, the deeper the penetration depth of light into the skin. For example, the penetration depth of light into the skin of the first wavelength may be 0.5 mm (millimeter) to 1.0 mm, and the penetration depth of light into the skin of the second wavelength may be 1.0 mm to 2.0 mm. In the sensing mode, when the user's hand US_F (reference Figure 1 ) contacts the window WM, the second light has a second wavelength, and thus can be reflected back from the artery in the blood vessel of the user's hand US_F. The first light has a first wavelength, and thus can be reflected back from the arteriole in the blood vessel of the user's hand US_F. The first sensor AFX1 can sense the reflected first light and the second light to sense the blood vessel. The first sensor AFX1 can read out the readout signal FSd (refer to Figure 4a ) is sent to the readout circuit 500.

[0276] According to an embodiment of the present invention, the light emitted from the 1-2 region XA1-2 configured with the turned-on first pixel APX1 may also have a radial gradation. According to the present invention, the wavelengths of the light emitted from the 1-2 region XA1-2 and the second region XA2 may be different. When the light emitted from the 1-2 region XA1-2 and the second region XA2 senses the user's hand US_F, the penetration depth of the light entering may be different. Therefore, the light emitted from the 1-2 region XA1-2 may obtain the signal of the arteriole, and the light emitted from the second region XA2 may obtain the signal of the artery. The readout circuit 500 may amplify only the signal of the artery and maximize the pulse wave signal. Therefore, an electronic device DD with improved sensing reliability may be provided (refer to Figure 1 ).

[0277] Fig.14FIG. 1 is an enlarged view showing an embodiment of the present invention. Figure 3 The AA area corresponds to the plan view of the area. Fig.14 When Figure 6 The constituent elements described above are denoted by the same reference numerals, and description thereof will be omitted.

[0278] Reference Figure 6 as well as Fig.14 , display area DA (refer to Figure 3 ) may include a first region XF1, a second region XF2 and a third region XF3.

[0279] The first region XF1 may include a 1-1 region XF1-1 and a 1-2 region XF1-2 adjacent to the 1-1 region XF1-1. The second region XF2 may include a 2-1 region XF2-1 and a 2-2 region XF2-2 and a 2-3 region XF2-3 separated from the 2-1 region XF2-1. The first region XF1 may be disposed between the 2-1 region XF2-1, the 2-2 region XF2-2 and the 2-3 region XF2-3. The third region XF3 may surround the first region XF1 and the second region XF2.

[0280] The second light may have a first wavelength and a second wavelength. The second light may include a 2-1 light having a second wavelength and a 2-2 light having a first wavelength different from the second wavelength. It may be that the second pixel APX2 configured in the 2-1 region XF2-1 and the 2-2 region XF2-2 emits the 2-1 light, and the second pixel APX2 configured in the 2-3 region XF2-3 emits the 2-2 light. The first wavelength may be shorter than the second wavelength. The first wavelength may have a shallower penetration depth than the second wavelength. For example, the first wavelength may be green light, and the second wavelength may be red light, but is not limited thereto.

[0281] The first sensor AFX1 arranged in the 1-1 region XF1-1 can receive the 2-1 light and the 2-2 light. The first sensor AFX1 arranged in the 1-2 region XF1-2 can receive the 2-1 light.

[0282] In the sensing mode, when the user's hand US_F contacts the window WM, the 2-1st light has the second wavelength and can be reflected back at the artery in the blood vessel of the user's hand US_F. The 2-2nd light has the first wavelength and can be reflected back at the arteriole in the blood vessel of the user's hand US_F. The first sensor AFX1 can sense the reflected 2-1st light and the 2-2nd light to sense the blood vessel. The first sensor AFX1 can send a readout signal FSd containing information of the sensed blood vessel to the readout circuit 500.

[0283] According to the present invention, the second pixel APX2 configured in the 2-1 region XF2-1 and the 2-2 region XF2-2 may have a second wavelength, and the second pixel APX2 configured in the 2-3 region XF2-3 may have a first wavelength. The first wavelength is shorter than the second wavelength, so when sensing the user's hand US_F (refer to Figure 1 ) The penetration depth of light can be different. Therefore, the light emitted from the 2-1 region XF2-1 and the 2-2 region XF2-2 can obtain the signal of the artery, and the light emitted from the 2-3 region XF2-3 can obtain the signal of the arteriole. Figure 3 ) can amplify only the arterial signal to maximize the pulse wave signal. An electronic device DD with improved sensing reliability can be provided (refer to Figure 1 ).

[0284] The above description is made with reference to the preferred embodiments of the present invention, but a person skilled in the art or a person with ordinary knowledge in the art will understand that various modifications and changes can be made to the present invention without departing from the concept and technical scope of the present invention as recorded in the attached claims. Therefore, the technical scope of the present invention is not limited by the contents recorded in the detailed description of the specification, but should only be determined by the claims.

Claims

1. An electronic device, wherein: include: The display panel comprises: pixels, including a pixel driving circuit and a light emitting element; and a sensor, including a sensor driving circuit and a sensing element, wherein the display panel defines a display area and operates in a sensing mode; and a readout circuit, electrically connected to the sensor, The pixels include a first pixel, a second pixel and a third pixel, The sensor includes a first sensor, a second sensor and a third sensor, The display area includes a first area, a second area adjacent to the first area, and a third area surrounding the first area and the second area. In the sensing mode, The first pixel disposed in the first area emits a first light with a first brightness, The second pixel disposed in the second area emits a second light with a second brightness different from the first brightness, The third pixel disposed in the third area does not emit light, The readout circuit receives a readout signal from the first sensor disposed in the first area.

2. The electronic device according to claim 1, wherein: The sensor disposed in the display area senses blood pressure in the sensing mode.

3. The electronic device according to claim 1, wherein: The third sensor is configured in the third area.

4. The electronic device according to claim 1, wherein: In the sensing mode, The first pixel and the first sensor are turned on, The second pixel is turned on, the second sensor is turned off, The third pixel and the third sensor are turned off.

5. The electronic device according to claim 1, wherein: The first brightness is lower than the second brightness.

6. The electronic device according to claim 1, wherein: The sensor driving circuit comprises: A reset transistor is electrically connected to the sensing element and includes: a gate electrode receiving a reset control signal; a first electrode receiving a reset voltage; and a second electrode connected to a first sensing node; an amplifying transistor, comprising: a first electrode receiving a sensor driving voltage; a second electrode connected to a second sensing node; and a gate electrode connected to the first sensing node; and The output transistor includes: a first electrode connected to the second sensing node; a second electrode connected to the readout line; and a gate electrode receiving an output control signal.

7. The electronic device according to claim 6, wherein: The readout circuit further comprises: an amplifier circuit that receives the transmission of the readout signal from the sensor drive circuit through the readout line and amplifies the signal; a sampling and holding section that samples and holds the signal provided from the amplification circuit; and The analog-to-digital converter digitizes the analog signal provided from the sampling and holding section. The sampling and holding section includes: a reset section including a first switch and a first capacitor; and a holding section including a second switch and a second capacitor.

8. The electronic device according to claim 1, wherein: The first region has a circular shape, The second region has a ring shape and surrounds the first region.

9. The electronic device according to claim 1, wherein: The first region has a polygonal shape, The second area surrounds the first area.

10. The electronic device according to claim 1, wherein: The second area includes the 2-1 area and the 2-2 area separated from the 2-1 area, The first region is arranged between the 2-1 region and the 2-2 region.

11. The electronic device according to claim 10, wherein: The second light includes: 2-1 light having a first wavelength; and 2-2 light having a second wavelength different from the first wavelength, The second region further includes: a 2-3 region, which is arranged above the first region, The 2-1 light is emitted in the 2-1 region and the 2-2 region, The 2-2 light is emitted in the 2-3 region, The first area includes area 1-1 and area 1-2, The 1-1 region receives light from the 2-1 region, the 2-2 region, and the 2-3 region, The 1-2 region receives light from the 2-1 region and the 2-2 region.

12. The electronic device according to claim 1, wherein: The first brightness gradually decreases along a first direction from a center of the first area.

13. The electronic device according to claim 1, wherein: The first light has a first wavelength, The second light has a second wavelength different from the first wavelength.

14. The electronic device according to claim 13, wherein: The first wavelength is shorter than the second wavelength.

15. An electronic device, wherein: include: The display panel includes: a plurality of pixels, each including a pixel driving circuit and a light emitting element; a plurality of sensors, each including a sensor driving circuit and a sensing element; and a readout line, wherein the display panel defines a display area. The plurality of sensors are electrically connected to a readout circuit via one of the readout lines, The display area includes a first area, a second area adjacent to the first area, and a third area surrounding the first area and the second area. The pixels arranged in the first area among the plurality of pixels emit light at a first brightness, The pixels arranged in the second area among the plurality of pixels emit second light at a second brightness different from the first brightness, The pixels arranged in the third area among the plurality of pixels do not emit light, The readout circuit receives a readout signal from a sensor disposed in the second area among the plurality of sensors.

16. The electronic device according to claim 15, wherein: The multiple sensors configured in the display area sense blood pressure.

17. The electronic device according to claim 15, wherein: The first brightness is lower than the second brightness.

18. The electronic device according to claim 15, wherein: The first region has a circular shape, The second region has a ring shape and surrounds the first region.

19. The electronic device according to claim 15, wherein: The first region has a polygonal shape, The second area surrounds the first area.

20. The electronic device according to claim 15, wherein: The second area includes the 2-1 area and the 2-2 area separated from the 2-1 area, The first region is arranged between the 2-1 region and the 2-2 region.

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