Parylene Coating and Demasking Methods for Microdevices with Internal Channels and Anisomorphic Surfaces

Abstract

The present invention provides a method for parylene coating and film removal of a micro-device with an internal channel and a shaped surface, which includes forming a mask layer on the micro-device and coating a parylene film layer; using laser to cut the sides of the top surface and the bottom surface of the micro-device and removing the mask layer and the parylene film layer; completely wrapping the micro-device inside a fixture, with the top of the shaped surface having the mask layer and the parylene film layer protruding from the top of the fixture; using oxygen and argon to perform plasma etching on the top of the shaped surface to remove the mask layer and the parylene film layer, wherein the etching power is 1000 - 2000 w, the gas flow rate of oxygen is 60 - 200 sccm, and the gas flow rate of argon is 5 - 20 sccm. The present invention adopts laser cutting and plasma etching technologies, which can effectively perform parylene film coating and film removal on a micro-device with an internal channel and a shaped surface, and make the fracture interface of the film neat and smooth, improve the film removal efficiency and accuracy, and at the same time greatly reduce the potential damage risk to the device.

Description

Technical Field

[0001] The present invention relates to the technical field of coating removal, and particularly to a method for parylene coating and film removal of a micro-device with internal channels and a shaped surface. Background Art

[0002] The unique structure and stable properties of the parylene film endow it with excellent protective performance, and it is usually used for the protection of electronic products, semiconductor devices and other products. Usually, due to the requirements of subsequent processing technology of the device, parylene film is not required in some areas, and parylene film is only required to be coated in some areas.

[0003] In view of this situation, since it is impossible to coat the parylene film on a certain area alone, in the prior art, the purpose of partially coating the parylene film is usually achieved by coating first and then removing.

[0004] Currently, there are usually two methods to form a partially coated parylene film. The first method is to directly deposit the parylene film on all areas, and then remove the film on the areas where the parylene film is not required. However, due to the high chemical stability and high adhesion of parylene, it is extremely difficult to directly remove it.

[0005] The second method is to first cover the areas where the parylene film is not required with a mask layer, deposit the parylene film on all areas, and then remove the parylene film and the mask layer together. Although this method increases the process cost to a certain extent, since the parylene film is not directly deposited on the surface, the difficulty of removing the parylene film is greatly reduced.

[0006] However, even with the second method, there are still technical problems in coating and removing the parylene film on the surface of current semiconductor devices.

[0007] First, the size of semiconductor devices is small. With the development of the semiconductor industry, the integration of devices is continuously increasing. Nowadays, centimeter-level and millimeter-level components are quite common. Miniaturization means that the chemical substances or physical methods used in the film removal process need to be more refined and controllable, and the film removal must be very precise, which greatly increases the difficulty of film removal.

[0008] Second, the structure of semiconductor devices is complex. There are some channel structures inside semiconductor devices, and there are often some shaped structures such as solder pillars and bumps on their surfaces. The particularity of these structures must be considered during film removal. However, traditional film removal methods cannot accurately and effectively remove the film on a specific area, and may damage the film that does not need to be removed or even these structures themselves during the removal process. At the same time, the structure of semiconductor devices also affects the setting of the mask layer in the coating method, and the matching between the film removal method and the coating method is also an issue that needs to be considered.

[0009] Thirdly, the parylene film layer has very good ductility, and the elongation at break can generally reach 100%-200%. Therefore, after removing the film layer, there is pulling at the film layer fracture, resulting in phenomena such as burrs, whitening, and film layer peeling at the fracture, which in turn affects the implementation of the next process of the product or the appearance of the product. Therefore, before removing the film, the film layer at the boundary between the area that needs to be protected by the film layer and the area that does not need to be protected by the film layer should be disconnected. In this way, after removing the film, the fracture interface of the film layer will be neat and smooth.

[0010] Common methods for disconnecting the film layer include mechanical cutting, laser cutting, etc., but these methods can only be used to process devices with regular shapes or devices with relatively large sizes. Based on the above situation, for some irregular shaped devices, micro-devices, and devices in areas with mutual occlusion, typically micro-devices with internal channels and irregular surfaces, the cutting tools or lasers in traditional methods cannot penetrate deeply for cutting.

[0011] Therefore, how to coat and remove the parylene film layer on a micro-device with internal channels and irregular surfaces, and make the fracture interface of the film layer neat and smooth, is an urgent problem that current researchers and technicians are eager to solve.

[0012] Plasma etching technology is an important process technology for removing substances on the surface of devices. It uses plasma bombardment on the surface of semiconductor devices to generate volatile gases for etching. However, there is no research in the existing technology on removing the parylene film layer on micro-devices with internal channels and irregular surfaces through plasma etching technology.

[0013] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or well-known technology. Summary of the Invention

[0014] In view of this, the purpose of the present invention is to provide a method for coating and removing parylene on a micro-device with internal channels and irregular surfaces, so as to at least solve the problems that the prior art cannot coat and remove the parylene film layer on a micro-device with internal channels and irregular surfaces, and cannot make the fracture interface of the film layer neat and smooth. The present invention adopts a combination of laser cutting and plasma etching technology. The laser cutting is used to remove the film on the plane, and the non-directional and batch processing characteristics of the plasma etching technology are used to process the irregular surface, so that the film layer in the area that cannot be cut by the traditional method can be disconnected, achieving the purpose of cutting the film layer. By reasonably selecting the coating and film removal methods of the parylene film layer, the present invention makes the fracture interface of the film layer neat and smooth, can effectively improve the efficiency and accuracy of removing the mask layer and the parylene film layer on the irregular surface of the micro-device, and at the same time greatly reduces the potential damage risk to the device.

[0015] The present invention provides a parylene coating and stripping method for a micro-device with an internal channel and a special-shaped surface, comprising the following steps:

[0016] S101. Form a mask layer on the top surface of the micro-device, the bottom surface of the micro-device, and the top of the special-shaped surface;

[0017] S102. Coat a parylene film layer on the internal and external surfaces of the micro-device by chemical vapor deposition;

[0018] S103. Use laser to cut the sides of the top surface and the bottom surface of the micro-device, and then remove the mask layer and the parylene film layer on the top surface and the bottom surface of the micro-device;

[0019] S104. Completely wrap the micro-device inside a fixture, and the top of the special-shaped surface with the mask layer and the parylene film layer extends out of the top of the fixture;

[0020] S105. Use oxygen and argon to perform plasma etching on the top of the special-shaped surface to remove the mask layer and the parylene film layer, wherein the etching power is 1000-2000 w, the gas flow rate of oxygen is 60-200 sccm, and the gas flow rate of argon is 5-20 sccm.

[0021] In some embodiments, in S105, the mixing ratio of oxygen to argon is 3:1-40:1.

[0022] In some embodiments, in S105, the etching pressure is 30-60 Pa.

[0023] In some embodiments, in S105, the etching time is 6-10 hours.

[0024] In some embodiments, in S101, the mask layer on the top surface and the bottom surface of the micro-device is formed by glue or tape material.

[0025] In some embodiments, in S101, the mask layer on the top of the special-shaped surface is formed by acrylate adhesive.

[0026] In some embodiments, in S101, the mask layer on the top of the special-shaped surface is formed by the lifting method, and the specific steps are as follows:

[0027] Completely immerse the top of the special-shaped surface into the acrylate adhesive, and the thickness of the acrylate adhesive is 0.1-0.3 mm;

[0028] Lift the micro-device to make the top of the special-shaped surface leave the acrylate adhesive, and the acrylate adhesive evenly wraps the top of the special-shaped surface;

[0029] Cure the acrylate adhesive to form a mask layer.

[0030] In some embodiments, in S102, the thickness of the parylene film layer is 10 - 25 μm.

[0031] In some embodiments, in S103, the laser is a pulsed laser with a wavelength of 355 - 1064 nm, the pulse width is in the femtosecond or picosecond level, the cutting power is 1 - 10 W, and the cutting time is 30 - 120 seconds.

[0032] In some embodiments, in S104, the fixture includes a substrate and a sealing plate; at least one blind hole matching the shape of the micro-device is formed on the substrate; a through hole corresponding to the blind hole is formed on the sealing plate; when the micro-device is placed in the blind hole, the sealing plate is covered on the top of the substrate to seal the blind hole, and the top of the special-shaped surface with the mask layer and the parylene film layer extends out of the through hole.

[0033] In some embodiments, in S104, the fixture is made of silica gel material, and the Shore A hardness is 50 - 70 degrees.

[0034] The beneficial effects that the present invention can achieve are as follows:

[0035] The present invention uses plasma etching technology to remove the mask layer and the parylene film layer from the special-shaped surface of the micro-device. By utilizing the non-directional and batch processing characteristics of plasma etching technology to process the special-shaped surface, the film layer in the area that cannot be cut by traditional methods can be disconnected, achieving the purpose of cutting the film layer, and the fracture interface of the film layer is neat and smooth. The peeling of the present invention has special requirements compared with traditional plasma etching, which requires simultaneous peeling of the mask layer and the parylene film layer loaded on it. To solve the above problems, the plasma etching technology of the present invention adopts a gas combination of oxygen and argon. On the one hand, the oxygen ions formed after the ionization of oxygen have high oxidizing properties, and can chemically react with the organic molecules of the film layer to generate gaseous carbon-containing molecules, which are then pumped away by the vacuum system of the equipment, achieving the purpose of etching. On the other hand, the argon plasma has high energy under the acceleration of the electrode and impacts the surface film layer, activating the molecules on the surface of the film layer and promoting the entry of oxygen ions into the mask layer for etching. The two gases complement each other, effectively improving the etching speed. By reasonably controlling the flow rates of the two gases, as well as the etching power and etching time of plasma etching, the impact effect and the oxidation effect can work together. Plasma etching can completely remove the mask layer and the parylene film layer on the special-shaped surface, without film layer residue, and at the same time avoid over-etching. Reasonable parameter settings can ensure that the film layer is completely removed, prevent the film layer from being pulled and deformed, and finally make the fracture interface of the film layer neat and smooth. The present invention can effectively improve the efficiency and accuracy of removing the mask layer and the parylene film layer on the special-shaped surface of the micro-device, while greatly reducing the potential damage risk to the device.

[0036] Furthermore, the present invention uses an acrylate adhesive as the material for forming the mask layer, and its etching rate by oxygen and argon plasma is moderate, which is beneficial to improving the integrity of film layer removal.

[0037] Furthermore, the present invention creatively uses the dipping method to form a mask layer on the irregular surface, which can ensure that the irregular surface is evenly wrapped by the mask layer and the thickness of the mask layer in each area is consistent. The present invention reasonably selects the coating and film removal methods of the parylene film layer. Through the reasonable setting of the mask layer, the combination between the film removal method and the coating method has good consistency and matching, and the purpose of partially coating the parylene film layer on the micro-device with internal channels and irregular surfaces is successfully achieved.

[0038] Furthermore, the present invention adopts a scheme combining laser cutting and plasma etching technologies. By using laser cutting to remove the film on the relatively easy-to-process plane, the use of plasma etching can be minimized, and plasma etching is only used on the difficult-to-process irregular surface. Through the synergistic cooperation of the two technologies, the potential damage risk to the device is further reduced.

[0039] Furthermore, the present invention adopts a special fixture design, which can prevent plasma from entering the internal channels of the micro-device during plasma etching, avoid damaging the parylene film layer in the internal channels, and ensure that the internal coating still has good protective performance after etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0041] Figure 1 Shows a schematic diagram of the TEC in the embodiment of the present invention;

[0042] Figure 2 Shows a schematic diagram of the TEC when it is disposed on the fixture in the embodiment of the present invention;

[0043] Figure 3 Shows an apparent top view microscope image of the TEC after film removal obtained in Embodiment 1 of the present invention;

[0044] Figure 4 Shows an apparent side view microscope image of the TEC after film removal obtained in Embodiment 1 of the present invention;

[0045] Figure 5 Shows an apparent top view microscope image of the TEC after film removal obtained in Embodiment 2 of the present invention;

[0046] Figure 6 Shows the top - view microscope image of the TEC after film removal obtained in Comparative Example 1 of the present invention;

[0047] Figure 7 Shows the top - view microscope image of the TEC after film removal obtained in Comparative Example 2 of the present invention;

[0048] Figure 8 Shows the front - view microscope image of the TEC after film removal obtained in Comparative Example 2 of the present invention;

[0049] Figure 9 Shows the top - view microscope image of the TEC after film removal obtained in Comparative Example 4 of the present invention;

[0050] Figure 10 Shows the top - view microscope image of each position of the internal channel of the TEC after removing the top cover plate in Comparative Example 6 of the present invention.

[0051] Explanation of reference numerals:

[0052] 11. Semiconductor; 12. Top cover plate; 13. Bottom cover plate; 14. Solder column; 20. Fixture; 21. Substrate; 22. Sealing plate. Detailed description of the invention

[0053] The terms "comprising", "including", "containing" or "characterized by" in the specification, claims and drawings of the present invention are synonymous, and are inclusive of endpoints or open - ended, and do not exclude additional unrecited elements or method steps. "Comprising" is a technical term used in claim language, meaning that the element exists, but other elements can also be added and still form a structure or method within the scope of the claim.

[0054] It should be noted that: Similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used for differential description and cannot be understood as indicating or implying relative importance. The term "about" in the present invention means including a small change (up to + / - 10%) of the value.

[0055] It should be noted that there are no particular restrictions on the micro-devices with internal channels and irregular surfaces mentioned in the present invention. Hereinafter, a TEC (thermoelectric cooler) will be taken as an example to illustrate the technical solution of the present invention, but the following description does not limit the protection scope of the present invention. The micro-devices mentioned in the present invention preferably include TEC but are not limited thereto, and may also be other micro-devices such as IC (integrated circuit), sensors, optoelectronic devices, etc. with internal channels and irregular structures. More specifically, the surfaces of various array-packaged semiconductor devices have irregular structures such as solder joints, bumps, pillars, pins, and leads, and also have array channels inside.

[0056] There are also no particular restrictions on the parylene coating and stripping method provided by the present invention for micro-devices with internal channels and irregular surfaces. As long as the micro-devices have internal array channels and irregular structures such as solder joints, bumps, pillars, pins, and leads, the method of the present invention can be used to partially coat the parylene film layer.

[0057] As Figure 1 shown, the TEC includes a semiconductor 11 inside, a conductive metal, a top cover plate 12, a bottom cover plate 13, and two spaced solder pillars 14 at one end of the TEC. The length of the bottom cover plate 13 of the TEC is greater than that of the top cover plate 12. The two solder pillars 14 are spaced and arranged on the part of the bottom cover plate 13 that extends beyond the top cover plate 12. A gold layer is plated on the surface of the solder pillars 14, and the height of the two solder pillars 14 is higher than that of the top cover plate 12.

[0058] Based on the above structure, the finished product of the TEC needs to be welded with wires to connect to the power supply. Therefore, the solder pillars are areas that do not require the parylene film layer. The top and bottom cover plates are heat transfer areas and also do not require the parylene film layer in order to reduce the thermal resistance. How to achieve the purpose of partially coating the parylene film layer on the TEC is one of the technical problems that the embodiments of the present invention at least solve.

[0059] Based on the above structure, the irregular surface of the TEC specifically refers to the irregular surface formed on the surface of the solder pillars. How to effectively remove the mask layer and the parylene film layer on the surface of the cover plate and the top of the solder pillars without damaging the cover plate and the solder pillars, and at the same time, the fracture interface of the film layer is neat and smooth, is one of the technical problems that the embodiments of the present invention at least solve.

[0060] Based on the above structure, the internal channel of the TEC specifically refers to the gap between the semiconductors between the upper and lower cover plates of the TEC. How to remove the mask layer and the parylene film layer on the surface of the cover plate and the top of the solder pillars without damaging the thickness of the parylene film layer in the gap is one of the technical problems that the embodiments of the present invention at least solve.

[0061] It should be noted that since the TEC itself is very small and the distance between the two solder posts is less than 1 mm, due to the mutual occlusion of the two solder posts, it is impossible to reach this area by laser or mechanical cutting methods.

[0062] Furthermore, in the prior art, the cutting depth is usually only 10 - 20 μm, so general cutting methods cannot completely remove the mask layer and the parylene film layer either.

[0063] Furthermore, the solder post substrate is made of gold-plated material, and the gold layer on its surface is thin and soft. Contact cutting is very likely to damage the gold layer, and the loss of the gold layer will cause the solder posts to be corroded during the use of the TEC.

[0064] The plasma etching adopted in the present invention has the characteristic of diffusivity, which can penetrate into the area occluded by the two solder posts and etch away the surface film layer. At the same time, the preferred etching process and gas composition have the dual functions of physical and chemical etching, which can effectively accelerate the etching speed.

[0065] The present invention provides a method for parylene coating and film removal of a micro-device with an internal channel and a special-shaped surface, including the following steps:

[0066] S101. Form a mask layer on the top surface of the micro-device, the bottom surface of the micro-device, and the top of the special-shaped surface;

[0067] S102. Coat the parylene film layer on the internal and external surfaces of the micro-device by chemical vapor deposition;

[0068] S103. Use laser to cut the sides of the top surface and the bottom surface of the micro-device, and then remove the mask layer and the parylene film layer on the top surface and the bottom surface of the micro-device;

[0069] S104. Completely wrap the micro-device inside a fixture, and the top of the special-shaped surface with the mask layer and the parylene film layer extends out of the top of the fixture;

[0070] S105. Use oxygen and argon to perform plasma etching on the top of the special-shaped surface to remove the mask layer and the parylene film layer, wherein the etching power is 1000 - 2000 w, the gas flow rate of oxygen is 60 - 200 sccm, and the gas flow rate of argon is 5 - 20 sccm.

[0071] In some embodiments, in S105, the mixing ratio of oxygen to argon is 3:1 - 40:1, which can be 3:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, and any value therebetween. Preferably, the mixing ratio of oxygen to argon is 19:1. The advantage of reasonably setting the mixing ratio of oxygen to argon in the present invention is that the etching rate can be increased. In the case of the same film thickness, the processing time can be shortened, thereby improving the production efficiency. Further, in the case of high etching efficiency, the etching time can be reduced, avoiding excessive heat accumulation at the etching interface during etching, and preventing the appearance quality of the device surface from being affected by abnormal colors and the like.

[0072] In some embodiments, in S105, the gas flow rate of oxygen is 60 - 200 sccm, which can be 60 sccm, 100 sccm, 150 sccm, 200 sccm, and any value therebetween. Preferably, the gas flow rate of oxygen is 95 sccm. The advantage of reasonably setting the gas flow rate of oxygen in plasma etching in the present invention is that the etching rate can be increased. The oxygen in the present invention is the gas source for ionization. The larger the flow rate, the more gas molecules available for ionization, the higher the plasma concentration, and the faster the etching rate. However, when exceeding the ionization ability limit of the electrode, continuing to increase the gas flow rate of oxygen will not increase the ionized ions, but instead block the plasma from reaching the film layer to be etched. The present invention optimizes the above situation by reasonably setting the gas flow rate of oxygen.

[0073] In some embodiments, in S105, the gas flow rate of argon is 5 - 20 sccm, which can be 5 sccm, 10 sccm, 15 sccm, 20 sccm, and any value therebetween. Preferably, the gas flow rate of argon is 5 sccm. The advantage of reasonably setting the gas flow rate of argon in plasma etching in the present invention is that the surface of the film layer can be activated. Argon plays a physical bombardment role in plasma etching, so argon is not consumed during etching. The loss of argon is mainly pumped away by the vacuum system, so only this part of the loss needs to be replenished. If the gas flow rate is too small, the consumed argon cannot be replenished, then the concentration of argon will become less and less, and the physical activation effect will gradually weaken. If the argon is too much, it will block the plasma, shorten the mean free path of the plasma, and reduce the etching rate. The present invention optimizes the above situation by reasonably setting the gas flow rate of argon.

[0074] The first reason for choosing oxygen in the present invention is that the film layer to be etched in the present invention is a parylene film layer. Parylene is an organic polymer material composed of carbon chains. Reactive oxygen can chemically react with it to generate gas and be evacuated by the vacuum system. The second reason is that oxygen is a common gas commonly used in industry, which does not require special container equipment. The exhaust gas generated by etching is non-toxic and harmless, with high economic efficiency and environmental friendliness.

[0075] The reason for choosing argon in the present invention is that argon is an inert gas with a large molecular weight. After ionization, it has a high kinetic energy, which is beneficial to physically activate the surface of the film layer.

[0076] Compared with the CF4 gas commonly used in plasma etching in the prior art, the etching gas of the technical solution of the present invention has significant economic benefits. Using argon and oxygen has low requirements for equipment and low equipment costs. Further, using argon and oxygen will not generate toxic and harmful exhaust gas, and has more advantages in environmental sustainability.

[0077] In some embodiments, in S105, the etching time is 6 - 10 hours, which can be 6 hours, 7 hours, 8 hours, 9 hours, 10 hours, and any value therebetween. Plasma etching is a way to remove the film layer at the molecular scale. As the etching progresses, the film layer will react gradually from the outer surface inward, generating gas and being evacuated by the vacuum system. The film layer protected by the fixture will not be etched, and a neat and smooth cross-sectional step will be formed at the interface. If the etching time is insufficient and the film layer is not completely removed, the film layer will be pulled when the mask is removed, deforming the interface. If the etching time is too long, the etching gas will etch the film layer at the cross-section of the film layer, resulting in the failure of fixture protection. The present invention reasonably controls the etching time of plasma etching, so that the plasma etching can completely remove the mask layer and parylene film layer on the irregular surface without film layer residue, and at the same time make the fracture interface of the film layer neat and smooth.

[0078] It should be noted that the etching time of the present invention depends on the thickness of the parylene film layer, and there is a positive correlation between the etching time and the thickness of the parylene film layer.

[0079] In some embodiments, the etching power is 1000 - 2000W, and it can be 1000W, 1200W, 1400W, 1600W, 1800W, 2000W, and any value between them. Preferably, the etching power is 1800W. The advantage of reasonably setting the etching power in the plasma etching of the present invention is that it can ensure a high etching rate while making the fracture interface of the film layer neat and smooth. The etching power not only provides the energy for gas molecule ionization but also accelerates the ionized ions. Therefore, an appropriate power can maintain a sufficient plasma concentration and also appropriately accelerate the plasma. Because too high ion energy will lead to too high bombardment energy of the ions on the film layer, resulting in too high temperature at the etching interface, causing the film layer to turn yellow or change color and even carbonize and turn black, resulting in black dust pollution of the product. In addition, too high plasma concentration or too high ion energy will lead to a weakening of the chemical etching effect and an increase in the physical bombardment effect, and the cross-section of the film layer will become rough and frosted. The present invention optimizes the above situation by reasonably setting the etching power.

[0080] In some embodiments, the etching pressure is 30 - 60Pa, and it can be 30Pa, 40Pa, 50Pa, 60Pa, and any value between them. Preferably, the etching pressure is 45Pa. The advantage of reasonably setting the etching pressure in the plasma etching of the present invention is that it can optimize the etching rate and etching result. An appropriate pressure can increase the mean free path of gas molecules, reduce the probability of plasma collision before reaching the etched surface, thereby improving the directionality and anisotropy of etching and enhancing the etching rate. At the same time, an appropriate pressure setting helps to reduce physical damage during etching and reduce the potential damage risk to the device.

[0081] It should be noted that in S101, the present invention does not particularly limit the material and specific formation method of the mask layer on the top surface and the bottom surface of the micro-device. Those well-known techniques in the art or commercially available products can be used. Preferably, a mask layer is formed on the top surface and the bottom surface of the micro-device using UV glue.

[0082] In some embodiments, in S101, a mask layer is formed on the top of the irregular surface using an acrylate adhesive. Preferably, the mask layer is composed of the following components by mass percentage: isobornyl acrylate 15 - 30%, polyurethane-modified methacrylic resin 45 - 65%, hexanediol diacrylate 5 - 15%, acrylic acid 5 - 10%, and adhesion promoter 0 - 1%.

[0083] In some embodiments, in S101, a mask layer is formed on the top of the irregular surface using the dipping method. The specific steps are as follows:

[0084] Completely immerse the top of the profiled surface into the acrylic adhesive, the thickness of the acrylic adhesive is 0.1-0.3mm;

[0085] The micro-device is pulled up so that the top of the irregular surface leaves the acrylic adhesive, and the acrylic adhesive uniformly wraps the top of the irregular surface;

[0086] The acrylate adhesive is cured to form a mask layer.

[0087] The present invention creatively adopts the pulling method to form a mask layer on the irregular surface, which can ensure that the irregular surface is evenly wrapped by the mask layer and the thickness of the mask layer in each area is consistent. If the thickness of the mask layer is inconsistent, during the plasma etching process, the thin position of the mask layer will be etched away by the plasma first, and then further etched to the gold layer of the solder column, causing the gold layer to appear different colors.

[0088] In some embodiments, in S102, the thickness of the parylene film layer is 10-25 μm. Preferably, the thickness of the parylene film layer is 15 μm. The present invention reasonably sets the thickness of the parylene film layer, and reasonably reduces the difficulty of removing the parylene film layer on the basis of ensuring the protective performance of the parylene.

[0089] In some embodiments, in S103, the laser is a pulsed laser with a wavelength of 355-1064nm, a pulse width of femtoseconds or picoseconds, a cutting power of 1-10W, and a cutting time of 30-120 seconds. Preferably, the laser is an ultraviolet laser with a wavelength of 355nm, a pulse width of 100 femtoseconds-20 picoseconds, a cutting power of 2W, and a cutting time of 120 seconds.

[0090] It should be noted that the cutting time of the present invention depends on the thickness of the parylene film layer, and the cutting time is positively correlated with the thickness of the parylene film layer.

[0091] In some embodiments, in S104, as Figure 2 As shown, the fixture 20 includes a substrate 21 and a sealing plate 22; the substrate 21 is provided with at least one blind hole matching the shape of the micro device; the sealing plate 22 is provided with a through hole corresponding to the blind hole; when the micro device is placed in the blind hole, the sealing plate 22 is covered on the top of the substrate 21 to close the blind hole, and the top of the profiled surface with the mask layer and the parylene film layer extends out of the through hole. Figure 2 As shown, the entire TEC is sealed in the fixture 20, with only the tops of the two solder pillars extending out of the through holes. The present invention adopts a special fixture design to prevent plasma from entering the gap between the semiconductors between the upper and lower cover plates of the TEC during the plasma etching process, thereby avoiding damage to the parylene film layer and ensuring that the internal coating still has good protective performance after etching.

[0092] In some embodiments, in S104, the fixture is made of silica gel with a Shore A hardness of 50 - 70 degrees. The reason for such a design in the present invention is that the silica gel material has certain elasticity and toughness, can completely fit the TEC, and prevent plasma from entering through the gaps of the fixture to damage the parylene layer.

[0093] Furthermore, silica gel is a soft material, which can effectively protect the TEC from being damaged by hard materials. If the fixture itself is made of hard materials, since the TEC is very small and difficult to operate, when the parylene film layer has been covered on the surface of the TEC, the film layer is easily damaged by the hard - material fixture, thus losing the protection effect.

[0094] Furthermore, although the molecular bond energy of the silica gel fixture is greater, chemical reactions rarely occur, so it will not be etched and can protect the area of the TEC that requires the parylene film layer.

[0095] In some embodiments, the size of the micro - device is 4×2×0.6 - 7×5×1.5 mm. The present invention can effectively coat and remove the parylene film layer on the micro - device with internal channels and irregular surfaces, and make the fracture interface of the film layer neat and smooth, improve the efficiency and accuracy of film removal, and at the same time greatly reduce the potential damage risk to the device.

[0096] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0097] Reference to "embodiments" in this document means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0098] Hereinafter, TEC (thermoelectric cooler) will be taken as an example to illustrate the technical solution of the present invention, but the following description does not limit the protection scope of the present invention. Among them, the mask layer in the embodiment and the comparative example is composed of the following components by mass percentage: isobornyl acrylate 20%, polyurethane - modified methacrylic resin 60%, hexanediol diacrylate 12%, acrylic acid 7%, and adhesion promoter 1%.

[0099] Example 1

[0100] S101. Form a mask layer on the top cover plate of the TEC, the bottom cover plate of the TEC, and the top of the TEC solder posts;

[0101] The mask layer is formed on the top of the TEC solder posts by the lifting method.

[0102] S102. Coat a parylene film layer on the inner and outer surfaces of the TEC by chemical vapor deposition;

[0103] The thickness of the parylene film layer is 15 μm.

[0104] S103. Use laser to cut the sides of the top cover plate and the bottom cover plate of the TEC, and then remove the mask layer and the parylene film layer on the top cover plate and the bottom cover plate of the TEC;

[0105] The laser is an ultraviolet laser with a wavelength of 355 nm, a pulse width of 15 picoseconds, a cutting power of 2 W, and a cutting time of 120 seconds.

[0106] S104. Completely wrap the TEC and place it inside the fixture, with the top of the solder posts having the mask layer and the parylene film layer protruding from the top of the fixture;

[0107] The fixture is made of silicone material with a Shore A hardness of 60 degrees.

[0108] S105. Use oxygen and argon to perform plasma etching on the top of the solder posts to remove the mask layer and the parylene film layer;

[0109] Among them, the etching power is 1800 w, the etching pressure is 45 Pa, the gas flow rate of oxygen is 95 sccm, the gas flow rate of argon is 5 sccm, the mixing ratio of oxygen to argon is 19:1, and the etching time is 8 hours.

[0110] Example 2

[0111] S101. Form a mask layer on the top cover plate of the TEC, the bottom cover plate of the TEC, and the top of the TEC solder posts;

[0112] The mask layer is formed on the top of the TEC solder posts by the lifting method.

[0113] S102. Coat a parylene film layer on the inner and outer surfaces of the TEC by chemical vapor deposition;

[0114] The thickness of the parylene film layer is 15 μm.

[0115] S103. Use laser to cut the sides of the top cover plate and the bottom cover plate of the TEC, and then remove the mask layer and the parylene film layer on the top cover plate and the bottom cover plate of the TEC;

[0116] The laser is an ultraviolet laser with a wavelength of 355 nm, a pulse width of 15 picoseconds, a cutting power of 2 W, and a cutting time of 120 seconds.

[0117] S104. Completely wrap the TEC and place it inside the fixture. The top of the solder column with the mask layer and the parylene film layer extends out of the top of the fixture.

[0118] The fixture is made of silicone material with a Shore A hardness of 60 degrees.

[0119] S105. Use oxygen and argon to perform plasma etching on the top of the solder column to remove the mask layer and the parylene film layer.

[0120] Among them, the etching power is 1200 w, the etching pressure is 45 Pa, the gas flow rate of oxygen is 95 sccm, the gas flow rate of argon is 5 sccm, the mixing ratio of oxygen to argon is 19:1, and the etching time is 8 hours.

[0121] Example 3

[0122] S101. Form a mask layer on the top cover of the TEC, the bottom cover of the TEC, and the top of the TEC solder column.

[0123] The mask layer is formed on the top of the TEC solder column by the lifting method.

[0124] S102. Use chemical vapor deposition to coat the parylene film layer on the inner and outer surfaces of the TEC.

[0125] The thickness of the parylene film layer is 15 μm.

[0126] S103. Use a laser to cut the sides of the top cover of the TEC and the bottom cover of the TEC, and then remove the mask layer and the parylene film layer on the top cover of the TEC and the bottom cover of the TEC.

[0127] The laser is an ultraviolet laser with a wavelength of 355 nm, a pulse width of 15 picoseconds, a cutting power of 2 W, and a cutting time of 120 seconds.

[0128] S104. Completely wrap the TEC and place it inside the fixture. The top of the solder column with the mask layer and the parylene film layer extends out of the top of the fixture.

[0129] The fixture is made of silicone material with a Shore A hardness of 60 degrees.

[0130] S105. Use oxygen and argon to perform plasma etching on the top of the solder column to remove the mask layer and the parylene film layer.

[0131] Among them, the etching power is 1800 w, the etching pressure is 30 Pa, the gas flow rate of oxygen is 60 sccm, the gas flow rate of argon is 5 sccm, the mixing ratio of oxygen to argon is 12:1, and the etching time is 8 hours.

[0132] Comparative Example 1

[0133] It is carried out according to the method of Example 1, except that in S101, a mask layer is formed on the top of the TEC solder column by the dispensing method. The specific operation of the dispensing method is as follows: 1. Put the product into the fixture of the automatic dispensing equipment; 2. Run the automatic dispensing program to seal the area to be masked with glue; 3. Cure with 365 nm UV light; 4. Remove the product.

[0134] Comparative Example 2

[0135] It is carried out according to the method of Example 1, except that in S105, the etching power is 2500 w.

[0136] Comparative Example 3

[0137] It is carried out according to the method of Example 1, except that in S105, the etching power is 500 w.

[0138] Comparative Example 4

[0139] It is carried out according to the method of Example 1, except that in S105, the etching pressure is 80 pa, the gas flow rate of oxygen is 250 sccm, the gas flow rate of argon is 5 sccm, and the mixing ratio of oxygen to argon is 50:1.

[0140] Comparative Example 5

[0141] It is carried out according to the method of Example 1, except that in S105, the etching pressure is 45 pa, the gas flow rate of oxygen is 50 sccm, the gas flow rate of argon is 50 sccm, and the mixing ratio of oxygen to argon is 1:1.

[0142] Test Example

[0143] The defilmed TECs obtained from the above examples and comparative examples were subjected to appearance inspection. The results of the appearance inspection are shown in Table 1. Among them, the method of appearance inspection is to fully inspect under a 10-fold microscope whether the fracture interface of the film layer on the top of the solder column is neat and smooth, whether there is film layer residue on the top of the solder column, and whether there is abnormal color on the gold layer on the top of the solder column.

[0144] It should be noted that the film layer residue of the TEC structure in Table 1 is divided into none, a small amount, and a large amount. None means that there is no film layer residue at this position or only a hardly observable film layer residue; a small amount means that there is a small area of observable film layer residue at this position, but it will not affect the subsequent use of the TEC and no further treatment is required; a large amount means that there is a large area of observable film layer residue at this position, which has affected the subsequent use of the TEC and further treatment is required to remove the residual film or it should be discarded as a defective product.

[0145] In the apparent fracture interface of the film layer of the TEC structure in Table 1, the slight warping and stretching of the film layer correspond to a small amount of film layer residue. The fracture interface of the film layer only has a small amount of burrs and warping, which will not affect the subsequent use of the TEC and no further treatment is required; the severe warping and stretching of the film layer correspond to a large amount of film layer residue. The fracture interface of the film layer has severe burrs and warping, and even exceeds the height of the solder column, which has affected the subsequent use of the TEC and further treatment is required to remove the residual film or it should be discarded as a defective product.

[0146] In the apparent different-color appearance of the TEC structure in Table 1, obvious different colors refer to that the area of different colors on the surface of the solder column is not large, but there are clear different-color points, which have a certain impact on the subsequent use of the TEC; severe different colors refer to that the surface of the solder column is basically completely covered by different colors, and this TEC is basically unusable subsequently.

[0147] Table 1

[0148]

[0149] The following are the apparent microscope images of the de-membraned TEC obtained from some examples and comparative examples.

[0150] Figure 3 and Figure 4 is the apparent microscope image of the de-membraned TEC obtained from Example 1. Under a 10-fold microscope, the fracture interface of the film layer at the top of the TEC solder column is neat and smooth, there is no film layer residue at the top of the solder column, and there is no different color at the top of the solder column.

[0151] Figure 5 is the apparent microscope image of the de-membraned TEC obtained from Example 2. Under a 10-fold microscope, there is slight warping and stretching of the film layer at the fracture interface of the film layer at the top of the TEC solder column, there is a small amount of film layer residue at the top of the solder column, and there is no different color at the top of the solder column. It can be seen from the figure that there is a small amount of film layer residue on both the left and right solder columns, and at the same time, the film layer on the right solder column has slight warping and stretching.

[0152] Figure 6The figure shows the appearance microscope image of the de-coated TEC obtained by Comparative Example 1. Under a 10x microscope, the fracture interface of the film layer on the top of the TEC solder column is neat and smooth, there is no film layer residue on the top of the solder column, and there is abnormal color on the top of the solder column. Since the mask layer is formed by the dispensing method, the thickness of the mask layer is inconsistent in some areas, especially in the corner areas. During the plasma etching process, the position with a thin mask layer will be etched away by the plasma, and then the gold layer of the solder column will be further etched, resulting in obvious abnormal color of the gold layer.

[0153] Figure 7 and Figure 8 The figure shows the appearance microscope image of the de-coated TEC obtained by Comparative Example 2. Under a 10x microscope, the fracture interface of the film layer on the top of the TEC solder column is rough and frosted, and at the same time the film layer turns yellow and discolored. There is no film layer residue on the top of the solder column, and there is serious abnormal color on the top of the solder column. It can be seen that when the technical solution of the present invention is not adopted, for example, when the etching power is significantly higher than the scope protected by the present invention, the corresponding technical effect cannot be achieved, and the technical problem to be solved by the present invention cannot be solved.

[0154] Figure 9 The figure shows the appearance microscope image of the de-coated TEC obtained by Comparative Example 4. Under a 10x microscope, there is serious warping and stretching of the film layer at the fracture interface of the film layer on the top of the TEC solder column, there is a large amount of film layer residue on the top of the solder column, and there is no abnormal color on the top of the solder column. It can be seen that when the technical solution of the present invention is not adopted, for example, when the etching pressure and the gas flow rate of the etching gas are significantly higher than the scope protected by the present invention, the corresponding technical effect cannot be achieved, and the technical problem to be solved by the present invention cannot be solved.

[0155] From the above results, it can be seen that compared with the comparative examples, by adopting the embodiment scheme of the present invention, it is possible to effectively coat and remove the parylene film layer on the micro-device with internal channels and irregular surfaces, and make the fracture interface of the film layer neat and smooth, improve the film removal efficiency and accuracy, and at the same time reduce the potential damage risk to the device.

[0156] Furthermore, according to Example 1 and Examples 2-3, it can be seen that by adopting the preferred etching process of the present invention, with the etching power, etching pressure and mixing ratio of oxygen and argon under the preferred values, through the synergistic effect of the three, the fracture interface of the film layer can be made more neat and smooth, more effectively improve the film removal efficiency and accuracy, and at the same time greatly reduce the potential damage risk to the device.

[0157] Furthermore, in order to specifically verify the technical effect of the fixture design of the present invention, the present invention conducted a performance test on the de-coated TEC obtained in Example 1. At this time, the fixture material was silica gel.

[0158] Redesign Comparative Example 6. Comparative Example 6 was carried out with reference to Example 1, except that the jig material at this time was aluminum with surface anodic oxidation treatment. The performance of the TEC after film removal of the obtained Comparative Example 6 was tested.

[0159] The test results of the protection performance of the TEC after film removal with different jig designs are shown in Table 2. The protection performance tested includes salt spray resistance and insulation withstand voltage performance.

[0160] Among them, the test method for salt spray resistance specifically refers to GB / T10125. After 48h of salt spray resistance test, check the appearance of the internal channels. If there is no rust or corrosion, it is qualified; if there is rust or corrosion, it is unqualified.

[0161] The test method for insulation withstand voltage performance includes connecting the negative pole of a withstand voltage tester to a welding post and the positive pole of the withstand voltage tester contacting the film layer. Specifically refer to GB / T1408.1-2016. After the insulation withstand voltage performance test, if the film layer can reach the breakdown voltage of 2500v, DC on the plane, it is qualified; if it is lower than this value, it is unqualified.

[0162] Table 2

[0163]

[0164] It can be seen that the jig design adopting the technical solution of the present invention can avoid plasma from entering the internal channels of the micro-devices during plasma etching, avoid damaging the parylene film layer of the internal channels, and ensure that the internal coating still has good protection performance after etching.

[0165] After uncovering the top cover plate of the TEC after film removal with different jig designs, measure the parylene film layer thickness at each position of the internal channels. The specific results are shown in Table 3. Among them, the parylene film layer thickness at each position in Table 3 was measured by the method of microtomy, specifically including embedding the sample, grinding, polishing, and then observing and measuring the film layer thickness under a microscope. Specifically refer to IPC TM-650 2.1.1.F.

[0166] Table 3

[0167]

[0168] As Figure 10 shown, Figure 10This is a schematic diagram of various positions of the internal channel of the TEC after the top cover plate is removed after the film is removed in Example 6. Positions 1-4 are the outer ring positions of the TEC, and the thickness of the parylene film should be consistent or close. Because the fixture is made of aluminum with anodized surface, the four positions are not completely sealed and there are gaps. During the plasma etching process, the plasma enters the four positions and etches away part of the film layer. The film thickness of the four positions is damaged to varying degrees, affecting the protective performance of the film layer. Among them, the film thickness of positions 3 and 4 is more significantly reduced.

[0169] The above results show that when the jig material is aluminum with anodized surface, it cannot be closely attached to TEC, resulting in a gap between the jig and TEC. Plasma enters the internal channel through the gap and corrodes part of the film layer. However, the silicone jig has good sealing performance and the film layer of the internal channel is not corroded. The special jig design of the present invention can prevent plasma from entering the internal channel of the micro device during plasma etching, avoid damaging the parylene film layer of the internal channel, and ensure that the internal coating still has good protective performance after etching.

[0170] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for coating and removing parylene from a micro device having an internal channel and a profiled surface, characterized in that: The following steps are involved: S101, forming a mask layer on the top surface of the micro device, the bottom surface of the micro device and the top of the special-shaped surface; S102, coating the inner and outer surfaces of the micro-device with a parylene film layer by a vapor deposition method; S103, cutting the sides of the top surface of the micro device and the bottom surface of the micro device by laser, and then removing the mask layer and the parylene film layer on the top surface of the micro device and the bottom surface of the micro device; S104, completely wrapping the micro device and placing it inside a jig, with the top of the special-shaped surface having the mask layer and the parylene film layer extending out of the top of the jig; S105, plasma etching the top of the irregular surface with oxygen and argon to remove the mask layer and the parylene film layer, wherein the etching power is 1000-2000w, the gas flow rate of oxygen is 60-200sccm, and the gas flow rate of argon is 5-20sccm.

2. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S105, the mixing ratio of oxygen to argon is 3:1-40:

1.

3. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to any one of claims 1 or 2, characterized in that: In S105, the etching pressure is 30-60Pa.

4. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S105 , the etching time is 6-10 hours.

5. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S101 , a mask layer is formed on the top surface of the micro device and the bottom surface of the micro device using glue or tape material.

6. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S101, an acrylic adhesive is used to form a mask layer on the top of the irregular surface.

7. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 6, characterized in that: In S101, a mask layer is formed on the top of the irregular surface by using a Czochralski method, and the specific steps are as follows: The top of the special-shaped surface is completely immersed in the acrylic adhesive, the thickness of the acrylic adhesive is 0.1-0.3 mm; Pulling up the micro-device so that the top of the irregular surface leaves the acrylic adhesive, and the acrylic adhesive uniformly wraps the top of the irregular surface; The acrylate adhesive is cured to form a mask layer.

8. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S102, the thickness of the parylene film layer is 10-25 μm.

9. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S103, the laser is a pulse laser with a wavelength of 355-1064 nm, a pulse width of femtosecond or picosecond level, a cutting power of 1-10 W, and a cutting time of 30-120 seconds.

10. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to claim 1, characterized in that: In S104, the fixture includes: A substrate, wherein at least one blind hole matching the shape of the micro-device is formed on the substrate; A sealing plate, wherein the sealing plate is provided with through holes corresponding to the blind holes; Wherein, after the micro device is placed in the blind hole, the sealing plate cover is arranged on the top of the substrate to close the blind hole, and the top of the special-shaped surface with the mask layer and the parylene film layer protrudes out of the through hole.

11. The method for coating and removing parylene from a micro device having an internal channel and a profiled surface according to any one of claims 1 or 10, characterized in that: In S104, the fixture is made of silicone with a Shore A hardness of 50-70 degrees.

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