Data transmission power optimization

Abstract

Systems and methods for data transmission power optimization are disclosed. In one aspect, the system combines signals from multiple narrowband channels in a radio frequency (RF) integrated circuit (IC) (RFIC) into a single shared buffer and uniformly distributes packets to modem circuits based on the signals across channels in a communication bus. Such uniform utilization of the lanes of the bus allows an idle period to occur on the bus during which a low power state or a sleep state may be used to reduce power consumption.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 821,935, filed on August 24, 2022, entitled “DATA TRANSMISSION POWEROPTIMIZATION,” which is incorporated herein by reference in its entirety. Background Art

[0003] I. Technical field

[0004] The technology of the present disclosure relates generally to communication buses, and more particularly to ways to optimize power consumption of communication buses.

[0005] II. Background

[0006] Computing devices, and more specifically mobile communication devices, are ubiquitous in modern society and have become increasingly common. The popularity of these mobile communication devices is due in part to the many features now enabled on such devices. The increased processing power in such devices has meant that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, enabling an enhanced user experience. With the advent of the myriad of features available for such devices, the pressure to find ways to reduce power consumption has become greater and greater. One way in which power consumption has been reduced is to put circuits and communication links into a sleep state or to change the duty cycle of the communication link. Reducing the duty cycle of a communication link creates its own challenges. Summary of the invention

[0007] Various aspects disclosed in the detailed description include systems and methods for data transmission power optimization. More specifically, exemplary aspects of the present disclosure combine signals from multiple narrowband channels in a radio frequency (RF) integrated circuit (IC) (RFIC) into a single shared buffer and distribute packets evenly to modem circuits based on the signals across the channels in a communication bus. Such even utilization of the channels of the bus allows idle periods to occur on the bus, during which low power states or sleep states can be used to reduce power consumption.

[0008] In this regard, in one aspect, an IC is disclosed. The IC includes a bus interface configured to be coupled to a plurality of channels in a communication bus. The IC also includes a memory structure, which includes a plurality of memory banks. The memory structure is configured to receive a first packet from a channel, divide the first packet into a plurality of cells equal in number to the plurality of memory banks, and store the plurality of cells into corresponding memory banks in the plurality of memory banks. The IC also includes a multiplexer associated with the memory structure and the bus interface. The multiplexer is configured to reassemble the first packets from the plurality of memory banks and route the first packets to the channels in the communication bus through the bus interface.

[0009] In another aspect, an IC is disclosed. The IC includes a bus interface configured to be coupled to a plurality of channels in a communication bus. The IC also includes a crossbar switch coupled to the bus interface. The crossbar switch is configured to receive a first packet from a first channel, read a channel identifier in the first packet, and route the first packet to a first memory based on the channel identifier.

[0010] In another aspect, a method for saving power is disclosed. The method includes aggregating packets from multiple channels into a shared memory structure. The method also includes draining the packets from the shared memory structure onto a channel of a communication bus. The method also includes putting the communication bus to sleep when the shared memory structure is drained.

[0011] On the other hand, a computing device is disclosed. The computing device includes a communication bus, which includes multiple channels. The computing device also includes a radio frequency (RF) IC (RFIC). The RFIC includes a first bus interface coupled to the communication bus and a memory structure having multiple memory banks. The memory structure is configured to receive a first packet from the channel, divide the first packet into multiple units equal in number to the multiple memory banks, and store the multiple units in corresponding memory banks in the multiple memory banks. The RFIC also includes a multiplexer associated with the memory structure and the first bus interface. The multiplexer is configured to reassemble the first packet from the multiple memory banks and route the first packet to the channel. The computing device also includes a modem IC. The modem IC includes a second bus interface coupled to the communication bus and a cross switch configured to route incoming packets from the communication bus to the memory for further processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of an exemplary mobile communication device that may include a radio frequency (RF) integrated circuit (IC) (RFIC) and modem circuitry;

[0013] Figure 2is a block diagram showing more details about the RFIC-modem circuit link;

[0014] Figure 3 is a block diagram illustrating how an RFIC may use a memory structure to segment signal packets according to an exemplary aspect of the present disclosure;

[0015] Figure 4 is to show how multiple signals can be grouped and loaded into Figure 3 A block diagram of the memory structure of FIG.

[0016] FIG. 5A to FIG. 5D A stylized block diagram is provided of how packets may be reassembled from a memory structure and placed on a channel of a communication bus;

[0017] FIG. 6A to FIG. 6C A stylized block diagram is provided of how multiple packets may be reassembled and placed on different lanes of a communication bus;

[0018] Figure 7 A block diagram of a modem circuit for routing reassembled packets from channels on a communications bus is provided; and

[0019] Figure 8 is a flow chart illustrating an exemplary process for putting a communication bus to sleep when a memory structure is drained. DETAILED DESCRIPTION

[0020] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Various aspects disclosed herein include systems and methods for data transmission power optimization. More specifically, exemplary aspects of the present disclosure combine signals from multiple narrowband channels in a radio frequency (RF) integrated circuit (IC) (RFIC) into a single shared buffer and distribute packets evenly to modem circuits based on the signals across the channels in a communication bus. Such even utilization of the channels of the bus allows idle periods to occur on the bus, during which low power states or sleep states can be used to reduce power consumption.

[0022] Before addressing certain aspects of the present disclosure, reference is made to Figure 1 and Figure 2 A brief overview of the context of a system using exemplary aspects of the present disclosure is provided, as well as a further discussion of the poor power optimization that may be found in conventional systems. Figure 3 Let's start discussing the details of this disclosure.

[0023] In this regard, Figure 1 1 is a system-level block diagram of an exemplary mobile terminal 100, such as a smartphone, a mobile computing device tablet, etc. The mobile terminal 100 includes an application processor 104 (sometimes referred to as a host) that communicates with a mass storage element 106 via a universal flash memory (UFS) bus 108. The application processor 104 may further be connected to a display 110 via a display serial interface (DSI) bus 112, and to a camera 114 via a camera serial interface (CSI) bus 116. Various audio elements, such as a microphone 118, a speaker 120, and an audio codec 122, may be coupled to the application processor 104 via a serial low-power chip-to-chip multimedia bus (SLIMbus) 124. In addition, the audio elements may communicate with each other via a SOUNDWIRE bus 126. A modem 128 may also be coupled to the SLIMbus 124 and / or the SOUNDWIRE bus 126. Modem 128 may further be connected to application processor 104 via a peripheral component interconnect (PCI) or PCI Express (PCIe) bus 130 and / or a system power management interface (SPMI) bus 132 .

[0024] Continue to refer Figure 1 , the SPMI bus 132 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 134, a power management integrated circuit (PMIC) 136, a companion IC (sometimes referred to as a bridge chip) 138, and an RFIC 140. It should be understood that separate PCI buses 142 and 144 may also couple the application processor 104 to the companion IC 138 and the WLAN IC 134. The application processor 104 may further be connected to a sensor 146 via a sensor bus 148. The modem 128 and the RFIC 140 may communicate using a bus 150 (sometimes referred to as a communication bus).

[0025] Continue to refer Figure 1 , RFIC 140 may be coupled to one or more RFFE elements, such as antenna tuner 152, switch 154, and power amplifier 156, via a radio frequency front end (RFFE) bus 158. Additionally, RFIC 140 may be coupled to envelope tracking power supply (ETPS) 160 via bus 162, and ETPS 160 may communicate with power amplifier 156. Together, these RFFE elements (including RFIC 140) may be considered an RFFE system 164. It should be understood that RFFE bus 158 may be formed of clock lines and data lines (not illustrated).

[0026] There may be multiple communication channels between the modem 128 and the RFIC 140. These channels are carried through physical links or channels of conductive material (e.g., copper wires). Figure 2 This is better illustrated in FIG. 1 , where the modem 128 (in Figure 2 ) is coupled to the RFIC 140 (in Figure 2 The bus is also named RC), which is composed of multiple channels 200(1)-200(N) (usually a single channel is channel 200), where each channel 200 is a physical electrical conductor.

[0027] Continue to refer Figure 2 , the modem 128 may include a control circuit 202 that works with a frequency domain (FD) processing circuit 204 that may include a fast Fourier transform (FFT) circuit 206 that acquires signals in the time domain and transforms them into the frequency domain. The FFT circuit 206 receives signals via a bus interface 208 that is configured to be coupled to the bus 150.

[0028] Continue to refer Figure 2 , RFIC 140 may be configured to couple to bus 150 via bus interface 210. RFIC 140 may also include control circuitry 212 that works in conjunction with digital front end circuitry 214 that may include time domain digital processing circuitry and analog processing circuitry 216 that may handle RF, intermediate frequency (IF), and baseband (BB) frequencies (and may therefore be referred to as RF analog processing circuitry or RF analog processing circuitry). Note that the precise division of what frequencies are handled in RFIC 140 relative to modem 128 is not central to the present disclosure, and the precise nature of circuits 214 and 216 may vary without departing from the present disclosure. RFIC 140 may receive signals from an antenna (such as a Figure 1 152). The RF signal may include a plurality of narrowband channels to be delivered to the modem 128. The signal may be processed by the circuits 214, 216, including assembling the signal into packets such as by an aggregation process (e.g., buffering a certain number of bits of the signal and then forming the packet with a header and bits of the signal as a payload), and then multiplexed by a multiplexer 218 (also referred to as a means for multiplexing) into a memory structure 220 (also referred to as a means for storing data). The signal is then read out of the memory structure 220 and delivered to the channel circuitry, which may include the bus interface 210, and thus to the channels 200(1)-200(N), through a second multiplexer 222, as better explained below.

[0029] In the absence of the present disclosure, channels can be assigned to specific channels on the bus. Based on the bandwidth requirements associated with the channels, channel usage may be uneven. For example, one channel may use twice the bandwidth of another channel. This difference in bandwidth translates into more packets transmitted on one channel than on another channel. Generally speaking, when a channel is active, the entire communication bus is considered active and consumes power. Therefore, the circuits associated with the idle channel are still active and consume power, even if no business occurs on the channel. That is, in conventional systems, the bus can be placed in low power mode or sleep mode only when all channels are idle. This limited low power option consumes power unnecessarily, which is generally undesirable in mobile terminals.

[0030] Exemplary aspects of the present disclosure combine channels into the memory structure 220 and distribute packets from the memory structure 220 evenly across the channels 200(1)-200(N) so that despite the different channel bandwidths, the channels 200(1)-200(N) are typically idle at the same time and for the same duration, thereby allowing for more frequent and / or longer sleep or low power modes of the communication bus 150. It should be understood that the memory structure 220 includes interfaces, such as input / output (I / O) pins (not explicitly shown and sometimes referred to as components for receiving packets), etc., configured to receive packets from the channels.

[0031] Figure 3 An exemplary technique for loading a packet 300 into a memory structure 220 is shown. Specifically, the packet 300 contains a portion of a signal from a channel, which in exemplary aspects is a narrowband channel. The packet 300 can be conceptually divided into equal-sized cells 302(1)-302(M) by a signal divider (not explicitly shown and sometimes referred to as a component for dividing). Similarly, the memory structure 220 can have M memory banks 304(0)-304(M-1) (also referred to as a component for storing multiple cells 302(1)-302(M)). Each cell 302(1)-302(M) is written to a corresponding memory bank 304(0)-304(M-1). More specifically, assuming there are M memory banks 304(0)-304(M-1), the packet 300 is divided into M cells 302(1)-302(M), and then the M cells are written to the corresponding memory banks 304(0)-304(M-1). It should be understood that the multiple memory banks 304(0)-304(M-1) can be considered parallel to each other.

[0032] If only a single channel exists, aspects of the present disclosure may still be valuable in extending signaling to all channels, but exemplary aspects of the present disclosure are well suited for operations that combine packets from multiple channels, such as in Figure 4 2. As shown in FIG. 2, the signals within channels 400(1)-400(K) are processed and aggregated by circuits 214, 216 to generate corresponding packets 300(1)-300(K). Multiplexer 218 may aggregate packets 300(1)-300(K) via an arbitration protocol that is used to arbitrate between channels to select packets 300 from within packets 300(1)-300(K) to be written to memory structure 220. As described above, each of packets 300(1)-300(K) is divided into M units 302(1)-302(M) and written to memory banks 304(0)-304(M-1). Exemplary arbitration schemes include round robin, weighting based on certain quality of service (QoS) requirements, weighted round robin based on bandwidth, and the like.

[0033] Although Figure 4 2, multiplexer 222 may also include an arbiter that selects an available channel 200 among the plurality of channels 200(1)-200(N) on which to transmit packet 300 from memory structure 220. Again, arbitration may be round-robin, weighted round-robin, etc.

[0034] Once arbitration has selected a channel 200 on which to transmit packet 300, channel 200 begins pulling cells 302(1)-302(M) from banks 304(0)-304(M-1) of memory structure 220, as shown in FIG. FIG. 5A to FIG. 5D Specifically, channel 200 has been selected by the arbitration scheme and the first memory bank 304 (0) is read, so that cell 302 (1) (in FIG. 5A to FIG. 5D is also D0 in the first clock cycle and is pulled to channel 200 (see Figure 5A ). As used herein, reading data from memory banks 304(0)-304(M-1) and pulling that data onto channel 200 may be referred to as "draining". Such terminology is based on an analogy with a tank (repository) that is filled with liquid (data) and drained into a single pipe (channel). Optionally, the first memory bank 304(0) may be rewritten immediately after being read, or memory bank 304(0) may remain unchanged until a subsequent write operation. On the next clock cycle, channel 200 writes data to the second memory bank 304(1) (see Figure 5B ) is discharged to pull unit 302 (2) (also D1) onto channel 200. Figure 5C The third memory bank 304(2) is shown being drained onto channel 200 on the next clock cycle. Thus, channel 200 steps through memory banks 304(0)-304(M-1), draining each memory bank in turn on sequential clock cycles until, as shown in FIG. Figure 5DAs shown, packet 300 has been reassembled and transmitted via bus 150 to modem 128.

[0035] FIG. 6A to FIG. 6C The same concept is shown applied to multiple channels 200(1)-200(3) operating concurrently to drain the memory structure 220. Fig. 6A , channel 200(1) has won arbitration (with respect to channel 200(2)) and begins draining first bank 304(0). At the next clock cycle, channel 200(2) now wins arbitration (without competing channels for the purposes of this example) and drains first bank 304(0), while first channel 200(1) drains second bank 304(1). These channels 200(1)-200(2) step through banks 304(0)-304(M-1) of memory structure 220 until, as shown in FIG. Figure 6C As shown, at some subsequent time (in this case, M-1 clock cycles after channel 200(1) won the first arbitration), another channel 200(3) wins arbitration against another channel 200(X) (not shown) and drains the first memory bank 304(0). Concurrently, channel 200(1) is draining the last memory bank 304(M-1) and channel 200(2) is draining memory bank 304(M-2). After draining the entire packet has been completed, channel 200(1) is then available to participate in arbitration against channel 200(4) (which, in this example, lost the previous arbitration and automatically re-enters the next arbitration). It should be understood that an arbitration may include more than two available channels.

[0036] Figure 7 Additional details are provided regarding the routing of packets received at modem 128. Modem 128 receives packets from channels 200(1)-200(N) via bus interface 208, and crossbar switch 700 may examine a channel identifier in the packet to route the packet to a memory bank 702(X) within a plurality of memory banks 702(1)-702(N) corresponding to a particular channel. Note that the channel identifier may be inserted when the packet is written to memory structure 220. Control circuitry 202 may be used to control crossbar switch 700.

[0037] Figure 8A flow chart of a process 800 is provided for placing the bus 150 in a low power mode or sleep mode. Specifically, the process 800 begins with data or packets being buffered in the shared memory structure 220 (block 802). The channels 200(1)-200(N) drain the shared memory structure 220 (block 804). When the memory structure 220 is drained, the bus 150 is placed in a sleep state (block 806). The data or packets are buffered in the memory structure 220 until a threshold has been exceeded (block 808) and the bus 150 is awakened (block 810). The channels 200(1)-200(N) drain the shared memory structure 220 (block 812), and the process 800 repeats at block 806.

[0038] It will be further understood by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of the two. As an example, the master device and slave device described herein may be employed in any circuit, hardware component, integrated circuit (IC) or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0039] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0040] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0041] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operation can be performed in many different orders except for the illustrated order. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. It will be equally understood by those skilled in the art that any of a variety of different technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0042] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0043] Specific implementation examples are described in the following numbered clauses:

[0044] 1. An integrated circuit (IC), comprising:

[0045] a bus interface configured to couple to a plurality of channels in a communication bus;

[0046] A memory structure, the memory structure comprising a plurality of memory banks, the memory structure being configured as follows:

[0047] receiving a first packet from the channel, and

[0048] dividing the first group into a plurality of units equal in number to the plurality of memory banks; and

[0049] storing the plurality of cells into corresponding memory banks among the plurality of memory banks; and

[0050] A multiplexer is associated with the memory structure and the bus interface, the multiplexer being configured to reassemble the first packets from the plurality of memory banks and route the first packets to channels in the communication bus through the bus interface.

[0051] 2. The IC of clause 1, wherein each cell of the plurality of cells has a uniform size.

[0052] 3. An IC according to clause 1 or 2, wherein the channel comprises a narrowband channel.

[0053] 4. An IC according to any preceding clause, further comprising a time-domain digital processing circuit, the time-domain digital processing circuit being configured to operate on a radio frequency (RF) signal received via an antenna.

[0054] 5. An IC according to any one of clauses 1 to 3, further comprising a radio frequency (RF) analog processing circuit configured to operate on an RF signal received via an antenna.

[0055] 6. An IC according to any preceding clause, further comprising a channel circuit configured to output a plurality of channels including the channel; and

[0056] A second multiplexer couples the channel circuit to the memory structure.

[0057] 7. The IC of clause 6, wherein the plurality of channels provide a plurality of packets including the first packet to the memory structure.

[0058] 8. The IC of clause 7, wherein the multiplexer is configured to reassemble each of the plurality of packets and route each of the plurality of packets to the bus interface.

[0059] 9. The IC of any preceding clause, further comprising an arbitrator configured to assign the first packet to the lane of the plurality of lanes.

[0060] 10. An IC according to any preceding clause, wherein the memory structure is further configured to add a channel identifier to the first packet to identify the channel.

[0061] 11. An IC according to any preceding clause, further comprising a control circuit configured to place the bus interface into a low power mode when the memory structure is empty.

[0062] 12. An IC according to any preceding clause, integrated into a radio frequency (RF) IC (RFIC).

[0063] 13. An integrated circuit (IC), comprising:

[0064] a bus interface configured to couple to a plurality of channels in a communications bus; and

[0065] a crossbar switch coupled to the bus interface and configured to:

[0066] receiving a first packet from a first channel;

[0067] reading a channel identifier in the first packet; and

[0068] The first packet is routed to a first memory based on the channel identifier. 14. The IC of clause 13, integrated into a modem.

[0069] 15. An IC according to clause 13 or 14, wherein the crossbar switch is further configured to:

[0070] receiving a second packet from a second channel;

[0071] reading a second channel identifier in the second packet; and

[0072] A determination is made that the second packet is routed to the first memory.

[0073] 16. An IC as described in any of clauses 13 to 15, further comprising frequency domain processing circuitry configured to operate on the first packet in the frequency domain.

[0074] 17. An IC as described in any of clauses 13 to 16, wherein the bus interface is configured to enter a low power mode when no packets are present on the communication bus.

[0075] 18. A method for saving power, the method comprising:

[0076] Aggregating packets from multiple channels into a shared memory structure;

[0077] draining the packets from the shared memory structure onto a lane of a communication bus; and

[0078] When the shared memory structure is drained, the communication bus is placed in a sleep state.

[0079] 19. The method of clause 18, further comprising partitioning the packets into corresponding databases within the shared memory structure.

[0080] 20. The method of clause 18 or 19, further comprising arbitrating between the plurality of channels when the packets are aggregated into the shared memory structure.

[0081] 21. The method of any of clauses 18 to 20, further comprising arbitrating between the lanes of the communication bus when draining the packets from the shared memory structure.

[0082] 22. The method of any of clauses 18 to 21, wherein aggregating the packets into the shared memory structure comprises aggregating the packets in a plurality of parallel memory banks.

[0083] 23. The method of clause 22, wherein aggregating the packets in the plurality of parallel memory banks comprises dividing the packets into a plurality of cells and spreading the plurality of cells across the plurality of parallel memory banks.

[0084] 24. The method of any of clauses 18 to 23, wherein draining the packets onto the lanes of the communications bus comprises draining a first packet onto a single lane of the communications bus.

[0085] 25. A computing device, the computing device comprising:

[0086] a communication bus, the communication bus comprising a plurality of channels;

[0087] Radio frequency (RF) integrated circuit (IC) (RFIC), the radio frequency (RF) integrated

[0088] Circuit (IC) (RFIC) includes:

[0089] a first bus interface coupled to the communication bus;

[0090] A memory structure, the memory structure comprising a plurality of memory banks, the memory structure being configured as follows:

[0091] receiving a first packet from a channel;

[0092] dividing the first group into a plurality of units equal in number to the plurality of memory banks; and

[0093] storing the plurality of cells into corresponding memory banks among the plurality of memory banks; and

[0094] A multiplexer, the multiplexer and the memory structure and the

[0095] associated with a first bus interface, the multiplexer being configured to reassemble the first packets from the plurality of memory banks and route the first packets to a channel; and

[0096] A modem IC, the modem IC comprising:

[0097] a second bus interface coupled to the communications bus; and

[0098] A crossbar switch is configured to route incoming packets from the communication bus to a memory for further processing.

[0099] 26. An integrated circuit (IC), comprising:

[0100] means for conveying a signal comprising a plurality of channels;

[0101] A component for storing data including a plurality of memory banks, the memory structure comprising:

[0103] means for receiving a first packet from a channel;

[0104] means for dividing the first group into a plurality of cells equal in number to the plurality of memory banks; and

[0105] means for storing the plurality of cells into corresponding memory banks among the plurality of memory banks; and

[0106] A multiplexing component is associated with the component for storing data and the component for transmitting signals, and the multiplexing component is configured to reassemble the first packets from the plurality of storage bodies and route the first packets to channels in the component for transmitting signals.

Claims

1. An integrated circuit (IC), comprising: a bus interface configured to couple to a plurality of channels in a communication bus; A memory structure, the memory structure comprising a plurality of memory banks, the memory structure being configured as follows: receiving a first packet from the channel, and dividing the first group into a plurality of units equal in number to the plurality of memory banks; as well as storing the plurality of cells into corresponding memory banks among the plurality of memory banks; and A multiplexer is associated with the memory structure and the bus interface, the multiplexer being configured to reassemble the first packets from the plurality of memory banks and route the first packets to channels in the communication bus through the bus interface. 2 . The IC of claim 1 , wherein each of the plurality of cells has a uniform size.

3. The IC of claim 1, wherein the channel comprises a narrowband channel.

4. The IC of claim 1, further comprising a time-domain digital processing circuit configured to operate on a radio frequency (RF) signal received via an antenna.

5. The IC of claim 1, further comprising a radio frequency (RF) analog processing circuit configured to operate on an RF signal received via an antenna.

6. The IC of claim 1 , further comprising a channel circuit configured to output a plurality of channels including the channel; and A second multiplexer couples the channel circuit to the memory structure.

7. The IC of claim 6, wherein the plurality of channels provide a plurality of packets including the first packet to the memory structure.

8. The IC of claim 7, wherein the multiplexer is configured to reassemble each of the plurality of packets and route each of the plurality of packets to the bus interface.

9. The IC of claim 1, further comprising an arbitrator configured to assign the first packet to the lane of the plurality of lanes.

10. The IC of claim 1, wherein the memory structure is further configured to add a channel identifier to the first packet to identify the channel.

11. The IC of claim 1 , further comprising a control circuit configured to place the bus interface into a low power mode when the memory structure is empty.

12. The IC of claim 1, the IC being integrated into a radio frequency (RF) IC (RFIC).

13. An integrated circuit (IC), comprising: a bus interface configured to couple to a plurality of channels in a communication bus; and a crossbar switch coupled to the bus interface and configured to: receiving a first packet from a first channel; reading a channel identifier in the first packet; and The first packet is routed to a first memory based on the channel identifier.

14. The IC of claim 13, integrated into a modem.

15. The IC of claim 13, wherein the crossbar switch is further configured to: receiving a second packet from a second channel; reading a second channel identifier in the second packet; and A determination is made that the second packet is routed to the first memory.

16. The IC of claim 13, further comprising a frequency domain processing circuit configured to operate on the first packet in the frequency domain.

17. The IC of claim 13, wherein the bus interface is configured to enter a low power mode when no packets are present on the communication bus.

18. A method for saving power, the method comprising: Aggregating packets from multiple channels into a shared memory structure; draining the packets from the shared memory structure onto a channel of a communication bus; as well as When the shared memory structure is drained, the communication bus is placed in a sleep state.

19. The method of claim 18, further comprising partitioning the packets into corresponding databases within the shared memory structure.

20. The method according to claim 18, further comprising: When the packets are aggregated into the shared memory structure, arbitration is performed between the plurality of channels.

21. The method of claim 18, further comprising arbitrating between the lanes of the communication bus when draining the packets from the shared memory structure.

22. The method of claim 18, wherein aggregating the packets into the shared memory structure comprises aggregating the packets in a plurality of parallel memory banks.

23. The method of claim 22, wherein aggregating the packets in the plurality of parallel memory banks comprises dividing the packets into a plurality of cells and spreading the plurality of cells across the plurality of parallel memory banks.

24. The method of claim 18, wherein flushing the packets onto the lanes of the communication bus comprises flushing a first packet onto a single lane of the communication bus.

25. A computing device, the computing device comprising: a communication bus, the communication bus comprising a plurality of channels; A radio frequency (RF) integrated circuit (IC) (RFIC), the radio frequency (RF) integrated circuit (IC) (RFIC) comprising: a first bus interface coupled to the communication bus; A memory structure, the memory structure comprising a plurality of memory banks, the memory structure being configured as follows: receiving a first packet from a channel; dividing the first group into a plurality of units equal in number to the plurality of memory banks; and storing the plurality of cells into corresponding memory banks among the plurality of memory banks; and a multiplexer associated with the memory structure and the first bus interface, the multiplexer configured to reassemble the first packets from the plurality of memory banks and route the first packets to channels; and A modem IC, the modem IC comprising: a second bus interface coupled to the communications bus; and A crossbar switch is configured to route incoming packets from the communication bus to a memory for further processing.

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