Power management circuit

Abstract

A power management circuit is provided. Herein, a transceiver circuit is configured to generate a modulated differential signal comprising information related to a time-varying amplitude of a radio frequency (RF) signal. Accordingly, a power management integrated circuit (PMIC) can generate a modulated voltage, a modulated phase correction voltage, and a modulated amplitude correction voltage based on the modulated differential signal. The modulated voltage is provided to the power amplifier circuit for amplifying the RF signal, and the modulated phase correction voltage and the modulated amplitude correction voltage are provided to the power amplifier circuit to cause phase and amplitude adjustment in the RF signal. By performing phase and amplitude adjustment in the RF signal, proper alignment between the modulated voltage and the time-varying amplitude of the RF signal can be ensured, thereby avoiding potential distortion in the RF signal.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 397,025, filed on August 11, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology of the present disclosure is generally directed to a power management circuit capable of supporting both envelope tracking (ET) and average power tracking (APT) operations. Background Art

[0004] Mobile communication devices have become increasingly common in today's society for providing wireless communication services. The popularity of these mobile communication devices is driven in part by the many functions now enabled on such devices. Increases in the processing power of such devices have meant that mobile communication devices have evolved from pure communication tools to sophisticated mobile multimedia centers capable of an enhanced user experience.

[0005] The fifth generation new radio (5G-NR) wireless communication system is widely regarded as a technological advancement that enables significantly higher data throughput, improved coverage, enhanced signaling efficiency, and reduced latency compared to existing third generation (3G) and fourth generation (4G) communication systems. 5G-NR mobile communication devices typically transmit and receive radio frequency (RF) signals, typically above 6 GHz, in the millimeter wave (mmWave) RF spectrum. It is worth noting that RF signals transmitted in the mmWave RF spectrum may be more susceptible to propagation attenuation and interference, which may result in a significant reduction in data throughput. To help mitigate propagation attenuation and maintain the desired data throughput, 5G-NR mobile communication devices employ power amplifiers to amplify the RF signals before transmitting them in the mmWave RF spectrum.

[0006] Envelope tracking (ET) and average power tracking (APT) are power management techniques designed to improve the operating efficiency of a power amplifier. Specifically, a power amplifier is configured to amplify an RF signal based on a modulation voltage (ET modulation or APT modulation) that closely tracks the time-varying power envelope of the RF signal. The modulation voltage is typically generated by a power management integrated circuit (PMIC) that is typically separate from the power amplifier. As a result, the modulation voltage may become misaligned in phase and / or amplitude with the time-varying power envelope of the RF signal, thereby potentially distorting the RF signal at the power amplifier. Therefore, it is desirable to align the modulation voltage at the power amplifier with the time-varying power envelope of the RF signal in both phase and amplitude. Summary of the invention

[0007] Embodiments of the present disclosure relate to a power management circuit. In this article, a transceiver circuit is configured to generate a modulated differential signal, which includes information related to the time-varying amplitude of a radio frequency (RF) signal. Therefore, a power management integrated circuit (PMIC) can generate a modulation voltage, a modulation phase correction voltage, and a modulation amplitude correction voltage based on the modulated differential signal. The modulation voltage is provided to a power amplifier circuit for amplifying the RF signal, and the modulation phase correction voltage and the modulation amplitude correction voltage are provided to the power amplifier circuit to cause phase and amplitude adjustments in the RF signal. By performing phase and amplitude adjustments in the RF signal, proper alignment between the modulation voltage and the time-varying amplitude of the RF signal can be ensured, thereby avoiding potential distortion in the RF signal.

[0008] In one aspect, a power management circuit is provided. The power management circuit includes a transceiver circuit. The transceiver circuit is configured to generate a digital signal having a time-varying amplitude. The transceiver circuit is also configured to convert the digital signal into an RF signal associated with the time-varying amplitude. The transceiver circuit is also configured to generate a modulated differential signal based on the time-varying amplitude. The power management circuit also includes a PMIC. The PMIC is configured to generate a modulation voltage, a modulation amplitude correction voltage, and a modulation phase correction voltage based on the modulated differential signal.

[0009] In another aspect, a transceiver circuit is provided. The transceiver circuit includes a first signal processing circuit. The first signal processing circuit is configured to generate a digital signal having a time-varying amplitude. The first signal processing circuit is also configured to convert the digital signal into an RF signal associated with the time-varying amplitude. The transceiver circuit also includes a second signal processing circuit. The second signal processing circuit is configured to generate a modulated differential signal based on the time-varying amplitude.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and become aware of additional aspects thereof after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary power management circuit that may be configured to align a modulation voltage with a time-varying amplitude of a radio frequency (RF) signal at a power amplifier circuit according to various embodiments of the present disclosure;

[0013] Figure 2 A configuration according to an embodiment of the present disclosure is provided Figure 1 A schematic diagram of an exemplary illustration of a power management circuit;

[0014] Figure 3 Provide the basis Figure 2 A schematic diagram of an exemplary illustration of a digital differential signal generated by an embodiment of the present invention;

[0015] Figure 4 Another embodiment of the present disclosure is provided. Figure 1 A schematic diagram of an exemplary illustration of a power management circuit;

[0016] Figure 5 Provide the basis Figure 4 A schematic diagram of an exemplary illustration of a digital differential signal generated by an embodiment of the present invention;

[0017] Figure 6 Another embodiment of the present disclosure is provided. Figure 1 A schematic diagram of an exemplary illustration of a power management circuit;

[0018] Figure 7 Provide the basis Figure 6 A schematic diagram of an exemplary illustration of a digital differential signal generated by an embodiment of the present invention; and

[0019] Figure 8 Which can provide Figure 2 , Figure 4 and Figure 6 Schematic diagram of an exemplary user element of a power management circuit. DETAILED DESCRIPTION

[0020] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0021] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0022] It should be understood that when an element such as a layer, a region or a substrate is referred to as being "on another element" or "extending onto another element", it may be directly on another element or directly extending onto another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "extending directly onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "above another element" or "extending above another element", it may be directly above another element or directly extending above another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0023] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0024] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "said" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0026] Embodiments of the present disclosure relate to a power management circuit. In this article, a transceiver circuit is configured to generate a modulated differential signal, which includes information related to the time-varying amplitude of a radio frequency (RF) signal. Therefore, a power management integrated circuit (PMIC) can generate a modulation voltage, a modulation phase correction voltage, and a modulation amplitude correction voltage based on the modulated differential signal. The modulation voltage is provided to a power amplifier circuit for amplifying the RF signal, and the modulation phase correction voltage and the modulation amplitude correction voltage are provided to the power amplifier circuit to cause phase and amplitude adjustments in the RF signal. By performing phase and amplitude adjustments in the RF signal, proper alignment between the modulation voltage and the time-varying amplitude of the RF signal can be ensured, thereby avoiding potential distortion in the RF signal.

[0027] Figure 1 The modulation voltage V CC The time-varying amplitude of the RF signal 12 Schematic diagram of an exemplary power management circuit 10 aligned. The power management circuit 10 also includes a transceiver circuit 16 and a PMIC 18, both of which are separate from the power amplifier circuit 14 and from each other. The transceiver circuit 16 is configured to generate a time-varying amplitude The RF signal 12 is correlated and provided to the power amplifier circuit 14 .

[0028] The transceiver circuit 16 is further configured to detect the time-varying amplitude of the RF signal 12 based on the time-varying amplitude of the RF signal 12. To generate the modulated differential signal S DIFF And modulate the differential signal S DIFF Provided to PMIC 18. As discussed in detail below, the modulated differential signal S may be generated based on various embodiments of the present disclosure. DIFF , to include enabling the PMIC 18 to generate in addition to the modulation voltage V CC The modulation phase correction voltage V and the modulation amplitude voltage V AM The modulation phase correction voltage V and the modulation amplitude voltage V AM may be provided to the power amplifier circuit 14 to induce phase and amplitude correction in the RF signal 12 such that the time-varying amplitude of the RF signal 12 at the power amplifier circuit 14 Can be modulated with voltage V CC Thus, when the RF signal 12 is amplified at the power amplifier circuit 14, potential distortion (eg, amplitude clipping) in the RF signal 12 may be prevented.

[0029] Figure 2is a schematic diagram providing an exemplary illustration of a power management circuit 10A configured in accordance with one embodiment of the present disclosure. Figure 1 and Figure 2 Common elements between the present invention are shown with common element numbers and will not be described again in this article.

[0030] In this context, the power management circuit 10A includes a circuit that is functionally equivalent to Figure 1 The power amplifier circuit 14 includes a phase shifter circuit 20, a driver stage amplifier 22, and an output stage amplifier 24. The phase shifter circuit 20 is configured to perform phase correction on the RF signal 12 based on the modulation phase correction voltage V to generate a phase-adjusted RF signal 26. The driver stage amplifier 22 is coupled to the phase shifter circuit 20. The driver stage amplifier 22 first performs phase correction based on the modulation amplitude correction voltage V AM To perform amplitude adjustment on the phase-adjusted RF signal 26 to generate a phase-amplitude-adjusted RF signal 28, and then based on the modulation voltage V CC The output stage amplifier 24 is coupled to the driver stage amplifier 22 and is configured to amplify the phase amplitude adjusted RF signal 28. CC To further amplify the phase-amplitude adjusted RF signal 28.

[0031] According to an embodiment of the present disclosure, the transceiver circuit 16A includes a first signal processing circuit 29, which includes a digital processing circuit 30. The transceiver circuit 16A also includes a second signal processing circuit 31A, which includes a first filter circuit 32, a first envelope detector 34, a phase correction lookup table (LUT) circuit 36, a second filter circuit 38, a second envelope detector 40, an amplitude correction LUT circuit 42, a combiner 44, a voltage LUT circuit 46, a modulator circuit 48, and a digital-to-analog converter (DAC) 50. The first signal processing circuit 29 also includes a signal processing circuit 52. The digital processing circuit 30 is configured to generate a time-varying amplitude The signal processing circuit 52 is configured to convert the digital signal 54 into the RF signal 12, which is also associated with the time-varying amplitude The RF signal 12 is associated and provided to the phase shifter circuit 20 in the power amplifier circuit 14. In a non-limiting example, the signal processing circuit 52 may include additional active / passive circuits (eg, DAC, frequency converter, etc.), which are omitted herein for simplicity.

[0032] The first filter circuit 32 is configured to convert the first complex filter H APT(s) is applied to the digital signal 54 to generate the first equalized digital signal 56. The first envelope detector 34 is configured to detect the time-varying amplitude of the first equalized digital signal 56. The phase correction LUT circuit 36 ​​may include an isophase LUT (not shown) and is configured to detect the time-varying amplitude of the first equalized digital signal 56 based on the detected time-varying amplitude of the first equalized digital signal 56. To generate the modulation phase correction voltage V.

[0033] The second filter circuit 38 is configured to convert the second complex filter H ET (s) is applied to the digital signal 54 to generate the second equalized digital signal 58. The second envelope detector 40 is configured to detect the time-varying amplitude of the second equalized digital signal 58. The amplitude correction LUT circuit 42 may include an equal gain LUT (not shown) and is configured to detect the time-varying amplitude of the second equalized digital signal 58 based on the detected time-varying amplitude of the second equalized digital signal 58. To generate the modulation amplitude correction voltage V AM The combiner 44 is configured to combine the modulation phase correction voltage V and the modulation amplitude correction voltage V AM To generate the modulation phase amplitude correction voltage V -AM .

[0034] The voltage LUT circuit 46 may include a voltage LUT (not shown) and is configured to detect the time-varying amplitude of the second equalized digital signal 58 based on the detected time-varying amplitude of the second equalized digital signal 58. To generate the modulation target voltage V CC-TGT In one embodiment, the modulation target voltage V CC-TGT It can be an envelope tracking (ET) modulation target voltage to generate a modulation voltage V CC As ET modulation voltage. In another embodiment, the modulation target voltage V CC-TGT It can be an average power tracking (APT) modulation target voltage for generating the modulation voltage V CC The modulator circuit 48 is configured to generate a digital differential signal D DIFF , the digital differential signal includes a modulated phase amplitude correction voltage V -AM and modulation target voltage V CC-TGT The DAC 50 is configured to convert the digital differential signal D DIFF Converted into a modulated differential signal S DIFF .

[0035] Figure 3 Provide the basis Figure 2 The implementation scheme generates a digital differential signal D DIFF A schematic diagram of an exemplary illustration of . Figure 2 and 3Common elements between the two are shown here with common element reference numerals and will not be re-described herein.

[0036] Herein, the modulator circuit 48 further includes a first modulator 60 and a second modulator 62. The first modulator 60 is configured to generate a digital differential signal D DIFF The first digital differential signal D DIFF-1 , and the second modulator 62 is configured to generate a digital differential signal D DIFF The second digital differential signal D DIFF-2 Specifically, the first modulator 60 modulates the target voltage V CC-TGT One half (1 / 2) of the modulation phase amplitude correction voltage V -AM The first digital differential signal D is generated by adding DIFF-1 (D DIFF-1 =V -AM +1 / 2V CC-TGT The second modulator 62 modulates the phase amplitude correction voltage V -AM Subtract the modulation target voltage V CC-TGT One half (1 / 2) of DIFF-2 (D DIFF-2 =V -AM -1 / 2V CC-TGT ). In other words, the digital differential signal D DIFF Including the common signal (also called the modulation phase amplitude correction voltage V -AM ) and the differential signal (also called the modulation target voltage V CC-TGT ).

[0037] Return to reference Figure 2 , the PMIC 18A may include a voltage modulation circuit 64 and a splitter circuit 66. The voltage modulation circuit 64 is configured to modulate the differential signal S DIFF Extract the modulation target voltage V CC-TGT , and based on the modulation target voltage V CC-TGT To generate the modulation voltage V CC The splitter circuit 66 is configured to separate the modulated differential signal S DIFF Extract the modulation phase amplitude correction voltage V -AM , and modulate the phase amplitude correction voltage V -AM Split into modulation phase correction voltage V and modulation amplitude correction voltage V AM .

[0038] Figure 4 is a schematic diagram providing an exemplary illustration of a power management circuit 10B configured in accordance with another embodiment of the present disclosure. Figure 1 , Figure 2 and Figure 4Common elements between the embodiments are shown here with common element numbers and will not be re-described herein.

[0039] In this context, the power management circuit 10B includes a circuit which is functionally equivalent to Figure 1 The transceiver circuit 16 and the PMIC 18 of the transceiver circuit 16B and the PMIC 18B in the embodiment of the present disclosure include a second signal processing circuit 31B, which includes a filter circuit 68, an envelope detector 70, a voltage LUT circuit 72, and a modulator circuit 74. The filter circuit 68 is configured to convert the complex filter H ET (s) is applied to the digital signal 54 to generate the equalized digital signal 76. The envelope detector 70 is configured to detect the time-varying amplitude of the equalized digital signal 76. The voltage LUT circuit 72 may include a voltage LUT (not shown) and is configured to detect the time-varying amplitude of the equalized digital signal 76 based on the detected time-varying amplitude of the equalized digital signal 76. To generate the modulation target voltage V CC-TGT The voltage LUT circuit 72 can be coupled to the voltage modulation circuit 64 via the RF front end (RFFE) interface, thereby modulating the target voltage V CC-TGT The voltage modulation circuit 64 is provided. The modulator circuit 74 is configured to generate a digital differential signal D DIFF , the digital differential signal includes the time-varying amplitude of the equalized digital signal 76 and modulation target voltage V CC-TGT .

[0040] Figure 5 Provide the basis Figure 4 The implementation scheme generates a digital differential signal D DIFF A schematic diagram of an exemplary illustration of . Figure 4 and Figure 5 Common elements between the embodiments are shown here with common element numbers and will not be re-described herein.

[0041] Herein, the modulator circuit 74 further includes a first modulator 78 and a second modulator 80. The first modulator 78 is configured to generate a digital differential signal D DIFF The first digital differential signal D DIFF-1 , and the second modulator 80 is configured to generate a digital differential signal D DIFF The second digital differential signal D DIFF-2 Specifically, the first modulator 78 modulates the target voltage V CC-TGT One half (1 / 2) of the time-varying amplitude of the equalized digital signal 76 The first digital differential signal is generated by adding The second modulator 80 generates a time-varying amplitude signal from the equalized digital signal 76. Subtract the modulation target voltage V CC-TGT One half (1 / 2) of In other words, the digital differential signal D DIFF The common signal (also referred to as the equalized digital signal 76) includes a time-varying amplitude ) and the differential signal (also called the modulation target voltage V CC-TGT ).

[0042] Return to reference Figure 4 , the PMIC 18B may include a voltage modulation circuit 64, a phase correction LUT circuit 36, and an amplitude correction LUT circuit 42. The voltage modulation circuit 64 is configured to modulate the target voltage V based on the phase correction LUT circuit 36. CC-TGT To generate the modulation voltage V CC The phase correction LUT circuit 36 ​​is configured to obtain the modulated differential signal S DIFF Extracting time-varying amplitude The amplitude correction LUT circuit 42 is configured to obtain the modulation phase correction voltage V from the modulation differential signal S DIFF Extracting time-varying amplitude And generate the modulation amplitude correction voltage V AM .

[0043] Figure 6 is a schematic diagram providing an exemplary illustration of a power management circuit 10C configured in accordance with one embodiment of the present disclosure. Figure 1 , Figure 2 and Figure 6 Common elements between the embodiments are shown here with common element numbers and will not be re-described herein.

[0044] In this context, the power management circuit 10C includes a circuit which is functionally equivalent to Figure 1 The transceiver circuit 16C of the transceiver circuit 16 in the embodiment. In the embodiment, the transceiver circuit 16C includes a second signal processing circuit 31C. Herein, the phase correction LUT circuit 36 ​​and the amplitude correction LUT circuit 42 are configured to modulate the phase correction voltage V and the amplitude correction voltage V AM Provided to the modulator 82, the modulator generates a modulated differential signal S DIFF The voltage LUT circuit 46 is configured to modulate the target voltage V CC-TGT is provided to the voltage modulation circuit 64 for generating a modulation voltage V CC .

[0045] Figure 7 Provide the basis Figure 6 The implementation scheme generates a digital differential signal D DIFF A schematic diagram of an exemplary illustration of . Figure 6 and Figure 7 Common elements between the embodiments are shown here with common element numbers and will not be re-described herein.

[0046] Herein, the modulator circuit 82 further includes a first modulator 84 and a second modulator 86. The first modulator 84 is configured to generate a digital differential signal D DIFF The first digital differential signal D DIFF-1 , and the second modulator 86 is configured to generate a digital differential signal D DIFF The second digital differential signal D DIFF-2 Specifically, the first modulator 84 modulates the amplitude correction voltage V AM The first digital differential signal D is generated by adding the modulated phase correction voltage V DIFF-1 (D DIFF-1 =V+V AM The second modulator 86 corrects the voltage V by modulating the amplitude AM Subtract the modulation amplitude correction voltage V AM To generate the second digital differential signal D DIFF-2 (D DIFF-2 =V–V AM ). In other words, the digital differential signal D DIFF It includes a common signal (also called a modulation phase correction voltage V) and a differential signal (also called a modulation amplitude correction voltage V AM ).

[0047] Figure 2 The power management circuit 10A, Figure 4 The power management circuit 10B and Figure 6 A power management circuit 10C may be provided in a user element to implement bandwidth adaptation according to the above-described embodiment. In this regard, Figure 8 Which can provide Figure 2 The power management circuit 10A, Figure 4 The power management circuit 10B and Figure 6 Schematic diagram of an exemplary user element 100 of a power management circuit 10C.

[0048] Herein, user element 100 can be any type of user element, such as a mobile terminal, smart watch, tablet computer, computer, navigation device, access point and similar wireless communication device supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth and near field communication. User element 100 will generally include control system 102, baseband processor 104, transmission circuit system 106, receiving circuit system 108, antenna switch circuit system 110, multiple antennas 112 and user interface circuit system 114. In a non-limiting example, for example, control system 102 can be a field programmable gate array (FPGA). In this regard, control system 102 can include at least a microprocessor, an embedded memory circuit and a communication bus interface. Receive circuit system 108 receives radio frequency signals from one or more base stations via antenna 112 and through antenna switch circuit system 110. Low noise amplifier and filter cooperate to amplify and eliminate broadband interference from received signals for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0049] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0050] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, and encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the desired transmit frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to an antenna 112 via an antenna switch circuit system 110. Multiple antennas 112 and duplicate transmit circuit systems 106 and receive circuit systems 108 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0051] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A power management circuit (10A, 10B, 10C), comprising: Transceiver circuits (16A, 16B, 16C) configured to: Generates a time-varying amplitude The digital signal (54) is converted into a time-varying amplitude an associated radio frequency (RF) signal (12); and Based on the time-varying amplitude To generate the modulated differential signal (S DIFF );as well as A power management integrated circuit PMIC (18A, 18B) is configured to be configured based on the modulated differential signal (S DIFF ) to generate the modulation voltage (V CC ), modulation amplitude correction voltage (V AM ) and modulated phase correction voltage (V).

2. The power management circuit (10A, 10B, 10C) of claim 1, further comprising a power amplifier circuit (14), wherein the power amplifier circuit (14) comprises: a phase shifter circuit (20) configured to perform phase adjustment on the RF signal (12) based on the modulated phase correction voltage (V) to generate a phase adjusted RF signal (26); A driver stage amplifier (22) coupled to the phase shifter circuit (20) and configured to: Based on the modulation amplitude correction voltage (V AM ) to perform amplitude adjustment on the phase-adjusted RF signal (26) to generate a phase-amplitude-adjusted RF signal (28); and Based on the modulation voltage (V CC ) to amplify the phase-amplitude adjusted RF signal (28); as well as An output stage amplifier (24) is coupled to the driver stage amplifier (22) and is configured to generate a modulation voltage (V CC ) to further amplify the amplified phase-amplitude adjusted RF signal (28).

3. The power management circuit (10A) of claim 1, wherein the transceiver circuit (16A) comprises: digital processing circuitry (30) configured to generate the digital signal (54) associated with the time-varying amplitude; The first filter circuit (32) is configured to convert a first complex filter (H APT (s)) is applied to the digital signal (54) to generate a first equalized digital signal (56); a first envelope detector (34) configured to detect the time-varying amplitude of the first equalized digital signal (56); a phase correction lookup table (LUT) circuit (36) configured to generate the modulated phase correction voltage (V) based on the detected time-varying amplitude of the first equalized digital signal (56); The second filter circuit (38) is configured to convert the second complex filter (H ET (s)) applied to the digital signal (54) to generate a second equalized digital signal (58); a second envelope detector (40) configured to detect the time-varying amplitude of the second equalized digital signal (58); an amplitude correction LUT circuit (42) configured to generate the modulation amplitude correction voltage (V AM ); A combiner (44) is configured to combine the modulation phase correction voltage (V) and the modulation amplitude correction voltage (V AM ) to generate the modulation phase amplitude correction voltage (V -AM ); A voltage LUT circuit (46) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (48) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the modulation phase amplitude correction voltage (V -AM ) and the modulation target voltage (V CC-TGT ); as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

4. The power management circuit (10A) of claim 3, wherein the modulated differential signal (S DIFF )include: The common component includes the modulation phase amplitude correction voltage (V -AM ); as well as The differential component includes the modulation target voltage (V CC-TGT ) and the modulation target voltage (V CC-TGT ) is negative one-half (1 / 2).

5. The power management circuit (10A) of claim 4, wherein the modulator circuit (48) comprises: The first modulator (60) is configured to modulate the target voltage (V CC-TGT ) is one-half (1 / 2) of the modulation phase amplitude correction voltage (V -AM ) are added to generate a voltage including the common component and the modulation target voltage (V CC-TGT ) of the positive half (1 / 2) of the first digital differential signal (D DIFF-1 ); as well as A second modulator (62) is configured to correct the phase amplitude of the modulation voltage (V -AM ) minus the modulation target voltage (V CC-TGT ), thereby generating a voltage including the common component and the modulation target voltage (V CC-TGT ) of the negative half (1 / 2) of the second digital differential signal (D DIFF-2 ).

6. The power management circuit (10A) of claim 4, wherein the PMIC (18A) comprises: A voltage modulation circuit (64) is configured to: From the modulated differential signal (S DIFF ) extracts the modulation target voltage (V CC-TGT );and Based on the modulation target voltage (V CC-TGT ) to generate the modulation voltage (V CC );as well as A splitter circuit (66) configured to: From the modulated differential signal (S DIFF ) extracts the modulation phase amplitude correction voltage (V -AM );and The modulation phase amplitude correction voltage (V -AM ) is separated into the modulation phase correction voltage (V) and the modulation amplitude correction voltage (V AM ).

7. The power management circuit (10B) of claim 1, wherein the transceiver circuit (16B) comprises: digital processing circuitry (30) configured to generate the digital signal (54) associated with the time-varying amplitude; A filter circuit (68) is configured to convert a complex filter (H ET (s)) applied to the digital signal (54) to generate an equalized digital signal (76); an envelope detector (70) configured to detect the time-varying amplitude of the equalized digital signal (76); A voltage lookup table LUT circuit (72) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (74) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the time-varying amplitude of the balanced digital signal (76) and the modulated target voltage (V CC-TGT );as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

8. The power management circuit (10B) as claimed in claim 7, wherein the modulated differential signal (S DIFF )include: a common component comprising said time-varying amplitude of said equalized digital signal (76); as well as The differential component includes the modulation target voltage (V CC-TGT ) and the modulation target voltage (V CC-TGT ) is negative one-half (1 / 2).

9. The power management circuit (10B) of claim 8, wherein the modulator circuit (48) comprises: The first modulator (60) is configured to modulate the target voltage (V CC-TGT ) is added to the time-varying amplitude of the balanced digital signal (76), thereby generating a voltage including the common component and the modulated target voltage (V CC-TGT ) of the positive half (1 / 2) of the first digital differential signal (D DIFF-1 ); as well as A second modulator (62) is configured to subtract the modulation target voltage (V CC-TGT ), thereby generating a voltage including the common component and the modulation target voltage (V CC-TGT ) of the negative half (1 / 2) of the second digital differential signal (D DIFF-2 ).

10. The power management circuit (10B) of claim 8, wherein the PMIC (18B) comprises: A voltage modulation circuit (64) is configured to: Receive the modulation target voltage (V CC-TGT );and Based on the modulation target voltage (V CC-TGT ) to generate the modulation voltage (V CC ); A phase correction LUT circuit (36) is configured to obtain a phase correction signal based on the modulated differential signal (S DIFF ) to generate the modulated phase correction voltage (V); and The amplitude correction LUT circuit (42) is configured to adjust the amplitude of the modulated differential signal (S DIFF ) to generate the modulation amplitude correction voltage (V AM ).

11. The power management circuit (10C) of claim 1, wherein the transceiver circuit (16C) comprises: digital processing circuitry (30) configured to generate the digital signal (54) associated with the time-varying amplitude; The first filter circuit (32) is configured to convert a first complex filter (H APT (s)) is applied to the digital signal (54) to generate a first equalized digital signal (56); a first envelope detector (34) configured to detect the time-varying amplitude of the first equalized digital signal (56); a phase correction lookup table (LUT) circuit (36) configured to generate the modulated phase correction voltage (V) based on the detected time-varying amplitude of the first equalized digital signal (56); The second filter circuit (38) is configured to convert the second complex filter (H ET (s)) applied to the digital signal (54) to generate a second equalized digital signal (58); a second envelope detector (40) configured to detect the time-varying amplitude of the second equalized digital signal (58); an amplitude correction LUT circuit (42) configured to generate the modulation amplitude correction voltage (V AM ); A voltage LUT circuit (46) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (82) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the modulation phase correction voltage (V) and the modulation amplitude correction voltage (V AM );as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

12. The power management circuit (10C) according to claim 11, wherein the modulated differential signal (S DIFF )include: The common component includes the modulation amplitude correction voltage (V AM ); as well as The differential component includes the positive modulation amplitude correction voltage (V AM ) and negative modulation amplitude correction voltage (V AM ).

13. The power management circuit (10C) of claim 12, wherein the modulator circuit (82) comprises: The first modulator (84) is configured to convert the modulation amplitude correction voltage (V AM ) is added to the modulation phase correction voltage (V) to generate a voltage including the common component and the positive modulation amplitude correction voltage (V AM ) of the first digital differential signal (D DIFF-1 );as well as A second modulator (86) is configured to subtract the modulation amplitude correction voltage (V) from the modulation phase correction voltage (V AM ), thereby generating a voltage including the common component and the negative modulation amplitude correction voltage (V AM ) of the second digital differential signal (D DIFF-2 ).

14. A transceiver circuit (16A, 16B, 16C), comprising: A first signal processing circuit (29) is configured to generate a signal having a time-varying amplitude The digital signal (54) is converted into a time-varying amplitude an associated radio frequency (RF) signal (12); as well as A second signal processing circuit (31A, 31B) is configured to process the time-varying amplitude To generate the modulated differential signal (S DIFF ).

15. The transceiver circuit (16A, 16B, 16C) of claim 14, wherein the first signal processing circuit (29) comprises: digital processing circuitry (30) configured to generate the digital signal (54) associated with the time-varying amplitude; and A signal processing circuit (52) is configured to convert the digital signal (54) into the RF signal (12) associated with the time-varying amplitude.

16. The transceiver circuit (16A) of claim 15, wherein the second signal processing circuit (31A) comprises: The first filter circuit (32) is configured to convert a first complex filter (H APT (s)) is applied to the digital signal (54) to generate a first equalized digital signal (56); a first envelope detector (34) configured to detect the time-varying amplitude of the first equalized digital signal (56); a phase correction lookup table (LUT) circuit (36) configured to generate a modulated phase correction voltage (V) based on the detected time-varying amplitude of the first equalized digital signal (56); The second filter circuit (38) is configured to convert the second complex filter (H ET (s)) applied to the digital signal (54) to generate a second equalized digital signal (58); a second envelope detector (40) configured to detect the time-varying amplitude of the second equalized digital signal (58); an amplitude correction LUT circuit (42) configured to generate a modulation amplitude correction voltage (V AM ); A combiner (44) is configured to combine the modulation phase correction voltage (V) and the modulation amplitude correction voltage (V AM ) to generate the modulation phase amplitude correction voltage (V -AM ); A voltage LUT circuit (46) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (48) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the modulation phase amplitude correction voltage (V -AM ) and the modulation target voltage (V CC-TGT ); as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

17. The transceiver circuit (16A) of claim 16, wherein the modulated differential signal (S DIFF )include: The common component includes the modulation phase amplitude correction voltage (V -AM ); as well as The differential component includes the modulation target voltage (V CC-TGT ) and the modulation target voltage (V CC-TGT ) is negative one-half (1 / 2).

18. The transceiver circuit (16A) of claim 17, wherein the modulator circuit (48) comprises: The first modulator (60) is configured to modulate the target voltage (V CC-TGT ) is one-half (1 / 2) of the modulation phase amplitude correction voltage (V -AM ) are added to generate a voltage including the common component and the modulation target voltage (V CC-TGT ) of the positive half (1 / 2) of the first digital differential signal (D DIFF-1 ); as well as A second modulator (62) is configured to correct the phase amplitude of the modulation voltage (V -AM ) minus the modulation target voltage (V CC-TGT ), thereby generating a voltage including the common component and the modulation target voltage (V CC-TGT ) of the negative half (1 / 2) of the second digital differential signal (D DIFF-2 ).

19. The transceiver circuit (16B) of claim 15, wherein the second signal processing circuit (31B) comprises: A filter circuit (68) is configured to convert a complex filter (H ET (s)) applied to the digital signal (54) to generate an equalized digital signal (76); an envelope detector (70) configured to detect the time-varying amplitude of the equalized digital signal (76); A voltage lookup table LUT circuit (72) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (74) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the time-varying amplitude of the balanced digital signal (76) and the modulated target voltage (V CC-TGT );as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

20. The transceiver circuit (16B) of claim 19, wherein the modulated differential signal (S DIFF )include: a common component comprising said time-varying amplitude of said equalized digital signal (76); as well as The differential component includes the modulation target voltage (V CC-TGT ) and the modulation target voltage (V CC-TGT ) is negative one-half (1 / 2).

21. The transceiver circuit (16B) of claim 20, wherein the modulator circuit (48) comprises: The first modulator (60) is configured to modulate the target voltage (V CC-TGT ) is added to the time-varying amplitude of the balanced digital signal (76), thereby generating a voltage including the common component and the modulated target voltage (V CC-TGT ) of the positive half (1 / 2) of the first digital differential signal (D DIFF-1 ); as well as A second modulator (62) is configured to subtract the modulation target voltage (V CC-TGT ), thereby generating a voltage including the common component and the modulation target voltage (V CC-TGT ) of the negative half (1 / 2) of the second digital differential signal (D DIFF-2 ).

22. The transceiver circuit (16C) of claim 15, wherein the second signal processing circuit (31C) comprises: The first filter circuit (32) is configured to convert a first complex filter (H APT (s)) is applied to the digital signal (54) to generate a first equalized digital signal (56); a first envelope detector (34) configured to detect the time-varying amplitude of the first equalized digital signal (56); a phase correction lookup table (LUT) circuit (36) configured to generate the modulated phase correction voltage (V) based on the detected time-varying amplitude of the first equalized digital signal (56); The second filter circuit (38) is configured to convert the second complex filter (H ET (s)) applied to the digital signal (54) to generate a second equalized digital signal (58); a second envelope detector (40) configured to detect the time-varying amplitude of the second equalized digital signal (58); an amplitude correction LUT circuit (42) configured to generate the modulation amplitude correction voltage (V AM ); A voltage LUT circuit (46) is configured to generate a modulation target voltage (V CC-TGT ); A modulator circuit (82) configured to generate a digital differential signal (D DIFF ), the digital differential signal includes the modulation phase correction voltage (V) and the modulation amplitude correction voltage (V AM );as well as A digital-to-analog converter DAC (50) is configured to convert the digital differential signal (D DIFF ) is converted into the modulated differential signal (S DIFF ).

23. The transceiver circuit (16C) of claim 22, wherein the modulated differential signal (S DIFF )include: The common component includes the modulation amplitude correction voltage (V AM ); as well as The differential component includes the positive modulation amplitude correction voltage (V AM ) and negative modulation amplitude correction voltage (V AM ).

24. The transceiver circuit (16C) of claim 23, wherein the modulator circuit (82) comprises: The first modulator (84) is configured to convert the modulation amplitude correction voltage (V AM ) is added to the modulation phase correction voltage (V) to generate a voltage including the common component and the positive modulation amplitude correction voltage (V AM ) of the first digital differential signal (D DIFF-1 );as well as A second modulator (86) is configured to subtract the modulation amplitude correction voltage (V) from the modulation phase correction voltage (V AM ), thereby generating a voltage including the common component and the negative modulation amplitude correction voltage (V AM ) of the second digital differential signal (D DIFF-2 ).

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