Light detection element, electronic device, and method for manufacturing light detection element

Abstract

[Problem] To improve detection accuracy. [Solution] This light-detecting element is provided with: a light-receiving unit that generates an electric charge corresponding to the amount of received light; a voltage conversion unit that acquires the charge generated by the light receiving unit via an input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node; a signal amplification unit that amplifies the voltage signal; and a comparison unit that compares a voltage of the voltage signal amplified by the signal amplification unit with a predetermined voltage. The voltage conversion unit includes an amplification circuit connected between an input node and an output node, and a feedback circuit connected between the input node and the output node. A gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplification unit and the comparison unit.

Description

Technical Field

[0001] Embodiments according to the present disclosure relate to a light detecting element, an electronic device, and a method for manufacturing the light detecting element. Background Art

[0002] An imaging device is known that acquires data of a portion whose brightness level changes due to an event only when some event occurs in an imaging scene. This type of imaging device is sometimes referred to as an event-based vision sensor (EVS) (see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: US2021 / 250,528A Summary of the invention

[0006] Technical Problems to be Solved by the Invention

[0007] However, in EVS, high detection sensitivity is desired.

[0008] Therefore, the present disclosure provides a light detecting element, an electronic device, and a method for manufacturing the light detecting element capable of improving detection sensitivity.

[0009] Technical solutions to technical problems

[0010] In order to solve the above problems, according to the present disclosure, a light detection element is provided, comprising:

[0011] a light receiving unit that generates electric charge according to the amount of light received;

[0012] a voltage conversion unit that acquires the charge generated in the light receiving unit via the input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node;

[0013] a signal amplifying unit that amplifies the voltage signal; and

[0014] a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage,

[0015] The voltage conversion unit includes:

[0016] an amplifier circuit connected between the input node and the output node; and

[0017] A feedback circuit is connected between the input node and the output node, and

[0018] A gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section.

[0019] A subthreshold slope of at least one transistor included in the feedback circuit is higher than subthreshold slopes of transistors included in the signal amplification section and the comparison section.

[0020] The amplifier circuit may include:

[0021] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0022] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0023] A gate insulating film of at least one transistor included in the feedback circuit may be thicker than a gate insulating film of the second transistor.

[0024] The amplifier circuit may include:

[0025] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0026] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0027] A subthreshold slope of at least one transistor included in the feedback circuit may be higher than a subthreshold slope of the second transistor.

[0028] The feedback circuit may include a first transistor connected between the input node and the third reference voltage node and including a gate electrically connected to the output node.

[0029] The feedback circuit may further include a third transistor connected between the input node and the first transistor, and

[0030] The third transistor amplifies a voltage of a node between the first transistor and the third transistor and outputs the amplified voltage to the input node.

[0031] The amplifier circuit may include:

[0032] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0033] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0034] A channel length of the first transistor may be shorter than a channel length of the second transistor.

[0035] A length of the gate electrode of the first transistor in the channel length direction may be shorter than a length of the gate electrode of the second transistor in the channel length direction.

[0036] The first transistor may include at least one of a source extension portion and a drain extension portion, the source extension portion being arranged to extend from the source layer toward the drain layer and having an impurity concentration lower than that of the source layer, the drain extension portion being arranged to extend from the drain layer toward the source layer and having an impurity concentration lower than that of the drain layer, and

[0037] The source extension and the drain extension may be arranged to overlap with the gate electrode of the first transistor when viewed from a direction substantially perpendicular to a surface of the substrate on which the first transistor is disposed.

[0038] A first transfer transistor may be further included, the first transfer transistor being connected between the light receiving portion and the input node and transferring the charge generated by the light receiving portion to the input node, and

[0039] A gate insulating film of at least one transistor included in the feedback circuit may be thicker than a gate insulating film of the first transfer transistor.

[0040] a charge accumulation portion that stores charges, and

[0041] A second transfer transistor connected between the light receiving portion and the charge accumulation portion and transferring the charge generated by the light receiving portion to the charge accumulation portion may be further included, and

[0042] A gate insulating film of at least one transistor included in the feedback circuit may be thicker than a gate insulating film of the second transfer transistor.

[0043] The amplifier circuit may include:

[0044] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0045] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0046] A gate insulating film of the second transistor may be thicker than gate insulating films of transistors included in the signal amplification section and the comparison section.

[0047] An end portion on the substrate side of a gate insulating film of at least one transistor included in the feedback circuit may be closer to the substrate side than an end portion on the substrate side of a gate insulating film of a transistor included in the amplifier circuit.

[0048] The amplifier circuit may include:

[0049] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0050] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0051] The light detection element may also include:

[0052] a first semiconductor chip on which the light receiving unit, the feedback circuit and the second transistor are arranged; and

[0053] The second semiconductor chip is stacked on the first semiconductor chip, and the current source, the signal amplification part and the comparison part are arranged on the second semiconductor chip.

[0054] The thickness of the gate insulating film of at least one transistor included in the feedback circuit may be 5 nm or more.

[0055] A threshold slope of at least one transistor included in the feedback circuit may be 100 mV / decade or more.

[0056] According to the present disclosure, there is provided an electronic device including a light detecting element.

[0057] According to the present disclosure, a method for manufacturing a light detection element is provided, the light detection element comprising:

[0058] a light receiving unit that generates electric charge according to the amount of light received;

[0059] a voltage conversion unit that acquires the charge generated in the light receiving unit via the input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node;

[0060] a signal amplifying unit that amplifies the voltage signal; and

[0061] a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage,

[0062] The voltage conversion unit includes:

[0063] an amplifier circuit connected between the input node and the output node; and

[0064] A feedback circuit is connected between the input node and the output node, and

[0065] A gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section, and the manufacturing method includes:

[0066] A gate insulating film of at least one transistor included in the feedback circuit is formed by local oxidation of silicon (LOCOS). BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a block diagram showing an embodiment of a system configuration of an imaging system to which the technology according to the present disclosure is applied.

[0068] Figure 2 is a block diagram showing an embodiment of a configuration of an imaging device according to a first configuration embodiment of the present disclosure.

[0069] Figure 3 is a block diagram showing an example of a configuration of a pixel array section.

[0070] Figure 4 is a circuit diagram showing an example of a circuit configuration of a pixel.

[0071] Figure 5 is a block diagram showing a first configuration example of an address event detection section.

[0072] Figure 6 is a circuit diagram showing an example of a configuration of a current-voltage conversion section in an address event detection section.

[0073] Figure 7 is a circuit diagram showing an example of the configuration of a subtractor and a quantizer in an address event detection section.

[0074] Figure 8 is a block diagram showing a second configuration example of the address event detection section.

[0075] Fig. 9 is a block diagram showing an embodiment of a configuration of an imaging device according to a second configuration embodiment of the present disclosure.

[0076] Fig.10 is an exploded perspective view schematically showing a stacked chip structure of an imaging device.

[0077] Fig.11 : is a block diagram showing an embodiment of the configuration of a column processing section of an imaging device according to a first configuration embodiment.

[0078] Fig.12 is a circuit diagram showing an example of the configuration of a pixel according to the first embodiment.

[0079] Fig.13 is a top view showing an example of the arrangement of the configuration of the pixel according to the first embodiment.

[0080] Fig.14 is a cross-sectional view showing an example of the configuration of the transistor according to the first embodiment.

[0081] Fig.15 is a diagram showing an example of transfer characteristics of the transistor according to the first embodiment.

[0082] Fig.16 : is a diagram showing an example of the relationship between the detection sensitivity and the light amount in the pixel according to the first embodiment.

[0083] Fig.17A is a cross-sectional view showing an example of a method for manufacturing the transistor according to the first embodiment.

[0084] Fig. 17B It is shown Fig.17A Cross-sectional view of the following steps.

[0085] Fig. 17C It is shown Fig. 17B Cross-sectional view of the following steps.

[0086] Fig.17D It is shown Fig. 17C Cross-sectional view of the following steps.

[0087] Fig.17E It is shown Fig.17D Cross-sectional view of the following steps.

[0088] Fig.17F It is shown Fig.17E Cross-sectional view of the following steps.

[0089] Figure 17G It is shown Fig.17F Cross-sectional view of the following steps.

[0090] Fig.17H It is shown Figure 17G Cross-sectional view of the following steps.

[0091] Fig.18A is a cross-sectional view showing an example of a method for manufacturing a transistor according to a modification of the first embodiment.

[0092] Fig.18B It is shown Fig.18A Cross-sectional view of the following steps.

[0093] Fig. 18C It is shown Fig.18B Cross-sectional view of the following steps.

[0094] Fig.18D It is shown Fig. 18C Cross-sectional view of the following steps.

[0095] Fig.18E It is shown Fig.18D Cross-sectional view of the following steps.

[0096] Fig.18F It is shown Fig.18E Cross-sectional view of the following steps.

[0097] Figure 18G It is shown Fig.18F Cross-sectional view of the following steps.

[0098] Fig.18H It is shown Figure 18G Cross-sectional view of the following steps.

[0099] Fig.18I It is shown Fig.18H Cross-sectional view of the following steps.

[0100] Fig.19 : is a diagram showing an example of the configuration of a pixel and a signal processing section according to the second embodiment.

[0101] Fig. 20 is a circuit diagram showing an example of a configuration of a pixel according to the third embodiment.

[0102] Fig.21 is a top view showing an example of the arrangement of a configuration of a pixel according to the third embodiment.

[0103] Fig. 22 is a cross-sectional view showing an example of a configuration of a transistor according to a fourth embodiment.

[0104] Fig.23 is a top view showing an example of the arrangement of a configuration of a pixel according to the fourth embodiment.

[0105] Fig.24 is a cross-sectional view showing an example of a configuration of a transistor according to a fifth embodiment.

[0106] Fig.25 is a top view showing an example of the arrangement of a configuration of a pixel according to the fourth embodiment.

[0107] Fig.26A is a cross-sectional view showing an example of a method for manufacturing a transistor according to a fifth embodiment.

[0108] Fig.26B It is shown Fig.26A Cross-sectional view of the following steps.

[0109] Fig.26C It is shown Fig.26B Cross-sectional view of the following steps.

[0110] Fig.26D It is shown Fig.26C Cross-sectional view of the following steps.

[0111] Fig.26E It is shown Fig.26D Cross-sectional view of the following steps.

[0112] Fig.26F It is shown Fig.26E Cross-sectional view of the following steps.

[0113] Figure 26G It is shown Fig.26F Cross-sectional view of the following steps.

[0114] Fig.26H It is shown Figure 26G Cross-sectional view of the following steps.

[0115] Fig.27A is a cross-sectional view showing an example of a method for manufacturing a transistor according to a modification of the fifth embodiment.

[0116] Fig.27B It is shown Fig.27A Cross-sectional view of the following steps.

[0117] Fig.27C It is shown Fig.27B Cross-sectional view of the following steps.

[0118] Fig.27D It is shown Fig.27C Cross-sectional view of the following steps.

[0119] Fig.27E It is shown Fig.27D Cross-sectional view of the following steps.

[0120] Fig.27F It is shown Fig.27E Cross-sectional view of the following steps.

[0121] Figure 27G It is shown Fig.27F Cross-sectional view of the following steps.

[0122] Fig.27H It is shown Figure 27G Cross-sectional view of the following steps.

[0123] Fig.27I It is shown Fig.27H Cross-sectional view of the following steps.

[0124] Fig.28 is a cross-sectional view showing an example of a configuration of a transistor according to a sixth embodiment.

[0125] Fig.29 is a top view showing an example of the arrangement of a configuration of a pixel according to the sixth embodiment.

[0126] Fig.30 is a circuit diagram showing an example of a configuration of a pixel according to a seventh embodiment.

[0127] Fig.31 is a circuit diagram showing an example of a configuration of a pixel according to an eighth embodiment.

[0128] Fig.32 is a circuit diagram showing an example of a configuration of a pixel according to a ninth embodiment.

[0129] Fig.33 is a circuit diagram showing an example of a configuration of a pixel according to a tenth embodiment.

[0130] Fig.34 is a circuit diagram showing an example of a configuration of a pixel according to the eleventh embodiment.

[0131] Fig.35 is a circuit diagram showing an example of a configuration of a pixel according to a twelfth embodiment.

[0132] Fig.36 is a schematic diagram showing an overall configuration example of an electronic device.

[0133] Fig.37 is a block diagram showing an embodiment of a schematic configuration of a vehicle control system.

[0134] Fig.38 It is an explanatory diagram showing an embodiment of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0135] Hereinafter, embodiments of a light detecting element, an electronic device, and a method for manufacturing a light detecting element will be described with reference to the accompanying drawings. Hereinafter, the main components of the light detecting element, the electronic device, and the method for manufacturing a light detecting element will be mainly described, but the light detecting element, the electronic device, and the method for manufacturing a light detecting element may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0136] Figure 1 is a block diagram showing an embodiment of a system configuration of an imaging system to which the technology according to the present disclosure is applied.

[0137] like Figure 1 As shown in FIG. 1 , an imaging system 10 to which the technology according to the present disclosure is applied includes an imaging lens 11, an imaging device 20, a recording section 12, and a control section 13. The imaging system 10 is an embodiment of an electronic device of the present disclosure, and embodiments of the electronic device include a camera system mounted on an industrial robot, a vehicle-mounted camera system, and the like.

[0138] In the imaging system 10 having the above configuration, the imaging lens 11 captures incident light from a subject and forms an image on an imaging surface of the imaging device 20. The imaging device 20 photoelectrically converts the incident light captured by the imaging lens 11 in units of pixels to obtain imaging data. As the imaging device 20, an imaging device of the present disclosure described later is used.

[0139] The imaging device 20 performs predetermined signal processing (such as image recognition processing) on ​​the captured image data, and outputs data indicating the processing result and a detection signal of an address event described later (hereinafter, may be simply described as a "detection signal") to the recording section 12. A generation method of the detection signal of the address event will be described later. The recording section 12 stores data provided from the imaging device 20 via the signal line 14. The control section 13 includes, for example, a microcomputer, and controls the imaging operation in the imaging device 20.

[0140] [Imaging Apparatus According to First Configuration Embodiment (Arbitrator Method)]

[0141] Figure 2 : is a block diagram showing an embodiment of the configuration of an imaging device according to a first configuration embodiment, which serves as the imaging device 20 in the imaging system 10 to which the technology according to the present disclosure is applied.

[0142] like Figure 2 As shown in , the imaging device 20 according to the first configuration embodiment of the imaging device of the present disclosure is an asynchronous imaging device called DVS, and includes a pixel array section 21, a driving section 22, an arbitrator section (arbitration section) 23, a column processing section 24 and a signal processing section 25.

[0143] In the imaging device 20 having the above configuration, a plurality of pixels 30 are two-dimensionally arranged in a matrix (array) in the pixel array section 21. A vertical signal line VSL to be described later is wired for each pixel column for this matrix-like pixel array.

[0144] Each of the plurality of pixels 30 generates an analog signal of a voltage corresponding to the photocurrent as a pixel signal. In addition, each of the plurality of pixels 30 detects the presence or absence of an address event according to whether the amount of change in the photocurrent exceeds a predetermined threshold. Then, when an address event occurs, the pixel 30 outputs a request to the arbitrator section 23.

[0145] The driving section 22 drives each of the plurality of pixels 30 to output a pixel signal generated in each pixel 30 to the column processing section 24 .

[0146] The arbitrator section 23 arbitrates requests from each of the plurality of pixels 30 and transmits a response based on the arbitration result to the pixel 30. The pixel 30 having received the response from the arbitrator section 23 supplies a detection signal indicating the detection result (a detection signal of an address event) to the drive section 22 and the signal processing section 25. Reading the detection signal from the pixel 30 may be performed by reading a plurality of rows.

[0147] The column processing section 24 includes, for example, an A / D converter and performs processing for converting analog pixel signals output from the pixels 30 of the column into digital signals for each pixel column of the pixel array section 21. The column processing section 24 then supplies the A / D-converted digital signals to the signal processing section 25.

[0148] The signal processing section 25 performs predetermined signal processing, such as correlated double sampling (CDS) processing or image recognition processing, on the digital signal supplied from the column processing section 24. Then, the signal processing section 25 transmits the digital signal to the recording section 12 (see FIG. 1 ) via the signal line 14. Figure 1 ) provides data indicating the processing result and a detection signal provided from the arbitrator unit 23.

[0149] [Configuration Example of Pixel Array Section]

[0150] Figure 3 2 is a block diagram showing an example of the configuration of the pixel array section 21 .

[0151] In the pixel array section 21 in which a plurality of pixels 30 are two-dimensionally arranged in a matrix, each of the plurality of pixels 30 includes a light receiving section 31 , a pixel signal generating section 32 , and an address event detecting section 33 .

[0152] In the pixel 30 having the above configuration, the light receiving section 31 performs photoelectric conversion on the incident light to generate a photocurrent. Then, the light receiving section 31 is driven by the driving section 22 (see Figure 2 ) under the control of the photoelectric conversion to provide the photocurrent generated by the photoelectric conversion to the pixel signal generating unit 32 or the address event detecting unit 33.

[0153] The pixel signal generating section 32 generates a signal of a voltage as a pixel signal SIG according to the photocurrent supplied from the light receiving section 31, and supplies the generated pixel signal SIG to the column processing section 24 via the vertical signal line VSL (see FIG. 1 ). Figure 2 ).

[0154] The address event detection unit 33 detects the presence or absence of an address event based on whether the amount of change in the photocurrent from each light receiving unit 31 exceeds a predetermined threshold. For example, an address event includes an on-event indicating that the amount of change in the photocurrent exceeds an upper threshold and an off-event indicating that the amount of change is lower than a lower threshold. In addition, the detection signal of the address event includes, for example, one bit indicating the detection result of the on-event and one bit indicating the detection result of the off-event. Note that the address event detection unit 33 can be configured to detect only an on-event.

[0155] When an address event occurs, the address event detection section 33 provides a request for transmitting a detection signal of the address event to the arbitrator section 23 (see Figure 2 Then, when receiving a response to the request from the arbitrator section 23 , the address event detection section 33 supplies a detection signal of the address event to the drive section 22 and the signal processing section 25 .

[0156] [Example of Circuit Configuration of Pixel]

[0157] Figure 4 is a circuit diagram showing an example of a circuit configuration of the pixel 30. As described above, each of the plurality of pixels 30 includes a light receiving section 31, a pixel signal generating section 32, and an address event detecting section 33.

[0158] In the pixel 30 having the above configuration, the light receiving portion 31 includes a light receiving element (photoelectric conversion element) 311, a transfer transistor 312, and an overflow gate (OFG) transistor 313. For example, an N-type metal oxide semiconductor (MOS) transistor is used as the transfer transistor 312 and the OFG transistor 313. The transfer transistor 312 and the OFG transistor 313 are connected in series with each other.

[0159] The light receiving element 311 is connected between a connection node N1 common to the transfer transistor 312 and the OFG transistor 313 and the ground, and performs photoelectric conversion on incident light to generate electric charges of an amount according to the amount of incident light.

[0160] Transfer signal TRG from Figure 2 The driving section 22 shown in FIG. 1 is supplied to the gate electrode of the transfer transistor 312. The transfer transistor 312 supplies the charge photoelectrically converted by the light receiving element 311 to the pixel signal generating section 32 in response to the transfer signal TRG.

[0161] The control signal OFG is supplied from the driving section 22 to the gate electrode of the OFG transistor 313. The OFG transistor 313 supplies the electric signal generated by the light receiving element 311 to the address event detecting section 33 in response to the control signal OFG. The electric signal supplied to the address event detecting section 33 is a photocurrent including electric charges.

[0162] The pixel signal generating section 32 includes a reset transistor 321, an amplifying transistor 322, a selecting transistor 323, and a floating diffusion layer 324. As the reset transistor 321, the amplifying transistor 322, and the selecting transistor 323, for example, N-type MOS transistors are used.

[0163] The charge photoelectrically converted by the light receiving element 311 is supplied from the light receiving section 31 to the pixel signal generating section 32 by the transfer transistor 312. The charge supplied from the light receiving section 31 is accumulated in the floating diffusion layer 324. The floating diffusion layer 324 generates a voltage signal having a voltage value according to the accumulated charge. That is, the floating diffusion layer 324 converts the charge into a voltage.

[0164] The reset transistor 321 is connected between a power supply line of a power supply voltage VDD and the floating diffusion layer 324. A reset signal RST is supplied from the driving section 22 to a gate electrode of the reset transistor 321. The reset transistor 321 initializes (resets) the amount of charge in the floating diffusion layer 324 in response to the reset signal RST.

[0165] The amplifier transistor 322 and the selection transistor 323 are connected in series between a power supply line of a power supply voltage VDD and a vertical signal line VSL. The amplifier transistor 322 amplifies a voltage signal subjected to charge-voltage conversion by the floating diffusion layer 324.

[0166] The selection signal SEL is supplied from the driving section 22 to the gate electrode of the selection transistor 323. The selection transistor 323 outputs the voltage signal amplified by the amplifier transistor 322 to the column processing section 24 (see FIG. 24 ) via the vertical signal line VSL in response to the selection signal SEL. Figure 2 ) as the pixel signal SIG.

[0167] In the imaging device 20 including the pixel array section 21 in which the pixels 30 having the above-described configuration are two-dimensionally arranged, when Figure 1 When the control section 13 shown in FIG. 1 gives an instruction to start detecting an address event, the drive section 22 supplies a control signal OFG to the OFG transistor 313 of the light receiving section 31 , thereby driving the OFG transistor 313 to supply a photocurrent to the address event detecting section 33 .

[0168] Then, when an address event is detected in a specific pixel 30, the driving section 22 turns off the OFG transistor 313 of the pixel 30 and stops supplying photocurrent to the address event detection section 33. Next, the driving section 22 drives the transfer transistor 312 by supplying a transfer signal TRG to the transfer transistor 312, and transfers the charge photoelectrically converted by the light receiving element 311 to the floating diffusion layer 324.

[0169] In this manner, the imaging device 20 including the pixel array section 21 in which the pixels 30 having the above-described configuration are two-dimensionally arranged outputs only the pixel signals of the pixels 30 in which the address event is detected to the column processing section 24. Therefore, compared with the case of outputting the pixel signals of all pixels, regardless of the presence or absence of the address event, the power consumption of the imaging device 20 and the processing amount of the image processing can be reduced.

[0170] Note that the configuration of the pixel 30 illustrated here is an embodiment and is not limited to this configuration embodiment. For example, a pixel configuration without the pixel signal generating section 32 is also possible. In this pixel configuration, it is only necessary that the light receiving section 31 does not include the OFG transistor 313 and the transfer transistor 312 has the function of the OFG transistor 313.

[0171] [First Configuration Example of Address Event Detection Section]

[0172] Figure 5 1 is a block diagram showing a first configuration example of the address event detection section 33. Figure 5 As shown, the address event detection section 33 according to the present configuration example includes a current-voltage conversion section 331 , a buffer 332 , a subtractor 333 , a quantizer 334 , and a transfer section 335 .

[0173] The current-voltage conversion section 331 converts the photocurrent from the light receiving section 31 of the pixel 30 into a logarithmic voltage signal. The current-voltage conversion section 331 supplies the converted voltage signal to the buffer 332. The buffer 332 buffers the voltage signal supplied from the current-voltage conversion section 331 and supplies the buffered voltage signal to the subtractor 333.

[0174] The row drive signal is supplied from the driving section 22 to the subtractor 333. The subtractor 333 reduces the level of the voltage signal supplied from the buffer 332 according to the row drive signal. Then, the subtractor 333 supplies the voltage signal whose level has been reduced to the quantizer 334. The quantizer 334 quantizes the voltage signal supplied from the subtractor 333 into a digital signal, and outputs the digital signal to the transfer section 335 as a detection signal of an address event.

[0175] The transfer section 335 transfers the detection signal of the address event supplied from the quantizer 334 to the arbitrator section 23 and the like. When an address event is detected, the transfer section 335 supplies a request for sending the detection signal of the address event to the arbitrator section 23. Then, when a response to the request is received from the arbitrator section 23, the transfer section 335 supplies the detection signal of the address event to the driver section 22 and the signal processing section 25.

[0176] Next, a configuration example of the current-voltage conversion section 331 , the subtractor 333 , and the quantizer 334 in the address event detection section 33 will be described.

[0177] (Configuration Example of Current-Voltage Converter)

[0178] Figure 6 1 is a circuit diagram showing an example of a configuration of the current-voltage conversion section 331 in the address event detection section 33. Figure 6 As shown, the current-voltage conversion section 331 according to the present embodiment has a circuit configuration including an N-type transistor 3311, a P-type transistor 3312, and an N-type transistor 3313. As these transistors 3311 to 3313, MOS transistors are used, for example.

[0179] The N-type transistor 3311 is connected between the power supply line of the power supply voltage VDD and the signal input line 3314. The P-type transistor 3312 and the N-type transistor 3313 are connected in series between the power supply line of the power supply voltage VDD and the ground. Then, the common connection node N2 of the P-type transistor 3312 and the N-type transistor 3313 is connected to Figure 5 The gate electrode of the N-type transistor 3311 and the input terminal of the buffer 332 are shown.

[0180] The predetermined bias voltage V 偏置 is applied to the gate electrode of the P-type transistor 3312. Therefore, the P-type transistor 3312 supplies a constant current to the N-type transistor 3313. The photocurrent is input from the light receiving unit 31 to the gate electrode of the N-type transistor 3313 through the signal input line 3314.

[0181] The drain electrodes of the N-type transistor 3311 and the N-type transistor 3313 are connected to the power supply side, and such a circuit is called a source follower. The photocurrent from the light receiving section 31 is converted into a logarithmic voltage signal by two source followers connected in a loop.

[0182] (Configuration Example of Subtractor and Quantizer)

[0183] Figure 7 2 is a circuit diagram showing an example of the configuration of the subtractor 333 and the quantizer 334 in the address event detection section 33 .

[0184] The subtractor 333 according to the present embodiment includes a capacitance element 3331 , an inverter circuit 3332 , a capacitance element 3333 , and a switch element 3334 .

[0185] One end of the capacitor 3331 is connected to Figure 53331 is connected to the output terminal of the buffer 332 shown in the figure, and the other end thereof is connected to the input terminal of the inverter circuit 3332. The capacitor element 3333 is connected in parallel with the inverter circuit 3332. The switch element 3334 is connected between the two ends of the capacitor element 3333. The row drive signal is provided from the driver 22 to the switch element 3334 as an opening / closing control signal. The switch element 3334 turns on or off the path connecting the two ends of the capacitor element 3333 according to the row drive signal. The inverter circuit 3332 reverses the polarity of the voltage signal input via the capacitor element 3331.

[0186] In the subtractor 333 having the above configuration, when the switch element 3334 is turned on (closed), the voltage signal V 初始 is input to the terminal of the capacitor 3331 on the buffer 332 side, and the terminal on the opposite side is used as a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance value of the capacitor 3331 is C1, the charge Q accumulated in the capacitor 3331 初始 It is expressed by the following formula (1). On the other hand, since both ends of the capacitor 3333 are short-circuited, the capacitor 3333 does not accumulate charge.

[0187] Q 初始 = C1 × V 初始 … (1)

[0188] Next, consider that the switch element 3334 is turned off (disconnected) and the voltage of the terminal of the capacitor element 3331 on the buffer 332 side becomes V 在后 In the case of 在后 It is expressed by the following formula (2).

[0189] Q 在后 = C1 × V 在后 … (2)

[0190] On the other hand, when the capacitance value of the capacitor element 3333 is C2 and the output voltage is V 输出 When , the charge Q2 accumulated in the capacitor element 3333 is expressed by the following formula (3).

[0191] Q2 = -C2 × V 输出 … (3)

[0192] At this time, since the total amount of charge of capacitor 3331 and capacitor 3333 does not change, the following formula (4) is established.

[0193] Q 初始 = Q 在后 + Q2... (4)

[0194] When Formula (1) to Formula (3) are substituted into Formula (4) and rearranged, the following Formula (5) is obtained.

[0195] V 输出 = -(C1 / C2) × (V 在后 -V 初始 ) … (5)

[0196] Formula (5) represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1 / C2. Since it is generally desired to maximize the gain, it is preferred to design C1 to be larger and C2 to be smaller. On the other hand, when C2 is too small, kTC noise increases and the noise characteristics deteriorate. Therefore, the reduction of capacitance C2 is limited to the range of tolerable noise. In addition, since the address event detection unit 33 including the subtractor 333 is installed for each pixel 30, the capacitance element 3331 and the capacitance element 3333 have area restrictions. Taking this into account, the capacitance values ​​C1 and C2 of the capacitance elements 3331 and 3333 are determined.

[0197] exist Figure 7 , the quantizer 334 includes a comparator 3341. The comparator 3341 takes the output signal of the inverter circuit 3332 (i.e., the voltage signal from the subtractor 430) as a non-inverting (+) input, and takes a predetermined threshold voltage Vth as an inverting (-) input. Then, the comparator 3341 compares the voltage signal from the subtractor 430 with the predetermined threshold voltage Vth, and outputs a signal indicating the comparison result as a detection signal of an address event to the transfer section 335.

[0198] [Second Configuration Example of Address Event Detection Section]

[0199] Figure 8 2 is a block diagram showing a second configuration example of the address event detection section 33. Figure 8 As shown, the address event detection section 33 according to the present configuration embodiment includes a storage section 336 and a control section 337 in addition to a current-voltage conversion section 331 , a buffer 332 , a subtractor 333 , a quantizer 334 , and a transfer section 335 .

[0200] The storage section 336 is provided between the quantizer 334 and the transfer section 335, and accumulates the output of the quantizer 334 (i.e., the comparison result of the comparator 3341) based on the sampling signal provided from the control section 337. The storage section 336 may be a sampling circuit such as a switch, plastic, or capacitor, or may be a digital memory circuit such as a latch or a flip-flop.

[0201] The control section 337 provides a predetermined threshold voltage Vth to the inverting (-) input terminal of the comparator 3341. The threshold voltage Vth provided from the control section 337 to the comparator 3341 may have different voltage values ​​in a time-division manner. For example, the control section 337 provides a threshold voltage Vth1 corresponding to a turn-on event indicating that the amount of change in the photocurrent exceeds an upper threshold value and a threshold voltage Vth2 corresponding to a turn-off event indicating that the amount of change in the photocurrent is lower than a lower threshold value at different time points, so that one comparator 3341 can detect multiple types of address events.

[0202] For example, during a period in which the threshold voltage Vth2 corresponding to the off event is provided from the control section 337 to the inverting (-) input terminal of the comparator 3341, the storage section 336 may accumulate the comparison result of the comparator 3341 using the threshold voltage Vth1 corresponding to the on event. Note that the storage section 336 may be inside the pixel 30 or may be outside the pixel 30. In addition, the storage section 336 is not an essential component of the address event detection section 33. That is, the storage section 336 may not be provided.

[0203] [Image forming apparatus (scanning type) according to second configuration embodiment]

[0204] The imaging device 20 according to the first configuration embodiment described above is an asynchronous imaging device that reads events by an asynchronous reading method. However, the event reading method is not limited to the asynchronous reading method, and may be a synchronous reading method. The imaging device to which the synchronous reading method is applied is a scanning type imaging device that is the same as a general imaging device that performs imaging at a predetermined frame rate.

[0205] Fig. 9 : is a block diagram showing an embodiment of the configuration of an imaging device according to a second configuration embodiment (ie, a scanning type imaging device used as the imaging device 20 in the imaging system 10 to which the technology according to the present invention is applied).

[0206] like Fig. 9 As shown in , an imaging device 20 according to a second configuration example as an imaging device of the present disclosure includes a pixel array section 21 , a drive section 22 , a signal processing section 25 , a read region selection section 27 , and a signal generation section 28 .

[0207] The pixel array section 21 includes a plurality of pixels 30. The plurality of pixels 30 outputs output signals in response to the selection signal of the read region selection section 27. For example, Figure 7 As shown, each of the plurality of pixels 30 may have a quantizer in the pixel. The plurality of pixels 30 output an output signal corresponding to the amount of change in light intensity. Fig. 9 As shown, the plurality of pixels 30 may be two-dimensionally arranged in a matrix.

[0208] The driving section 22 drives each of the plurality of pixels 30 to output a pixel signal generated in each pixel 30 to the signal processing section 25. Note that the driving section 22 and the signal processing section 25 are circuit sections for acquiring grayscale information. Therefore, in the case of acquiring only event information, the driving section 22 and the signal processing section 25 may not be provided.

[0209] The read region selection section 27 selects some of the plurality of pixels 30 included in the pixel array section 21. For example, the read region selection section 27 selects any one or more rows among the rows included in the structure of the two-dimensional matrix corresponding to the pixel array section 21. The read region selection section 27 sequentially selects one or more rows according to a preset cycle. In addition, the read region selection section 27 may determine the selected region according to a request from each pixel 30 of the pixel array section 21.

[0210] Based on the output signal of the pixel selected by the read area selection unit 27, the signal generation unit 28 generates an event signal corresponding to an active pixel in which an event has been detected among the selected pixels. An event is an event in which light intensity changes. An active pixel is a pixel in which the amount of change in light intensity corresponding to the output signal exceeds or falls below a preset threshold. For example, the signal generation unit 28 compares the output signal of the pixel with a reference signal, detects an active pixel that outputs an output signal when the output signal is greater than or less than the reference signal, and generates an event signal corresponding to the active pixel.

[0211] Signal generation section 28 may include, for example, a column selection circuit that arbitrates signals entering signal generation section 28. Furthermore, signal generation section 28 may be configured to output not only information of active pixels that have detected an event, but also information of inactive pixels that have not detected an event.

[0212] The address information and time stamp information (e.g., (X, Y, T)) of the active pixel where the event has been detected are output from the signal generating section 28 through the output line 15. However, the data output from the signal generating section 28 may be not only the address information and time stamp information but also information in a frame format (e.g., (0, 0, 1, 0, ...)).

[0213] [Configuration Example of Chip Structure]

[0214] As a chip (semiconductor integrated circuit) structure of the imaging device 20 according to the above-described first configuration example or second configuration example, for example, a stacked chip structure may be employed. Fig.10 is an exploded perspective view schematically showing a stacked chip structure of the imaging device 20 .

[0215] like Fig.10As shown, the stacked chip structure (ie, stacked structure) has a structure in which at least two chips, a light receiving chip 201 as a first chip and a detection chip 202 as a second chip, are stacked. Figure 4 In the circuit configuration of the pixel 30 shown, each of the light receiving elements 311 is arranged on the light receiving chip 201, and all elements other than the light receiving element 311, elements of other circuit parts of the pixel 30, etc. are arranged on the detection chip 202. The light receiving chip 201 and the detection chip 202 are electrically connected via a connection portion such as a via (VIA), Cu-Cu bonding, or a bump.

[0216] Note that a configuration example in which the light receiving element 311 is arranged on the light receiving chip 201 and elements other than the light receiving element 311, elements of other circuit parts of the pixel 30, etc. are arranged on the detection chip 202 is illustrated here, but the present disclosure is not limited to this configuration example.

[0217] For example, in Figure 4 In the circuit configuration of the pixel 30 shown, each element of the light receiving section 31 can be arranged on the light receiving chip 201, and elements other than the light receiving section 31, elements of other circuit parts of the pixel 30, etc. can be arranged on the detection chip 202. In addition, each element of the light receiving section 31 and the reset transistor 321 and the floating diffusion layer 324 of the pixel signal generating section 32 can be arranged on the light receiving chip 201, and other elements can be arranged on the detection chip 202. In addition, part of the elements constituting the address event detecting section 33 can be arranged on the light receiving chip 201 together with each element of the light receiving section 31, etc.

[0218] [Configuration Example of Column Processing Unit]

[0219] Fig.11 1 is a block diagram showing an example of a configuration of the column processing section 24 of the imaging device 20 according to the first configuration example. Fig.11 As shown, the column processing section 24 according to the present embodiment includes a plurality of analog-to-digital converters (ADCs) 241 arranged for each pixel column of the pixel array section 21 .

[0220] Note that an example of a configuration in which the analog-to-digital converters 241 are arranged in a one-to-one correspondence with respect to the pixel columns of the pixel array section 21 has been illustrated here, but the present disclosure is not limited to this example of a configuration. For example, the analog-to-digital converters 241 may be arranged in units of a plurality of pixel columns, and the analog-to-digital converters 241 may be used in a time-division manner between the plurality of pixel columns.

[0221] The analog-to-digital converter 241 converts the analog pixel signal SIG provided via the vertical signal line VSL into a digital signal having a bit depth greater than the detection signal of the above-mentioned address event. For example, when the detection signal of the address event is 2 bits, the pixel signal is converted into a digital signal of 3 bits or more (16 bits, etc.). The analog-to-digital converter 241 provides the digital signal generated by the analog-to-digital conversion to the signal processing unit 25.

[0222] <First Embodiment>

[0223] [Example of Circuit Configuration of Pixel]

[0224] Fig.12 is a circuit diagram showing an example of the configuration of the pixel 30 according to the first embodiment.

[0225] In the first embodiment, no Figure 4 The pixel signal generating unit 32 and the transfer transistor 312 and the OFG transistor 313 of the light receiving unit 31 are shown in FIG. Fig.12 3 is a diagram showing the light receiving section 31 and the current-voltage conversion section 331 .

[0226] The current-voltage conversion section 331 includes an amplifier circuit AMPC and a feedback circuit FC.

[0227] The amplifier circuit AMPC is connected to the input node N 输入 With output node N 输出 The amplifier circuit AMPC amplifies the input node N 输入 The input signal is output to the output node N. 输出 The amplifier circuit AMPC includes a transistor MA1 and a current source 3315. The transistor MA1 is connected to the output node N 输出 The gate of transistor MA1 is electrically connected to input node N 输入 The current source 3315 is connected between the power supply voltage VDD and the output node N 输出 between.

[0228] Feedback circuit FC is connected to the input node N 输入 With output node N 输出 The feedback circuit FC is based on the output node N 输出 By setting the feedback loop of the feedback circuit FC, at the input node N 输入 The input signal at can be logarithmically transformed and output to the output node N 输出 The feedback circuit FC includes a transistor ML1. The transistor ML1 is connected to the input node N 输入 The gate of transistor ML1 is electrically connected to output node N输出 .

[0229] Fig.12 Each of the transistors ML1 and MA1 shown in FIG. Figure 6 The N-type transistors 3311 and 3313 shown in FIG. Fig.12 The current source 3315 shown in FIG. Figure 6 Corresponding to the P-type transistor 3312 shown in .

[0230] Fig.13 is a top view showing an example of the arrangement of the configuration of the pixel 30 according to the first embodiment. Fig.13 Shows Fig.12 The arrangement of the pixel 30 configuration is shown.

[0231] The pixel 30 further includes an extraction electrode 315. The extraction electrode 315 is connected between the light receiving element 311 and the source of the transistor ML1. The photocurrent is extracted via the extraction electrode 315.

[0232] exist Fig.13 In the illustrated embodiment, for example, the length of the gate electrode of transistor ML1 in the channel length direction is substantially the same as the length of the gate electrode of transistor MA1 in the channel length direction.

[0233] Fig.14 is a cross-sectional view showing an example of the configuration of the transistors ML1 and MA1 according to the first embodiment. Fig.14 The upper part of FIG. 1 shows a cross-sectional view of the transistor MA1 . Fig.14 The lower part of FIG. 1 shows a cross-sectional view of transistor ML1 .

[0234] The transistors ML1 and MA1 are provided on a substrate surface S1 of a substrate S. The substrate S is, for example, a semiconductor substrate such as a silicon (Si) substrate. In addition, the substrate S is, for example, a P-type silicon substrate.

[0235] The transistor ML1 includes a gate electrode 101a, a source layer 102a, a drain layer 103a, and a gate insulating film 104a. The transistor MA1 includes a gate electrode 101b, a source layer 102b, a drain layer 103b, and a gate insulating film 104b.

[0236] The gate insulating film 104a of the transistor ML1 is thicker than the gate insulating film ab of the transistor MA1. Therefore, the subthreshold slope of the transistor ML1 can be made higher than the subthreshold slope of the transistor MA1. Therefore, the event detection sensitivity can be improved. Note that reference will be made later. Fig.15 Describe the details of the subthreshold slope.

[0237] Fig.15is a diagram showing an example of transfer characteristics of the transistors ML1 and MA1 according to the first embodiment. Fig.15 is a graph showing the results of the simulation. Fig.15 In the graph shown, the vertical axis represents the drain current (Id), and the horizontal axis represents the gate-source voltage (Vgs).

[0238] The subthreshold slope is when the drain current (Id) is Fig.15 The change in voltage (Vgs) when a single digit is added to the IV curve shown in FIG.

[0239] The subthreshold slope Ss-th is expressed by the following formula (6) using the capacitance Cd of the depletion layer, the capacitance Cox of the gate insulating film (gate oxide film), and the thermal voltage kT / q.

[0240] [Mathematical formula 1]

[0241]

[0242] There is a relationship between the capacitance Cox of the gate insulating film and the thickness Tox of the gate insulating film: Cox∝1 / Tox. Fig.14 As shown, the subthreshold slope of the transistor ML1 can be increased by increasing the gate insulating film of the transistor ML1. By increasing the subthreshold slope of the transistor ML1 included in the feedback circuit FC, the event detection sensitivity can be improved.

[0243] exist Fig.15 In the illustrated embodiment, the subthreshold slope of transistor ML1 is greater than the subthreshold slope of transistor MA1. The subthreshold slope of transistor ML1 is, for example, about 100 mV / decade or more. The subthreshold slope of transistor MA1 is, for example, about 60 mV / decade to about 100 mV / decade.

[0244] Fig.16 is a diagram showing an example of the relationship between the detection sensitivity and the light amount in the pixel 30 according to the first embodiment. Fig.16 In the graph of , the vertical axis represents detection sensitivity (logarithmic sensitivity), and the horizontal axis represents light quantity. Fig.16 It is shown Fig.15 A graph of the slope of the IV curve.

[0245] In the first embodiment, the subthreshold slope of the transistor TL1 is, for example, 10 mV / decae or more. On the other hand, in the comparative example, the subthreshold slope of the transistor TL1 is approximately the same as the subthreshold slope of the transistor TA1 (approximately 60 mV / decade to approximately 100 mV / decade).

[0246] like Fig.16As shown, in the weak inversion region of the gate-source voltage Vgs in which the transistor ML1 operates, the detection sensitivity in the first embodiment is higher than that in the comparative example.

[0247] The thickness of the gate insulating film of the transistor ML1 is, for example, not less than 5 nm. The threshold slope of the transistor ML1 is, for example, not less than 100 mV / decade.

[0248] [Manufacturing method]

[0249] 17A to 17H is a cross-sectional view showing an example of a method for manufacturing the transistors ML1 and MA1 according to the first embodiment. 17A to 17H The left side of shows a method of manufacturing the transistor ML1 , and the right side of shows a method of manufacturing the transistor MA1 .

[0250] First, if Fig.17A As shown, a sacrificial oxide film 111 is formed on a substrate S. Afterwards, channel impurities are introduced into the substrate S by ion implantation, and the wafer is heat treated to activate the impurities. Thus, a channel impurity layer (channel impurity implantation region) 112 is formed. The channel impurity is, for example, a P-type impurity such as boron.

[0251] Next, if Fig. 17B As shown, the sacrificial oxide film 111 is removed, and an insulating film 113 is formed on the channel impurity layer 112. The insulating film 113 is a relatively thick oxide film.

[0252] Next, if Fig. 17C As shown in FIG. 1 , a resist 114 is formed in a region Ar of the insulating film 113. Fig.13 The region of the gate electrode of transistor ML1 shown corresponds.

[0253] Next, if Fig.17D As shown, the insulating film 113 is removed using the resist 114 as a mask. For example, the insulating film 113 is removed by solution etching.

[0254] Next, if Fig.17E As shown, the resist 114 is removed. Then, an insulating film 115 is formed. The insulating film 115 is an oxide film thinner than the insulating film 113. Note that Fig.17E In the step shown, the insulating film 113 also becomes thicker.

[0255] Next, if Fig.17F As shown, a conductive layer 116 is formed on the insulating films 113 and 115. The conductive layer 116 is, for example, a polysilicon layer.

[0256] Next, if Figure 17G As shown in FIG. 1 , the conductive layer 116 is processed. Thus, a Fig.14 The gate electrodes 101a and 101b of the transistors ML1 and MA1 are shown. In addition, the insulating film 113 corresponds to the gate insulating film 104a of the transistor ML1. The insulating film 115 corresponds to the gate insulating film 104b of the transistor MA1.

[0257] Next, if Fig.17H As shown in , lightly doped drain (LDD) impurities are introduced into the substrate S by ion implantation using the conductive layer 116 (gate electrode) as a mask. Thereafter, sidewall insulating films 117 are formed on both sides of the conductive layer 116. Thereafter, using each sidewall insulating film 117 as a mask, source impurities and drain impurities are introduced into the substrate S by ion implantation. The source impurities and drain impurities are, for example, N-type impurities such as phosphorus. Thereafter, the impurities are activated by heat treatment to form an LDD layer 118, source layers 102a and 102b, and drain layers 103a and 103b.

[0258] As described above, according to the first embodiment, the gate insulating film 104a of the transistor TL1 is thicker than the gate insulating film 104b of the transistor TA1. Therefore, the subthreshold slope of the transistor TL1 can be increased, and the event detection sensitivity can be improved.

[0259] In a first embodiment, if Fig.12 As shown, the current-voltage conversion unit 331 is provided with two transistors. Generally, the event detection sensitivity can be improved by increasing the number of transistors. However, when the number of transistors increases, miniaturization becomes difficult due to the increase in occupied area. On the other hand, in the first embodiment, the event detection sensitivity can be improved while suppressing the increase in the number of transistors by adjusting the thickness of the gate insulating film.

[0260] <Modification of First Embodiment>

[0261] FIG. 18A to FIG. 18I 2 is a cross-sectional view showing an example of a method for manufacturing transistors ML1 and MA1 according to a modification of the first embodiment. 18A to 18H The left side of shows a method for manufacturing the transistor ML1 , and the right side of shows a method for manufacturing the transistor MA1 .

[0262] The modification example of the first embodiment is different from the first embodiment in the method of forming the gate insulating film 104 a of the transistor ML1 .

[0263] First, if Fig.18A As shown, a sacrificial oxide film 111 is formed on a substrate S. Afterwards, channel impurities are introduced into the substrate S by ion implantation, and the wafer is heat treated to activate the impurities. Thus, a channel impurity layer (channel impurity implantation region) 112 is formed. The channel impurity is, for example, a P-type impurity such as boron.

[0264] Next, if Fig.18B As shown, the sacrificial oxide film 111 is removed, and an insulating film 121 is formed on the channel impurity layer 112. The insulating film 121 is a relatively thin oxide film.

[0265] Next, if Fig. 18C As shown, a material layer 122 is formed on the insulating film 121. The material layer 122 is, for example, a silicon nitride (SiN) layer.

[0266] Next, if Fig.18D As shown, the material layer 122 in the region Ar is removed. Fig.13 The region of the gate electrode of transistor ML1 shown corresponds.

[0267] Next, if Fig.18E As shown in FIG. 1 , a local oxidation of silicon (LOCOS) oxidation process is performed to form an insulating film 123. The insulating film 123 is an oxide film thicker than the insulating film 121.

[0268] Next, if Fig.18F As shown, material layer 122 is removed.

[0269] Next, if Figure 18G As shown, a conductive layer 116 is formed on the insulating films 121 and 123. The conductive layer 116 is, for example, a polysilicon layer.

[0270] Next, if Fig.18H As shown in FIG. 1 , the conductive layer 116 is processed. Thus, a Fig.14 The gate electrodes 101a and 101b of the transistors ML1 and MA1 are shown. In addition, the insulating film 123 corresponds to the gate insulating film 104a of the transistor ML1. The insulating film 121 corresponds to the gate insulating film 104b of the transistor MA1. Therefore, the insulating film 123 is formed as the gate insulating film 104a of the transistor ML1 by the LOCOS oxidation process.

[0271] Next, if Fig.18I As shown, an LDD layer 118, source layers 102a and 102b, and drain layers 103a and 103b are formed. Note that Fig.18I The steps shown in Fig.17H The steps are the same as shown in .

[0272] In addition, if Fig.18H As shown, the end of the insulating film 123 on the substrate S side is closer to the substrate side than the end of the insulating film 121 on the substrate S side. This is because the insulating film 123 is formed to penetrate the substrate S by the LOCOS oxidation process.

[0273] As in the modification of the first embodiment, the method of forming the gate insulating film 104a of the transistor ML1 may be changed. In this case, similar effects to those of the first embodiment can be obtained.

[0274] <Second Embodiment>

[0275] Fig.19 2 is a diagram showing an example of the configuration of the pixel 30 and the signal processing section 25 according to the second embodiment. Fig.19 and Figure 5 and Figure 7 The corresponding part in .

[0276] The second embodiment is different from the first embodiment in that the configuration of the pixels 30 is divided and arranged on a plurality of substrates.

[0277] The imaging device 20 further includes a first semiconductor chip CH1 and a second semiconductor chip CH2. The first semiconductor chip CH1 and the second semiconductor chip CH2 are electrically connected to each other using, for example, wire bonding (Cu-Cu bonding) CCC.

[0278] The first semiconductor chip CH1 is, for example, Fig.10 The second semiconductor chip CH2 corresponds to the light receiving chip 201 shown in FIG. Fig.10 It corresponds to the detection chip 202 shown in FIG.

[0279] exist Fig.19 In the embodiment shown in , the light receiving element 311 and the transistors ML1 and MA1 are arranged on the first semiconductor chip CH1. Fig.19 In the embodiment shown in , the current source 3315 and subsequent circuits after the buffer 332 are arranged in the second semiconductor chip CH2. Fig.19 The subsequent circuits shown include, for example, a buffer 332, a comparator 3341, a signal processing section 25, etc. Note that the arrangement and division of the configuration of the pixels 30 between the first semiconductor chip CH1 and the second semiconductor chip CH2 are not limited to Fig.19 The embodiment shown in .

[0280] The buffer 332 also functions as a buffer amplifier (signal amplification section). That is, the buffer 332 amplifies the voltage signal.

[0281] The comparator (comparison section) 3341 compares the voltage of the voltage signal amplified by the buffer 332 with a predetermined voltage. As described above, the comparator 3341 outputs a signal indicating the comparison result as a detection signal of an address event.

[0282] Here, the thickness of the gate insulating film of the transistor ML1 is defined as thickness Tox1. The thickness of the gate insulating film of the transistor MA1 is defined as thickness Tox2. The thickness of the gate insulating film of the transistor constituting the subsequent circuit is defined as thickness Tox0.

[0283] The gate insulating film of transistor ML1 is thicker than the gate insulating film of the transistor included in the subsequent circuit (Tox1>Tox0). Generally, in order to increase speed, reduce power consumption, etc., the gate insulating film of the transistor of the subsequent circuit is preferably thin. On the other hand, for event detection sensitivity, the gate insulating film of transistor ML1 is preferably thick.

[0284] Furthermore, according to the second embodiment, the subthreshold slope of the transistor ML1 can be made higher than the subthreshold slope of a transistor included in a subsequent circuit. Therefore, the event detection sensitivity can be improved.

[0285] As in the second embodiment, the configuration of the pixel 30 may be divided and arranged on a plurality of substrates. In this case, similar effects to those of the first embodiment can also be obtained.

[0286] Note that, as in the first embodiment, the thickness Tox1 of the gate insulating film of the transistor ML1 may be thicker than the thickness Tox2 of the gate insulating film of the transistor MA1 (Tox1>Tox2), but may be substantially the same as the thickness Tx2 (Tox1≈Tox2>Tox0). That is, the gate insulating film of the transistor MA1 may also be thicker than the gate insulating film of a transistor included in a subsequent circuit. In this case, the transistors ML1 and MA1 can be manufactured in the same step, and an increase in the number of steps can be suppressed.

[0287] <Third Embodiment>

[0288] Fig. 20 is a circuit diagram showing an example of the configuration of the pixel 30 according to the third embodiment. The third embodiment is different from the first embodiment in that a Figure 4 2 and 3. The pixel signal generating section 32 and the transistors TG0 and TG1 of the light receiving section 31 are shown in FIG.

[0289] The pixel 30 further includes a pixel signal generating section 32 .

[0290] The light receiving unit 31 further includes transistors TG0 and TG1. Fig. 20 In the light receiving unit 31 shown in FIG. 1 , transistors TG0 and TG1 are connected to Figure 4 The transfer transistor 312 and OFG transistor 313 are shown to correspond.

[0291] The transistor TG0 is connected between the light receiving element 311 and the floating diffusion layer 324 of the pixel signal generating section 32. The transistor TG0 transfers the charge generated in the light receiving element 311 to the floating diffusion layer (charge accumulating section) 324.

[0292] The transistor TG1 is connected between the light receiving element 311 and the input node N of the current-voltage conversion unit 331. 输入 The transistor TG1 transfers the charge generated by the light receiving element 311 to the input node N 输入 .

[0293] At the time of event detection, transistor TG0 is turned off, and transistor TG1 is turned on. Therefore, event detection by the photocurrent generated in the light receiving element 311 is performed. At the time of imaging, transistors TG0 and TG1 are turned off, and transistor TG0 is turned on after a predetermined accumulation time has passed. Therefore, the signal charge accumulated in the light receiving element 311 can be transferred to the floating diffusion layer 324.

[0294] exist Fig. 20 In the pixel signal generating section 32 shown in FIG. 1 , each of the transistors RST, AMP, and SEL is connected to, for example, Figure 6 The reset transistor 321, the amplifying transistor 322, and the selecting transistor 323 shown in FIG. 3 correspond to each other.

[0295] As described above, the thickness of the gate insulating film of the transistors ML1 and MA1 is thickness Tox1 and Tox2, respectively. As described above, the thickness of the gate insulating film of the transistor included in the subsequent circuit is thickness Tox0. The thickness of the gate insulating film of the transistors AMP, SEL, RST, TG0 and TG1 is defined as thickness Tox3, Tox4, Tox5, Tox6 and Tox7, respectively.

[0296] The relationship between the thicknesses of the gate insulating films of the respective transistors is expressed by, for example, the following formula (7).

[0297] Tox1 > Tox2 ≈ Tox3 ≈ Tox4 ≈ Tox5 ≈ Tox6 ≈Tox7 … (7)

[0298] That is, the gate insulating film of the transistor ML1 is thicker than the gate insulating films of the transistors TG0 and TG1 .

[0299] Specifically, the relationship between the thicknesses of the gate insulating films of the transistors is expressed by, for example, the following formula (8).

[0300] Tox1 > Tox4 ≈ Tox5 ≈ Tox6 ≈ Tox7 > Tox2 ≈ Tox3 … (8)

[0301] In the case of formula (8), the gate insulating films of the transistors MA1 and AMP are relatively thin, so that the current gain can be improved.

[0302] Fig.21 is a top view showing an example of the arrangement of the configuration of the pixel 30 according to the third embodiment.

[0303] like Fig.21 As shown, the light receiving element 311 is connected to the pixel signal generating section 32 and the current-voltage converting section 331 (address event detecting section 33 ) via each of transistors TG0 and TG1 .

[0304] As in the third embodiment, it is possible to provide the pixel signal generating section 32 and the transistors TG0 and TG1 of the light receiving section 31. In this case as well, it is possible to obtain effects similar to those of the first embodiment.

[0305] <Fourth Embodiment>

[0306] Fig. 22 is a cross-sectional view showing an example of the configuration of transistors ML1 and MA1 according to the fourth embodiment. In the fourth embodiment, the channel length of the transistor ML1 is different from that of the first embodiment.

[0307] like Fig. 22 As shown, the channel length of transistor ML1 is shorter than the channel length of transistor MA1. More specifically, the length of the channel length direction of gate electrode 101a of transistor ML1 is shorter than the length of the channel length direction of gate electrode 101b of transistor MA1. Therefore, the effective gate length L of transistor ML1 can be shortened. Therefore, the subthreshold slope of transistor ML1 can be increased by the short channel effect, and the event detection sensitivity can be improved.

[0308] Note that the configuration of the transistor ML1 can be determined based on, for example, the following formula (9) which is Brews' formula in order to obtain a short channel effect.

[0309] Lmin = 0.4× {rj × d × (Ws + Wd) 2} 1 / 3 … (9)

[0310] In formula (9), Lmin represents the minimum channel length. rj represents the junction depth of the source-drain impurity region. d represents the thickness of the gate insulating film converted into a silicon oxide film. Ws represents the length of the depletion layer extending from the source terminal. Wd represents the length of the depletion layer extending from the drain terminal.

[0311] Fig.23 is a top view showing an example of the arrangement of the configuration of the pixel 30 according to the fourth embodiment.

[0312] like Fig.23 As shown, the gate electrode 101 a of the transistor ML1 is smaller than the gate electrode 101 b of the transistor MA1 .

[0313] As in the fourth embodiment, the magnitude relationship of the channel lengths between the transistors MA1 and ML1 may be changed. In this case, similar effects to those of the first embodiment can be obtained.

[0314] <Fifth Embodiment>

[0315] Fig.24 is a cross-sectional view showing an example of the configuration of transistors ML1 and MA1 according to the fifth embodiment. In the fifth embodiment, the channel length of the transistor ML1 is different from that of the first embodiment.

[0316] The transistor ML1 includes a drain extension (drain extension region) 103c in contact with the drain layer 103a. The impurity concentration of the drain extension 103c is lower than the impurity concentration of the drain layer 103a. The drain extension 103c extends toward the opposite source layer 102a below the gate electrode 101a (on the substrate S side). The effective gate length L of the transistor ML1 can be shortened by the drain extension 103c. Therefore, the subthreshold slope of the transistor ML1 can be increased by the short channel effect, and the event detection sensitivity can be improved.

[0317] Fig.25 is a top view showing an example of the arrangement of the configuration of the pixel 30 according to the fourth embodiment.

[0318] The drain extension 103c extends from the drain layer 103a. Furthermore, the drain extension 103c is arranged to overlap with the gate electrode 101a of the transistor ML1 when viewed from a direction substantially perpendicular to the substrate surface (substrate surface S1) on which the transistor ML1 is provided.

[0319] Note that Fig.25 As shown, the gate electrode 101 a of the transistor ML1 may have substantially the same size as the gate electrode 101 b of the transistor MA1 .

[0320] FIG. 26A to FIG. 26H is a cross-sectional view showing an example of a method for manufacturing transistors ML1 and MA1 according to the fifth embodiment. FIG. 26A to FIG. 26H The left side of shows a method of manufacturing the transistor ML1 , and the right side of shows a method of manufacturing the transistor MA1 .

[0321] First, if Fig.26AAs shown, a sacrificial oxide film 111 is formed on a substrate S. After that, channel impurities are introduced into the substrate S by ion implantation, drain impurities are introduced into the substrate S by ion implantation, and the wafer is heat treated to activate the impurities. Thus, a channel impurity layer (channel impurity implantation region) 112 and a drain extension 103c are formed. The channel impurity is, for example, a P-type impurity such as boron. The drain impurity is, for example, an N-type impurity such as phosphorus.

[0322] Afterwards, if FIG. 26B to FIG. 26H As shown, the same method as described in the first embodiment is performed. FIG. 17B to FIG. 17H The steps are similar to the steps in .

[0323] Note that in the fifth embodiment, if Fig.26A As shown, the drain extension 103c is formed before forming the insulating film 113. The drain impurities can be implanted with low energy, and the drain extension 103c can be formed relatively shallowly in some cases. By forming the drain extension 103c to be shallow, the change in threshold voltage due to the short channel effect can be suppressed. However, the formation of the drain extension 103c can be performed after the insulating film 113 is formed. Since the heat treatment time after the ion implantation of the drain impurities is short, the diffusion of the impurities after the ion implantation is small, and the drain extension 103c can be formed relatively shallowly in some cases. By forming the drain extension 103c to be shallow, the change in threshold voltage due to the short channel effect can be suppressed.

[0324] As in the fifth embodiment, the magnitude relationship of the channel lengths may be changed between the transistor MA1 and the transistor ML1. In this case, similar effects to those of the first embodiment can be obtained.

[0325] <Variation of Fifth Embodiment>

[0326] FIG. 27A to FIG. 27I is a cross-sectional view showing an example of a method for manufacturing transistors ML1 and MA1 according to a modification of the fifth embodiment. FIG. 27A to FIG. 27I The left side of shows a method of manufacturing the transistor ML1 , and the right side of shows a method of manufacturing the transistor MA1 .

[0327] The modification of the fifth embodiment is different from the fifth embodiment in the method of forming the gate insulating film 101 a of the transistor ML1 . The modification of the fifth embodiment is a combination of the modification of the fifth embodiment and the first embodiment.

[0328] First, if Fig.27AAs shown, a sacrificial oxide film 111 is formed on a substrate S. After that, channel impurities are introduced into the substrate S by ion implantation, drain impurities are introduced into the substrate S by ion implantation, and the wafer is heat treated to activate the impurities. Thus, a channel impurity layer (channel impurity implantation region) 112 and a drain extension 103c are formed. The channel impurity is, for example, a P-type impurity such as boron. The drain impurity is, for example, an N-type impurity such as phosphorus.

[0329] Afterwards, if FIG. 27B to FIG. 27I As shown, the same modification as described in the first embodiment is performed. FIG. 18B to FIG. 18I The steps are similar to the steps in .

[0330] Note that in a modification of the fifth embodiment, Fig.27A As shown, the drain extension portion 103c is formed before forming the insulating film 123. However, as described in the fifth embodiment, the formation of the drain extension portion 103c may be performed after forming the insulating film 123.

[0331] <Sixth Implementation Method>

[0332] Fig.28 is a cross-sectional view showing an example of the configuration of transistors ML1 and MA1 according to the sixth embodiment. The sixth embodiment is different from the fifth embodiment in that an extension (extension region) is provided in the source layer of the transistor ML1 instead of the drain layer.

[0333] The transistor ML1 includes a source extension (source extension region) 102c in contact with the source layer 102a. The impurity concentration of the source extension 102c is lower than that of the source layer 102a. The source extension 102c extends toward the opposite drain layer 103a below the gate electrode 101a (on the substrate S side). The source extension 102c can shorten the effective gate length L of the transistor ML1. Therefore, the subthreshold slope of the transistor ML1 can be increased by the short channel effect, and the event detection sensitivity can be improved.

[0334] Fig.29 is a top view showing an example of the arrangement of the configuration of the pixel 30 according to the sixth embodiment.

[0335] The source extension portion 102c extends from the source layer 102a. In addition, the source extension portion 102c is arranged to overlap with the gate electrode 101a of the transistor ML1 when viewed from a direction substantially perpendicular to the substrate surface (substrate surface S1) on which the transistor ML1 is provided.

[0336] Note that Fig.29 As shown, the gate electrode 101 a of the transistor ML1 may have substantially the same size as the gate electrode 101 b of the transistor MA1 .

[0337] As in the sixth embodiment, the extension portion (extension region) may be provided in the source layer of the transistor ML1 instead of the drain layer. In this case, similar effects to those of the fifth embodiment can be obtained.

[0338] <Seventh Embodiment>

[0339] Fig.30 2 is a circuit diagram showing an example of a configuration of a pixel 30 according to a seventh embodiment. The seventh embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0340] The feedback circuit FC further includes a transistor MB1. The transistor MB1 is connected to the input node N 输入 The transistor MB1 is connected to the diode.

[0341] As a boost circuit, the transistor MB1 amplifies the voltage of the node between the transistor ML1 and the transistor MB1, and outputs the amplified voltage to the input node N 输入 By setting transistor MB1, the event detection sensitivity can be improved.

[0342] Furthermore, at least one gate insulating film of the transistors ML1 and MB1 is thicker than the gate insulating film of the transistor MA1 .

[0343] As in the seventh embodiment, the configuration of the current-voltage conversion section 331 may be different. In this case as well, similar effects to those of the first embodiment can be obtained.

[0344] The second embodiment can be combined with the seventh embodiment. In this case, at least one gate insulating film of the transistors ML1 and MB1 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistor MA1 may also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0345] <Eighth Implementation Method>

[0346] Fig.31 2 is a circuit diagram showing an example of a configuration of a pixel 30 according to an eighth embodiment. The eighth embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0347] Compared with the seventh embodiment, the feedback circuit FC further includes a transistor MB2. The transistor MB2 is connected to the input node N 输入 The transistor MB1 is connected to the diode.

[0348] As a boost circuit, the transistors MB1 and MB2 amplify the voltage of the node between the transistors ML1 and MB2, and output the amplified voltage to the input node N 输入 By setting transistors MB1 and MB2, the event detection sensitivity can be improved.

[0349] Therefore, multiple transistors can be connected at the input node N 输入 and between transistor ML1.

[0350] In addition, at least one gate insulating film of the transistors ML1 , MB1 , and MB2 is thicker than the gate insulating film of the transistor MA1 .

[0351] As in the eighth embodiment, the configuration of the current-voltage conversion section 331 may be different. In this case as well, similar effects to those of the first embodiment can be obtained.

[0352] In addition, the second embodiment can be combined with the eighth embodiment. In this case, at least one gate insulating film of the transistors ML1, MB1, and MB2 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistor MA1 may also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0353] <Ninth Embodiment>

[0354] Fig.32 2 is a circuit diagram showing an example of a configuration of a pixel 30 according to a ninth embodiment. The ninth embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0355] The feedback circuit FC further comprises a transistor ML2. The amplifier circuit AMPC further comprises a transistor MA2.

[0356] Transistor ML2 is connected to the input node N 输入 The transistor ML2 is, for example, an N-type transistor. The gate of the transistor ML2 is connected to a node between the transistors MA1 and MA2.

[0357] Transistor MA2 is connected to the output node N 输出 The transistor MA2 is, for example, an N-type transistor. The gate of the transistor MA2 is connected to a node between the transistors ML1 and ML2.

[0358] The transistors ML1 and MA2 constitute a logarithmic conversion circuit (logarithmic conversion section), and the transistors ML2 and MA1 constitute a logarithmic conversion circuit.

[0359] As a boost circuit, the transistor ML2 amplifies the voltage of the node between the transistor ML1 and the transistor ML2 and outputs the amplified voltage to the input node N 输入 By setting transistors ML2 and MA2, the event detection sensitivity can be improved.

[0360] Furthermore, at least one gate insulating film of the transistors ML1 and ML2 is thicker than the gate insulating films of the transistors MA1 and MA2 .

[0361] As in the ninth embodiment, the configuration of the current-voltage conversion section 331 may be changed. In this case as well, similar effects to those of the first embodiment can be obtained.

[0362] In addition, the second embodiment can be combined with the ninth embodiment. In this case, at least one gate insulating film of the transistors ML1 and ML2 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistors MA1 and MA2 may also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0363] <Tenth Implementation Method>

[0364] Fig.33 10 is a circuit diagram showing an example of a configuration of a pixel 30 according to the tenth embodiment. The eighth embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0365] Compared with the ninth embodiment, the feedback circuit FC further includes a transistor ML3. Compared with the ninth embodiment, the amplifier circuit AMPC further includes a transistor MA3.

[0366] Transistor ML3 is connected to the input node N 输入 The transistor ML3 is, for example, an N-type transistor. The gate of the transistor ML3 is connected to a node between the transistors MA1 and MA2.

[0367] Note that the gate of transistor ML2 is connected to a node between transistors MA2 and MA3 .

[0368] Transistor MA3 is connected to the output node N 输出 The transistor MA3 is, for example, an N-type transistor. The gate of the transistor MA3 is connected to a node between the transistor ML1 and the transistor ML2.

[0369] Note that the gate of transistor MA2 is connected to a node between transistor ML2 and transistor ML3 .

[0370] Therefore, multiple transistors can be connected at the input node N 输入Between the transistor ML1 and the output node N. 输出 Between transistor MA1.

[0371] The transistors ML1 and MA3 constitute a logarithmic conversion circuit (logarithmic conversion section), the transistors ML2 and MA2 constitute a logarithmic conversion circuit, and the transistors ML3 and MA1 constitute a logarithmic conversion circuit.

[0372] As a boost circuit, the transistors ML2 and ML3 amplify the voltage of the node between the transistors ML1 and ML2 and output the amplified voltage to the input node N 输入 By setting transistors ML2, ML3, MA2, and MA3, the event detection sensitivity can be improved.

[0373] Furthermore, at least one gate insulating film of the transistors ML1 , ML2 , and ML3 is thicker than the gate insulating films of the transistors MA1 , MA2 , and MA3 .

[0374] As in the tenth embodiment, the configuration of the current-voltage conversion section 331 may be different. In this case as well, similar effects to those of the first embodiment can be obtained.

[0375] In addition, the second embodiment can be combined with the tenth embodiment. In this case, at least one gate insulating film of the transistors ML1, ML2, and ML3 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistors MA1, MA2, and MA3 may also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0376] <Eleventh Embodiment>

[0377] Fig.34 3 is a circuit diagram showing an example of a configuration of a pixel 30 according to an eleventh embodiment. The eleventh embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0378] The current-voltage conversion unit 331 further includes a buffer BF. The buffer BF is connected to the input node N 输入 With the amplification node N 放大 between.

[0379] Buffer BF includes transistor MBF and current source 3316 .

[0380] The transistor MBF is connected between the power supply voltage VDD and the amplification node N 放大 The gate of transistor MBF is connected to the input node N 输入 The transistor MBF is, for example, an N-type transistor.

[0381] The current source 3316 is connected to the amplification node N 放大 The current source 3316 provides a bias current to the transistor MBF.

[0382] As in the eleventh embodiment, the configuration of the current-voltage conversion section 331 may be different. In this case as well, similar effects to those of the first embodiment can be obtained.

[0383] In addition, the second embodiment can be combined with the eleventh embodiment. In this case, the gate insulating film of the transistor ML1 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistors MA1 and MBF can also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0384] <Twelfth Implementation Method>

[0385] Fig.35 2 is a circuit diagram showing an example of a configuration of a pixel 30 according to a twelfth embodiment. The twelfth embodiment is different from the first embodiment in the configuration of a current-voltage conversion section 331 .

[0386] Compared with the eleventh embodiment, the feedback circuit FC in the twelfth embodiment is further provided with a transistor MB1. Therefore, the twelfth embodiment is a combination of the eleventh embodiment and the seventh embodiment.

[0387] Furthermore, at least one of the gate insulating films of the transistor ML1 and the transistor MB1 is thicker than the gate insulating film of the transistor MA1 .

[0388] As in the twelfth embodiment, the configuration of the current-voltage conversion section 331 may be different. In this case as well, similar effects to those of the first embodiment can be obtained.

[0389] In addition, the second embodiment can be combined with the twelfth embodiment. At least one gate insulating film of the transistors ML1 and MB1 is thicker than the gate insulating film of the transistor included in the subsequent circuit. Note that the gate insulating film of the transistor MA1 and the transistor MBF may also be thicker than the gate insulating film of the transistor included in the subsequent circuit.

[0390] <Application Example of Electronic Device>

[0391] Fig.36 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0392] The camera 2000 includes an optical section 2001 including a lens group and the like, an imaging device 2002 to which the above-described imaging system 10 and the like (hereinafter, the imaging system is referred to as the imaging system 10 and the like) is applied, and a digital signal processor (DSP) circuit 2003 as a camera signal processing circuit. In addition, the camera 2000 includes a frame memory 2004, a display section 2005, a recording section 2006, an operation section 2007, and a power supply section 2008. The DSP circuit 2003, the frame memory 2004, the display section 2005, the recording section 2006, the operation section 2007, and the power supply section 2008 are connected to each other via a bus 2009.

[0393] The optical section 2001 captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 2002. The imaging device 2002 converts the amount of incident light that forms an image on the imaging surface through the optical section 2001 into an electrical signal in units of pixels and outputs the electrical signal as a pixel signal.

[0394] The display section 2005 is formed of, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays a moving image or a still image captured by the imaging device 2002. The recording section 2006 records the moving image or the still image captured by the imaging device 2002 on a recording medium such as a hard disk or a semiconductor memory.

[0395] The operation section 2007 issues operation commands for various functions of the camera 2000 in response to operations performed by the user. The power supply section 2008 supplies various power sources as operation power sources of the DSP circuit 2003, frame memory 2004, display section 2005, recording section 2006, and operation section 2007 to these supply targets as appropriate.

[0396] As described above, by using the above-described imaging system 10 or the like as the imaging device 2002 , it can be expected that a good image can be acquired.

[0397] <Application Example of Mobile Body>

[0398] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility tool, an airplane, a drone, a ship, or a robot).

[0399] Fig.37 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0400] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.37 In the illustrated embodiment, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0401] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0402] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0403] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, text on the road surface, etc., or detect the distance of these objects based on the received image.

[0404] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0405] The in-vehicle information detection unit 12040 detects information about the inside of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0406] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside or outside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, follow-up driving based on a following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from a lane, etc.

[0407] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, and can perform coordinated control of automatic driving aimed at making the vehicle drive automatically without relying on the driver's operation.

[0408] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the outside vehicle information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0409] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of the information. Fig.37 In the embodiment of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0410] Fig.38 12031 is a diagram showing an embodiment of the installation position of the imaging unit 12031.

[0411] exist Fig.38In the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are included.

[0412] The imaging units 12101, 12102, 12103, 12104 and 12105 are arranged, for example, at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper part of the windshield inside the vehicle. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly obtain images on the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly obtains images at the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0413] Notice, Fig.38 An embodiment of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0414] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0415] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object that exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / hour) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance in front of the leading vehicle to be maintained, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Thereby, coordinated control of automatic driving that aims to automatically drive the vehicle without relying on the driver's operation, etc. can be performed.

[0416] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0417] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This recognition of pedestrians is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0418] Embodiments of vehicle control systems to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be applied to the imaging units 12031, 12101, 12102, 12103, 12104, 12105, etc. in the above configuration. Specifically, for example, Figure 1 The imaging system 10 in can be applied to these imaging sections. By applying the technology according to the present disclosure to these imaging sections, a captured image with higher sensitivity can be obtained, and therefore, highly accurate control can be performed using the captured image in the mobile body control system.

[0419] Note that the present technology can have the following configurations. (1)

[0421] A light detection element, comprising:

[0422] a light receiving unit that generates electric charge according to the amount of light received;

[0423] a voltage conversion unit that acquires the charge generated in the light receiving unit via the input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node;

[0424] a signal amplifying unit that amplifies the voltage signal; and

[0425] a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage,

[0426] The voltage conversion unit includes:

[0427] an amplifier circuit connected between the input node and the output node; and

[0428] A feedback circuit is connected between the input node and the output node, and

[0429] A gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section. (2)

[0431] The light detection element according to (1), wherein a subthreshold slope of at least one transistor included in the feedback circuit is higher than subthreshold slopes of transistors included in the signal amplification section and the comparison section. (3)

[0433] The light detection element according to (1) or (2), wherein:

[0434] The amplifier circuit includes:

[0435] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0436] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0437] A gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the second transistor. (4)

[0439] The light detecting element according to any one of (1) to (3), wherein:

[0440] The amplifier circuit includes:

[0441] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0442] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0443] At least one transistor included in the feedback circuit has a subthreshold slope higher than a subthreshold slope of the second transistor. (5)

[0445] The light detection element according to any one of (1) to (4), wherein the feedback circuit includes a first transistor connected between the input node and the third reference voltage node and including a gate electrically connected to the output node. (6)

[0447] The light detecting element according to (5), wherein

[0448] The feedback circuit further includes a third transistor connected between the input node and the first transistor, and

[0449] The third transistor amplifies a voltage of a node between the first transistor and the third transistor and outputs the amplified voltage to the input node. (7)

[0451] The light detection element according to (5) or (6), wherein:

[0452] The amplifier circuit includes:

[0453] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0454] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0455] A channel length of the first transistor is shorter than a channel length of the second transistor. (8)

[0457] The light detection element according to (7), wherein the length of the gate electrode of the first transistor in the channel length direction is shorter than the length of the gate electrode of the second transistor in the channel length direction. (9)

[0459] The light detecting element according to (7), wherein

[0460] The first transistor includes at least one of a source extension portion and a drain extension portion, the source extension portion being arranged to extend from the source layer toward the drain layer and having an impurity concentration lower than that of the source layer, the drain extension portion being arranged to extend from the drain layer toward the source layer and having an impurity concentration lower than that of the drain layer, and

[0461] The source extension and the drain extension are arranged to overlap with the gate electrode of the first transistor when viewed from a direction substantially perpendicular to a surface of the substrate on which the first transistor is provided. (10)

[0463] The light detecting element according to any one of (1) to (9), further comprising:

[0464] a first transfer transistor connected between the light receiving portion and the input node and transferring the charge generated by the light receiving portion to the input node,

[0465] Here, a gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the first transfer transistor. (11)

[0467] The light detection element according to (10), further comprising:

[0468] a charge accumulation portion that stores charges; and

[0469] a second transfer transistor connected between the light receiving portion and the charge accumulation portion and transferring the charge generated by the light receiving portion to the charge accumulation portion,

[0470] Here, a gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the second transfer transistor. (12)

[0472] The light detecting element according to any one of (1) to (11), wherein:

[0473] The amplifier circuit includes:

[0474] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0475] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0476] The gate insulating film of the second transistor is thicker than the gate insulating films of transistors included in the signal amplifying section and the comparing section. (13)

[0478] A light detecting element according to any one of (1) to (12), wherein an end portion on the substrate side of a gate insulating film of at least one transistor included in a feedback circuit is closer to the substrate side than an end portion on the substrate side of a gate insulating film of a transistor included in an amplifier circuit. (14)

[0480] The light detecting element according to any one of (1) to (13), wherein:

[0481] The amplifier circuit includes:

[0482] a second transistor connected between the output node and the first reference voltage node and including a gate electrically connected to the input node; and

[0483] a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and

[0484] The light detection element also includes:

[0485] a first semiconductor chip on which the light receiving unit, the feedback circuit and the second transistor are arranged; and

[0486] The second semiconductor chip is stacked on the first semiconductor chip, and the current source, the signal amplification part and the comparison part are arranged on the second semiconductor chip. (15)

[0488] The light detection element according to any one of (1) to (14), wherein a thickness of a gate insulating film of at least one transistor included in the feedback circuit is 5 nm or more. (16)

[0490] The light detection element according to any one of (1) to (15), wherein a threshold slope of at least one transistor included in the feedback circuit is 100 mV / decade or more. (17)

[0492] An electronic device includes the light detection element according to any one of (1) to (16). (18)

[0494] A method for manufacturing a light detection element, the light detection element comprising:

[0495] a light receiving unit that generates electric charge according to the amount of light received;

[0496] a voltage conversion unit that acquires the charge generated in the light receiving unit via the input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node;

[0497] a signal amplifying unit that amplifies the voltage signal; and

[0498] a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage,

[0499] The voltage conversion unit includes:

[0500] an amplifier circuit connected between the input node and the output node; and

[0501] A feedback circuit is connected between the input node and the output node, and

[0502] A gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section, and the manufacturing method includes:

[0503] A gate insulating film of at least one transistor included in the feedback circuit is formed by local oxidation of silicon (LOCOS).

[0504] The various aspects of the present disclosure are not limited to the above-mentioned embodiments, but include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, modifications, and partial deletions may be made without departing from the concept and spirit of the present disclosure obtained from the contents defined in the claims and their equivalents.

[0505] Reference Symbols List

[0506] 10 Imaging System

[0507] 11 Imaging lens

[0508] 12 Records Department

[0509] 13. Control Unit

[0510] 20 Imaging device

[0511] 21 Pixel array unit

[0512] 22. Drive unit

[0513] 23 Arbitrator Department

[0514] 24 Column Processing Unit

[0515] 25 Signal Processing Unit

[0516] 27 Reading area selection section

[0517] 28 Signal Generation Department

[0518] 30 pixels

[0519] 31 Light receiving part

[0520] 32 pixel signal generating unit

[0521] 33 Address event detection unit

[0522] 101a to 101b gate electrodes

[0523] 102c Source extension

[0524] 103c Drain extension

[0525] 104a to 104b gate insulating film

[0526] 311 Light receiving element

[0527] 333 Subtractor

[0528] 334 Quantizer

[0529] CH1 First Semiconductor Chip

[0530] CH2 Second semiconductor chip

[0531] S substrate

[0532] S1 substrate surface

[0533] ML1 to ML3 transistors

[0534] MB1 to MB2 transistors

[0535] MA1 to MA3 transistors

[0536] MBF transistor

[0537] TG0 to TG1 transistors

[0538] N 输入 Input Node

[0539] N 输出 Output Node

[0540] L is the effective gate length.

Claims

1. A light detection element, comprising: a light receiving unit, wherein the light receiving unit generates electric charge according to the amount of light received; a voltage conversion unit that obtains the charge generated in the light receiving unit via an input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node; a signal amplifying unit, the signal amplifying unit amplifying the voltage signal; as well as a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage, Wherein, the voltage conversion unit includes: an amplifier circuit connected between the input node and the output node; and A feedback circuit is connected between the input node and the output node, and a gate insulating film of at least one transistor included in the feedback circuit is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section.

2. The light detecting element according to claim 1, wherein A subthreshold slope of at least one transistor included in the feedback circuit is higher than subthreshold slopes of transistors included in the signal amplifying section and the comparing section.

3. The light detecting element according to claim 1, wherein The amplifying circuit comprises: a second transistor connected between the output node and a first reference voltage node and including a gate electrically connected to the input node; and a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and A gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the second transistor.

4. The light detecting element according to claim 1, wherein The amplifying circuit comprises: a second transistor connected between the output node and a first reference voltage node and including a gate electrically connected to the input node; and a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and A subthreshold slope of at least one transistor included in the feedback circuit is higher than a subthreshold slope of the second transistor.

5. The light detecting element according to claim 1, wherein The feedback circuit includes a first transistor connected between the input node and a third reference voltage node and including a gate electrically connected to the output node.

6. The light detecting element according to claim 5, wherein The feedback circuit further includes a third transistor connected between the input node and the first transistor, and The third transistor amplifies a voltage of a node between the first transistor and the third transistor and outputs the amplified voltage to the input node.

7. The light detecting element according to claim 5, wherein The amplifying circuit comprises: a second transistor connected between the output node and a first reference voltage node and including a gate electrically connected to the input node; and a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and A channel length of the first transistor is shorter than a channel length of the second transistor.

8. The light detecting element according to claim 7, wherein A length of the gate electrode of the first transistor in a channel length direction is shorter than a length of the gate electrode of the second transistor in the channel length direction.

9. The light detecting element according to claim 7, wherein: The first transistor includes at least one of a source extension portion and a drain extension portion, the source extension portion being arranged to extend from the source layer toward the drain layer and having an impurity concentration lower than that of the source layer, the drain extension portion being arranged to extend from the drain layer toward the source layer and having an impurity concentration lower than that of the drain layer, and The source extension and the drain extension are arranged to overlap with a gate electrode of the first transistor when viewed from a direction substantially perpendicular to a surface of a substrate on which the first transistor is provided.

10. The light detecting element according to claim 1, further comprising: a first transfer transistor connected between the light receiving portion and the input node and transferring the charge generated by the light receiving portion to the input node, Here, a gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the first transfer transistor.

11. The light detecting element according to claim 10, further comprising: a charge accumulation section storing charges; as well as a second transfer transistor connected between the light receiving section and the charge accumulation section and transferring the charge generated by the light receiving section to the charge accumulation section, Here, a gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of the second transfer transistor.

12. The light detecting element according to claim 1, wherein The amplifying circuit comprises: a second transistor connected between the output node and a first reference voltage node and including a gate electrically connected to the input node; and a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and A gate insulating film of the second transistor is thicker than gate insulating films of transistors included in the signal amplifying section and the comparing section.

13. The light detecting element according to claim 1, wherein An end portion on the substrate side of a gate insulating film of at least one transistor included in the feedback circuit is closer to the substrate side than an end portion on the substrate side of a gate insulating film of a transistor included in the amplifier circuit.

14. The light detecting element according to claim 1, wherein The amplifying circuit comprises: a second transistor connected between the output node and a first reference voltage node and including a gate electrically connected to the input node; and a current source connected between the output node and a second reference voltage node different from the first reference voltage node, and The light detection element also includes: a first semiconductor chip on which the light receiving unit, the feedback circuit, and the second transistor are arranged; and A second semiconductor chip is stacked on the first semiconductor chip, and the current source, the signal amplifying section, and the comparing section are arranged on the second semiconductor chip.

15. The light detecting element according to claim 1, wherein The gate insulating film of at least one transistor included in the feedback circuit has a thickness of 5 nm or more.

16. The light detecting element according to claim 1, wherein At least one transistor included in the feedback circuit has a threshold slope of 100 mV / decade or more. 17 . An electronic device comprising the light detecting element according to claim 1 .

18. A method for manufacturing a light detection element, the light detection element comprising: a light receiving unit, wherein the light receiving unit generates electric charge according to the amount of light received; a voltage conversion unit that obtains the charge generated in the light receiving unit via an input node, converts the charge into a voltage signal, and outputs the voltage signal from an output node; a signal amplifying unit, the signal amplifying unit amplifying the voltage signal; as well as a comparing unit that compares the voltage of the voltage signal amplified by the signal amplifying unit with a predetermined voltage, The voltage conversion unit includes: an amplifier circuit connected between the input node and the output node; and A feedback circuit is connected between the input node and the output node, and a gate insulating film of at least one transistor included in the feedback circuit is thicker than a gate insulating film of transistors included in the signal amplifying section and the comparing section, and the manufacturing method includes: The gate insulating film of at least one transistor included in the feedback circuit is formed by local oxidation of silicon (LOCOS).

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