Train supervisory display control system and method for automatic redundant switching

Abstract

The application discloses a kind of automatic redundant switching train monitoring display control system and method, it is related to automatic redundant control technical field, when monitoring display fails during train operation, it is difficult to realize the automatic redundant switching of main and standby monitoring display system, and when heartbeat signal detection is carried out, the technical problem that dynamic detection cycle can improve detection safety is ignored;The application is through the minimum system that display device is most prone to failure to carry out hot standby redundancy, when FPGA is monitored to main control system exception by the dynamic sending cycle of heartbeat signal, immediately automatically switch to standby system;The application can activate standby system immediately when main control system fails, take over, ensure the continuous work of monitoring display during train operation, avoid information loss or operation interruption caused by display failure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of rail transit safety, and relates to an automatic redundant control technology, in particular to a train monitoring display control system and method with automatic redundant switching. BACKGROUND

[0002] With the rapid development of rail transit systems, the safety and reliability of train operation become particularly important. As a key monitoring device, the train monitoring display is used to display the state information of the train in real time, and its stability and real-time performance directly affect the safe operation of the train. During the operation of the train, occasional display failures may occur, which may require the train driver to stop the train, restart the display or enable the backup display, and then start the train. Such operation may cause the train to be late, and may affect the operation time of the train on the entire line, and may further affect the scheduling of the train network.

[0003] Currently, most train monitoring display control systems cannot automatically and imperceptibly switch the main and backup monitoring display systems when a fault occurs in the monitoring display during train operation, and manual intervention is required. In addition, there is a certain time delay during switching, which may cause the train to have a certain risk during the switching time, and may not be able to guarantee the safety of passengers' lives and property. In addition, most train monitoring display control systems use a fixed detection period to detect the heartbeat signal, and ignore the dynamic detection period that can improve the detection safety, which reduces the reliability and practicability of the system.

[0004] Therefore, the present application discloses a train monitoring display control system and method with automatic redundant switching, which is used to solve the above technical problems. SUMMARY

[0005] The present application aims to at least solve one of the technical problems in the prior art. To this end, the present application provides a train monitoring display control system and method with automatic redundant switching, which is used to solve the technical problems that it is difficult to automatically switch the main and backup monitoring display systems when a fault occurs in the monitoring display during train operation, and the dynamic detection period that can improve the detection safety is ignored when detecting the heartbeat signal. The present application solves the above problems by performing hot backup redundancy on the smallest system that is most prone to failure in the display device. When the FPGA detects an abnormality in the main control system through the dynamic sending period of the heartbeat signal, it automatically switches to the backup system.

[0006] To achieve the above purpose, the first aspect of the present application provides a train monitoring display control system with automatic redundant switching, comprising: an auxiliary processing module, and a display configuration module, a redundant switching module and a database connected thereto.

[0007] The display configuration module is used for marking a display master system as an A system and marking a display backup system as a B system; and respectively configuring a regulation module for the A system and the B system;

[0008] The auxiliary processing module is used for synchronizing MVB data of the A system and the B system and selecting a running system by the FPGA, and acquiring and recording heartbeat signals of the A system and the B system;

[0009] The redundancy switching module is used for detecting the heartbeat signals of the A system, switching redundancy when the heartbeat signals of the A system are abnormal, selecting a voice broadcast module by the FPGA, and controlling backlight of a display screen.

[0010] Preferably, the respectively configuring a regulation module for the A system and the B system comprises:

[0011] The A system is provided with independent CPU, MVB communication module, Ethernet communication module and voice broadcast module; and the B system is provided with independent CPU, MVB communication module, Ethernet communication module and voice broadcast module.

[0012] The key module, the display screen module and the touch screen module are set as common modules of the A system and the B system.

[0013] Preferably, the key circuit in the key module is a matrix key, which is connected with the FPGA and realizes automatic scanning of the matrix key through the FPGA.

[0014] Preferably, the automatic scanning of the matrix key through the FPGA comprises:

[0015] The FPGA detects whether a pressing signal exists in the matrix key; if yes, the pressing signal is de-bounced, a pressing interrupt is generated, and the pressing interrupt is sent to the CPU of the A system and the B system;

[0016] The FPGA detects whether a releasing signal exists in the matrix key; if yes, the releasing signal is de-bounced, a releasing interrupt is generated, and the releasing interrupt is sent to the CPU of the A system and the B system;

[0017] The key code value is sent to the CPU of the A system and the B system through a serial signal.

[0018] Preferably, the synchronizing MVB data of the A system and the B system and selecting a running system by the FPGA comprises:

[0019] The FPGA connects front-end receiving signals of the MVB to the MVB communication module of the A system and the MVB communication module of the B system respectively;

[0020] The front-end sending signal of the MVB is connected to the A system, the A system is marked as a running system, the key module, the display screen module and the touch screen module are all switched to the A system, and the signal sending of the whole train monitoring display is guided through the A system.

[0021] Preferably, the heartbeat signals of the A system and the B system are acquired and recorded, including:

[0022] C1: acquiring a failure rate G1 of the current train monitoring display and a failure rate G2 of a train monitoring display with the same number as the current train monitoring display, and obtaining a dynamic sending period DZ based on a formula DZ=CZ+CZ×(β×(1 / exp(α1×G1+α2×G2)-1)); wherein CZ is a standard sending period set through experience, β is an amplitude adjustment coefficient of an exp() function set artificially, and the value range of β is (0, 2); α1 and α2 are proportional adjustment coefficients set artificially, and α1+α2=1, α1≥α2;

[0023] C2: judging whether the dynamic sending period DZ is greater than the maximum value of a safety period range; if yes, updating the dynamic sending period DZ using the maximum value of the safety period range; if no, jumping to C3; wherein the safety period range is obtained through artificial setting;

[0024] C3: judging whether the dynamic sending period DZ is less than the minimum value of the safety period range; if yes, updating the dynamic sending period DZ using the minimum value of the safety period range; if no, not updating the dynamic sending period DZ;

[0025] C4: the CPUs of the A system and the B system respectively send heartbeat signals to the FPGA based on the dynamic sending period DZ through a GPIO, and the FPGA records the heartbeat signals of the A system and the B system.

[0026] Preferably, the heartbeat signal detection of the A system includes:

[0027] D1: acquiring a train operation quantity YL1 of a train network in a current time and an average value PYL1 of the train operation quantity YL1 in historical days in the current time; and acquiring a train operation quantity YL2 of a current line in the current time and an average value PYL2 of the train operation quantity YL2 of the current line in historical days in the current time;

[0028] D2: obtaining a time difference determination threshold TZ based on a formula TZ=DZ*ZB*mu*exp(dl*YL1 / PYL1+dl*YL2 / PYL2); wherein, ZB is a reference multiple artificially set, mu is an amplitude adjustment coefficient of the exp() function artificially set, and the value range of mu is (0, 2); dl and d2 are proportional adjustment coefficients greater than 0, and dl+d2=1;

[0029] D3: judging whether the time difference determination threshold TZ is greater than the maximum value of the safety threshold range; if yes, updating the time difference determination threshold TZ using the maximum value of the safety threshold range; if no, jumping to D4; wherein, the safety threshold range is obtained by artificial setting;

[0030] D4: judging whether the time difference determination threshold TZ is less than the minimum value of the safety threshold range; if yes, updating the time difference determination threshold TZ using the minimum value of the safety threshold range; if no, not updating the time difference determination threshold TZ;

[0031] D5: obtaining a time difference between the sending time of the latest heartbeat signal of the A system and the current time, and judging whether the time difference is greater than the time difference determination threshold TZ by the FPGA; if yes, issuing an A system heartbeat signal abnormal signal; if no, not doing operation.

[0032] Preferably, the redundant switching when the A system heartbeat signal is abnormal comprises:

[0033] When receiving the A system heartbeat signal abnormal signal, marking the B system as a running system, switching the key module, the display screen module and the touch screen module to the B system by the FPGA, and leading the signal sending of the whole train monitoring display by the B system.

[0034] Preferably, the selecting the voice broadcast module and the backlight control of the display screen by the FPGA comprises:

[0035] Obtaining the voice broadcast signals of the A system and the B system, and sending the voice broadcast signals into the corresponding voice decoding modules of the A system and the B system for decoding output;

[0036] Judging whether the A system heartbeat signal is abnormal; if yes, connecting the voice broadcast module to the voice decoding module of the B system by the arbitration function of the FPGA; if no, connecting the voice broadcast module to the voice decoding module of the A system by the arbitration function of the FPGA;

[0037] The voice broadcast module receives the output signal of the connected voice decoding module, and opens the voice loudspeaker to broadcast according to the content contained in the output signal;

[0038] Judge whether the heartbeat signal of the A system is abnormal or not, if yes, receive the PWM value of the B system, and the FPGA adjusts the brightness of the display screen through the PWM duty cycle; if no, receive the PWM value of the A system, and the FPGA adjusts the brightness of the display screen through the PWM duty cycle.

[0039] The second aspect of the application provides a train monitoring display control method for automatic redundant switching, comprising the following steps:

[0040] S1: mark the display master control system as the A system, and mark the display standby system as the B system; configure the A system and the B system with a control module respectively;

[0041] S2: synchronize the A system and the B system through the FPGA, select the running system, acquire and record the heartbeat signals of the A system and the B system;

[0042] S3: detect the heartbeat signal of the A system, when the heartbeat signal of the A system is abnormal, perform redundant switching, select a voice broadcast module through the FPGA, and control the backlight of the display screen.

[0043] Compared with the prior art, the application has the following beneficial effects:

[0044] 1. The application can automatically switch to the standby system when the FPGA detects that the master control system is abnormal through the dynamic sending period of the heartbeat signal, solve the technical problems that it is difficult to realize automatic redundant switching of the master and standby monitoring display systems when the monitoring display fails during train operation, and that the dynamic detection period is ignored when detecting the heartbeat signal, thereby improving the detection safety; the application can activate the standby system to take over immediately when the master control system fails, ensure the continuous operation of the monitoring display during train operation, and avoid information loss or operation interruption caused by display failure.

[0045] 2. The application optimizes the fault detection of the train monitoring display by dynamically adjusting the acquisition period of the heartbeat signal. The application does not use a fixed period to acquire the heartbeat signals of the master control system and the standby system, but comprehensively analyzes the current fault rate of the train monitoring display and the historical fault rate of the same number display, thereby determining a dynamic sending period, and the system adaptively acquires the heartbeat signal through the dynamic sending period; this method makes the sending period of the heartbeat signal flexible according to the actual fault condition of the train monitoring display: when the fault rate is high, the sending period is shortened to improve the timeliness and accuracy of fault detection; when the fault rate is low, the sending period is lengthened, the operation burden of the system is reduced, and the operation efficiency is improved. This dynamic adjustment mechanism not only enhances the reliability of the system, but also effectively optimizes the resource utilization.

[0046] 3. The application sets the time difference determination threshold corresponding to the time difference between the sending time of the last heartbeat signal and the current time, and does not set the time difference determination threshold as a fixed value, but is dynamically set according to the current time of the train network and the number of train operation of the current line. This is because the communication load in the train network may increase with the increase of the number of trains, and in the case of high load, the transmission of the heartbeat signal may be delayed, resulting in misjudgment. When the number of trains is large and the network load is high, the transmission of the heartbeat signal may be delayed, and the dynamic setting of the threshold can appropriately prolong the determination threshold according to the current network load, reduce the misjudgment caused by network delay; When the number of trains is small and the network load is low, the transmission of the heartbeat signal is stable, and at this time a shorter determination threshold can be set to improve the response speed of the system and the accuracy of fault detection. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0048] Figure 1 The operation steps of the present application are shown in the figure;

[0049] Figure 2 The system module of the present application is shown in the figure;

[0050] Figure 3 The operation steps of the present application are shown in the figure;

[0051] Figure 4 The implementation logic diagram of the present application is shown in the figure. DETAILED DESCRIPTION

[0052] The technical solutions of the present application will be described in detail below in combination with the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0053] Please refer to Figures 1-2 The first aspect of the present application provides a kind of automatic redundant switching train monitoring display control system, comprising: auxiliary processing module, and display configuration module, redundancy switching module and database connected therewith;

[0054] The display configuration module is used for marking the display master system as an A system and marking the display backup system as a B system, and respectively configuring the A system and the B system.

[0055] The auxiliary processing module is used for synchronizing MVB data of the A system and the B system and selecting a running system by the FPGA, and acquiring and recording heartbeat signals of the A system and the B system.

[0056] The redundancy switching module is used for detecting the heartbeat signals of the A system, switching redundancy when the heartbeat signals of the A system are abnormal, selecting a voice broadcast module by the FPGA, and controlling backlight of the display screen.

[0057] It should be noted that the MVB is a kind of serial data communication bus mainly used for interconnection between interconnected devices with interoperability and interchangeability requirements.

[0058] It should be noted that the LVDS is a kind of high-speed digital signal transmission technology.

[0059] Please refer to Figure 4 The UART is a kind of serial communication interface used for asynchronous data transmission between a computer system and an external device, and the UART communication is used between the CPU and the FPGA in the embodiment, and the UART baud rate is 115200.

[0060] The A system and the B system are respectively configured in the application, including:

[0061] The A system is provided with an independent CPU, an MVB communication module, an Ethernet communication module and a voice broadcast module, and the B system is provided with an independent CPU, an MVB communication module, an Ethernet communication module and a voice broadcast module.

[0062] The key module, the display screen module and the touch screen module are set as common modules of the A system and the B system.

[0063] It should be noted that the FPGA and the CPU are connected by using IO signals and serial port signals to realize communication between the FPGA and the CPU.

[0064] The key circuit in the key module in the application is a matrix key, which is connected with the FPGA and realizes automatic scanning of the matrix key by the FPGA.

[0065] The automatic scanning of the matrix key by the FPGA in the application includes:

[0066] The FPGA detects whether there is a press signal of the matrix key, and if yes, the press signal is de-bounced, a press interrupt is generated, and the press interrupt is sent to the CPU of the A system and the B system.

[0067] Use FPGA to detect whether there is a release signal on the matrix button; if so, debounce the release signal and generate a release interrupt, which is then sent to the CPU of system A and system B;

[0068] The key code value is sent to the A series and B series CPUs through the serial port signal.

[0069] It is worth noting that sending the press interrupt, release interrupt and key code value to the CPU of system A and system B can ensure that the key operation functions of system A and system B are synchronized in the hot standby state, the display of the program running interface of system A and system B is unified, and the display interface does not change when a fault redundancy switching occurs.

[0070] In this application, FPGA is used to synchronize MVB data between system A and system B and select the operating system, including:

[0071] Connect the front-end receiving signals of the MVB to the MVB communication modules of system A and system B respectively through FPGA;

[0072] Connect the front-end sending signal of the MVB to system A, mark system A as the operating system, switch the key module, display module and touch screen module to system A, and use system A to dominate the signal sending of the entire train monitoring display.

[0073] It should be noted that by connecting the front-end receiving signal of the MVB to the MVB communication modules of the CPU of system A and system B respectively through FPGA, it can be ensured that during the hot standby period, system A and system B can ensure the synchronization of MVB data reception in real time and ensure data uniformity.

[0074] It should be noted that hot standby means that during normal system operation, the backup resource is always in operation to maintain synchronization with the primary resource. Once the primary resource fails, the backup resource can immediately take over the work, thereby achieving high availability.

[0075] See also Figure 3 , in this application, the heartbeat signals of system A and system B are obtained and recorded, including:

[0076] C1: Obtain the failure rate G1 of the current train monitoring display and the failure rate G2 of the train monitoring display with the same number as the current train monitoring display, and obtain the dynamic transmission period DZ based on the formula DZ=CZ+CZ×(β×(1 / exp(α1×G1+α2×G2)-1)). CZ is the standard transmission period set by experience, β is the manually set amplitude adjustment coefficient of the exp() function, and the value range of β is (0,2). α1 and α2 are manually set proportional adjustment coefficients, and α1+α2=1, α1≥α2.

[0077] C2: judging whether the dynamic sending period DZ is greater than the maximum value of the safety period range; yes, updating the dynamic sending period DZ using the maximum value of the safety period range; no, jumping to C3; wherein the safety period range is obtained by manual setting;

[0078] C3: judging whether the dynamic sending period DZ is less than the minimum value of the safety period range; yes, updating the dynamic sending period DZ using the minimum value of the safety period range; no, not updating the dynamic sending period DZ;

[0079] C4: the CPUs of the A system and the B system respectively send the heartbeat signals to the FPGA based on the dynamic sending period DZ through a GPIO, and the FPGA records the heartbeat signals of the A system and the B system.

[0080] It is worth noting that the heartbeat signal of the current train monitoring display is obtained according to a dynamic sending period obtained by comprehensively analyzing the failure rate G1 of the current train monitoring display and the failure rate of the train monitoring display with the same number as the current train monitoring display, instead of according to a fixed time period. In this way, the sending period of the heartbeat signal can be adjusted according to the failure condition of the current train monitoring display, the sending period is reduced when the failure of the train monitoring display is high, the timeliness of failure detection can be improved, the sending period is increased when the failure of the train monitoring display is low, the operation amount of the system can be reduced and the operation efficiency of the system can be improved.

[0081] It should be noted that the failure rate of the train monitoring display is the number of failures of the current train monitoring display after being installed on the current train, divided by the number of train operations after the current train monitoring display is installed on the current train.

[0082] It should be noted that β is the amplitude adjustment coefficient of the exp() function set by manual setting, and β is used to adjust the influence degree of the failure rate G1 and the failure rate G2 on the dynamic sending period DZ; when other conditions are unchanged, the greater β is, the greater the value of the dynamic sending period DZ is, and the smaller β is, the smaller the value of the dynamic sending period DZ is.

[0083] It should be noted that the dependent variable of the 1 / exp(x) function decreases with the increase of the independent variable, which is a downward trend curve.

[0084] It should be noted that, α1 and α2 are proportional adjustment coefficients, and α1≥α2 because: for the train monitoring display, the failure rate of the train monitoring display with the same number can only be a reference data for the train monitoring display, and cannot absolutely reflect the possible failure of the current train monitoring display. The failure rate of the current train monitoring display can directly reflect the possible failure of the current train monitoring display. Therefore, the importance of the failure rate of the current train monitoring display will not be less than the failure rate of the train monitoring display with the same number, and therefore, the value of the proportional adjustment coefficient α1 is not less than the value of the proportional adjustment coefficient α2.

[0085] It should be noted that, in the train monitoring display with the same number as the current train monitoring display, the same type refers to the same type of train monitoring display produced by the same manufacturer.

[0086] It should be noted that, GPIO is a general-purpose input / output interface used to connect and control various external devices.

[0087] In the present application, the A system is detected for a heartbeat signal, including:

[0088] D1: obtaining the number of train operations YL1 of the train network in the current time, and the average value PYL1 of the number of train operations YL1 of the train network in the current time in the historical days; obtaining the number of train operations YL2 of the current line in the current time, and the average value PYL2 of the number of train operations YL2 of the current line in the current time in the historical days;

[0089] D2: obtaining the time difference determination threshold TZ based on the formula TZ=DZ×ZB×μ×exp(δ1×YL1 / PYL1+δ2×YL2 / PYL2); wherein, ZB is a reference multiple set by a human, μ is an amplitude adjustment coefficient of the exp() function set by a human, and the value range of μ is (0, 2); δ1 and δ2 are proportional adjustment coefficients greater than 0, and δ1+δ2=1;

[0090] D3: determining whether the time difference determination threshold TZ is greater than the maximum value of the safety threshold range; if yes, updating the time difference determination threshold TZ using the maximum value of the safety threshold range; if no, jumping to D4; wherein, the safety threshold range is obtained by manual setting;

[0091] D4: determining whether the time difference determination threshold TZ is less than the minimum value of the safety threshold range; if yes, updating the time difference determination threshold TZ using the minimum value of the safety threshold range; if no, not updating the time difference determination threshold TZ;

[0092] D5: Acquire the time difference between the sending time of the last heartbeat signal of the A system and the current time, and determine whether the time difference is greater than the time difference determination threshold TZ through the FPGA; yes, issue an A system heartbeat signal abnormal signal; no, do not operate.

[0093] It is worth noting that when setting the time difference determination threshold corresponding to the time difference between the sending time of the last heartbeat signal and the current time, the time difference determination threshold is not set as a fixed value, but is dynamically set according to the number of train operations in the train network and the current line in the current time. This is because the communication load in the train network may increase with the increase of the number of trains, and in the case of high load, the transmission of the heartbeat signal may be delayed, resulting in misjudgment. When the number of trains is large and the network load is high, the transmission of the heartbeat signal may be delayed, and the dynamic setting of the threshold can appropriately extend the determination threshold according to the current network load, reduce the misjudgment caused by network delay; when the number of trains is small and the network load is low, the transmission of the heartbeat signal is stable, and at this time a shorter determination threshold can be set to improve the response speed of the system and the accuracy of fault detection.

[0094] It should be noted that when the A system is abnormal or the application program of the A system is abnormal, the A system will not be able to send the heartbeat signal to the FPGA.

[0095] It should be noted that μ is the amplitude adjustment coefficient of the exp() function set by the user, and μ is used to adjust the influence degree of the number of train operations YL1 in the train network in the current time and the number of train operations YL2 in the current time in the historical days; when other conditions are unchanged, the greater μ is, the greater the value of the time difference determination threshold TZ is, and the smaller the value of the time difference determination threshold TZ is.

[0096] It should be noted that the dependent variable of the 1 / exp(x) function decreases with the increase of the independent variable, which is a downward trend curve.

[0097] It should be noted that the current line in the number of train operations YL2 in the current line is: marking the starting point and the terminal point of the current train as the current line.

[0098] In the present application, when the A system heartbeat signal is abnormal, redundancy switching is performed, including:

[0099] When receiving the A system heartbeat signal abnormal signal, mark the B system as the running system, switch the key module, the display screen module and the touch screen module to the B system through the FPGA, and send the signal of the entire train monitoring display through the B system.

[0100] In the present application, the FPGA selects the voice broadcast module and controls the backlight of the display screen, including:

[0101] Acquire the voice broadcast signal of the A system and the B system, and send the voice broadcast signal into the voice decoding module corresponding to the A system and the B system for decoding and output;

[0102] Determine whether the heartbeat signal of the A system is abnormal; if yes, connect the voice broadcast module to the voice decoding module of the B system through the arbitration function of the FPGA; if no, connect the voice broadcast module to the voice decoding module of the A system through the arbitration function of the FPGA;

[0103] The voice broadcast module receives the output signal of the connected voice decoding module, and starts the voice loudspeaker to broadcast according to the content contained in the output signal;

[0104] Determine whether the heartbeat signal of the A system is abnormal; if yes, receive the PWM value of the B system, and adjust the brightness of the display screen backlight through the PWM duty cycle of the FPGA; if no, receive the PWM value of the A system, and adjust the brightness of the display screen backlight through the PWM duty cycle of the FPGA.

[0105] It should be noted that the arbitration function of the FPGA is mainly used to solve the resource allocation problem when multiple request sources send requests at the same time. In the FPGA, the main function of the arbitrator is to determine which source should be responded to according to the current priority when multiple sources send requests at the same time.

[0106] It should be noted that the backlight control of the display screen adopts a PWM driving circuit, and the CPU sends the PWM duty cycle to the FPGA through the serial port, so as to adjust the brightness of the display screen backlight.

[0107] It should be noted that the specific explanation of the FPGA adjusting the brightness of the display screen backlight through the PWM duty cycle of the FPGA is as follows: receiving the PWM value sent by the system, the FPGA generates a corresponding PWM signal according to the received PWM value, and outputs the generated PWM signal to the display screen backlight control circuit, which is used to adjust the brightness of the display screen backlight by adjusting the current or voltage of the LED.

[0108] The second aspect embodiment of the present application provides a train monitoring display control method for automatic redundancy switching, comprising the following steps:

[0109] S1: marking a display master control system as an A system and a display standby system as a B system, and configuring a control module for the A system and the B system respectively;

[0110] S2: synchronizing the MVB data of the A system and the B system through the FPGA, selecting a running system, acquiring and recording the heartbeat signals of the A system and the B system;

[0111] S3: heartbeat signal detection is carried out on the A system, redundancy switching is carried out when the heartbeat signal of the A system is abnormal, a voice broadcast module is selected through the FPGA, and backlight control is carried out on the display screen.

[0112] Part of the data in the above formula is the value calculated by removing the dimension, and the formula is obtained by software simulation of a large amount of collected data to obtain a formula closest to the real situation; the preset parameters and the preset threshold in the formula are set by the person skilled in the art according to the actual situation or obtained by a large amount of data simulation.

[0113] The working principle of the present application is as follows:

[0114] The display device of the present application can perform hot standby redundancy on the minimum system most prone to failure, and can realize hot standby redundancy function on the minimum system and software; the two minimum systems are monitored by the FPGA, when the main system appears abnormal, the FPGA monitors the fault and automatically switches to the standby system immediately, and continues to run. During the hot standby period, the main and standby system data is shared, the display, communication and key are always kept unified. When switching to the standby system, it can be seamlessly switched in for normal operation without manual intervention by the driver.

[0115] The above examples are only used to illustrate the technical method of the present application and not to limit it, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical method of the present application.

Claims

1. An automatic redundant switching train supervisory display control system characterized by, The application relates to a display configuration system, which comprises an auxiliary processing module and a display configuration module, a redundancy switching module and a database connected to the auxiliary processing module. The display configuration module is used for marking a display master system as an A system and marking a display standby system as a B system, and respectively configuring a regulation module for the A system and the B system. The auxiliary processing module is used for synchronizing MVB data of the A system and the B system through FPGA, selecting a running system, and acquiring and recording heartbeat signals of the A system and the B system. The redundancy switching module is used for detecting the heartbeat signals of the A system, performing redundancy switching when the heartbeat signals of the A system are abnormal, selecting a voice broadcast module through FPGA, and controlling the backlight of a display screen. The heartbeat signals of the A system and the B system are acquired and recorded, and the method comprises the following steps. C1: acquiring a failure rate G1 of a current train monitoring display and a failure rate G2 of a train monitoring display with the same number as the current train monitoring display, and obtaining a dynamic sending period DZ based on a formula DZ=CZ+CZx(beta x (1 / exp(alpha1xG1+alpha2xG2)-1)), wherein CZ is a standard sending period, beta is an amplitude adjustment coefficient of an exp() function, and the value range of beta is (0, 2); alpha1 and alpha2 are proportional adjustment coefficients, and alpha1+alpha2=1, alpha1>=alpha2. C2: judging whether the dynamic sending period DZ is greater than the maximum value of a safety period range; if yes, updating the dynamic sending period DZ by using the maximum value of the safety period range; if no, jumping to C3. C3: judging whether the dynamic sending period DZ is less than the minimum value of the safety period range; if yes, updating the dynamic sending period DZ by using the minimum value of the safety period range; if no, not updating the dynamic sending period DZ. C4: the CPUs of the A system and the B system respectively send heartbeat signals to the FPGA based on the dynamic sending period DZ through a GPIO, and the FPGA records the heartbeat signals of the A system and the B system. The heartbeat signals of the A system are detected, and the method comprises the following steps. D1: acquiring a train running quantity YL1 of a train network in a current time and an average value PYL1 of the train running quantity YL1 in a historical time period, and acquiring a train running quantity YL2 of a current line in the current time and an average value PYL2 of the train running quantity YL2 of the current line in the historical time period; D2: obtaining a time difference judgment threshold value TZ based on a formula TZ=DZxZBxmu x exp(delta1xYL1 / PYL1+delta2xYL2 / PYL2); wherein ZB is a reference multiple, mu is an amplitude adjustment coefficient of an exp() function, and the value range of mu is (0, 2); delta1 and delta2 are proportional adjustment coefficients greater than 0, and delta1+delta2=1. D3: judging whether the time difference judgment threshold value TZ is greater than the maximum value of a safety threshold range; if yes, updating the time difference judgment threshold value TZ by using the maximum value of the safety threshold range; if no, jumping to D4. ​ D4: judging whether the time difference determination threshold TZ is less than the minimum value of the safety threshold range; yes, updating the time difference determination threshold TZ using the minimum value of the safety threshold range; no, not updating the time difference determination threshold TZ; D5: obtaining the time difference between the sending time of the last heartbeat signal of the A system and the current time, and judging whether the time difference is greater than the time difference determination threshold TZ through the FPGA; yes, issuing an A system heartbeat signal abnormal signal; no, no operation.

2. An automatically redundant switching train monitoring display control system according to claim 1, wherein, The module configuration for respectively regulating the A system and the B system comprises: The A system is provided with an independent CPU, an MVB communication module, an Ethernet communication module and a voice broadcast module; the B system is provided with an independent CPU, an MVB communication module, an Ethernet communication module and a voice broadcast module; The key module, the display screen module and the touch screen module are common modules of the A system and the B system.

3. An automatically redundant switching train monitoring display control system according to claim 2, wherein, The key circuit in the key module is a matrix key, which is connected with the FPGA and realizes automatic scanning of the matrix key through the FPGA.

4. An automatically failover switching train monitoring display control system according to claim 3, wherein, The automatic scanning of the matrix key through the FPGA comprises: detecting whether the matrix key has a press signal through the FPGA; yes, performing debouncing on the press signal and generating a press interrupt, and sending the press interrupt to the CPU of the A system and the B system; detecting whether the matrix key has a release signal through the FPGA; yes, performing debouncing on the release signal and generating a release interrupt, and sending the release interrupt to the CPU of the A system and the B system; sending the key code value to the CPUs of the A system and the B system through a serial signal.

5. The automatic redundant switching train monitoring display control system according to claim 1, characterized in that: The MVB data synchronization of the A system and the B system and the selection of the running system through the FPGA comprise: connecting the front-end receiving signal of the MVB to the MVB communication module of the A system and the B system respectively through the FPGA; connecting the front-end sending signal of the MVB to the A system, marking the A system as the running system, switching the key module, the display screen module and the touch screen module to the A system, and leading the signal sending of the whole train monitoring display through the A system.

6. An automatically redundant switching train monitoring display control system according to claim 1, wherein, The redundancy switching when the A system heartbeat signal is abnormal comprises: when receiving the signal of the abnormal A system heartbeat signal, marking the B system as the running system, switching the key module, the display screen module and the touch screen module to the B system through the FPGA, and leading the signal sending of the whole train monitoring display through the B system.

7. An automatically redundant switching train monitoring display control system as in claim 1, wherein, The selection of the voice broadcast module and the backlight control of the display screen through the FPGA comprise: obtaining the voice broadcast signal of the A system and the B system, and sending the voice broadcast signal to the corresponding voice decoding module of the A system and the B system for decoding and output; judging whether the A system heartbeat signal is abnormal; yes, connecting the voice broadcast module to the voice decoding module of the B system through the arbitration function of the FPGA; no, connecting the voice broadcast module to the voice decoding module of the A system through the arbitration function of the FPGA; the voice broadcast module receives the output signal of the connected voice decoding module, and starts the voice loudspeaker to broadcast according to the content contained in the output signal; Judgment A system heartbeat signal is abnormal; yes, receiving B system PWM value, FPGA through PWM duty ratio FPGA display screen backlight brightness adjustment; no, receiving A system PWM value, FPGA through PWM duty ratio FPGA display screen backlight brightness adjustment.

8. A kind of train monitoring display control method of automatic redundancy switching, based on the train monitoring display control system of automatic redundancy switching of any one of claims 1 to 7 operation, characterized in that: S1: the display master system is marked as A system, and the display standby system is marked as B system; A system and B system are configured with control module respectively; S2: MVB data synchronization is carried out on A system and B system by FPGA, and the running system is selected, the heartbeat signal of A system and B system is acquired and recorded; S3: A system heartbeat signal detection is carried out, when A system heartbeat signal is abnormal, redundancy switching is carried out, and the voice broadcast module is selected by FPGA and the backlight of display screen is controlled.

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