High-precision ultrasonic flow measurement system, method, equipment and medium

Abstract

The invention discloses a high-precision ultrasonic flow measurement system, method and device and a medium. The system comprises an ultrasonic flow detection circuit based on a TDC and a multi-mode comparator module; the multi-mode comparator module is used for carrying out threshold detection and zero-crossing comparison on the echo signal to be detected by adopting a single-comparator strategy or a double-comparator strategy; the TDC is used for counting or interrupting according to a Standby mechanism and a starting signal of the ultrasonic flow detection circuit; the ultrasonic flow detection circuit is also used for setting the generation delay of the starting signal; according to the invention, high-precision and low-power-consumption ultrasonic flow measurement can be realized without complex devices, flexible switching between a single comparator and double comparators can be supported, the comparators can be directly called to carry out zero-crossing comparison without voltage regulation and control, the consistency of circuit device parameters is good, the integration level is high, and the cost is low. And more flexible TDC work control logic is realized.

Description

Technical Field

[0001] The present invention relates to the field of ultrasonic measurement technology, and in particular to a high-precision ultrasonic flow measurement system, method, equipment and medium. Background Art

[0002] At present, ultrasonic measurement technology measures and calculates the flow rate of the medium passing through by measuring the flight time (TOF) of ultrasonic waves in the medium (liquid or gas) and using the correlation between flight time and flow velocity. Its technical principle is to use the time difference between ultrasonic wave propagation downstream and upstream to achieve parameter measurement, and it can achieve reliable and accurate flow measurement within a wide flow range. Ultrasonic measurement technology is widely used in water meters, gas meters, flow meters, ranging, ultrasonic radar and other fields.

[0003] Specifically, in the ultrasonic measurement process, how to calculate the difTOF differential flight time and the absTOF absolute flight time is particularly important. In the prior art, the TDC design architecture is often used for testing. During the test, the flight time of the ultrasonic wave in the medium and the system delay under different conditions are substituted into the formula to calculate the above parameters; therefore, different TDC scheme architectures and measurement logics will directly affect the measurement accuracy, efficiency and power consumption of the final result; the existing TDC schemes are as follows: 1. Single comparator solution using capacitor coupled echo signal; Figure 1 As shown, it mainly includes: DAC, CMP-0, Analog Switch, TDC and Capacitor; its working logic is: DAC generates a comparison voltage V ref , usually set to 1 / 2Vcc or 1 / 3Vcc; Analog Switch connects 1 to V by selecting the signal ref ;Capacitor terminal 4 will be charged to V ref (It will be fully charged before the echo signal arrives); TDC starts counting after receiving the rising edge of Start; CMP-0, at the initial stage of the echo, the negative terminal of the comparator will be V offset (Offset voltage) is set to the threshold voltage V of the first wave of the echo threshold , such as 35mV, which is equivalent to the compared voltage of CMP-0 being V ref +V threshold ; After the echo signal reaches the threshold voltage, the negative terminal V will be reset offset is 0mV, which is equivalent to resetting the compared voltage to V ref; TDC responds to receiving the rising edge of Stop and records the count value of Stop; TDC will receive 3 consecutive rising edges of Stop and record all the count values ​​of Stop; Analog Switch selects the signal to connect 1 to the ground and discharge the electricity in the capacitor; At this point, a measurement is completed, and TDC outputs Start and all the count values ​​of the 3 Stops to the subsequent processing module.

[0004] Second, the dual comparator solution through analog bias voltage; Figure 2 As shown, its working logic is: Set the analog bias voltage to: V com =V cm =1 / 2Vcc; Capacitor-50pF, charge the terminal 4 of the capacitor to 1 / 2Vcc through a 5KΩ resistor; CMP-0 negative terminal connected to V com , as zero-crossing detection; the DAC is based on the analog bias voltage V com , generating a comparison voltage V com +V threshold , as the compared voltage of CMP-1; the negative terminal of CMP-1 is connected to the output V of DAC com +V threshold , as threshold detection; TDC starts counting after receiving the rising edge of Start; when the echo signal exceeds V com +V threshold After that, the rising edge of CMP-1 output signal C11 is captured by Event Manger, and then E2 is set high; after AND2's E2 is set high, CMP-0 output C01 is directly passed to Stop; TDC responds to receiving the Stop rising edge and records the Stop count value; TDC may receive up to 8 Stop rising edges in succession and record all Stop count values; at this point, a measurement is completed, TDC outputs Start, and all count values ​​of up to 8 Stop are given to the subsequent processing module.

[0005] For solution 1, a capacitor is needed to raise the voltage. The capacitive reactance of the capacitor will change with time and temperature, resulting in the raised voltage V ref There is a lot of noise, because the capacitor brings additional noise and the superimposed V ref , will directly affect the compared voltage of the comparator, causing a large random change in the output delay of the comparator, affecting the measurement accuracy; at the same time, the threshold voltage of CMP0 is set by the negative terminal V offset achievable, thus complicating the comparator design; For solution 2, it is necessary to generate the bias voltage V required by the DAC and comparator. com At the same time, the echo signal Vecho Coupled to this bias voltage V com So that the signal entering the comparator becomes V com +V echo ; This solution is essentially the same as Solution 1, except that the implementation method is different. It also has the same defects as Solution 1.

[0006] In addition, there are measurement solutions that use ADC architecture in the prior art. However, the measurement solution based on ADC architecture requires a high-speed ADC to sample the echo signal, and requires strong digital signal processing capabilities (such as correlation calculations and interpolation). It also requires strong storage capabilities to store data from at least 1,000 sampling points in the uplink and downlink. This will also lead to system complexity, increase usage and design costs, and increase the overall power consumption of the solution.

[0007] In summary, the circuit architecture of existing ultrasonic measurement solutions is complex, and either requires a large-capacity internal storage unit or a special model processing module, and has or needs to be equipped with a capacitor design, which is prone to cause noise, resulting in higher usage costs and power consumption, reducing measurement accuracy, and has great limitations. Summary of the invention

[0008] The object of the present invention is to provide a high-precision ultrasonic flow measurement system, method, device and medium, thereby solving all or one of the above-mentioned problems existing in the prior art.

[0009] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows: In one aspect, the present invention provides a high-precision ultrasonic flow measurement system, comprising: Ultrasonic flow detection circuit based on TDC and multi-mode comparator module; The multi-mode comparator module is used to adopt a single comparator strategy or a dual comparator strategy to perform threshold detection and zero-crossing comparison on the echo signal to be measured; The TDC is used to count or interrupt according to the Standby mechanism and the TDC start signal of the ultrasonic flow detection circuit; The ultrasonic flow detection circuit is also used to set the generation delay of the TDC start signal.

[0010] As an improved solution, the multi-mode comparator module is: a single comparator module; The single comparator module is point-to-point connected to the echo signal in the ultrasonic flow detection circuit; The single comparator module is used to support the single comparator strategy; the single comparator module uses one comparator to perform zero-crossing comparison and threshold detection in a time-sharing manner; or, The multi-mode comparator module is: a dual comparator module; The dual comparator module is connected to the echo signal via an analog switch capable of switching uplink and downlink paths; The dual comparator module is used to support the dual comparator strategy; the dual comparator module uses one comparator to perform threshold detection and another comparator to perform zero-crossing comparison.

[0011] As an improved solution, the ultrasonic flow detection circuit further includes: a potential manager; The potential manager is provided with a DAC, and the DAC is connected to the multi-mode comparator module; The potential manager is used to control the DAC to output a threshold voltage for the multi-mode comparator module.

[0012] As an improved solution, the ultrasonic flow detection circuit further includes: a transducer AFE; The transducer AFE is provided with a sensor pulse generator, and the sensor pulse generator is connected to the first end or the second end of the measurement structure according to the uplink and downlink measurement conditions; The transducer AFE is used to output a square wave to the measurement structure, and the measurement structure outputs an echo signal to the multi-mode comparator module based on the square wave; The transducer AFE is used to generate the TDC start signal and the MASK start signal; the transducer AFE sends the TDC start signal to the TDC; the transducer AFE sends the MASK start signal to the measurement manager of the ultrasonic flow detection circuit; The transducer AFE is further used to set a delay time between the TDC start signal and the MASK start signal, and the delay time serves as a generation delay of the TDC start signal.

[0013] As an improved solution, the ultrasonic flow detection circuit further includes: a path distributor; The path distributor is provided with a first selector, a second selector and a third selector; The input of the first selector is connected to the sensor pulse generator, and the output of the first selector is connected to the TDC; the inputs of the second selector and the third selector are respectively connected to the multi-mode comparator module, and the outputs of the second selector and the third selector are respectively connected to the measurement manager; The path distributor is used to set the connection strategy between the second selector, the third selector and the multi-mode comparator module to the first connection strategy when the dual comparator strategy is used; The path distributor is used to set the connection strategy between the second selector, the third selector and the multi-mode comparator module to the second connection strategy when the single comparator strategy is used.

[0014] The path distributor connects the output of the multi-mode comparator module to the TDC through the first connection strategy or the second connection strategy.

[0015] As an improved solution, the ultrasonic flow detection circuit further includes: an event manager; The event manager is provided with a DFF and an AND gate; the input of the DFF is respectively connected to the second selector and the measurement manager, and the output of the DFF is respectively connected to the potential manager and the AND gate; the input of the AND gate is connected to the third selector and the DFF, and the output of the AND gate is connected to the TDC and the measurement manager; The event manager senses the first wave signal through the port configuration of the DFF, and controls the zero-crossing comparison output of the multi-mode comparator module to enter the TDC in time according to the sensed first wave signal through the AND gate.

[0016] As an improved solution, the ultrasonic flow detection circuit further includes: the measurement manager; The measurement manager is connected to the DFF, the TDC and the transducer AFE respectively; the measurement manager is used to receive the MASK start signal and perform pulse counting according to the MASK start signal; the measurement manager generates a mask signal for the TDC counting according to the pulse counting.

[0017] On the other hand, the present invention also provides a high-precision ultrasonic flow measurement method, comprising the following steps: A single comparator strategy or a double comparator strategy is used to perform threshold detection and zero-crossing comparison on the echo signal to be measured; TDC is called to process the zero-crossing comparison output based on the Standby mechanism and to generate a start signal with variable delay.

[0018] On the other hand, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the high-precision ultrasonic flow measurement method are implemented.

[0019] On the other hand, the present invention further provides a computer device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; wherein: The memory is used to store computer programs; The processor is used to execute the steps of the high-precision ultrasonic flow measurement method by running the program stored in the memory.

[0020] The beneficial effects of the technical solution of the present invention are: 1. The high-precision ultrasonic flow measurement system described in the present invention can realize high-precision and low-power ultrasonic flow measurement without the need for complex devices, can support flexible switching between single comparator and dual comparator, and supports direct calling of comparator for zero-crossing comparison without voltage regulation. The circuit device parameters have good consistency, high integration, and more flexible TDC working control logic, which makes up for the defects of the prior art and has high application value.

[0021] 2. The high-precision ultrasonic flow measurement method described in the present invention can orderly call the system modules of the ultrasonic flow measurement system, thereby realizing the system logic of the high-precision ultrasonic flow measurement system described in the present invention.

[0022] 3. The computer-readable storage medium described in the present invention can guide the system modules of the high-precision ultrasonic flow measurement system to cooperate, thereby realizing the high-precision ultrasonic flow measurement method described in the present invention, and the computer-readable storage medium described in the present invention also effectively improves the operability of the high-precision ultrasonic flow measurement method.

[0023] 4. The computer device described in the present invention can store and execute the computer-readable storage medium, thereby realizing the high-precision ultrasonic flow measurement method described in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Attached Figure 1 It is a dual comparator solution, with Figure 2 It is a single comparator solution.

[0026] Figure 1 It is a schematic diagram of the circuit structure of solution 1 in the background technology; Figure 2 It is a circuit structure diagram of solution 2 in the background technology; Figure 3It is a schematic diagram of the circuit architecture of the high-precision ultrasonic flow measurement system based on a dual comparator module according to Embodiment 1 of the present invention; Figure 4 It is a schematic diagram of the circuit architecture of the high-precision ultrasonic flow measurement system based on a single comparator module according to Embodiment 1 of the present invention; Figure 5 Schematic diagram of signal generation of the high-precision ultrasonic flow measurement system according to Embodiment 1 of the present invention; Figure 6 Schematic diagram of signal generation of the high-precision ultrasonic flow measurement system according to Embodiment 1 of the present invention; Figure 7 Schematic diagram of signal generation of the high-precision ultrasonic flow measurement system according to Embodiment 1 of the present invention; Figure 8 is a flow chart of a high-precision ultrasonic flow measurement method according to Embodiment 2 of the present invention; Fig. 9 is a schematic diagram of the structure of the computer device described in Example 4 of the present invention; The symbols in the accompanying drawings are explained as follows: 1501, processor; 1502, communication interface; 1503, memory; 1504, communication bus. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0028] In the description of the present invention, it should be noted that the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all of the embodiments; based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention.

[0029] The terms "first", "second", etc. in the specification and claims of this article and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of this article described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0030] In the description of the present invention, it should be noted that: TDC (Time to Digital Converter) is a time-to-digital converter, specifically a converter that converts flight time into digital expression.

[0031] TOF (Time of Flight) refers to flight time.

[0032] Ultrasonic Transducers are energy conversion devices that are mainly used to convert input electrical signals into mechanical signals (i.e. ultrasonic waves) and then transmit them while consuming very little power themselves; or convert received mechanical signals (i.e. ultrasonic waves) into electrical signals and then transmit them while consuming very little power themselves.

[0033] Upward means that the direction of the ultrasonic wave is opposite to the direction of the water flow.

[0034] Downward means that the direction of the ultrasonic wave is the same as the direction of the water flow.

[0035] absTOF (absolute TOF) refers to absolute time of flight.

[0036] difTOF (difference TOF) refers to differential flight time.

[0037] ZFC (Zero Flow Calibrate) refers to zero flow calibration, that is, when there is no water flow, the total time of the ultrasonic wave in the upward and downward paths in the static water flow is measured. and ,according to and Then the calibration value at zero flow can be further calculated ,this It is caused by system errors, which may include differences in device delays, wiring differences, transducer delay differences, and other factors.

[0038] ZFD (Zero Flow Drift) refers to zero flow drift, that is, the drift of the upstream and downstream differential time with temperature when there is no water flow.

[0039] DAC (Digital Analog Converter) is a converter that converts digital codes into corresponding analog signals. Example 1

[0040] This embodiment provides a high-precision ultrasonic flow measurement system, such as Figure 1 to Figure 7 As shown, including: (1) Potentiometer Manager: Specifically, the core module of the potential manager is DAC, and it also includes AND2 and M4; the output of DAC is grounded and connected to the time detector; M4 is connected to the hw_dac_cfg_disable signal; AND2 is connected to the sw_dacen signal; Specifically, the potential manager is used to turn on or off the DAC; wherein, when the DAC is turned off, its output is 0; the enable signal of the DAC is based on software control and hardware control; Specifically, when hw_dac_cfg_disable=1, the switch of DAC is completely controlled by the software control signal sw_dacen; when hw_dac_cfg_disable=0 and sw_dacen=1, the switch of DAC is completely controlled by HW_DACEN; Specifically, since the time detector of this system supports a single and double comparator solution, therefore: When the time detector is a dual comparator solution, sw_dacen = 1, hw_dac_cfg_disable = 0, the DAC output voltage V threshold =i*R1 is the threshold voltage for CMP1; When the time detector is a single comparator solution, sw_dacen = 1, hw_dac_cfg_disable = 1, the DAC output voltage V threshold =i*R1 is used for the threshold voltage of CMP1 and CMP0.

[0041] (2) Transducer front end (Transducer AFE): Specifically, the transducer front end is composed of: Transducer Pulse Gen and two Pules IO; the two Pules IO are connected to FireDn and FireUp respectively; FireDn and FireUp are connected to Transducer-1 and Transducer-2 of the measurement structure respectively; when measuring downlink, the output of Transducer Pulse Gen is connected to FireDn, and FireUp is grounded; when measuring uplink, the output of Transducer Pulse Gen is connected to FireUp, and FireDn is grounded; Specifically, this module is used to generate and drive the transducer excitation signal, and generate the measurement start signal Start at the same time to enable downlink measurement or uplink measurement; the transducer front end can generate two types of Start at the same time, namely: start_to_tdc and start_to_mask; start_to_tdc is used to send to TDC Core through Path router to trigger timing start; start_to_mask is used to send to Measurement Manager to generate a trigger signal for shielding ultrasonic crosstalk; Specifically, the module is also used to select the downstream Pulse IO during the downstream measurement and send the attached Figure 5 In the figure, transducer-1 shows a square wave. The square wave signal is sent to transducer-1 through the FireDn port, and an echo signal is generated in transducer-2. When measuring uplink, the uplink Pulse IO is selected and the signal is sent as shown in the attached figure. Figure 5 In the figure, transducer-2 shows a square wave. The square wave signal is sent to transducer-2 through the FireUp port, and an echo signal is generated at transducer-1. Specifically, Figure 5 This module is also used to configure different del_val values ​​according to the uplink and downlink. When the downlink is completed, T stop_dn_delay Time delay, and when uplink, T stop_up_delay Time delay; where T start_delay The delay between the start_to_tdc signal and the start_to_masker signal is generated, that is, the transducer front end can be flexibly configured to send out the start_to_masker signal some time after the start_to_tdc signal is valid, which is used for the start of TDC Core timing; of course, T start_delay Can be configured as 0, T start_delay When it is 0, it means that start_to_tdc and start_to_masker are consistent; in addition, T start_delay It is consistent for both up and down lines; Specifically, the module is also used to set the hw_threshold_det_en signal after the delay is completed; thereafter, the DFF in the EventManager starts to wait for the arrival of the first wave of the echo signal.

[0042] (3) Measurement structure: Specifically, Transducer-1 and Transducer-2 of the measurement structure are connected to the time detector through analog switches S1 and S2 respectively; Specifically, the measurement structure is used to convert the FireUp electrical signal / FireDn electrical signal into a mechanical signal through Transducer-2 (uplink measurement) / Transducer-1 (downlink measurement) (the uplink and downlink situations occur in time-sharing, respectively, between the uplink measurement and downlink measurement time intervals); after flying through the medium, it reaches Transducer-1 / Transducer-2 respectively and is converted into an echo electrical signal; that is, the FireDn square wave drives Transducer-1 and generates an echo signal on Transducer-2; the FireUp square wave drives Transducer-2 and generates an echo signal on Transducer-1; Specifically, the measurement structure feeds back the subsequently converted echo electrical signal to the port of the comparator EventDetector through different electrical paths.

[0043] (4) Event Detector: Specifically, the time detector is composed of a pair of low-delay, low-offset voltage comparators; the two comparators are based on different external signal connection methods to flexibly realize the switching between single comparator and dual comparator; the outputs of the two comparators are directly connected to the path distributor; the inputs of the two comparators are connected to the measurement structure through analog switches; Optionally, in the dual comparator solution, both comparators need to be enabled, and an analog switch is used to select the uplink echo path or the downlink echo path; During downlink measurement, S2 is connected to the COM port (S1 disconnects COM) through the analog switch control signal, and the echo signal on Transducer-2 is applied to the positive terminals of comparators CMP-0 and CMP-1; During uplink measurement, the analog switch control signal, S1 is connected to the COM port (S2 disconnects COM), and the echo signal on Transducer-1 is applied to the positive terminals of comparators CMP-0 and CMP-1; during uplink / downlink measurement, the negative terminal of CMP-0 is grounded and the negative terminal of CMP1 is connected to DACO (or the negative terminal of CMP-1 is grounded and the negative terminal of CMP0 is connected to DACO); Optionally, in a single comparator solution, CMP1 is enabled during downlink measurement, and CMP0 is enabled during uplink measurement, and the echo signal is directly connected to the positive terminal of the comparator point-to-point; During downlink measurement, the echo signal of Transducer-2 is applied to the positive terminal of comparator CMP-1, and comparator CMP-0 is turned off; or, the echo signal of Transducer-2 is applied to the positive terminal of comparator CMP-0, and comparator CMP-1 can be turned off; During uplink measurement, the echo signal of Transducer-1 is applied to the positive terminal of comparator CMP-0, and comparator CMP-1 is turned off; or, the echo signal of Transducer-1 is applied to the positive terminal of comparator CMP-1, and comparator CMP-0 is turned off; During up / down measurement, the negative terminals of CMP-0 and CMP-1 are connected to DACO; Specifically, the time detector is used to compare the echo signals in real time according to different configurations, and to send the compared digital signals to the path distributor; Optionally, in the dual comparator solution, one comparator in the time detector is used as a threshold detection, and the other comparator is used as a zero-crossing detection; when the threshold event comparator outputs a high level, it indicates that the echo signal has reached the set threshold level. This signal is mainly used to determine when to send the zero-crossing waveform to the TDC Core for counting; and the zero-crossing event comparator is used to output a zero-crossing comparison waveform of the detected echo signal, which is used for TDC Core counting; Optionally, in a single comparator solution, a time detector uses a time-sharing method based on a comparator to serve as both a zero-crossing comparison and a threshold comparison; in this solution, the DACO output needs to be set, and the negative end of the comparator is set to a threshold voltage (such as 35mV), and this level will be connected to two comparators at the same time (one is used for uplink measurement and the other is used for downlink measurement); during downlink measurement, CMP-0 is turned off; during uplink measurement, CMP-1 is turned off; after the first wave is detected, the DAC is turned off through the Qn end of the DFF of the event manager, so that the DAC output is high impedance, and then the negative end of the comparator is grounded through the resistor R1, so that the comparator becomes a zero-crossing comparator.

[0044] (5) Path Router: Specifically, the path distributor consists of M1 (i.e., the first selector), M2 (the second selector), and M3 (the third selector); the input of M1 includes the Transducer Pulse Gen, and the output of M1 is connected to the TDC. When configured as an internal start, the start_to_tdc signal will be connected to the TDC Core through M1; the inputs of M2 and M3 are CMP-0 and CMP-1, respectively; the outputs of M2 and M3 are event managers, respectively; Alternatively, if Figure 3As shown, in the dual comparator solution, M2 is configured to select the output (path 22) of CMP-1 as thre_cross_pulse; M3 is configured to select the output (path 21) of CMP-0 as zero_cross_pulse; or, according to the position of the comparator connected to the external zero-crossing and threshold levels, M2 is configured to select the output (path 21) of CMP-0 as thre_cross_pulse; M3 is configured to select the output (path 22) of CMP-1 as zero_cross_pulse; finally, the output (path 22) of CMP-1 is connected to path 31 via M2, and the output (path 21) of CMP-0 is connected to path 32 via M3; or, when the negative terminal of CMP-1 is grounded and the negative terminal of CMP0 is connected to DACO, the output (path 22) of CMP1 is selected to path 32 via M3, and the output (path 21) of CMP0 is selected to path 31 via M2 (the above is the first connection strategy); Alternatively, if Figure 4 As shown, in the single comparator solution, during downlink measurement, the signal on path 105 is a valid echo signal, M2 is configured, the output path 22 of CMP-1 is thre_cross_pulse, and M3 is configured, the output path 22 of CMP-1 is zero_cross_pulse; during uplink measurement, the signal on path 104 is a valid echo signal, M2 is configured, the output path 21 of CMP-0 is thre_cross_pulse, and M3 is configured, the output path 21 of CMP-0 is zero_cross_pulse; finally, during downlink measurement, the output path 22 of CMP1 is connected to path 31 via M2 and to path 32 via M3; during uplink measurement, the output path 21 of CMP0 is connected to path 31 via M2 and to path 32 via M3 (the above is the second connection strategy); Specifically, this module is used to process the selection of various start and stop paths under the single / dual comparator solution, so that the output of the comparator can enter the stop path of the first wave detection circuit and the TDC Core respectively.

[0045] (6) Event Manager: Specifically, the module includes: a D flip-flop (DFF) and an AND gate; the D flip-flop is used to sense the first wave signal; the AND gate is used to control the zero-crossing output to enter the TDC in time according to the sensed first wave signal; the input of the D flip-flop is respectively connected to M2 of the path distributor and the measurement manager; the output of the D flip-flop is respectively connected to the potential manager and the AND gate; the output of the AND gate is connected to the STOP of the TDC and the measurement manager, and the input of the AND gate is connected to M3 of the path distributor and Q of the D flip-flop; Among them, there are SN port, RN port, CK port and Qn port on DFF; SN port, used to access the sw_threshold_det_en signal, used to set the port signal to 1 during the initialization phase to enable the first wave detection function; RN port, used in T stop_dn_delay or T stop_up_delay After the delay, the CLR port is set to 1 through the hw_threshold_det_en signal. When the RN port is valid at the same time, its priority is lower than the SN port; The CK port is used to access thre_cross_puls. After the SN port and the RN port are set to 1, the rising edge of the thre_cross_pulse threshold comparison is monitored. Once there is a rising pulse at the CK end, the Q end outputs 1 and opens the EN port of the AND gate through path 41. The Qn port is used to output 0 once there is a rising pulse at the CK terminal, and is connected to M4 through path 61; In addition, in the dual comparator solution, M4 is set to select 1 as the output in the initialization stage, so the Qn terminal cannot control whether the DAC is enabled or not (whether the DAC is enabled or not depends on sw_dacen); in the single comparator solution, M4 selects Qn as the M4 output in the initialization stage, and then outputs it to path 63 through AND2, so when the Qn output is 0, the DAC is automatically turned off, and the negative terminal of the comparator is grounded through the resistor R1, so that both comparators are zero-crossing comparison; Among them, AND is provided with EN port and SI port; M3 zero-crossing comparison result output path 32 will be transmitted to SI port, when Q end enables EN port of AND gate, SI signal will be directly passed to STOP of TDC Core, such as Figure 5 The corresponding behaviors of 41, 32, and 33 in the AND are as follows; the output path 33 of AND is not only used for the STOP of TDC Core for measurement, but also output to the measurement manager for stop counting to generate a Mask signal; Specifically, to summarize the above, the event manager receives control signals from the path distributor, the measurement manager, and the configuration interface, and manages the zero_cross_pulse signal bypassed by the AND gate to enter the STOP port of the TDC Core at the appropriate time; in addition, the STOP port is also used to feed back to the measurement manager for counting the number of stops and generating the Mask signal of the TDC Core.

[0046] (7) Measurement Manager: Specifically, the measurement manager is composed of M5, cross_signal_masker, Echo pulse spread, Echopulse counter and Echo pulse Masker; the input of M5 is connected to Transducer Pulse Gen and M1 respectively, and the output of M5 is connected to cross_signal_masker; the output of cross_signal_masker is connected to DFF; the input of Echo pulsespread is connected to AND, and the output of Echo pulse spread is connected to Echo pulse counter; the output of Echo pulsecounter is connected to Echo pulse Masker; the output of Echo pulse Masker is connected to the MASKn pin of TDC Core; Specifically, in the measurement manager, M5 is configured to select start_to_masker to path 14, and the delay counter del_val of cross_signal_masker is configured; cross_signal_masker is used to start counting after detecting that the start_to_masker signal is valid, and generate a hw_threshold_det_en signal after del_val is full; in one implementation, del_val is configured as T during downlink measurement. stop_dn_delay , del_val is configured as T for uplink measurement stop_up_delay ; Specifically, since the first high pulse of the stop signal waveform may be relatively narrow and not enough to reach the width of the counting clock, in the measurement manager, Echo pulse spread is used to widen the first pulse to be wide enough to be sampled by the counting clock, thus realizing the pulse width expansion function; Specifically, in the measurement manager, the Echo pulse counter is used to count the number of stop pulses and to record the number of stop signals currently received. Figure 4 ; Specifically, in the measurement manager, Echo pulse Masker is used to filter the stop signal from the event manager, generate MASKn signal, and mask the stop entering the TDC Core; in one implementation, Echo pulseMasker generates MASKn signal based on the current stop count value and the index of the stop to be measured; Echo pulseMasker contains a total of 8 Masker Index Registers (MIRs), which are used to configure the stop index expected to be measured and turn on the MASKn signal in time before the expected stop arrives (taking the measurement of 4 stops as an example, MIR1=0, MIR2=4, MIR3=6, MIR4=7; then MASK1, MASK2, MASK3, MASK4 signals are generated, and the corresponding measurement time is T 12 M1 , T 12 M2 , T 12 M3 and T 12 M4 ); Specifically, to summarize the above, the measurement manager is used to monitor the start signal to shield the interference signal that crosstalks from the transmitter to the receiver; at the same time, the measurement manager also monitors the Stop signal that finally enters the TDC Core, generates the Mask signal of the TDC Core, and implements the screening of the Stop signal that is actually to be measured; wherein, the measurement manager starts timing after receiving the rising edge of start_to_masker, and before the timing ends, the Q end of the trigger will be output to 0 through the zero_cross_en signal, and the zero_cross_pulse signal will be shielded to 0; subsequently, the measurement manager monitors each stop signal and compares it with the configuration, and through the mask signal of the TDC Core, the TDC determines whether the current stop is valid, and implements the latch judgment of the counter for the current stop.

[0047] (8) Time-to-digital converter (TDC Core): Specifically, the time digital converter is provided with ports such as Start, Stop, Standby, and MASKn (n=1…8); it is connected to the measurement manager, M1, and AND through the ports respectively; Specifically, the module is used to count from the rising edge of the start signal until the MASKx signal is received, determine the count value stored at the valid STOP rising edge, and output an interrupt and each count value after the conversion is completed; Specifically, only when MASKn is high, the rising edge of Stop captured by TDC Core is a valid stop for latching the counter; Specifically, the Standby function of the time-to-digital converter is used to put the TDC in standby mode. Only when the Start or Stop pulse (rising edge) arrives, the high-frequency counting unit inside the time-to-digital converter is turned on, and after the current count ends, it is in standby mode again, waiting for the arrival of the next stop. The Standby mechanism saves power consumption. In addition, other configuration ports Configure Interface appear in the drawings. These ports are used by the system to control other components and belong to peripheral connections. The configuration ports are all controlled by the system to send or receive and are not within the scope of discussion of this application. Example 2

[0048] This embodiment is based on the same inventive concept as the high-precision ultrasonic flow measurement system described in Embodiment 1, and provides a high-precision ultrasonic flow measurement method for use in the high-precision ultrasonic flow measurement system, such as Figure 8 As shown, the method comprises the following steps: S100, initialization step: In this step, each module of the ultrasonic flow measurement system is initialized, and the corresponding control signals are configured and the appropriate signal path is selected according to the actual application requirements; Specifically, initialize the Potentiometer Manger: configure the appropriate codeword (codebus) according to the required threshold value; configure sw_dacen and hw_dac_cfg_disable; in the dual comparator solution, configure sw_dacen=1, hw_dac_cfg_disable=0; in the single comparator solution, configure sw_dacen=1, hw_dac_cfg_disable=1; configure the current-type digital-to-analog converter DAC to output current i, and the current passes through the R1 resistor to form a voltage to the ground; in the dual comparator solution, set M4 to select 1 as the output of M4; in the single comparator solution, set M4 to select Qn as the output of M4, and then output it to 63 through AND2; Specifically, initialize the Event Detector: in the dual comparator solution, enable both comparators; in the single comparator solution, enable CMP-1 for downlink measurement and enable CMP-0 for uplink measurement; Specifically, initialize the Path router: set M1 to select the start_to_tdc signal to TDC Core; in the dual comparator solution, S2 is connected to the COM port for downstream measurement, and S1 is connected to the COM port for upstream measurement; set the output 22 of M2-selected CMP-1 to thre_cross_pulse; set the output 21 of M3-selected CMP-0 to zero_cross_pulse; optionally, corresponding configuration can be performed according to the position of the external zero-crossing and threshold level connected to the comparator, such as: configure the output 21 of M2-selected CMP-0 to thre_cross_pulse; set the output 22 of M3-selected CMP-1 to zero_cross_pulse; in the single comparator solution, set the output 22 of M2-selected CMP-1 to thre_cross_pulse for downstream measurement, and set the output 22 of M3-selected CMP-1 to zero_cross_pulse; set the output 21 of M2-selected CMP-0 to thre_cross_pulse for upstream measurement; set the output 21 of M3-selected CMP-0 to zero_cross_pulse; Specifically, initialize the Transducer AFE: set the square wave excitation signal of the Transducer Pulse Gen output transducer; when measuring downlink, connect the Transducer Pulse Gen to FireDn through line 100 and ground FireUp; when measuring uplink, connect the Transducer Pulse Gen to FireUp through line 100 and ground FireDn; in addition, configure T start_delay ; Specifically, initialize the Measurement manager: configure M5 to select start_to_masker to path 14, configure the delay counter del_val of cross_signal_masker, which is used to control the delay to generate the hw_threshold_det_en signal; when measuring downlink, configure del_val to T stop_dn_delay ; When measuring uplink, set del_val to T stop_up_delay ; Specifically, initialize the Event manager: enable sw_threshold_det_en to activate DFF; that is, set the SN port signal of DFF to 1; Specifically, initialize the Measurement Core: enable tdc_core_en to put the TDC core in measurement state; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0049] S200, test enabling steps: In this step, the Transducer AFE function is enabled and downlink or uplink measurement is started; Specifically, the measurement mode of Pulse IO is as follows: in downlink measurement, downlink Pulse IO is enabled, Transducer Pulse Gen is enabled, an excitation square wave of the transducer is emitted, the square wave signal is sent to Transducer-1 through the FireDn port, and an echo signal is generated in Transducer-2; in uplink measurement, uplink Pulse IO is enabled, Transducer Pulse Gen is enabled, an excitation square wave of the transducer is emitted, the square wave signal is sent to Transducer-2 through the FireUp port, and an echo signal is generated in Transducer-1; Specifically, the Start signal is generated: when the square wave is emitted, start_to_masker is generated at the same time and sent to the Measurement Manger, triggering the Measurement Manger module to start counting the configured del_val count value; after the delay is completed, the hw_threshold_det_en signal is set to generate the trigger signal start_to_tdc for TDC Core to start measurement, and start_to_tdc is connected to TDC Core; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0050] S300, echo feedback steps: In this step, the FireUp electrical signal / FireDn electrical signal is converted into a mechanical signal by Transducer-2 (uplink measurement) / Transducer-1 (downlink measurement) respectively. After flying through the medium, it reaches Transducer-1 / Transducer-2 and is converted into an echo electrical signal. The echo electrical signal is fed back to Event Detecto through different paths. Specifically, the FireDn square wave signal passes through line 101, drives the square wave excitation signal to Transducer-1, and the FireDn square wave drives Transducer-1, generating an echo signal on Transducer-2; Specifically, the FireUp square wave signal passes through line 102, the square wave excitation signal drives Transducer-2, and the FireUp square wave drives Transducer-2, generating an echo signal on Transducer-1; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0051] S400, first wave of detection steps: In this step, the echo signal enters the Event Detector, which implements real-time comparison of the echo signal (performs threshold detection and zero-crossing comparison) according to the single / dual comparator solution, and the compared digital signal is sent to the PathRouter; Specifically, in the dual comparator solution, one comparator is used as a threshold detector and the other comparator is used as a zero-crossing detector; the zero-crossing event comparator will output a zero-crossing comparison waveform for detecting the echo signal; the threshold event comparator outputs a high level to indicate that the echo signal has reached the set threshold level, which is used to determine when to send the zero-crossing waveform generated by the zero-crossing event comparator to the TDC Core count; and during downlink measurement, the echo signal on Transducer-2 is applied to the positive terminals of comparators CMP-0 and CMP-1; during uplink measurement, the echo signal on Transducer-1 is applied to the positive terminals of comparators CMP-0 and CMP-1; during uplink / downlink measurement, the negative terminal of CMP-0 is grounded, and the negative terminal of CMP1 is connected to DACO (as shown in the attached figure). Figure 3 ); or, the negative terminal of CMP-1 is grounded, and the negative terminal of CMP0 is connected to DACO; Specifically, in the single comparator solution, a comparator is used to perform both zero-crossing comparison and threshold comparison in a time-sharing manner; the DACO output is set, and the negative end of the comparator is set to the threshold voltage; during downlink measurement, the echo signal of Transducer-2 is applied to the positive end of the comparator CMP-1, and the comparator CMP-0 is turned off; or, the echo signal of Transducer-2 is applied to the positive end of the comparator CMP-0, and the comparator CMP-1 is turned off; during uplink measurement, the echo signal of Transducer-1 is applied to the positive end of the comparator CMP-0, and the comparator CMP-1 is turned off; or, the echo signal of Transducer-1 is applied to the positive end of the comparator CMP-1, and the comparator CMP-0 is turned off; during uplink / downlink measurement, the negative ends of CMP-0 and CMP-1 are both connected to DACO; after the first wave is detected, the Event Manager turns off the DAC through the Qn end of the DFF, so that the DAC output is high impedance, and the comparator becomes a zero-crossing comparator at this time; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0052] S500, path selection step: In this step, different path selections are configured according to different application modes through Path Router, so that the output of the comparator enters the first wave detection circuit and the stop path of the TDC Core respectively; Specifically, configuration M1: When configured as internal start, the start_to_tdc signal is connected to the TDC Core; Specifically, configure M2 and M3: in the dual comparator solution, adjust the output 22 of CMP1 to 31 via M2, and the output 21 of CMP0 to 32 via M3; when the negative terminal of CMP-1 is grounded and the negative terminal of CMP0 is connected to DACO, select the output 22 of CMP1 to 32 via M3, and select the output 21 of CMP0 to 31 via M2; in the single comparator solution, when measuring downlink, adjust the output 22 of CMP1 to 31 via M2 and to 32 via M3; when measuring uplink, adjust the output 21 of CMP0 to 31 via M2 and to 32 via M3; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0053] S600, signal selection steps: In this step, the Event Manager controls the control signals from the Path Router, Measure Management, and the configuration interface to bypass the AND gate at the appropriate time and enter the stop port of the TDC Core. At the same time, the stop port also feeds back a signal to the Measure Management to control the Measure Management to count the number of stops and generate the Mask signal of the TDC Core. Specifically, the SN port is connected to the sw_threshold_det_en signal; based on the RN port at T stop_dn_delay or T stop_up_delay After the delay, the CLR port is set to 1 through the hw_threshold_det_en signal; after the SN port and the RN port are set to 1, the rising edge of the threshold comparison signal is monitored based on the CK terminal through the thre_cross_pulse connected to the CK terminal; in response to a rising pulse at the CK terminal, the Q terminal is controlled to output 1, and the EN port of the AND gate is opened through 41; in response to a rising pulse at the CK terminal, the Qn terminal is controlled to output 0; and connected to M4 through 61; Specifically, the zero-crossing comparison result of M3 is output 32 to the SI port of AND, and in response to the Q terminal enabling the EN port of the AND gate, the SI signal is directly passed to the stop terminal of the TDC Core; in addition, the output 33 of AND is also output to the Measurement manager module for stop counting to generate a Mask signal; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0054] S700, STOP counting steps: In this step, Measure management is called to start timing after receiving the rising edge of start_to_masker. Before the timing ends, the Q end of the trigger is output to 0 through the zero_cross_en signal, and the zero_cross_pulse signal is masked to 0. Then, each stop signal is monitored based on Measure management and compared with the configuration. Through the mask signal of TDC Core, it is determined whether to latch the counter for the current stop. Specifically, the first pulse is widened based on Echo pulse spread; the number of stop pulses is counted based on Echo pulse counter, and the number of stop signals is recorded; the Echo pulse masker is called to generate the MASKn signal based on the current stop count value and the Stop index to be measured; for example, when measuring 4 stops, there are: MIR1=0, MIR2=4, MIR3=6 and MIR4=7; the MASK1, MASK2, MASK3 and MASK4 signals are generated, and the corresponding measurement time is T 12 M1 、T 12 M2 、T 12 M3 and T 12 M4 ; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention.

[0055] S800, result output step: In this step, based on the TDC Core, the count starts from the rising edge of the start signal, to the MASKx signal, and the count value stored at the valid STOP rising edge is determined. After the conversion is completed, the interrupt and each count value are output; Specifically, when the technology is being used, the TDC Core is put into standby state based on the Standby mechanism, and the internal high-frequency counting unit is turned on only when the Start or Stop pulse (rising edge) arrives; after the current count ends, the TDC Core is put into standby state again, waiting for the arrival of the next stop, to achieve high-precision and low-power measurement; It should be noted that the examples herein are only for explaining the present invention and are not intended to limit the protection scope of the present invention. Example 3

[0056] This embodiment provides a computer-readable storage medium, including: The storage medium is used to store computer software instructions used to implement the high-precision ultrasonic flow measurement method described in the above-mentioned embodiment 2, which includes a program for executing the above-mentioned program set for the high-precision ultrasonic flow measurement method; specifically, the executable program can be built into the high-precision ultrasonic flow measurement system described in embodiment 1, so that the high-precision ultrasonic flow measurement system can implement the high-precision ultrasonic flow measurement method described in embodiment 2 by executing the built-in executable program.

[0057] In addition, the computer-readable storage medium of this embodiment may adopt any combination of one or more computer-readable storage media, wherein the computer-readable storage medium includes electrical, optical, electromagnetic, infrared or semiconductor systems, devices or components, or any combination thereof. Example 4

[0058] This embodiment provides an electronic device, such as Fig. 9 As shown, the electronic device may include: a processor 1501 , a communication interface 1502 , a memory 1503 and a communication bus 1504 , wherein the processor 1501 , the communication interface 1502 , and the memory 1503 communicate with each other via the communication bus 1504 .

[0059] Memory 1503, used for storing computer programs; The processor 1501 is used to implement the steps of the high-precision ultrasonic flow measurement method described in the above-mentioned embodiment 1 when executing the computer program stored in the memory 1503.

[0060] As an embodiment of the present invention, the communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0061] As an implementation mode of the present invention, the communication interface is used for communication between the above-mentioned terminal and other devices.

[0062] As an embodiment of the present invention, the memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0063] As an embodiment of the present invention, the above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0064] Different from the prior art, the present application adopts a high-precision ultrasonic flow measurement system, method, equipment and medium, which can achieve high-precision and low-power ultrasonic flow measurement without the need for complex devices, support flexible switching between single comparator and dual comparator, support direct calling of comparator for zero-crossing comparison without voltage regulation, have good circuit device parameter consistency, high integration, and more flexible TDC working control logic, which makes up for the defects of the prior art and has high application value.

[0065] It should be understood that in the various embodiments of this document, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this document.

[0066] It should also be understood that in the embodiments of this article, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0067] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.

[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific logical process of the method described above can refer to the corresponding working processes of the systems, devices and units in the aforementioned method embodiments, and will not be repeated here.

[0069] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0070] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.

[0071] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0072] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0073] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-precision ultrasonic flow measurement system, characterized in that: include: Ultrasonic flow detection circuit based on TDC and multi-mode comparator module; The multi-mode comparator module is used to: adopt a single comparator strategy or a dual comparator strategy to perform threshold detection and zero-crossing comparison on the echo signal to be measured; The TDC is used to count or interrupt according to the Standby mechanism and the TDC start signal of the ultrasonic flow detection circuit; The ultrasonic flow detection circuit is further used to set a generation delay of the TDC start signal.

2. The high-precision ultrasonic flow measurement system according to claim 1, characterized in that: The multi-mode comparator module is: a single comparator module; The single comparator module is point-to-point connected to the echo signal in the ultrasonic flow detection circuit; The single comparator module is used to support the single comparator strategy; the single comparator module uses one comparator to perform zero-crossing comparison and threshold detection in a time-sharing manner; or, The multi-mode comparator module is: a dual comparator module; The dual comparator module is connected to the echo signal via an analog switch capable of switching uplink and downlink paths; The dual comparator module is used to support the dual comparator strategy; the dual comparator module uses one comparator to perform threshold detection and another comparator to perform zero-crossing comparison.

3. The high-precision ultrasonic flow measurement system according to claim 2, characterized in that: The ultrasonic flow detection circuit further includes: a potential manager; The potential manager is provided with a DAC; The DAC is connected to the multi-mode comparator module; The potential manager is used to control the DAC to output a threshold voltage for the multi-mode comparator module.

4. The high-precision ultrasonic flow measurement system according to claim 2, characterized in that: The ultrasonic flow detection circuit further includes: a transducer AFE; The transducer AFE is provided with a sensor pulse generator; The sensor pulse generator is connected to the first end or the second end of the measurement structure according to the uplink and downlink measurement conditions; The transducer AFE is used to: output a square wave to the measurement structure, and the measurement structure outputs an echo signal to the multi-mode comparator module based on the square wave; The transducer AFE is further used to: generate the TDC start signal and the MASK start signal; the transducer AFE sends the TDC start signal to the TDC; the transducer AFE sends the MASK start signal to the measurement manager of the ultrasonic flow detection circuit; The transducer AFE is further used to: set a delay time between the TDC start signal and the MASK start signal, and the delay time is used as a generation delay of the TDC start signal.

5. The high-precision ultrasonic flow measurement system according to claim 4, characterized in that: The ultrasonic flow detection circuit further includes: a path distributor; The path distributor is provided with a first selector, a second selector and a third selector; An input of the first selector is connected to the sensor pulse generator, and an output of the first selector is connected to the TDC; The inputs of the second selector and the third selector are respectively connected to the multi-mode comparator module, and the outputs of the second selector and the third selector are respectively connected to the measurement manager; The path distributor is used to: when the dual comparator strategy is used, set the connection strategy between the second selector, the third selector and the multi-mode comparator module to the first connection strategy; The path distributor is further used to: when the single comparator strategy is used, set the connection strategy between the second selector, the third selector and the multi-mode comparator module to be the second connection strategy; The path distributor connects the output of the multi-mode comparator module to the TDC through the first connection strategy or the second connection strategy.

6. The high-precision ultrasonic flow measurement system according to claim 5, characterized in that: The ultrasonic flow detection circuit further includes: an event manager; The event manager is provided with a DFF and an AND gate; The input of the DFF is connected to the second selector and the measurement manager respectively, and the output of the DFF is connected to the potential manager and the AND gate respectively; An input of the AND gate is connected to the third selector and the DFF, and an output of the AND gate is connected to the TDC and the measurement manager; The event manager senses the first wave signal through the port configuration of the DFF; The event manager controls the zero-crossing comparison output of the multi-mode comparator module to enter the TDC in a timely manner according to the sensed first wave signal through the AND gate.

7. The high-precision ultrasonic flow measurement system according to claim 6, characterized in that: The ultrasonic flow detection circuit further includes: the measurement manager; The measurement manager is connected to the DFF, the TDC and the transducer AFE respectively; The measurement manager is used to: receive the MASK start signal and perform pulse counting according to the MASK start signal; and generate a mask signal for TDC counting according to the pulse counting.

8. A high-precision ultrasonic flow measurement method, characterized in that: The following steps are involved: A single comparator strategy or a double comparator strategy is used to perform threshold detection and zero-crossing comparison on the echo signal to be measured; TDC is called to process the zero-crossing comparison output based on the Standby mechanism and to generate a start signal with variable delay.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the high-precision ultrasonic flow measurement method of claim 8 are implemented.

10. A computer device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; wherein: The memory is used to store computer programs; The processor is used to execute the steps of the high-precision ultrasonic flow measurement method of claim 8 by running the program stored in the memory.

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