Power device pin parasitic inductance measuring circuit and electronic equipment

Abstract

The invention provides a power device pin parasitic inductance measuring circuit and electronic equipment. The measuring circuit is characterized in that a measured power device is connected between the output end of a double-pulse circuit and the ground; the measuring circuit comprises a double-pulse circuit, and the double-pulse circuit is used for outputting a changing current signal to the measured power device under the driving of the first pulse signal and the second pulse signal. According to the measuring circuit, the power device measuring assembly is connected between the lower tube of the double-pulse circuit and the negative electrode of the direct-current power supply, so that the parasitic inductance of the pin of the measured power device can be accurately measured.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and more specifically to a circuit and electronic device for measuring parasitic inductance of a power device pin. Background Art

[0002] Power semiconductor devices such as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) are used as switching devices to form topologies such as half-bridge, full-bridge, and three-phase bridge. They are widely used in various electronic systems, and the corresponding functions are realized by switching power semiconductor devices. During the switching process of the device, the current path in the system changes significantly, the current increases on some paths, and the current decreases on some paths, completing the "current commutation" process. During this process, the current change rate on the path is very fast, reaching more than 2000A / us.

[0003] In actual electronic systems, power device pins cannot be regarded as ideal wires and have corresponding parasitic inductances. These parasitic inductances will cause voltage overshoot, voltage and current oscillation, and increased switching losses during system commutation. Accurately evaluating and measuring the size of parasitic inductances is of great significance for electronic system design and optimization.

[0004] However, since the parasitic inductance of the pins of power devices is very small, generally around 10 nanohenries, it cannot be accurately measured using existing test equipment (such as digital bridges, etc.). Therefore, how to measure the parasitic inductance of the pins of power devices has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application is proposed in view of the above problems. The present application provides a circuit and electronic device for measuring the parasitic inductance of a power device pin, which can accurately measure the parasitic inductance of the pin of the power device under test.

[0006] According to a first aspect of the present application, a circuit for measuring parasitic inductance of a power device pin is provided, the measuring circuit comprising:

[0007] A double pulse circuit, the double pulse circuit is configured to be driven by a first pulse signal and a second pulse signal, and an upper tube of the double pulse circuit is connected to a positive electrode of a DC power supply;

[0008] A power device measuring component, wherein the power device measuring component comprises a power device to be measured, and the power device measuring component is connected between the lower tube of the double pulse circuit and the negative electrode of the direct current power supply.

[0009] The above technical solution has the following advantages or beneficial effects: by connecting the power device measurement component between the lower tube of the dual pulse circuit and the negative pole of the DC power supply, the switching characteristics of the dual pulse circuit are used to test the power device under test, thereby effectively measuring the parasitic inductance of the power device under test.

[0010] In some embodiments of the present application, the power device measurement component further includes:

[0011] A voltage acquisition circuit, used for acquiring the voltage between the control pin and the measured pin of the power device under test;

[0012] A current collection circuit, used for collecting the current flowing through the pin under test;

[0013] The control circuit is used to obtain the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives.

[0014] The above technical solution has the following advantages or beneficial effects: the voltage value and the current value can be collected respectively by the voltage collection circuit and the current collection circuit, and then the parasitic inductance can be calculated according to the inductance calculation formula using the control circuit.

[0015] In some embodiments of the present application, the control circuit is further used to obtain the parasitic inductance of the pin under test based on the ratio of the switching transient voltage change and the switching transient current change rate of the pin under test when the second pulse signal arrives.

[0016] The above technical solution has the following advantages or beneficial effects: by calculating the ratio of the switching transient voltage change amount and the switching transient current change rate through the control circuit, the parasitic inductance of the measured pin can be accurately obtained.

[0017] In some embodiments of the present application, the current acquisition circuit includes:

[0018] A fourth resistor is connected in series between the second end of the power device under test and the negative electrode of the DC power supply.

[0019] The above technical solution has the following advantages or beneficial effects: by setting the fourth resistor, the current can be measured by measuring the voltage of the fourth resistor, and the circuit structure is simple and easy to implement.

[0020] In some embodiments of the present application, the control terminal of the power device under test is configured to continuously input a positive voltage signal to keep the power device under test in a conducting state.

[0021] The above technical solution has the following advantages or beneficial effects: since the power device under test remains in the on state, the driving circuit of the control end of the power device under test is simplified, and the measured voltage is kept positive, so that the voltage signal generated by the parasitic inductance can be effectively collected.

[0022] In some embodiments of the present application, the double pulse circuit includes:

[0023] a first switch device, the first switch device serving as an upper tube of the double pulse circuit, a control end of which is configured to continuously input a zero voltage signal to keep the first switch device in an off state, and a first end of the first switch device being connected to a positive electrode of the DC power supply;

[0024] First inductor;

[0025] a first diode, wherein the first diode and the first inductor are connected in parallel between a first terminal and a second terminal of the first switching device;

[0026] A second switching device, the second switching device serves as a lower tube of the dual pulse circuit, a first end of the second switching device is connected to the second end of the first switching device, a second end is connected to the first end of the power device under test, and a control end of the second switching device is connected to a pulse signal generator; a second diode, the second diode is connected between the first end and the second end of the second switching device.

[0027] The above technical solution has the following advantages or beneficial effects: the dynamic characteristics of the power device under test can be analyzed through the double pulse circuit, so that the performance of the power device can be easily evaluated and the main parameters in the steady state and dynamic process can be obtained.

[0028] In some embodiments of the present application, the double pulse circuit further includes:

[0029] A first capacitor is connected in parallel with the DC power supply.

[0030] The above technical solution has the following advantages or beneficial effects: since the first capacitor is connected in parallel between the DC power supply and the ground, it can be used as a filter capacitor to filter out high-frequency noise and AC components of the power supply to prevent the circuit from self-excitation.

[0031] According to a second aspect of the present application, an electronic device is provided, and the electronic device includes the above-mentioned circuit for measuring parasitic inductance of a power device pin.

[0032] The above technical solution has the following advantages or beneficial effects: since the electronic device includes a circuit for measuring the parasitic inductance of the pin of the power device, the parasitic inductance of the pin of the power device under test can be accurately measured.

[0033] According to a third aspect of the present application, a method for measuring parasitic inductance of a power device pin is provided, comprising:

[0034] Measuring the voltage between the control pin and the measured pin of the power device under test and the current of the measured pin by the above-mentioned measurement circuit of the parasitic inductance of the power device pin;

[0035] The parasitic inductance of the pin under test is obtained based on the voltage value and the current change rate of the pin under test when the second pulse signal arrives.

[0036] The above technical solution has the following advantages or beneficial effects: the parasitic inductance of the pin of the power device is measured by using the measurement circuit, so that the parasitic inductance of the pin of the measured power device can be accurately obtained.

[0037] In some embodiments of the present application, obtaining the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives includes:

[0038] The parasitic inductance of the pin under test is obtained based on the ratio of the switching transient voltage change amount and the switching transient current change rate of the pin under test when the second pulse signal arrives.

[0039] The above technical solution has the following advantages or beneficial effects: by calculating the ratio of the switching transient voltage change amount and the switching transient current change rate, the parasitic inductance of the measured pin can be accurately obtained.

[0040] The parasitic inductance measurement circuit of the power device pin of the present application can accurately measure the parasitic inductance of the pin of the power device being measured by connecting the power device measurement component between the lower tube of the dual pulse circuit and the negative pole of the DC power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other purposes, features and advantages of the present invention will become more apparent by describing the embodiments of the present invention in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0042] Figure 1 is a schematic block diagram of a circuit for measuring parasitic inductance of a power device pin according to some embodiments of the present application;

[0043] Figure 2 is a schematic connection diagram of a circuit for measuring parasitic inductance of a power device pin according to some embodiments of the present application;

[0044] Figure 3ais the emitter current waveform collected at the fourth resistor;

[0045] Figure 3b is a waveform diagram of the gate-emitter voltage of the second switching device;

[0046] Figure 3c It is the gate-emitter voltage waveform of the power device under test;

[0047] Figure 4a yes Figure 3a The local amplified waveform diagram of the emitter current collected at the fourth resistor shown;

[0048] Figure 4b yes Figure 3c The local enlarged waveform of the gate-emitter voltage of the power device under test is shown;

[0049] Figure 5 It is a schematic flow chart of a method for measuring parasitic inductance of a power device pin according to some embodiments of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the present invention more obvious, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described in the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the present invention.

[0051] In order to solve the problem that the parasitic inductance of the pins of power devices is very small and cannot be accurately measured using existing test equipment (such as digital bridges, etc.), the present application proposes a measurement circuit and electronic equipment for the parasitic inductance of the pins of power devices, which are described in detail below.

[0052] The first aspect of the present application provides a circuit for measuring the parasitic inductance of a power device pin, such as Figure 1 As shown, the measurement circuit 100 includes:

[0053] A double pulse circuit 110, the double pulse circuit 110 is configured to be driven by a first pulse signal and a second pulse signal, and an upper tube of the double pulse circuit 110 is connected to a positive electrode of a DC power supply;

[0054] The power device measuring component 120 includes a power device to be measured, and the power device measuring component 120 is connected between the lower tube of the double pulse circuit 110 and the negative electrode of the DC power supply.

[0055] In the present application, the dual pulse circuit 110 includes two switching devices, an upper tube and a lower tube. The switching device and the power device under test can be a metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), an insulated gate bipolar power tube (Insulated Gate Bipolar Transistor, IGBT), a junction field-effect transistor (Junction Field-Effect Transistor, JFET), etc.

[0056] In the present application, the power device measurement component 120 is connected between the lower tube of the dual pulse circuit 110 and the negative pole of the DC power supply, and the negative pole of the DC power supply is grounded, so that the switching characteristics of the dual pulse circuit 110 can be used to test the power device under test, and the parasitic inductance of the power device under test can be effectively measured.

[0057] In some embodiments of the present application, the power device measurement component further includes:

[0058] A voltage acquisition circuit is used to acquire the voltage between the control pin and the measured pin of the power device under test;

[0059] A current collection circuit, used for collecting the current flowing through the pin under test;

[0060] The control circuit is used to obtain the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives.

[0061] In this embodiment, the control circuit may be a controller, and the controller may be various controllers commonly used by those skilled in the art, such as a single-chip microcomputer controller, a microcontroller unit, and a programmable logic controller.

[0062] In this embodiment, the voltage collection circuit can adopt the existing technology, which will not be described in detail here.

[0063] For an inductor, the voltage across its two ends and the current flowing through it satisfy the functional relationship shown in the following formula (1):

[0064]

[0065] Among them, V is the voltage across the inductor, i is the current flowing through the inductor, L is the inductance, and t is the time.

[0066] According to formula (1), the following formula (2) can be derived:

[0067]

[0068] According to the formula, as long as the voltage and current of the measured pin of the measured power device are measured, its parasitic inductance can be obtained. Therefore, in this embodiment, the voltage value between the control pin and the measured pin of the measured power device is collected by the voltage collection circuit, and the current value flowing through the measured pin is collected by the current collection circuit; then the control circuit can calculate the parasitic inductance of the measured pin based on the current change rate obtained by derivation of the voltage value and current value with respect to time when the second pulse signal arrives.

[0069] In a specific implementation, the control circuit also obtains the parasitic inductance of the pin under test based on the ratio of the switching transient voltage change amount and the switching transient current change rate of the pin under test when the second pulse signal arrives.

[0070] Here, the switching transient voltage change of the measured pin when the second pulse signal arrives is the difference in the voltage value of the measured pin when the second pulse signal drives the switching state of the measured power device to switch; the switching transient current change rate is the result obtained by taking the derivative of the current value of the measured pin with respect to time when the second pulse signal drives the switching state of the measured power device to switch.

[0071] Since the tested pin will have a driving voltage when the tested power device is turned on, the switching transient voltage change is the actual induced voltage of the parasitic inductance. Accordingly, the voltage signal collected by the voltage acquisition circuit should at least include the starting voltage signal when the second pulse signal arrives.

[0072] Based on the switching transient voltage change and the switching transient current change rate, the ratio of the two is calculated to accurately obtain the inductance of the parasitic inductance.

[0073] The following reference Figure 2 A circuit for measuring the parasitic inductance of a power device pin according to some embodiments of the present application is described.

[0074] like Figure 2 As shown in FIG. 1 , the measurement circuit of the parasitic inductance of the power device pin includes:

[0075] A first switch device U1, the first switch device U1 is used as an upper tube of the double pulse circuit, and its control terminal is used to input a zero voltage signal to keep the first switch device U1 in an off state, and a first terminal of the first switch device U1 is connected to the positive electrode of the DC power supply V4;

[0076] A first inductor L1;

[0077] A first diode D1, wherein the first diode D1 and a first inductor L1 are connected in parallel between a first terminal and a second terminal of the first switching device U1;

[0078] A second switch device U2, the second switch device U2 serves as a lower tube of the double pulse circuit, a first end of which is connected to the second end of the first switch device U1, a second end of the second switch device U2 is connected to the first end of the power device U3 under test, and a control end of the second switch device U2 is connected to the pulse signal generator M;

[0079] The second diode D2 is connected between the first end and the second end of the second switch device U2.

[0080] In this embodiment, the first power supply V1 is used to output a zero voltage signal to the control end of the first switch device U1. The DC power supply V4 is used to output a DC voltage signal, and the first inductor L1 serves as a load of the DC power supply V4. The pulse signal generator M is used to output a pulse signal to drive the second switch device U2, and these pulse signals trigger the gate of the second switch device U2, so that it turns on and starts to conduct.

[0081] In this embodiment, the measurement circuit of the parasitic inductance of the power device pin also includes a first resistor R1, a second resistor R2 and a third resistor R3. The first resistor R1, the second resistor R2 and the third resistor R3 serve as gate resistors, and the first ends are respectively connected to the power supply or the pulse signal generator, and the second ends are respectively connected to the gate of the first switching device U1, the gate of the second switching device U2 and the gate of the power device U3 under test.

[0082] In this embodiment, the first switching device U1 and the second switching device U2 can be a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), an insulated gate bipolar power transistor (Insulated Gate Bipolar Transistor, IGBT), a junction field-effect transistor (Junction Field-Effect Transistor, JFET), etc.

[0083] As an example, Figure 2 The first switch device U1 and the second switch device U2 are N-channel IGBTs, the control end of the first switch device U1 and the second switch device U2 is a gate (Gate, G), the first end is a collector (Collector, C), and the second end is an emitter (Emitter, E).

[0084] In this embodiment, the positive terminal of the first diode D1 is connected to the collector of the first switching device U1, and the negative terminal is connected to the emitter of the first switching device U1. The positive terminal of the second diode D2 is connected to the collector of the second switching device U2, and the negative terminal is connected to the emitter of the second switching device U2.

[0085] Preferably, Figure 2 The first switching device U1 and the second switching device U2 can also be reverse-conducting IGBT (RC-IGBT), that is, the IGBT and the freewheeling diode are integrated on a single chip, and the freewheeling diode is connected in reverse parallel to the IGBT, so there is no need to set up independent first diodes D1 and second diodes D2, thereby improving the integration of the test circuit and reducing the circuit area and cost.

[0086] The gate of the first switch device U1 is applied with zero voltage or is directly short-circuited to ensure that the tube is in the off state, so the first diode D1 connected in parallel with it plays a freewheeling role.

[0087] The freewheeling diode is connected in parallel at both ends of the first inductor L1. When the first inductor L1 is energized, an induced electromotive force is generated at both ends. When the current disappears, the induced electromotive force generated by the first inductor L1 is consumed through the loop formed by the first diode D1 and the first inductor L1, thereby protecting other devices in the circuit.

[0088] In order to collect the current value flowing through the pin under test, the measurement circuit of the parasitic inductance of the power device pin may further include a fourth resistor R4, which is connected in series between the second end of the power device under test U3 and the negative electrode of the DC power supply V4.

[0089] By setting the fourth resistor R4, the current can be measured by measuring the voltage of the fourth resistor R4. The circuit structure is simple and easy to implement.

[0090] In order to filter out high-frequency noise and AC components of the DC power supply to prevent the circuit from self-excitation, the circuit for measuring the parasitic inductance of the power device pin may further include a first capacitor C1 connected in parallel with the DC power supply V4.

[0091] The measurement circuit of the parasitic inductance of the power device pin of this embodiment can be independently provided, or can be integrated with the circuit module, and this application does not make any specific limitation on this.

[0092] It should be noted that Figure 2 The components and structures of the circuit for measuring the parasitic inductance of the pin of a power device are merely exemplary and non-limiting. The circuit for measuring the parasitic inductance of the pin of a power device may also have other components and structures as required.

[0093] During the measurement process, the first power supply V1 used to drive the first switching device U1 outputs a 0 volt voltage, the first switching device U1 remains in the cut-off state, and its parallel first diode D1 serves as the path for the first inductor L1 to continue current. The pulse signal generator M used to drive the second switching device U2 outputs a double-pulse voltage signal, the first pulse starts from 5us and ends at 50us, with a 20us interval in between, and the second pulse starts from 70us and ends at 90us (the double pulse time can be freely defined, and this setting is used as an example of simulation). The third power supply V3 used to drive the power device U3 under test outputs a 15 volt voltage signal, and the power device U3 under test remains in the normally open state. The DC power supply V4 is used to output a 200 volt DC voltage signal.

[0094] Since the power device under test is kept in a normally open state, the driving circuit of the control end of the power device under test is simplified, and the measured voltage is kept positive, so that the voltage signal generated by the parasitic inductance can be effectively collected.

[0095] Figure 3a is the emitter current waveform collected at the fourth resistor, Figure 3b is the gate-emitter voltage waveform of the second switching device, Figure 3c It is the gate-emitter voltage waveform of the power device under test.

[0096] like Figure 3a-3c As shown:

[0097] At t0=5us, the gate of the second switch device U2 receives the first pulse, the first switch device U1 remains off, the second switch device U2 is turned on, and the current flowing through the first inductor L and the emitter of the power device U3 under test rises linearly. The value of the current is determined by the pulse width of the first pulse. The longer the pulse width, the greater the current. Therefore, by adjusting the pulse width of the first pulse, that is, the conduction time of the second switch device U2, the emitter current of the power device U3 under test can be controlled.

[0098] At t1=50us, the first pulse ends, the second switch device U2 is turned off, the current of the first inductor flows to the first diode, and the current of the emitter of the power device U3 under test drops to 0.

[0099] At t2=70us, the second switch device U2 receives the second pulse and turns on again. The upper bridge arm diode reverse recovers, causing a reverse recovery current to pass through the second switch device U2. The reverse recovery current and the current of the first inductor L are superimposed to generate a current spike.

[0100] At t3=90us, the second pulse ends, the second switch device U2 is turned off again, and the current at the emitter of the power device U3 under test drops to 0 again.

[0101] Since parasitic inductance and parasitic capacitance exist inside the second switch device U2 and the power device under test U3, the gate-emitter voltage has spikes at the beginning and end of the pulse.

[0102] In order to measure the parasitic inductance of the power device U3 under test, the emitter current and the gate-emitter voltage of the power device U3 under test are collected at the start time of the second pulse signal.

[0103] Figure 4a yes Figure 3a The local amplified waveform of the emitter current collected at the fourth resistor is shown in FIG. Figure 4b yes Figure 3c The locally enlarged waveform of the gate-emitter voltage of the power device under test is shown.

[0104] From the start of the second pulse, the switching transient current value of the emitter of the power device U3 under test and the switching transient voltage of the gate-emitter are collected. For details, please refer to Figure 3a , select the point at 70.08us to measure the switching transient current value and calculate the switching transient current change rate di / dt; at the same time, refer to Figure 3c , measure the switching transient voltage between the gate and the emitter and calculate the change in the switching transient voltage △V GE .

[0105] Finally, the parasitic inductance of the emitter of the power device U3 under test is calculated according to the above formula (2), as shown in the following formula (3):

[0106]

[0107] Among them, L e It is the parasitic inductance of the emitter of the power device U3 under test.

[0108] In another aspect of the present application, an electronic device is provided, and the electronic device includes the above-mentioned circuit for measuring the parasitic inductance of the pin of the power device.

[0109] Since the electronic device of the present application includes a circuit for measuring the parasitic inductance of the pins of the power device, the parasitic inductance of the pins of the power device under test can be accurately measured.

[0110] In a third aspect of the present application, a method for measuring the parasitic inductance of a power device pin is provided.

[0111] The following reference Figure 5 A method for measuring the parasitic inductance of a power device pin according to some embodiments of the present application is described.

[0112] like Figure 5 As shown, the method comprises the following steps:

[0113] Step S510, measuring the voltage between the control pin and the measured pin of the power device under test and the current of the measured pin by using the above-mentioned measurement circuit of the parasitic inductance of the power device pin;

[0114] Step S520: Obtain the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives.

[0115] The method utilizes a measurement circuit for the parasitic inductance of a power device pin to perform measurement, thereby accurately obtaining the parasitic inductance of the pin of the power device being measured.

[0116] In some embodiments of the present application, obtaining the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives includes:

[0117] The parasitic inductance of the pin under test is obtained based on the ratio of the switching transient voltage change amount and the switching transient current change rate of the pin under test when the second pulse signal arrives.

[0118] By calculating the ratio of the switching transient voltage change and the switching transient current change rate, the parasitic inductance of the measured pin can be accurately obtained.

[0119] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present invention thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as required by the appended claims.

[0120] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0122] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0123] Similarly, it should be understood that in order to streamline the present invention and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0124] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0125] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0126] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some modules in the article analysis device according to an embodiment of the present invention. The present invention may also be implemented as a device program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may have the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0127] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of devices or steps not listed in the claims. The word "one" or "an" preceding a device does not exclude the presence of a plurality of such devices. The present invention may be implemented by means of hardware comprising a number of different devices and by means of appropriately programmed computers. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0128] The above is only a specific embodiment of the present invention or an explanation of a specific embodiment, and the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A circuit for measuring parasitic inductance of a power device pin, characterized in that: The measuring circuit comprises: A double pulse circuit, the double pulse circuit is configured to be driven by a first pulse signal and a second pulse signal, and an upper tube of the double pulse circuit is connected to a positive electrode of a DC power supply; A power device measuring component, wherein the power device measuring component comprises a power device to be measured, and the power device measuring component is connected between the lower tube of the double pulse circuit and the negative electrode of the direct current power supply.

2. The circuit for measuring parasitic inductance of a power device pin according to claim 1, characterized in that: The power device measurement component also includes: A voltage acquisition circuit, used for acquiring the voltage between the control pin and the measured pin of the power device under test; A current collection circuit, used for collecting the current flowing through the pin under test; The control circuit is used to obtain the parasitic inductance of the pin under test based on the voltage value and current change rate of the pin under test when the second pulse signal arrives.

3. The circuit for measuring parasitic inductance of a power device pin according to claim 2, characterized in that: The control circuit is further used to obtain the parasitic inductance of the pin under test based on the ratio of the switching transient voltage change amount and the switching transient current change rate of the pin under test when the second pulse signal arrives.

4. The circuit for measuring parasitic inductance of a power device pin according to claim 2, characterized in that: The current collection circuit comprises: A fourth resistor is connected in series between the second end of the power device under test and the negative electrode of the DC power supply.

5. The circuit for measuring the parasitic inductance of a power device pin according to any one of claims 1 to 4, characterized in that: The control terminal of the power device under test is configured to continuously input a positive voltage signal to keep the power device under test in a conducting state.

6. The circuit for measuring parasitic inductance of a power device pin according to claim 1, characterized in that: The double pulse circuit comprises: a first switch device, the first switch device serving as an upper tube of the double pulse circuit, a control end of which is configured to continuously input a zero voltage signal to keep the first switch device in an off state, and a first end of the first switch device being connected to a positive electrode of the DC power supply; First inductor; a first diode, wherein the first diode and the first inductor are connected in parallel between a first terminal and a second terminal of the first switching device; A second switch device, the second switch device serves as a lower tube of the double pulse circuit, a first end of the second switch device is connected to the second end of the first switch device, a second end of the second switch device is connected to the first end of the power device under test, and a control end of the second switch device is connected to a pulse signal generator; A second diode is connected between the first terminal and the second terminal of the second switching device.

7. The circuit for measuring parasitic inductance of a power device pin according to claim 6, characterized in that: The double pulse circuit also includes: A first capacitor is connected in parallel with the DC power supply.

8. An electronic device, characterized in that: The electronic device comprises the circuit for measuring the parasitic inductance of a power device pin according to any one of claims 1 to 7.

9. A method for measuring parasitic inductance of a power device pin, characterized in that: include: Measuring the voltage between the control pin and the measured pin of the power device under test and the current of the measured pin by using the measurement circuit of the parasitic inductance of the power device pin according to any one of claims 1 to 7; The parasitic inductance of the pin under test is obtained based on the voltage value and the current change rate of the pin under test when the second pulse signal arrives.

10. The method for measuring the parasitic inductance of a power device pin according to claim 9, characterized in that: The obtaining of the parasitic inductance of the pin under test based on the voltage value and the current change rate of the pin under test when the second pulse signal arrives includes: The parasitic inductance of the pin under test is obtained based on the ratio of the switching transient voltage change amount and the switching transient current change rate of the pin under test when the second pulse signal arrives.

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