An adaptive dead time test circuit and method

Abstract

The application relates to the technical field of integrated circuits, and provides a self-adaptive dead time test circuit and a test method, which are used for testing an HVIC chip and comprise a first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator and a second capacitor; a first end of the first power supply is connected with a first end of the first capacitor and grounded, a second end of the first power supply is connected with a second end of the first capacitor and connected to a VCC port of the HVIC chip; a first end of the first oscilloscope is connected with a first end of the first signal generator and connected to an HIN port of the HVIC chip, and a second end of the first oscilloscope and a second end of the first signal generator are grounded respectively. The self-adaptive dead time test circuit has good test effect and high product qualification rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an adaptive dead time test circuit and a test method. BACKGROUND

[0002] High voltage integrated circuit, namely HVIC, is an integrated circuit product for converting MCU signal into driving IGBT signal. The HVIC integrates PMOS, NMOS, triode, diode, voltage stabilizing tube, resistance and capacitor together to form Smith, low voltage LEVELSHIFT, high voltage LEVELSHIFT, pulse generating circuit, dead zone circuit, interlocking circuit, delay circuit, filter circuit, overcurrent protection circuit and overheat protection circuit, under-voltage protection circuit and enable EN circuit and other circuits. The HVIC receives the control signal of MCU on one hand to drive the subsequent IGBT or MOS to work, and sends the state detection signal of the system back to the MCU on the other hand, which is the key chip inside the IPM.

[0003] With the rapid development of industry, IPM intelligent power module is widely applied in various fields, and driving IC (HVIC) is one of the key elements inside the IPM, and its performance determines the performance of the IPM, and the EN enable circuit is a very important circuit inside the HVIC. The function of the circuit is to control the opening or closing of the HVIC through the threshold value of the EN. In the application of motor control of IPM intelligent power module, the EN enable signal is used to control the switching of the whole circuit. By controlling the enable signal, it can be determined whether the motor receives the driving signal to rotate. The enable circuit plays an important role in ensuring the safety of the equipment, improving the flexibility of the function and optimizing the use of energy.

[0004] Therefore, when the HVIC is produced off-line, it is necessary to test whether the performance index of the adaptive dead zone circuit meets the standard. SUMMARY

[0005] The present application provides an adaptive dead time test circuit and a test method, which aims to solve the problem of poor test effect and poor pass rate of the existing HVIC chip at different temperatures.

[0006] The present application provides an adaptive dead time test circuit for testing HVIC chip, comprising: a first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator and a second capacitor.

[0007] A first end of the first power supply is connected to a first end of the first capacitor and is grounded, a second end of the first power supply is connected to a second end of the first capacitor and is connected to a VCC port of the HVIC chip; a first end of the first oscilloscope is connected to a first end of the first signal generator and is connected to a HIN port of the HVIC chip, and a second end of the first oscilloscope and a second end of the first signal generator are grounded respectively;

[0008] A first end of the second oscilloscope is connected to a first end of the second signal generator and is connected to a LIN port of the HVIC chip, a second end of the second oscilloscope is connected to a second end of the second signal generator and is grounded, and the second end of the second signal generator is further connected to an ITRIP port of the HVIC chip;

[0009] The first end of the third oscilloscope is connected to the first end of the third signal generator and is connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and is grounded;

[0010] A first end of the second power supply is grounded, a second end of the second power supply is connected to a first end of the first resistor, and a second end of the first resistor is connected to a FAULT port of the HVIC chip;

[0011] A first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, a second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and to the COM port of the HVIC chip, a second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, a first end of the second capacitor is connected to the VB port of the HVIC chip, and a second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope.

[0012] In a second aspect, an embodiment of the present invention provides an adaptive dead time testing method, which is implemented based on the above-mentioned adaptive dead time testing circuit and includes the following steps:

[0013] S1, start the thermostat and set the temperature to the preset temperature;

[0014] S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip;

[0015] S3, start the second DC power supply and set it to 5V, and pull up the EN port of the HVIC chip to 5V through the first resistor;

[0016] S4, starting the first signal generator, the second signal generator and the third signal generator to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip respectively;

[0017] S5. Input and output signals to the HIN port, LIN port, EN port, HO port, LO port, and FAULT port respectively through the first oscilloscope, the second oscilloscope, the third oscilloscope, the fourth oscilloscope, and the fifth oscilloscope;

[0018] S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port, and FAULT port; record the EN voltage when the EN signal rises from 0V to 5V and HO and LO have outputs, which is recorded as VEN1; record the EN voltage when the EN signal rises from 5V to 0V and HO and LO are turned off, which is recorded as EN2;

[0019] S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%);

[0020] V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if so, cycle through S1-S6; if not, the test ends and the product fails.

[0021] Preferably, the preset temperature of S1 is 25°C.

[0022] Preferably, the preset temperature of S1 is -40°C.

[0023] Preferably, the preset temperature of S1 is 125°C.

[0024] Compared with the prior art, the beneficial effect of the present invention lies in that, by connecting the first end of the first power supply to the first end of the first capacitor and grounding, the second end of the first power supply is connected to the second end of the first capacitor and connected to the VCC port of the HVIC chip; the first end of the first oscilloscope is connected to the first end of the first signal generator and connected to the HIN port of the HVIC chip, the second end of the first oscilloscope and the second end of the first signal generator are grounded respectively; the first end of the second oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip, the second end of the second oscilloscope is connected to the second end of the second signal generator and grounded, and the second end of the second signal generator is also connected to the ITRIP port of the HVIC chip; the first end of the third oscilloscope is connected to the first end of the second signal generator and connected to the LIN port of the HVIC chip The first end of the third signal generator is connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and grounded; the first end of the second power supply is grounded, the second end of the second power supply is connected to the first end of the first resistor, and the second end of the first resistor is connected to the FAULT port of the HVIC chip; the first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, the second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and connected to the COM port of the HVIC chip, the second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, the first end of the second capacitor is connected to the VB port of the HVIC chip, and the second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope. The test circuit and test method of the present invention test the EN enable threshold at different temperatures, with an EN input of 0-5V, a rise time of 10ms, and a fall time of 10ms. During the rising process of the EN signal, the voltage of EN is detected when the HVIC is working normally and has a drive output; during the falling process of the EN signal, the voltage of EN is detected when the HVIC stops working and has no drive output; and whether the EN enable threshold and the shutoff threshold are within a qualified range is judged to prevent products with unqualified EN enable thresholds from entering the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0026] Figure 1 is a circuit diagram of an adaptive dead time test circuit provided by an embodiment of the present invention;

[0027] Figure 2 : is the waveform of the fault output port / FAULT provided by an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of PWM parameters of an EN input signal provided by an embodiment of the present invention;

[0029] Figure 4 This is a test timing diagram of an adaptive dead time test circuit provided by an embodiment of the present invention;

[0030] Figure 5 is a flow chart of an adaptive dead time testing method provided by an embodiment of the present invention;

[0031] Figure 6 4 is a flow chart of different temperatures of the adaptive dead time testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] First, combined with the Figures 1-4 As shown, an embodiment of the present invention provides an adaptive dead time test circuit for testing an HVIC chip 0201, comprising: a first power supply 0202, a first capacitor C1, a second power supply 0212, a first resistor R1, a first oscilloscope 0204, a second oscilloscope 0205, a third oscilloscope 0209, a fourth oscilloscope 0210, a fifth oscilloscope 0211, a first signal generator 0206, a second signal generator 0207, a third signal generator 0208, and a second capacitor C2;

[0034] A first end of the first power supply 0202 is connected to a first end of the first capacitor C1 and is grounded. A second end of the first power supply 0202 is connected to a second end of the first capacitor C1 and is connected to a VCC port of the HVIC chip 0201. A first end of the first oscilloscope 0204 is connected to a first end of the first signal generator 0206 and is connected to a HIN port of the HVIC chip 0201. A second end of the first oscilloscope 0204 and a second end of the first signal generator 0206 are grounded, respectively.

[0035] A first end of the second oscilloscope 0205 is connected to a first end of the second signal generator 0207 and is connected to a LIN port of the HVIC chip 0201. A second end of the second oscilloscope 0205 is connected to a second end of the second signal generator 0207 and is grounded. A second end of the second signal generator 0207 is also connected to an ITRIP port of the HVIC chip 0201.

[0036] A first end of the third oscilloscope 0209 is connected to a first end of the third signal generator 0208 and to an EN port of the HVIC chip 0201, and a second end of the third oscilloscope 0209 is connected to a second end of the third signal generator 0208 and to ground;

[0037] A first end of the second power supply 0212 is grounded, a second end of the second power supply 0212 is connected to a first end of the first resistor R1, and a second end of the first resistor R1 is connected to a FAULT port of the HVIC chip 0201;

[0038] A first end of the fourth oscilloscope 0210 is connected to the HO port of the HVIC chip 0201, a second end of the fourth oscilloscope 0210 is connected to the first end of the fifth oscilloscope 0211 and to the COM port of the HVIC chip 0201, a second end of the fifth oscilloscope 0211 is connected to the LO port of the HVIC chip 0201, a first end of the second capacitor C2 is connected to the VB port of the HVIC chip 0201, and a second end of the second capacitor C2 is respectively connected to the VS port of the HVIC chip 0201 and the first end of the fifth oscilloscope 0211.

[0039] Specifically, a bridge arm input port HIN1, LIN1, VB1, VS1, enable input port EN and overcurrent protection port ITRIP, output ports HO1, LO1, fault output port / FAULT, power supply VCC and ground terminals GND, COM.

[0040] The first power supply 0202 is a DC power supply with a maximum output voltage of ≥20 V and a maximum output current of >0.5 A. The first capacitor C1 is a pin capacitor of the first power supply 0202 , which is generally 1 uF.

[0041] The first oscilloscope 0204, the second oscilloscope 0205, the third oscilloscope 0209, the fourth oscilloscope 0210, and the fifth oscilloscope 0211 are the voltage differences between the low-voltage side output and the low-voltage side of five common probes.

[0042] The three output ports PWM1, PWM2, and PWM3 of the first signal generator 0206, the second signal generator 0207, and the third signal generator 0208 are complementary PWM signals. The fault output port / FAULT is connected to 5V via a 6.8K resistor R1. The positive output of the first DC power supply is connected to the VCC of the HVIC under test and one end of the first capacitor C1, while the negative output is connected to the GND of the HVIC under test and the other end of the first capacitor C1. The output port PWM1 of the first signal generator 0206 is connected to HIN123 of the HVIC under test, and the output port PWM2 of the second signal generator 0207 is connected to LIN123 of the HVIC under test. The output port PWM3 of the third signal generator 0208 is connected to EN of the HVIC under test. The PWM wave has a pulse period of T, a pulse width of W, a rise time of ton, and a fall time of 0 to 5V. VB123 of the tested HVIC chip 0201 is connected to one end of the bootstrap capacitor C1, and VS123, the other end of the second capacitor C2, and VS123 are connected to COM.

[0043] In a specific implementation, the first end of the first power supply 0202 is connected to the first end of the first capacitor C1 and is grounded, the second end of the first power supply 0202 is connected to the second end of the first capacitor C1 and is connected to the VCC port of the HVIC chip 0201; the first end of the first oscilloscope 0204 is connected to the first end of the first signal generator 0206 and is connected to the HIN port of the HVIC chip 0201, the second end of the first oscilloscope 0204 and the second end of the first signal generator 0206 are grounded respectively; the first end of the second oscilloscope 0205 is connected to the first end of the second signal generator 0207 and is connected to the LIN port of the HVIC chip 0201, the second end of the second oscilloscope 0205 is connected to the second end of the second signal generator 0207 and is grounded, and the second end of the second signal generator 0207 is also connected to the ITRIP port of the HVIC chip 0201; the first end of the third oscilloscope 0209 is connected to the third signal generator 0208 The first end of the third oscilloscope 0209 is connected to the EN port of the HVIC chip 0201, the second end of the third oscilloscope 0209 is connected to the second end of the third signal generator 0208 and grounded; the first end of the second power supply 0212 is grounded, the second end of the second power supply 0212 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the FAULT port of the HVIC chip 0201; the first end of the fourth oscilloscope 0210 is connected to the HO port of the HVIC chip 0201, the second end of the fourth oscilloscope 0210 is connected to the first end of the fifth oscilloscope 0211 and connected to the COM port of the HVIC chip 0201, the second end of the fifth oscilloscope 0211 is connected to the LO port of the HVIC chip 0201, the first end of the second capacitor C2 is connected to the VB port of the HVIC chip 0201, and the second end of the second capacitor C2 is respectively connected to the VS port of the HVIC chip 0201 and the first end of the fifth oscilloscope 0211. The test circuit and test method of the present invention test the EN enable threshold at different temperatures, with an EN input of 0-5V, a rise time of 10ms, and a fall time of 10ms. During the rising process of the EN signal, the voltage of EN is detected when the HVIC is working normally and has a drive output; during the falling process of the EN signal, the voltage of EN is detected when the HVIC stops working and has no drive output; and whether the EN enable threshold and the shutoff threshold are within a qualified range is judged to prevent products with unqualified EN enable thresholds from entering the market.

[0044] Secondly, combined with the Figures 1-6 As shown, an embodiment of the present invention provides an adaptive dead time testing method, which is implemented based on the above-mentioned adaptive dead time testing circuit and includes the following steps:

[0045] S1, start the thermostat and set the temperature to the preset temperature;

[0046] S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip 0201;

[0047] S3, start the second DC power supply and set it to 5V, pull up the EN port of the HVIC chip 0201 to 5V through the first resistor R1;

[0048] S4, starting the first signal generator 0206, the second signal generator 0207 and the third signal generator 0208 to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip 0201 respectively;

[0049] S5. Input and output signals to the HIN port, LIN port, EN port, HO port, LO port, and FAULT port respectively through the first oscilloscope 0204, the second oscilloscope 0205, the third oscilloscope 0209, the fourth oscilloscope 0210, and the fifth oscilloscope 0211;

[0050] S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port, and FAULT port; record the EN voltage when the EN signal rises from 0V to 5V and HO and LO have outputs, which is recorded as VEN1; record the EN voltage when the EN signal rises from 5V to 0V and HO and LO are turned off, which is recorded as EN2;

[0051] S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%);

[0052] V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if so, cycle through S1-S6; if not, the test ends and the product fails.

[0053] In this embodiment, the preset temperature of S1 is 25°C.

[0054] In this embodiment, the preset temperature of S1 is -40°C.

[0055] In this embodiment, the preset temperature of S1 is 125°C.

[0056] Specifically, this test method tests the EN enable threshold at different temperatures. The EN input is 0-5V, with a rise time of 10ms and a fall time of 10ms. During the rising process of the EN signal, the voltage of EN is detected when the HVIC is working normally and there is a drive output. During the falling process of the EN signal, the voltage of EN is detected when the HVIC stops working and there is no drive output. The method also determines whether the EN enable turn-on threshold and turn-off threshold are within the qualified range to prevent products with unqualified EN enable thresholds from entering the market.

[0057] The six-channel HVIC has three bridge arms. The upper and lower bridges of each bridge arm drive the HIN and LIN signals, and the output terminals HO and LO each control the conduction of an IGBT. The upper and lower bridge drive signal outputs are given to the HVIC enable EN. When the enable EN signal input is above the turn-on threshold, the upper and lower bridge drive signals are output. When the enable EN signal input is below the turn-on threshold, the upper and lower bridge drive signals are shut down and the fault signal / FAULT is pulled low.

[0058] The operating power supply for a six-channel HVIC is 12V-20V, with 15V being the most common. Its operating temperature is -40°C-125°C. The operating characteristics of an HVIC will vary at different temperatures. Therefore, to determine whether an HVIC's performance meets the standards, it is necessary to test the parameters of each functional circuit at different temperatures to see if they meet the standards.

[0059] This test method: Under 15V power supply, select three temperature tests: the highest temperature 125℃, the normal temperature 25℃, and the lowest temperature -40℃.

[0060] This method is mainly used to test the EN threshold voltage parameter. Shorter connections should be used as much as possible to reduce the impact of external connection parasitic capacitance on the results.

[0061] The test equipment is as follows:

[0062] 1. Temperature control box: Temperature control range: -45℃~145℃; control accuracy: 1℃.

[0063] 2. Signal generator: three-channel output; Vp-p > 20V; current output capability > 0.5A; bandwidth > 500MHz.

[0064] 3. Oscilloscope: multiple inputs; >500MHz bandwidth.

[0065] 4. Power supply: Multi-channel output DC power supply, maximum output voltage>20V; maximum output current>0.5A.

[0066] Test standard: Connect the HVIC's VCC to a 15V power supply, pull the fault output to 5V via resistor R, connect the overcurrent protection input to ground, connect the bootstrap circuit terminals VB123 and VS123 to bootstrap capacitors, connect the signal generator's output 0206PWM1 to the HIN123 of the HVIC under test, and the signal generator's output 0208PWM2 to the HVIC under test's LIN123. The EN input uses a PWM wave with a pulse period of T, a pulse width of W, a rise time of ton, and a fall time of toff from 0 to 5V. During the EN signal's rising phase, check that the HVIC is operating normally. When the driver output is present, the EN voltage is within ±5% of the HVIC enable threshold. During the EN signal's falling phase, check that the HVIC is not operating properly. When the driver output is absent, the EN voltage is within ±5% of the HVIC enable threshold. The HVIC under test passes the test.

[0067] Figure 4 It is the EN input signal PWM parameter description: T is the pulse period, W is the pulse width, ton is the rise time of the pulse from 0 to 5V, and toff is the fall time of the pulse from 5V to 0.

[0068] Figure 5 The test timing diagram is as follows: HIN is the PWM signal input to the upper bridge driver of the HVIC under test, LIN is the PWM signal input to the lower bridge driver of the HVIC under test, EN is the EN enable input PWM signal of the HVIC under test, V ENH+ EN enable turn-on threshold, V ENH- EN is the enable shutdown threshold, HO is the upper bridge driver output signal of the HVIC under test, LO is the lower bridge driver output signal of the HVIC under test, and / FAULT is the fault signal output signal of the HVIC under test.

[0069] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, article, or device comprising the element.

[0070] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. An adaptive dead time test circuit for testing HVIC chips, characterized in that: include: A first power supply, a first capacitor, a second power supply, a first resistor, a first oscilloscope, a second oscilloscope, a third oscilloscope, a fourth oscilloscope, a fifth oscilloscope, a first signal generator, a second signal generator, a third signal generator, and a second capacitor; A first end of the first power supply is connected to a first end of the first capacitor and is grounded, a second end of the first power supply is connected to a second end of the first capacitor and is connected to a VCC port of the HVIC chip; a first end of the first oscilloscope is connected to a first end of the first signal generator and is connected to a HIN port of the HVIC chip, and a second end of the first oscilloscope and a second end of the first signal generator are grounded respectively; A first end of the second oscilloscope is connected to a first end of the second signal generator and is connected to a LIN port of the HVIC chip, a second end of the second oscilloscope is connected to a second end of the second signal generator and is grounded, and the second end of the second signal generator is further connected to an ITRIP port of the HVIC chip; The first end of the third oscilloscope is connected to the first end of the third signal generator and is connected to the EN port of the HVIC chip, and the second end of the third oscilloscope is connected to the second end of the third signal generator and is grounded; A first end of the second power supply is grounded, a second end of the second power supply is connected to a first end of the first resistor, and a second end of the first resistor is connected to a FAULT port of the HVIC chip; A first end of the fourth oscilloscope is connected to the HO port of the HVIC chip, a second end of the fourth oscilloscope is connected to the first end of the fifth oscilloscope and to the COM port of the HVIC chip, a second end of the fifth oscilloscope is connected to the LO port of the HVIC chip, a first end of the second capacitor is connected to the VB port of the HVIC chip, and a second end of the second capacitor is respectively connected to the VS port of the HVIC chip and the first end of the fifth oscilloscope.

2. An adaptive dead time testing method, characterized in that: The test method is implemented based on the adaptive dead time test circuit according to claim 1, and the test method comprises the following steps: S1, start the thermostat and set the temperature to the preset temperature; S2, start the first DC power supply and set it to 15V, and supply power to the HVIC chip; S3, start the second DC power supply and set it to 5V, and pull up the EN port of the HVIC chip to 5V through the first resistor; S4, starting the first signal generator, the second signal generator and the third signal generator to output pulse signals to the HIN port, the LIN port and the EN port of the HVIC chip respectively; S5. Input and output signals to the HIN port, LIN port, EN port, HO port, LO port, and FAULT port respectively through the first oscilloscope, the second oscilloscope, the third oscilloscope, the fourth oscilloscope, and the fifth oscilloscope; S6. Collect and record the signals of the HIN port, LIN port, EN port, HO port, LO port, and FAULT port; record the EN voltage when the EN signal rises from 0 to 5V and HO and LO have outputs, which is recorded as V EN1 When the EN signal drops from 5V to 0V and HO and LO turn off the output, what is the EN voltage? It is recorded as V EN2 ; S7, judge V ENH +(95%) <V EN1 <V ENH +(1+5%); V ENH -(95%) <V EN2 <V ENH -(1+5%); whether it meets the requirements, if yes, then loop through S1-S6; if not, then the test ends and the product fails; Among them, V ENH+ Indicates the enable threshold, V ENH- Indicates the enable shutdown threshold.

3. The adaptive dead time testing method according to claim 2, wherein: The preset temperature of S1 is 25°C.

4. The adaptive dead time testing method according to claim 2, wherein: The preset temperature of S1 is -40°C.

5. The adaptive dead time testing method according to claim 2, wherein: The preset temperature of S1 is 125°C.

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