Simulation circuit test excitation generation method based on heuristic greedy algorithm

Abstract

The application discloses a simulation circuit test excitation generation method based on a heuristic greedy algorithm. Defect modeling is performed on a to-be-tested simulation circuit to obtain a defect simulation analog circuit, a search space is set according to an excitation source of the to-be-tested simulation circuit, the search space is equally divided to obtain a plurality of sub-search spaces, a search point where a geometric center of each sub-search space is located is taken as an initial point, a search starting point is determined according to a detectable defect quantity of each initial point, and then the test excitation is searched from the search starting point based on the heuristic greedy algorithm, so that a test excitation set required by the simulation circuit is obtained. The simulation circuit test excitation generation efficiency can be effectively improved by adopting the application.

Description

Technical Field

[0001] This invention belongs to the field of analog circuit testing technology, and more specifically, relates to a method for generating test stimuli for analog circuits based on a heuristic greedy algorithm. Background Technology

[0002] As the integration level and component complexity of circuit boards increase exponentially, the requirements for controllability, testability, and observability become increasingly stringent, leading to higher testing requirements and increased difficulty and cost in chip fault testing. Under specific stimuli, if the presence of a defect in a circuit affects the circuit voltage to a degree sufficient to distinguish it from a defect-free circuit, then the defect is considered detectable. Research has found that the choice of test stimuli directly impacts the cost and efficiency of circuit defect detection.

[0003] Test stimulus generation can be viewed as a search and optimization problem. The number of detectable defects is evaluated as a function of the DC excitation voltage. However, since the excitation signal of analog circuits is a continuous real value, it can take any value within the allowable range, resulting in an infinite number of possible excitation combinations. Furthermore, due to complex behaviors such as signal fluctuations, distortions, and nonlinear responses that may exist in the circuit, the curve showing the number of detectable defects changing with the DC excitation is generally discontinuous and differentiable, making it difficult to obtain an optimal solution through mathematical optimization methods. However, existing analog circuit test stimulus optimization methods mostly suffer from drawbacks such as time-consuming circuit simulation analysis, complex feature acquisition processes, weak universality of decision function constraints, and poor scalability, resulting in unsatisfactory solution performance. Therefore, new algorithms are needed to obtain better solutions. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for generating test stimuli for analog circuits based on a heuristic greedy algorithm. The method evaluates the test stimuli by the number of detectable defects and then uses a heuristic greedy algorithm to gradually adjust the test stimuli to move towards a larger number of detectable defects. Finally, a set of test stimuli is generated in the shortest possible time, thereby effectively improving the generation efficiency of test stimuli for analog circuits.

[0005] To achieve the above-mentioned objectives, the present invention provides a method for generating analog circuit test stimuli based on a heuristic greedy algorithm, comprising the following steps:

[0006] S1: For the simulation circuit under test, identify all components in the circuit netlist, establish defect models for all components except the power supply, generate a defect list, perform equivalent compression on each defect model, and inject them one by one into the simulation circuit under test to obtain the defect simulation circuit.

[0007] S2: Based on the number N of excitation sources of the analog circuit under test, establish an N-dimensional search space, and discretize the search space according to the accuracy that the test excitation can achieve to obtain the coordinates of each search grid point;

[0008] S3: Divide the search space into D=2 equal parts. N This yields D sub-search spaces, with the geometric center of each sub-search space located at the search grid point as the initial point (start). d d = 1, 2, ..., D, in the analog circuit, for each initial point start d Perform defect simulation and record each initial point (start). d Detectable defect set Choose the initial point with the largest number of detectable defects as the search starting point base;

[0009] S4: Search the test incentive set based on a heuristic greedy algorithm. The specific method is as follows:

[0010] S4.1: Initialize the cumulative set of detectable defects Initialize the test stimulus set E = {start1, start2, ..., start D};

[0011] S4.2: Initialize the search step size L = L0, where L0 represents the preset initial value of the search step size;

[0012] S4.3: Sample K search grid points that are L distances from the search base point in the search space as neighborhood search points p. k k = 1, 2, ..., K, where K represents the preset number of sampling points;

[0013] S4.4: Search for each neighborhood point p in the analog circuit. k Defect simulation is performed to obtain the corresponding set of detectable defects f. k , search the neighborhood point p k Add the test stimulus set E, and let the cumulative detectable defect set F′=F∪f1∪f2∪…∪f K ;

[0014] S4.5: Determine whether the search termination condition has been met. If yes, proceed to step S4.9; otherwise, proceed to step S4.6.

[0015] S4.6: Determine whether |F′| > |F|, where || represents the number of detectable defects in the set. If yes, proceed to step S4.7; otherwise, proceed to step S4.8.

[0016] S4.7: Let the cumulative set of detectable defects F = F′, and then search for point p from the K neighborhoods. kThe search point in the neighborhood with the highest number of detectable defects is selected. Update search baseline Return to step S4.3;

[0017] S4.8: Let the search step size L = λ × L, where λ represents the preset search step size scaling factor, λ∈(0,1), and return to step S4.3;

[0018] S4.9: Use the current test stimulus set E as the test stimulus set for the final analog circuit test.

[0019] This invention relates to a method for generating test stimuli for analog circuits based on a heuristic greedy algorithm. The method involves creating a defect simulation circuit by modeling defects in the analog circuit under test. Then, a search space is set according to the excitation sources of the analog circuit under test. This search space is divided into several sub-search spaces. The geometric center of each sub-search space is taken as the initial point. The starting point of the search is determined based on the number of detectable defects at each initial point. Finally, a heuristic greedy algorithm is used to search for test stimuli from the starting point, thereby obtaining the set of test stimuli required for the analog circuit.

[0020] The present invention has the following effects:

[0021] 1) This invention utilizes a greedy algorithm, always selecting the grid point that maximizes the heuristic function as the next search point, ensuring that each step of the algorithm moves towards the direction of triggering more defect exposure and improving defect coverage, thus enabling the algorithm to gradually approach the ideal test stimulus configuration, optimizing the search process, and enhancing the efficiency and accuracy of reliability verification of analog circuits.

[0022] 2) This invention can quickly and automatically provide test engineers with a test strategy that is both widely applicable and robust without the need for prior knowledge of the circuit, especially highlighting its rapid response and processing capabilities when facing the challenge of generating test vectors for large-scale analog circuits. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a specific implementation of the analog circuit test stimulus generation method based on a heuristic greedy algorithm according to the present invention.

[0024] Figure 2 This is an example diagram of a hard defect model for components as specified in IEEE P2427;

[0025] Figure 3 This is a schematic diagram of a two-dimensional search space;

[0026] Figure 4 yes Figure 3 The diagram shows the spatial division of the search space.

[0027] Figure 5This is a flowchart of the heuristic greedy algorithm for searching the test incentive set in this invention;

[0028] Figure 6 This is a flowchart of the test incentive optimization based on the Pareto genetic algorithm in this embodiment;

[0029] Figure 7 This is a structural diagram of the bandgap reference circuit in this embodiment;

[0030] Figure 8 This is a schematic diagram of the search space partitioning in this embodiment;

[0031] Figure 9 This is a schematic diagram showing the function values ​​of individuals in the initial population with respect to the two optimization objective functions and the current Pareto optimal solution in this embodiment;

[0032] Figure 10 This is a schematic diagram showing the function values ​​of individuals in the final generation of the population with respect to the two optimization objective functions and the current Pareto optimal solution in this embodiment. Detailed Implementation

[0033] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0034] To better illustrate the technical solution of the present invention, the technical principles of the present invention will be briefly explained first.

[0035] Heuristic greedy algorithms, as a simple and direct optimization strategy, are widely used in various optimization problems. The core idea of ​​this algorithm is to select only the optimal decision under the current state in each iteration, incorporate it into the solution, update the state of the solved portion of the problem, and then make another selection based on this, until a preset termination condition is reached. Through the accumulation of continuous locally optimal decisions, greedy algorithms can provide relatively good solutions to complex objective functions in a short time. By making locally optimal decisions to achieve a globally approximate optimal solution, they avoid the high computational complexity of directly searching for the global optimum.

[0036] 1) Design of heuristic functions

[0037] Assume there are K types of defects in the simulated circuit under test, and T measurement points are used to evaluate whether the circuit defects can be detected. Under each specific stimulus, the simulation software performs static analysis on the circuit under test, comparing the voltage differences at each measurement point when there are defects and when there are no defects. It is defined that when the voltage difference at measurement point j under the influence of defect k exceeds a threshold of 0.01V compared to the defect-free state, it can be determined that measurement point j can detect defect k under the current test stimulus, where k = 1, 2, ..., K, j = 1, 2, ..., T. The detection capability of measurement point j for defect k is quantified by the following formula, where a logic value of 0 indicates that defect k can be detected at measurement point j, and 1 indicates that it cannot be detected:

[0038]

[0039] In the formula, This represents the voltage value at measuring point j under defect condition k. This represents the voltage value at measurement point j when there are no defects.

[0040] To synthesize the detection capabilities of all measurement points for defect k under a specific excitation, the following formula is used to express whether defect k can be successfully detected by the set of measurement points under this excitation condition:

[0041]

[0042] Therefore, under the voltage excitation vector V, the number of detectable defects F(V) can be expressed by the following formula:

[0043]

[0044] The above formula is the heuristic function of the heuristic greedy algorithm of this invention. Its value directly reflects the number of detectable defects under the action of excitation V. The larger the value, the more defects can be detected by the excitation and the better the excitation performance.

[0045] Based on the above principles, this invention proposes a method for generating test stimuli for analog circuits based on a heuristic greedy algorithm. Figure 1 This is a flowchart illustrating a specific implementation of the analog circuit test stimulus generation method based on a heuristic greedy algorithm according to the present invention. Figure 1 As shown, the specific steps of the analog circuit test stimulus generation method based on heuristic greedy algorithm of the present invention include:

[0046] S101: Component Defect Modeling and Injection:

[0047] For the simulated circuit under test, all components in the circuit netlist are identified, defect models are established for all components except the power supply, and a defect list is generated. Each defect model is equivalently compressed and injected into the simulated circuit under test one by one to obtain the defect simulation circuit.

[0048] This approach simulates defects that may arise during actual manufacturing processes due to various defect mechanisms (such as additional metal deposition). This embodiment employs the defect model provided by the IEEE P2427 standard proposal. According to the definition in the IEEE P2427 draft standard, a defect is considered an unexpected, permanent change in a circuit element or its connection that is outside the component's manufacturing specifications. Defects in integrated circuits are generally classified into two categories: parametric defects and hard defects. Hard defects are typically caused by problems in the silicon manufacturing process, such as dust particles or insufficient etching, which can alter the topology of the manufactured circuit. Defect-oriented tests (DOTs) rely on using well-defined defect models to quantify defect coverage. While defect modeling in analog circuits is not yet as standardized as in digital circuits, the IEEE P2427 working group has proposed an emerging standard that addresses the standardization of hard defect modeling in analog circuits and power electronics. Figure 2 This is the component hard defect model information table specified in IEEE P2427. For example... Figure 2 As shown, two defect models are established for two-port components (resistors, capacitors, etc.): open circuit and short circuit. For three-port components (MOSFETs, transistors, etc.), six defect models are established: each of the three ports is open-circuited, and each pair of ports is short-circuited. The defect models can include open-circuit defects and short-circuit defects. In this embodiment, to improve simulation efficiency and avoid unnecessary computational overhead, short-circuit defects are not injected into components with the same number of ports.

[0049] In this embodiment, the specific method for defect injection is as follows: A Python script is used to generate an `.alter` declaration for each defect listed in the defect list. The goal is to simulate each transistor-level defect one by one and capture its impact on the circuit. `.alter` is a declaration in the SPICE language used to modify parameters. An open-circuit defect is injected by connecting an open model in series with a component port in the `.alter` declaration, or a short-circuit defect is injected by connecting a short model in parallel with a component port. The generated `.alter` declarations are then imported into the circuit netlist and simulated using HSPICE software, i.e., simulating a circuit with various defects and obtaining circuit performance parameters. By comparing the response of the defective circuit with the baseline response of the defect-free circuit, the defect detection results can be analyzed.

[0050] S102: Establish the search space:

[0051] Based on the number N of excitation sources of the analog circuit under test, an N-dimensional search space is established, and the search space is discretized according to the accuracy that the test excitation can achieve, so as to obtain the coordinates of each search grid point.

[0052] In the N-dimensional search space, each dimension represents an independent stimulus source, and its value range defines the boundary of that dimension. The entire space contains all possible combinations of stimulus sources, that is, all possible combinations of test stimuli. Furthermore, this N-dimensional search space can be divided into multiple small grids, and the intersection of each grid represents a specific set of stimulus source values. Figure 3 This is a schematic diagram of a two-dimensional search space. For example... Figure 3 As shown, when the circuit under test contains two excitation sources, a two-dimensional search space is constructed, where the x-axis and y-axis map the value ranges of the two excitation sources, respectively. Assuming this space is uniformly divided into several grids with a resolution of 0.1V, each coordinate point on the grid represents a specific combination of test excitations. This gridding strategy of discretizing a continuous space helps to systematically explore the excitation space, ensuring comprehensive test coverage and making the heuristic greedy search algorithm easier to implement. By traversing or selecting these grid points as test excitations, it is possible to try to find test excitations that can trigger as many potential defects in the circuit as possible. Considering that the resolution of voltage sources in practice is generally maintained at the level of 0.01V, this embodiment uses 0.01V as the benchmark unit for grid division, thereby ensuring accurate alignment between the model and the real test environment, while maintaining the accuracy of the analysis and practical feasibility.

[0053] S103: Determine the starting point of the search:

[0054] Since the specific DC excitation values ​​that can detect different defects vary, to ensure the comprehensiveness of the search process and effectively locate a set of excitations that maximizes the number of defects detected, this invention adopts a balanced exploration initialization strategy. That is, before formally searching for excitations, the search space is divided into D=2 equal parts. N This yields D sub-search spaces, with the geometric center of each sub-search space located at the search point where the two spaces begin. d d = 1, 2, ..., D, in the analog circuit, for each initial point start d Perform defect simulation and record each initial point (start). d Detectable defect set The initial point with the largest number of detectable defects is selected as the search starting point, `base`. This approach allows for a comprehensive search of the stimulus space while accelerating the approximation process to a local optimum, thereby improving overall testing efficiency and effectiveness.

[0055] Figure 4 yes Figure 3 The diagram shows the spatial partitioning of the search space. Figure 4As shown, when the circuit under test has two excitation sources, the search space is divided into four equal parts. The center of the four subspaces is taken as the initial point. Then, the set of detectable defects at the four initial points is simulated and recorded. Then, the one with the most detectable defects is selected as the starting point base for the subsequent search.

[0056] S104: Searching the test incentive set based on a heuristic greedy algorithm:

[0057] Next, the incentive space is iteratively searched using a heuristic greedy algorithm to obtain the test incentive set. Figure 5 This is a flowchart of the heuristic greedy algorithm for searching the test stimulus set in this invention. For example... Figure 5 As shown, the specific steps of the heuristic greedy algorithm for searching the test incentive set in this invention include:

[0058] S501: Initialize the cumulative set of detectable defects and the set of test stimuli.

[0059] Initialize the cumulative set of detectable defects Initialize the test stimulus set E = {start1, start2, ..., start D}

[0060] S502: Initialize the search step size L = L0, where L0 represents the preset initial value of the search step size.

[0061] In this embodiment, the initial search step size L0 is set to half the distance between adjacent initial points. By systematically traversing all grid points centered at the current point with a Euclidean distance of L, the system actively seeks directions that can induce more defect exposure.

[0062] S503: Obtain neighborhood search points:

[0063] K search grid points with a distance L from the search base point are sampled in the search space and used as neighborhood search points p. k k = 1, 2, ..., K, where K represents the preset number of sampling points. In this embodiment, K = 2N.

[0064] S504: Defect Simulation

[0065] For each neighborhood search point p in the analog circuit k Defect simulation is performed to obtain the corresponding set of detectable defects f. k , search the neighborhood point p k Add the test stimulus set E, that is, let E = E∪{p1,p2,…,p} K Let the cumulative set of detectable defects F′=F∪f1∪f2∪…∪f K .

[0066] S505: Determine whether the search termination condition has been met. If yes, proceed to step S509; otherwise, proceed to step S506.

[0067] The search termination condition can be set according to actual needs. Generally, it can be determined by whether the cumulative number of detectable defects exceeds a preset threshold. In this embodiment, the search termination condition is whether... || indicates calculating the number of detectable defects in the set. This indicates the preset threshold for the number of defects to be detected.

[0068] Furthermore, when the cumulative number of detectable defects converges and there are no neighboring search points in the current search base point whose number of detectable defects exceeds that of previously evaluated search grid points, this indicates that the marginal benefit of continuing exploration is diminishing, and can also be used as a criterion for stopping the current search cycle. This strategy ensures that the algorithm can focus on the most effective test-incentivized exploration path while avoiding ineffective searches, further improving solution efficiency and practical application value.

[0069] S506: Determine whether |F′|>|F|. If yes, proceed to step S507; otherwise, proceed to step S508.

[0070] S507: Update the cumulative set of detectable defects and search baseline:

[0071] Let the cumulative set of detectable defects be F = F′, and search for point p from the K neighborhoods. k The screening method with the highest number of detectable defects is |f k |Largest neighborhood search point Update search baseline Return to step S503.

[0072] S508: Let the search step size L = λ × L, where λ represents the preset search step size scaling factor, λ ∈ (0, 1), and return to step S503.

[0073] As can be seen, in this invention, if there is a grid point with a distance L containing more measurable defects than the current grid point, then that point is used as the center point for the next search; conversely, if no better point is found, the search step size L is shortened by a predetermined ratio. This process, through continuous range adjustment and iterative search, ensures that each step is based on maximizing the benefits of immediate detection, thereby steadily driving the overall test scheme towards a higher defect coverage rate. This not only ensures execution efficiency but also improves the performance of the obtained test stimulus set, providing strong support for the reliability verification of analog circuits.

[0074] S509: Determine the test stimulus set:

[0075] Use the current test stimulus set E as the test stimulus set for the final analog circuit test.

[0076] The test stimulus set obtained above covers all simulated stimuli in the search process. While this ensures comprehensive testing, it inevitably introduces a large number of redundant test stimuli. To more effectively control testing costs and improve testing efficiency, after the defect coverage of the test stimulus set reaches the expected target, the test stimuli need to be screened and optimized to achieve the highest possible defect detection rate with the fewest possible test stimuli. However, in reality, the goals of low testing cost and high testing performance are often conflicting, making it difficult to find an absolutely optimal solution that satisfies both simultaneously. In this case, the problem falls under the category of multi-objective optimization problems. Multi-objective optimization problems are widespread in engineering applications, and these problems typically involve multiple objectives. Specifically, the sub-objectives of multi-objective optimization problems often conflict with each other; that is, improving the performance of one sub-objective may come at the expense of a decrease in the performance of another. Therefore, in the traditional sense, there is no absolutely optimal solution that can simultaneously make all sub-objective functions optimal. In this context, the key to solving the problem lies in finding a compromise and coordination solution to achieve the optimal balance among the various sub-objective functions as much as possible. To address this challenge, the concept of Pareto optimal solutions was introduced into multi-objective optimization problems. Since multi-objective optimization problems typically have multiple Pareto optimal solutions, finding and determining the Pareto optimal solution set is crucial for solving multi-objective problems.

[0077] A multi-objective problem can be described as follows: Given a decision vector x = [x1, x2, ..., x...] N ] T Under the condition that Q inequality constraints g are satisfied q While (x)≤0, q=1,2…,Q, make M competing objective functions f m Simultaneously minimize (or maximize) (x), m=1,2,…,M:

[0078]

[0079] Because of conflicts between objective functions, it is usually difficult to find a solution that simultaneously optimizes all sub-objectives. Conversely, one solution may outperform another on some sub-objective functions but underperform on others. Such solutions, whose superiority is difficult to determine definitively in comparison, are called non-dominated solutions, and their specific definition is as follows:

[0080] Definition 1 If individual x 1 With individual x 2 Individual x is called a species if it meets the following conditions. 1 Dominant individual x 2 x 1 It is a non-dominated solution, and x2 This is the dominant solution.

[0081] a. For all sub-goals, x 1 Their performance was no worse than x 2 ,Right now Satisfy f m (x 1 )≤f m (x 2 ).

[0082] b. There exists at least one sub-objective, x 1 outperforms x 2 ,Right now Satisfying inequality f k (x 1 ) < f k (x 2 ).

[0083] Iterate through all individuals, comparing the current individual's dominance and non-dominance relationships with other individuals. If no individual is superior to the current individual, mark the current individual as non-dominant. Mark the dominance level of all non-dominant individuals as level 1. Ignore these already marked non-dominant individuals (i.e., they will not participate in the next round of comparison) and repeat the above steps to obtain level 2 non-dominant individuals. Continue in this manner until the entire population is stratified. This process is called fast non-dominant sorting. The first-level individuals obtained from fast non-dominant sorting are the desired Pareto optimal solution.

[0084] The core idea of ​​multi-objective optimization algorithms lies in continuously extracting non-dominated solutions from each generation of the population during the iteration process, thereby constructing the non-dominated solution set of the current population. As the iteration steps continue, the non-dominated solution set gradually approaches the desired optimal solution set, eventually converging towards the global optimum and reaching the optimal state.

[0085] Genetic Algorithm (GA) is a biological evolutionary process that simulates the natural selection and genetic mechanisms of Darwin's theory of evolution. It mainly achieves the evolution of species through selection and mutation. It is a metaheuristic algorithm with natural evolutionary characteristics, suitable for solving complex optimization problems. It is widely used in many fields such as optimization problems in data mining and rule extraction, path planning problems for mobile robots, scheduling problems, and task allocation problems.

[0086] Genetic algorithms begin with a population representing the potential solutions to a problem, consisting of a certain number of individuals encoded with genes. Each individual is essentially a chromosome-based entity with specific characteristics. Chromosomes, as the primary carriers of genetic material—a collection of genes—determine an individual's external appearance through a specific gene combination. For example, the characteristic of black hair is determined by a specific gene combination on the chromosome that controls this trait. Therefore, initially, a mapping from phenotype to genotype—encoding—is required. Since mimicking gene encoding is complex, simplification is often employed, such as binary encoding. After the initial population is generated, it evolves generation by generation according to the principles of survival of the fittest, producing increasingly better approximate solutions. In each generation, individuals are selected based on their fitness within the problem domain, and genetic operators from natural genetics are used for crossover and mutation to generate a new population representing the solution set. This process leads to a population where subsequent generations are more adapted to the environment than previous generations, much like natural evolution. The optimal individual in the final generation, after decoding, can serve as an approximate optimal solution to the problem.

[0087] Based on the above principles, this embodiment uses the Pareto genetic algorithm to further optimize the test incentive set E obtained by the heuristic greedy algorithm search, in order to find a series of Pareto optimal solutions, thereby providing a diverse set of choices, enabling it to make more reasonable decisions by balancing cost and performance according to actual conditions and needs. Figure 6 This is a flowchart illustrating the optimal test incentive based on the Pareto genetic algorithm in this embodiment. For example... Figure 6 As shown, the specific steps for test incentive optimization based on the Pareto genetic algorithm in this embodiment include:

[0088] S601: Define the optimization objective:

[0089] Determine the optimization objective for the test stimulus selection based on actual needs, denoted as M for the number of optimization objectives, and set the optimization objective function g for the test stimulus selection scheme. m (X), m = 1, 2, ..., M, the smaller the objective function value, the better the test plan. In this embodiment, there are two optimization objectives: the number of test stimulus vectors and the defect detection rate. The number of test stimulus vectors is related to the testing cost; generally, the larger the number of test stimulus vectors, the higher the testing cost. Therefore, it is necessary to minimize the number of test stimulus vectors. The objective function expression for optimizing the number of test stimulus vectors is:

[0090]

[0091] Where X = [x1, x2, ..., x D ] represents the test stimulus vector selection scheme, x d Let x be a binary variable.d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. d =1 indicates that the d-th test stimulus vector is selected in the test plan corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E.

[0092] Regarding defect detection rate, a higher defect detection rate allows for a better selection of test stimulus schemes. Therefore, the objective function expression for optimizing the defect detection rate is:

[0093] g2(X)=1-fdr(X)

[0094] Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme. Defect coverage equals the number of detectable defects divided by the total number of injected defects. all The calculation formula is as follows:

[0095]

[0096] Therefore, the multi-objective function expression in this embodiment is as follows:

[0097]

[0098] S602: Generate the initial population.

[0099] Generating the initial population is the first step in a genetic algorithm, and its quality directly affects the effectiveness of subsequent evolution. In practical applications, a random method is usually used to generate the initial population. In this embodiment, H individuals X are randomly generated. h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, where each individual represents a test stimulus vector selection scheme, x h,d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. h,d =1 indicates that the d-th test stimulus vector is selected in the test scheme corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E. The H randomly generated individuals form the initial population P.

[0100] S603: Set the iteration count t = 1.

[0101] S604: Generate a new population:

[0102] Select, crossover, and mutate individuals in population P to generate a new population Q.

[0103] Since each individual in this embodiment is a binary encoded vector, the classic single-point crossover method is used for individual crossover, and the classic single-point mutation method is used for individual mutation.

[0104] S605: Merging populations:

[0105] The populations P and Q are merged to obtain the population S = P∪Q.

[0106] S606: Individual selection based on Pareto optimality:

[0107] Calculate the M optimization objective function values ​​for each individual in population S. Determine the Pareto dominance relationship between any two individuals based on the optimization objective function values. Count the number of times each individual is dominated. Sort all individuals in ascending order of the number of times they are dominated. Select the top H individuals to form the preferred population P′.

[0108] S607: Determine if the iteration count t < t max , t max This indicates the preset maximum number of iterations. If so, proceed to step S608; otherwise, proceed to step S609.

[0109] S608: Let the iteration number t = t + 1, let the population P = P′, and return to step S604.

[0110] S109: Obtain the optimal solution for the test stimulus vector:

[0111] Non-dominated individuals in the preferred population P′ are selected based on Pareto dominance, and the test incentive vector selection schemes corresponding to these non-dominated individuals are considered as the preferred schemes. It is evident that by selecting non-dominated individuals, decision-makers are provided with the information needed to weigh multiple objectives.

[0112] To better illustrate the technical solution of this invention, a specific example is used to experimentally verify the invention. In this embodiment, the bandgap reference circuit provided by the IEEE P2427 working group is used to verify the feasibility of this invention. Figure 7 This is a structural diagram of the bandgap reference circuit in this embodiment. (See diagram below.) Figure 7 As shown, the Bandgap reference circuit contains a total of 102 components, including 43 three-terminal components and 59 two-terminal components. A detailed analysis of the test stimulus generation for the Bandgap reference circuit is performed using the Python scripting language and Hspice simulation software.

[0113] Based on the defect simulation framework described in the IEEE standard proposal, defect models were constructed for all components in the bandgap reference circuit. Open-circuit defects were simulated as a 1GΩ resistor in series with the defective terminal, while short-circuit defects were modeled as a 200Ω resistor in parallel between the defective terminals. There are 376 complete defects, which, after redundancy reduction, generate a total of 340 defects for the bandgap circuit.

[0114] The IEE bandgap reference circuit has three nominal 2.5V excitation sources, so the voltage range is limited to the [0, 2.5] interval. In this embodiment, 12 MOS transistor gate nodes and 1 output node are used, for a total of 13 nodes as measurement points.

[0115] The bandgap reference circuit has three voltage sources, therefore a three-dimensional test stimulus search space is established. In this embodiment, the space is divided into 2 equal parts. 3 =8 portions. Figure 8 This is a schematic diagram of the search space partitioning in this embodiment. For example... Figure 8 As shown, the geometric center point of each sub-search space is taken ( Figure 8 The black dot in the middle represents the initial point. Table 8 shows the coordinates of the initial point and the corresponding number of detectable defects in this embodiment. The detected defects are stored in the set detected_defect, at which point there are a total of 200 detectable defects. Table 1 is a comparison table of the number of detectable defects at the initial point in this embodiment.

[0116] initial point coordinates Number of detectable defects (pieces) (0.62,0.62,0.62) 29 (0.62,1.88,0.62) 29 (0.62,0.62,1.88) 29 (0.62,1.88,1.88) 29 (1.88,0.62,0.62) 188 (1.88,1.88,0.62) 188 (1.88,0.62,1.88) 36 (1.88,1.88,1.88) 36

[0117] Table 1

[0118] As shown in Table 1, (1.88, 0.62, 0.62) and (1.88, 1.88, 0.62) have the highest number of detectable defects. Therefore, this embodiment uses (1.88, 0.62, 0.62) as the search starting point to iteratively search the search space of the test stimulus. The first round of search is performed with an initial step size of 0.62V. Since this embodiment searches in three-dimensional space, six neighboring search points (up, down, left, right, front, and back) of the search base point are sampled in each search. Table 2 is a list of search point coordinates and the corresponding number of detectable defects in the first round of search in this embodiment.

[0119] Neighborhood search point Number of detectable defects (pieces) (1.25,0.62,0.62) 148 (1.88,0,0.62) 188 (1.88,0.62,0) 186 (1.88,0.62,1.25) 39 (1.88,1.25,0.62) 186 (2.5,0.62,0.62) 184

[0120] Table 2

[0121] After the first round of searching, a total of 218 detectable defects have been identified. However, since there are no points with more detectable defects among the adjacent coordinates (1.88, 0.62, 0.62), the step size is halved, i.e., a step size of 0.31V is used to continue the second round of searching for the adjacent coordinates (1.88, 0.62, 0.62). Table 3 is a list of search point coordinates and corresponding number of detectable defects during the first round of searching in this embodiment.

[0122] Neighborhood search point coordinates Number of detectable defects (pieces) (1.57,0.62,0.62) 192 (1.88,0.31,0.62) 188 (1.88,0.62,0.31) 187 (1.88,0.62,0.93) 50 (1.88,0.93,0.62) 188 (2.19,0.62,0.62) 185

[0123] Table 3

[0124] After the second round of search, a total of 221 detectable defects have been found. Among the adjacent coordinates of (1.88, 0.62, 0.62), the number of detectable defects is greater at (1.57, 0.62, 0.62). Therefore, (1.57, 0.62, 0.62) is chosen as the next search point, and the iterative search continues with a step size of 0.31V until the search termination condition is met.

[0125] Ultimately, after 19 minutes and searching 55 sets of stimuli, 339 defects were successfully detected, achieving a defect coverage rate of 99.71%. In fact, the algorithm achieved a 99.5% defect coverage rate after searching 21 stimuli in 8 minutes; subsequently, it took almost twice as long to further improve the coverage rate by 0.21%. Towards the end of defect detection, the remaining few defects are often difficult to trigger using conventional methods, requiring in-depth exploration of the vast stimulus space, which undoubtedly significantly reduces the efficiency and cost-effectiveness of the test. Therefore, appropriately relaxing the defect coverage threshold may be a more reasonable strategy, helping to save test generation time.

[0126] Of the 55 test stimuli generated, redundant tests are inevitable. To optimize the testing process, reduce testing costs, and improve overall testing efficiency, a Pareto genetic algorithm is used to select the best test stimuli.

[0127] In its implementation, a binary encoding method is used, where the length D of an individual gene is set to the total number of search stimuli, i.e., 55. The population size H is set to 100, and the maximum number of iterations t is... max The algorithm is set to 50 generations, with the mutation probability set to the reciprocal of the individual's gene length, i.e., 1 / 55. During the algorithm's initialization phase, the `rand` function is used to randomly generate 50 1×55 0 / 1 arrays, each array representing an individual and one possible test incentive selection scheme. Then, the two objective function values ​​for each individual are calculated. To compare the incentive vectors before and after optimization, all individuals in the initial population are first non-dominated sorted to obtain the function values ​​of the initial population individuals with respect to the two objective functions and the Pareto optimal solution for the current population. Figure 9 This diagram illustrates the function values ​​of individuals in the initial population of this embodiment with respect to the two objective functions and the current Pareto optimal solution. For example... Figure 9 As shown in the figure, the horizontal axis represents the number of test vectors selected by an individual, and the vertical axis represents the defect coverage that can be achieved by using all selected test vectors. From the Pareto optimal solution of the current population represented by the triangle points, it can be seen that in the current state, 99.71% defect coverage can be achieved using 18 stimuli.

[0128] The population was then evolved using a genetic algorithm, and after 50 rounds of selection, crossover, and mutation operations, the final generation population was obtained. Figure 10 This diagram illustrates the function values ​​of individuals in the final generation of the population with respect to the two objective functions and the current Pareto optimal solution in this embodiment. For example... Figure 10 As shown, all individuals in the final generation of the population have evolved to Pareto optimal states, ultimately yielding three Pareto optimal solutions: one covering 314 defects using one test stimulus (V1_V2_V3 = 1.65_0.54_0.31), and another covering 339 defects using two test stimuli (V1_V2_V3 = 1.65_0.54_0.31 and V1_V2_V3 = 1.65_0.54_0.39). These results provide test engineers with diverse test plan options, allowing them to flexibly adjust test strategies based on actual test cost budgets and expected test benefits.

[0129] After verifying the feasibility and effectiveness of the present invention, its performance was compared with that of traditional random methods, full-scan methods, and particle swarm optimization algorithms. Using the controlled variable method, the defect coverage achieved by the present invention and other comparative methods in the same timeframe was compared. Table 4 is a comparison table of the experimental results of the present invention and the comparative methods in this embodiment.

[0130] algorithm Simulation times Number of detectable defects Minimum Incentive Required This invention 55 339 3 Random generation method 55 286 11 Full scan method (step size 0.5V) 75 249 13 Particle Swarm Optimization 60 307 8

[0131] Table 4

[0132] As shown in Table 4, under the same test generation time, compared with the random generation method, the full scan method and the particle swarm algorithm, the defect coverage of the present invention is improved by 15.59%, 26.47% and 9.42% respectively, which further verifies the superior performance of the present invention in optimizing the test process and improving the test quality.

[0133] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for generating test stimuli for analog circuits based on a heuristic greedy algorithm, characterized in that, Includes the following steps: S1: For the simulation circuit under test, identify all components in the circuit netlist, establish defect models for all components except the power supply, generate a defect list, perform equivalent compression on each defect model, and inject them one by one into the simulation circuit under test to obtain the defect simulation circuit. S2: Based on the number N of excitation sources of the analog circuit under test, establish an N-dimensional search space, and discretize the search space according to the accuracy that the test excitation can achieve to obtain the coordinates of each search grid point; S3: Divide the search space into D=2 equal parts. N This yields D sub-search spaces, with the geometric center of each sub-search space located at the search grid point as the initial point (start). d d = 1, 2, ..., D, in the analog circuit, for each initial point start d Perform defect simulation and record each initial point (start). d Detectable defect set Choose the initial point with the largest number of detectable defects as the search starting point base; S4: Search the test incentive set based on a heuristic greedy algorithm. The specific method is as follows: S4.1: Initialize the cumulative set of detectable defects Initialize the test stimulus set E = {start1, start2, ..., start D }; S4.2: Initialize the search step size L = L0, where L0 represents the preset initial value of the search step size; S4.3: Sample K search grid points that are L distances from the search base point in the search space as neighborhood search points p. k k = 1, 2, ..., K, where K represents the preset number of sampling points; S4.4: Search for each neighborhood point p in the analog circuit. k Defect simulation is performed to obtain the corresponding set of detectable defects f. k , search the neighborhood point p k Add the test stimulus set E, and let the cumulative detectable defect set F′=F∪f1∪f2∪…∪f K ; S4.5: Determine whether the search termination condition has been met. If yes, proceed to step S4.9; otherwise, proceed to step S4.

6. S4.6: Determine whether |F′| > |F|, where |F′| represents the number of detectable defects in the set. If yes, proceed to step S4.7; otherwise, proceed to step S4.

8. S4.7: Let the cumulative set of detectable defects F = F′, and then search for point p from the K neighborhoods. k The search point p with the highest number of detectable defects is selected from the neighborhood search points. k * Update the search base point base = p k * Return to step S4.3; S4.8: Let the search step size L = λ × L, where λ represents the preset search step size scaling factor, λ∈(0,1), and return to step S4.3; S4.9: Use the current test stimulus set E as the test stimulus set for the final analog circuit test.

2. The analog circuit test stimulus generation method according to claim 1, characterized in that, In step S1, the defect model used is the defect model provided by the IEEE P2427 standard proposal.

3. The analog circuit test stimulus generation method according to claim 1, characterized in that, In step S4.2, the initial search step size L0 is set to half the distance between adjacent initial points.

4. The analog circuit test stimulus generation method according to claim 1, characterized in that, In step S4.5, the number of sampling points K = 2N.

5. The analog circuit test stimulus generation method according to claim 1, characterized in that, The search termination condition in step S4.5 is whether... | | represents the number of detectable defects in the set, and F represents the preset threshold for the number of detectable defects.

6. The analog circuit test stimulus generation method according to claim 1, characterized in that, In step S4.5, the search termination condition is whether the cumulative number of detectable defects converges and whether there are no neighboring search points in the neighborhood of the current search base point whose number of detectable defects exceeds the previously evaluated search grid points.

7. The analog circuit test stimulus generation method according to claim 1, characterized in that, Step S4.9 further includes optimizing the test incentives for the current test incentive set E based on the Pareto genetic algorithm. The specific method is as follows: S4.9.1: Determine the optimization objective for the test stimulus selection based on actual needs, denoted as M for the number of optimization objectives, and set the optimization objective function g for the test stimulus selection scheme. m (X), m=1,2,…,M, the smaller the value of the objective function, the better the test plan; S4.9.2: Randomly generate H individuals X h =[x h,1 ,x h,2 ,…,x h,D′ ], h = 1, 2, ..., H, where each individual represents a test stimulus vector selection scheme, x h,d′ =0 indicates that the d′-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. h,d′ =1 indicates that the d′-th test stimulus vector is selected in the test scheme corresponding to the individual, where d′ = 1, 2, ..., D′, and D′ represents the number of test stimulus vectors in the test stimulus set E; the H randomly generated individuals form the initial population P; S4.9.3: Set the iteration count t = 1; S4.9.4: Perform selection, crossover, and mutation operations on individuals in population P to generate a new population Q; S4.9.5: Merge population P and population Q to obtain population S = P∪Q; S4.9.6: Calculate the M optimization objective function values ​​corresponding to each individual in the population S, determine the Pareto dominance relationship between any two individuals based on the optimization objective function values, count the number of times each individual is dominated, sort all individuals in ascending order of the number of times they are dominated, and select the top H individuals to form the preferred population P′. S4.9.7: Determine if the iteration count t < t max , t max This indicates the preset maximum number of iterations. If so, proceed to step S4.9.8; otherwise, proceed to step S4.9.

9. S4.9.8: Let the iteration number t = t + 1, let the population P = P′, and return to step S4.9.4; S4.9.9: Select non-dominated individuals from the preferred population P′ based on the Pareto dominance relationship, and use the test incentive vector selection scheme corresponding to these non-dominated individuals as a preferred scheme.

8. The analog circuit test stimulus generation method according to claim 7, characterized in that, The optimization objective function in step S4.9.1 includes an optimization objective function for the number of test stimulus vectors and an optimization objective function for the defect detection rate. The expression for the optimization objective function for the number of test stimulus vectors is: Where X = [x1, x2, ..., x D′ ] represents the test stimulus vector selection scheme, x d′ Let x be a binary variable. d′ =0 indicates that the d′-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. d′ =1 indicates that the d′-th test stimulus vector is selected in the test plan corresponding to the individual, where d′ = 1, 2, ..., D′, and D′ represents the number of test stimulus vectors in the test stimulus set E; The objective function for optimizing the defect detection rate is expressed as follows: g2(X)=1-fdr(X) Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme.

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