Photomask, graphic element placing method, equipment and medium

Abstract

The invention provides a photomask, a graphic element placing method, equipment and a medium. The photomask comprises a main chip graphic area, an inner cutting channel area and an outer cutting channel area, the plurality of first overlay mark pattern groups are respectively placed on the outer cutting channel areas; the plurality of test element patterns are placed on the inner cutting channel area; the alignment mark pattern groups are placed on the inner cutting channel area; the plurality of second overlay mark pattern groups are placed on the inner cutting channel area; the first overlay mark pattern group comprises a plurality of overlay mark patterns, the second overlay mark pattern group comprises a plurality of overlay mark patterns, the alignment mark pattern group comprises a plurality of alignment mark patterns, and the type and the number of pattern units are set according to the requirements of a manufacturing process. According to the photomask, the graphic element placing method and device and the medium, a small space can be fully utilized for effective mark arrangement, and the space utilization rate of the whole design is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method, equipment and medium for placing a photomask and graphic elements. Background Art

[0002] In the process of integrated circuit manufacturing, as the complexity of products increases, multiple functional modules and components need to be formed on the wafer, which requires a high degree of alignment accuracy and pattern overlay accuracy between multiple film layers. For this reason, alignment marks and overlay marks, as well as test key patterns for process monitoring, are usually arranged during the design of the mask.

[0003] In current technology, if a platform product needs to share a common process flow, designers usually form a common version mark on the mask that includes all layers. As the number of layers required by the process increases, the length of the common version mark continues to increase. At the same time, its length and area requirements cause it to occupy a large amount of space on the scribe line, resulting in a lack of flexibility in the layout of the longer common version mark, and the inability to fully utilize the smaller space for effective mark layout, resulting in reduced space utilization of the entire design. Therefore, there is room for improvement. Summary of the invention

[0004] The object of the present invention is to provide a method, device and medium for placing masks and graphic elements, which can make full use of a small space for effective marking arrangement and improve the space utilization of the entire design.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a photomask, comprising: A plurality of main chip graphic areas, two adjacent main chip graphic areas are arranged in parallel; An inner cutting road area is formed between two adjacent main chip pattern areas; An outer cutting road area is formed at the periphery of the plurality of main chip pattern areas, and the shape of the outer cutting road area is a rectangle; A plurality of first set of engraved mark pattern groups are respectively placed on the outer cutting road area and located on the four sides of the rectangle; A plurality of test element patterns are placed on the inner cutting track area; A plurality of alignment mark graphic groups are placed on the inner cutting road area; and A plurality of second sets of engraved marking graphic groups are placed on the inner cutting track area; Among them, the first overlay mark graphic group includes multiple overlay mark graphics, the second overlay mark graphic group includes multiple overlay mark graphics, the alignment mark graphic group includes multiple alignment mark graphics, the overlay mark graphics, the alignment mark graphics, and the test element graphics are graphic units, and the type and quantity of the graphic units are set according to the process technology requirements.

[0006] In one embodiment of the present invention, the first set of engraved mark graphics group is located on one side of the end of the rectangle; the two opposite outer cutting road areas of the rectangle are divided into a first outer cutting road area and a second outer cutting road area, and the projection of the first set of engraved mark graphics group on the first outer cutting road area on the second outer cutting road area does not contact the first set of engraved mark graphics group on the second outer cutting road area.

[0007] In one embodiment of the present invention, the inner cutting street area is a single cutting street area.

[0008] In one embodiment of the present invention, the inner cutting road area includes: A first inner cutting track area is used to place the test element pattern; and A second inner cutting track area is used to place the alignment mark pattern group and the second set engraving mark pattern group; The priority of placing the graphic unit in the first inner cutting lane area is greater than the priority of placing the graphic unit in the second inner cutting lane area.

[0009] In one embodiment of the present invention, on the same first inner cutting street area, a plurality of the test element patterns are placed in sequence, and a distance between two adjacent test element patterns is greater than or equal to 5 um.

[0010] In one embodiment of the present invention, a plurality of the alignment mark pattern groups and / or the second overlay mark pattern groups are placed in sequence on the same second inner cutting street area.

[0011] In one embodiment of the present invention, when the remaining space in the second inner cutting zone is insufficient to accommodate the alignment mark graphic group or the second engraving mark graphic group, part of the alignment mark graphic group or part of the second engraving mark graphic group is placed in the remaining space in the second inner cutting zone, and the other remaining alignment mark graphic group or other remaining second engraving mark graphic group is placed in the remaining space in the first inner cutting zone and / or between two adjacent test element graphics.

[0012] The present invention also discloses a method for placing graphic elements of a photomask, comprising: Obtain corresponding graphics units of different types and quantities according to process technology requirements; Combining the graphic units of different types and quantities to form a plurality of first overlay mark graphic groups, a plurality of second overlay mark graphic groups, a plurality of alignment mark graphic groups, and a plurality of test element graphics, wherein the first overlay mark graphic group includes a plurality of overlay mark graphics, the second overlay mark graphic group includes a plurality of overlay mark graphics, and the alignment mark graphic group includes a plurality of alignment mark graphics; Placing multiple sets of the first set of engraved mark pattern groups on the outer cutting road area outside the plurality of main chip pattern areas, wherein the outer cutting road area is in a rectangular shape, and the multiple sets of the first set of engraved mark pattern groups are respectively located on the four sides of the rectangle; A plurality of the test element patterns, a plurality of the second set engraving mark pattern groups, and a plurality of the alignment mark pattern groups are placed on an inner cutting path area formed between two adjacent main chip pattern areas.

[0013] The present invention also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for placing the graphic elements of the mask are implemented.

[0014] The present invention also discloses a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method for placing the graphic elements of the mask are realized.

[0015] As described above, the present invention provides a method, device and medium for placing masks and graphic elements, which significantly reduces the length of a single overlay mark graphic group or alignment mark graphic group by dividing the alignment mark graphic and the overlay mark graphic into independent units according to process requirements and only combining the layers of the mask required by the current process technology.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of a photomask according to an embodiment of the present invention; Figure 2 is a flow chart of a method for placing graphic elements of a mask in one embodiment of the present invention; Figure 3 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0019] In the figure: 10, main chip graphic area; 20, inner cutting track area; 30, outer cutting track area; 40, test element graphic; 50, first set of engraved mark graphic group; 60, second set of engraved mark graphic group; 70, alignment mark graphic group; 1, electronic device; 12, memory; 13, processor. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 The present invention provides a photomask, which can rearrange the graphic units, thereby increasing the chip output by increasing the use area of ​​the chip on the wafer. The photomask can include a main chip graphic area 10, an inner cutting road area 20, an outer cutting road area 30, a test element graphic 40, a first set of engraved mark graphic groups 50, a second set of engraved mark graphic groups 60, and an alignment mark graphic group 70.

[0022] See also Figure 1 In one embodiment, the main chip graphic area 10 refers to an area on the mask specifically used to contain chip design patterns. The main chip graphic area 10 contains the detailed layout of the circuit, including transistors, connecting lines, components, etc., and is directly drawn according to the designed circuit. The specific shape of the main chip graphic area 10 may not be limited. For example, in this embodiment, the shape of the main chip graphic area 10 is rectangular, and two adjacent main chip graphic areas 10 may be parallel to each other to optimize space utilization so that more chips can be formed on a limited wafer area.

[0023] See also Figure 1 In one embodiment, the inner cutting road area 20 can be formed between two adjacent main chip graphic areas 10. The inner cutting road area 20 refers to an elongated area on the wafer used to cut a single main chip graphic area 10, so that each main chip graphic area 10 can be finally separated independently. Among them, the inner cutting road area 20 can be a single cutting road, and the width of the single cutting road is generally controlled to a minimum to ensure effective segmentation without wasting space. In this embodiment, the inner cutting road area 20 is designed as a single cutting road. By reducing the width or number of the cutting roads, more wafer space can be released for the actual chip production, and more chips can be arranged on the same wafer area.

[0024] See also Figure 1In one embodiment, the outer cutting area 30 can be located at the periphery of the entire main chip pattern area 10 array. The outer cutting area 30 can be used to separate the chips at the wafer boundary. The outer cutting area 30 can ensure that the peripheral chips will not be damaged or incomplete when cutting. Since the chip layout on the wafer will present a rectangular arrangement. Therefore, the overall shape of the outer cutting area 30 can also be rectangular.

[0025] In one embodiment, in the semiconductor manufacturing process, the precise design of graphic units is crucial to ensure chip functions and performance. The types of graphic units may include contact area graphics (Contact), active area graphics (ActiveArea), gate area graphics (Gate / Poly), metal layer graphics (Metal), channel graphics (Via) and test element graphics (Test Key), etc.

[0026] See also Figure 1 In one embodiment, when placing graphic units on the inner cutting lane area 20 and the outer cutting lane area 30, an overlay mark graphic may be placed preferentially on the outer cutting lane area 30. The overlay mark graphic may be used as a mark to improve alignment accuracy, by precisely defining the position of one layer relative to another layer, so as to accurately superimpose patterns in different process steps and ensure accurate alignment. The overlay mark graphic may be selected from the above-mentioned graphic units.

[0027] In one embodiment, different types, quantities, and arrangements of overlay mark patterns may be required for different process technologies. For example, a high-precision node may require a more complex mark configuration. For different process technologies, the corresponding overlay mark patterns may be selected and then combined and arranged. After selecting the overlay mark patterns, the overlay mark patterns may be arranged in order to form a first overlay mark pattern group 50.

[0028] In one embodiment, the type, quantity, and arrangement of the overlay mark patterns included in the first overlay mark pattern group 50 can be set according to different process technologies. For example, the first overlay mark pattern group 50 can include a first contact area pattern, a first active area pattern, a first gate area pattern, a metal layer pattern, a channel pattern, a second contact area pattern, a second active area pattern, etc. arranged in sequence. For another example, the first overlay mark pattern group 50 can include a first gate area pattern, a metal layer pattern, a channel pattern, a contact area pattern, an active area pattern, a second gate area pattern, etc. arranged in sequence.

[0029] In one embodiment, the number of the first set of engraved mark pattern groups 50 may be multiple groups, for example, four groups. Since the overall shape of the outer cutting lane area 30 is a rectangle, at least one set of the first set of engraved mark pattern groups 50 may be placed on each side of the rectangle. Through this placement, a multi-directional alignment reference can be provided to effectively compensate for alignment errors caused by equipment deviation or wafer warpage.

[0030] In one embodiment, the first set of engraved mark pattern group 50 can be located on one side of the end of the rectangle. By preferentially placing the first set of engraved mark pattern group 50 at the four ends of the rectangle, the position of the end helps to form a comprehensive reference system to ensure that reliable alignment guidance can be provided during the overall exposure process. Specifically, different layers (such as the layers corresponding to the active area pattern) need to be accurately aligned. The first set of engraved mark pattern group 50 can provide a reference so that the upper and lower layers of graphic elements can form a complete structure.

[0031] In one embodiment, the two opposite outer cutting lanes of the rectangle can be divided into a first outer cutting lane area and a second outer cutting lane area. For example, in the length direction of the main chip graphic area 10, the two opposite outer cutting lanes of the rectangle can be divided into a first outer cutting lane area and a second outer cutting lane area. For another example, in the width direction of the main chip graphic area 10, the two opposite outer cutting lanes of the rectangle can be divided into a first outer cutting lane area and a second outer cutting lane area. At this time, since the first set of engraved mark graphic group 50 needs to be placed on both the first outer cutting lane area and the second outer cutting lane area, in order to ensure the uniqueness and consistency of the position of the first set of engraved mark graphic group 50, so as to avoid interference and overlap between the mark groups, therefore, the projection of the first set of engraved mark graphic group 50 on the first outer cutting lane area on the second outer cutting lane area and the first set of engraved mark graphic group 50 on the second outer cutting lane area need to be set to be non-contacting.

[0032] See also Figure 1 In one embodiment, the inner cutting zone 20 can be divided into two parts, namely, a first inner cutting zone and a second inner cutting zone, each part having different uses and functions. The priority of placing the graphic unit in the first inner cutting zone is greater than the priority of placing the graphic unit in the second inner cutting zone.

[0033] In one embodiment, after placing the first set of engraved mark pattern groups 50 in the outer cutting street area 30, the test component pattern 40 can be placed in the first inner cutting street area. The test component pattern 40 can be used to test various electrical and physical properties during the production process to ensure that the manufactured chip meets the design requirements. The type and number of the test component pattern 40 can be set according to different process technology requirements.

[0034] In one embodiment, in the same first inner cutting area, multiple test element graphics 40 need to be placed in sequence. The spacing between two adjacent test element graphics 40 must be greater than or equal to 5 microns (um) to avoid interference between adjacent components and ensure the accuracy of the test. In each first inner cutting area, the number of test element graphics 40 that need to be placed can be unlimited, for example, it can be 7 to 8, and the specific number can be set based on process design and test requirements. For all first inner cutting areas, at least 40 test element graphics 40 need to be placed, that is, the design of the entire wafer needs to reach at least 40 in total in all test element graphics 40 distributed in multiple first inner cutting areas, so as to ensure sufficient test coverage and data sampling to evaluate production quality.

[0035] In one embodiment, after the test element pattern 40 is placed in the first inner cutting street area, the alignment mark pattern group 70 and the second set of engraving mark pattern group 60 can be placed in the second inner cutting street area. The priority order of the alignment mark pattern group 70 and the second set of engraving mark pattern group 60 can be unlimited, and the priorities of the two can be the same or different, which is not limited here.

[0036] In one embodiment, the second overlay mark graphic group 60 can be used as an overlay mark for alignment and precision monitoring between layers in a multi-layer manufacturing process. The number of the second overlay mark graphic group 60 can be multiple groups, for example, four groups. The second overlay mark graphic group 60 can include multiple overlay mark graphics. Overlay mark graphics. The overlay mark graphics can be selected from the above-mentioned graphic units. For different process technologies, overlay mark graphics of different types, quantities and arrangements may be required. For different process technologies, the corresponding required overlay mark graphics can be selected and combined and placed. After selecting the overlay mark graphics, the overlay mark graphics can be arranged in sequence to form a group of second overlay mark graphic groups 60. Among them, the type, quantity and placement order of the overlay mark graphics included in the first overlay mark graphic group 50 and the second overlay mark graphic group 60 can be the same.

[0037] In one embodiment, the alignment mark graphic group 70 can be used for alignment in the process steps to ensure precise alignment between different manufacturing steps. The alignment mark graphic group 70 may include multiple alignment mark graphics. The alignment mark graphics can be selected from the above-mentioned graphic units. For different process technologies, different types, quantities and arrangements of alignment mark graphics may be required. For different process technologies, the corresponding required alignment mark graphics can be selected and combined and placed. After selecting the alignment mark graphics, the alignment mark graphics can be arranged in sequence to form a group of alignment mark graphic groups 70.

[0038] In one embodiment, the number of the alignment mark pattern groups 70 is multiple, for example, four. The number of the second set of engraved mark pattern groups 60 is at least 4. In the same second inner cutting lane area, multiple alignment mark pattern groups 70 and / or multiple second set of engraved mark pattern groups 60 can be arranged sequentially or alternately to ensure different levels of alignment accuracy during the production process.

[0039] In one embodiment, after all the second inner cutting road areas are filled with the alignment mark pattern group 70 and / or the second set of engraved mark pattern group 60, there is still a certain amount of remaining space for some second inner cutting road areas, but due to space limitations, this part of the remaining space cannot be filled with the entire alignment mark pattern group 70 or the second set of engraved mark pattern group 60. Therefore, when the space of the second inner cutting road area is not enough to completely accommodate the entire alignment mark pattern group 70 or the second set of engraved mark pattern group 60, a partial layout strategy can be adopted, that is, part of the alignment mark pattern group 70 or part of the second set of engraved mark pattern group 60 can be placed in the above-mentioned remaining space, and all available space in the second inner cutting road area is used as much as possible. For other remaining alignment mark pattern groups 70 or second set of engraved mark pattern groups 60, they also need to be placed. At this time, other remaining alignment mark pattern groups 70 or second set of engraved mark pattern groups 60 can be placed in the remaining space of the first inner cutting road area and / or the space between two adjacent test element patterns 40. By distributing the alignment mark pattern group 70 and the mark pattern groups in the second engraved mark pattern group 60 in different areas and utilizing the gaps between adjacent test element patterns 40 , every available tiny space can be utilized to the maximum extent.

[0040] It can be seen that in the above scheme, the unexpected effect of the present invention is: by dividing the alignment mark graphics and the overlay mark graphics into independent units according to the process requirements, and only combining the layers of the mask required by the current process technology, the length of a single overlay mark graphic group or an alignment mark graphic group is significantly reduced. Since the overlay mark graphic group or the alignment mark graphic group can be placed in sections and flexibly, this reduces the waste of space caused by the overlay mark graphic group or the alignment mark graphic group being too long to be placed, allowing more efficient use of the area within the limited cutting path space. By freely combining and arranging the overlay mark graphic group or the alignment mark graphic group, the area of ​​the cutting path is reduced, the effective chip area is increased, and the chip usage area on the wafer is increased. Without increasing the wafer size, by optimizing the layout of the overlay mark graphic group or the alignment mark graphic group, the chip area is increased and the number of chips on each wafer is increased, the cost of a single chip is reduced, and the overall production efficiency is improved. Since products that originally required double or multiple cutting lanes can now be processed using a single cutting lane, this further increases the effective utilization area of ​​the wafer and improves process simplicity and process flexibility.

[0041] See also Figure 2 The present invention also provides a method for placing graphic elements of a mask, which can be applied to the above-mentioned mask to place the graphic elements. The placement method can include the following steps: Step S10, obtaining corresponding graphics units of different types and quantities according to process technology requirements; Step S20, combining different types and quantities of pattern units to form a plurality of first set mark pattern groups, a plurality of second set mark pattern groups, a plurality of alignment mark pattern groups, and a plurality of test element patterns, wherein the first set mark pattern group includes a plurality of set mark patterns, the second set mark pattern group includes a plurality of set mark patterns, and the alignment mark pattern group includes a plurality of alignment mark patterns; Step S30, placing the plurality of first set engraved mark pattern groups on the outer cutting street areas outside the plurality of main chip pattern areas, the outer cutting street areas are in the shape of a rectangle, and the plurality of first set engraved mark pattern groups are respectively located on the four sides of the rectangle; Step S40, placing a plurality of test element patterns, a plurality of second set engraving mark pattern groups, and a plurality of alignment mark pattern groups on an inner cutting street area formed between two adjacent main chip pattern areas.

[0042] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0043] See also Figure 3 In one embodiment, the electronic device 1 may include a memory 12, a processor 13 and a bus, and may also include a computer program stored in the memory 12 and executable on the processor 13, such as a battery health status test program.

[0044] In one embodiment, the memory 12 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 12 may be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 12 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 12 may also include both an internal storage unit of the electronic device 1 and an external storage device. The memory 12 may not only be used to store application software and various types of data installed in the electronic device 1, such as the code for placing the graphic elements of the mask, etc., but may also be used to temporarily store data that has been output or is to be output.

[0045] In one embodiment, the processor 13 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips. The processor 13 is the control core (ControlUnit) of the electronic device 1, and uses various interfaces and lines to connect various components of the entire electronic device 1, and executes or executes programs or modules stored in the memory 12 (such as the placement program of the graphic elements of the mask, etc.), and calls the data stored in the memory 12 to execute various functions of the electronic device 1 and process data.

[0046] In one embodiment, the processor 13 executes the operating system and various installed application programs of the electronic device 1. The processor 13 executes the application programs to implement the steps in the above-mentioned method for placing graphic elements of the mask.

[0047] In one embodiment, the computer program may be divided into one or more modules, one or more modules are stored in the memory 12, and executed by the processor 13 to complete the present application. One or more modules may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device 1.

[0048] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A photomask, characterized in that: include: A plurality of main chip graphic areas, two adjacent main chip graphic areas are arranged in parallel; An inner cutting road area is formed between two adjacent main chip pattern areas; An outer cutting road area is formed at the periphery of the plurality of main chip pattern areas, and the shape of the outer cutting road area is a rectangle; A plurality of first set of engraved mark pattern groups are respectively placed on the outer cutting road area and located on the four sides of the rectangle; A plurality of test element patterns are placed on the inner cutting track area; A plurality of alignment mark graphic groups are placed on the inner cutting track area; as well as A plurality of second sets of engraved marking graphic groups are placed on the inner cutting track area; Among them, the first overlay mark graphic group includes multiple overlay mark graphics, the second overlay mark graphic group includes multiple overlay mark graphics, the alignment mark graphic group includes multiple alignment mark graphics, the overlay mark graphics, the alignment mark graphics, and the test element graphics are graphic units, and the type and quantity of the graphic units are set according to the process technology requirements.

2. The photomask according to claim 1, wherein: The first set of engraved mark graphics group is located on one side of the end of the rectangle; the two opposite outer cutting lane areas of the rectangle are divided into a first outer cutting lane area and a second outer cutting lane area, and the projection of the first set of engraved mark graphics group on the first outer cutting lane area on the second outer cutting lane area does not contact the first set of engraved mark graphics group on the second outer cutting lane area.

3. The photomask according to claim 1, wherein: The inner cutting street area is a single cutting street area.

4. The photomask according to claim 1, wherein: The inner cutting zone comprises: A first inner cutting track area is used to place the test element pattern; and A second inner cutting track area is used to place the alignment mark pattern group and the second set engraving mark pattern group; The priority of placing the graphic unit in the first inner cutting lane area is greater than the priority of placing the graphic unit in the second inner cutting lane area.

5. The photomask according to claim 4, wherein: On the same first inner cutting road area, a plurality of the test element patterns are placed in sequence, and a distance between two adjacent test element patterns is greater than or equal to 5 um.

6. The photomask according to claim 4, wherein: On the same second inner cutting track area, a plurality of the alignment mark pattern groups and / or the second overlay mark pattern groups are placed in sequence.

7. The photomask according to claim 6, wherein: When the remaining space in the second inner cutting zone is insufficient to accommodate the alignment mark graphic group or the second engraving mark graphic group, part of the alignment mark graphic group or part of the second engraving mark graphic group is placed in the remaining space in the second inner cutting zone, and the other remaining alignment mark graphic group or other remaining second engraving mark graphic group is placed in the remaining space in the first inner cutting zone and / or between two adjacent test element graphics.

8. A method for placing graphic elements of a photomask, characterized in that: include: Obtain corresponding graphics units of different types and quantities according to process technology requirements; Combining the graphic units of different types and quantities to form a plurality of first overlay mark graphic groups, a plurality of second overlay mark graphic groups, a plurality of alignment mark graphic groups, and a plurality of test element graphics, wherein the first overlay mark graphic group includes a plurality of overlay mark graphics, the second overlay mark graphic group includes a plurality of overlay mark graphics, and the alignment mark graphic group includes a plurality of alignment mark graphics; Placing multiple sets of the first set of engraved mark pattern groups on the outer cutting road area outside the plurality of main chip pattern areas, wherein the outer cutting road area is in a rectangular shape, and the multiple sets of the first set of engraved mark pattern groups are respectively located on the four sides of the rectangle; A plurality of the test element patterns, a plurality of the second set engraving mark pattern groups, and a plurality of the alignment mark pattern groups are placed on an inner cutting street area formed between two adjacent main chip pattern areas.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for placing the graphic elements of the mask as claimed in claim 8 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for placing graphic elements of a mask as claimed in claim 8 are implemented.

Images