Correction circuit for bandgap circuit

Abstract

The embodiment of the invention relates to a correction circuit for a bandgap circuit. The present specification relates to a correction circuit for a bandgap circuit, the bandgap circuit comprising a first bipolar transistor and a second bipolar transistor, the bandgap circuit configured to deliver a temperature-stable DC voltage based on the first bipolar transistor and the second bipolar transistor, the correction circuit configured to: generate a correction current, the correction current is equal to a difference between a base current of the first transistor and a base current of the second transistor, and is injected onto an emitter of one of the first bipolar transistor and the second bipolar transistor. The first bipolar transistor and the second bipolar transistor are coupled to each other to correct an error with respect to a temperature-stable voltage caused by a current gain difference between the first bipolar transistor and the second bipolar transistor.

Description

[0001] This application claims the benefit of priority to French patent application No. 23 / 10175, filed on September 26, 2023, entitled “Circuit de correction pour circuit à bande interdite”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0002] The present disclosure relates generally to electronic circuits, such as integrated circuits, and more particularly to bandgap electronic circuits for generating temperature-stabilized DC ("direct current") voltages and electronic devices including such bandgap electronic circuits. Background Art

[0003] A known bandgap circuit comprises at least two bipolar transistors which receive equal currents at their respective collectors. The two bipolar transistors are of the same type, for example NPN, and their bases are interconnected. Furthermore, one of the two bipolar transistors is P times larger than the other, P being a positive number greater than 1, that is, for example, the dimensions of the collector, emitter and base regions of this bipolar transistor are P times larger than the dimensions of the collector, emitter and base regions of the other bipolar transistor. For example, a transistor that is P times larger than the other transistor corresponds to placing P transistors in parallel, each transistor being identical to a transistor that is P times smaller than the other transistor.

[0004] The difference between the base-emitter voltages of the two transistors, i.e. a voltage equal to the base-emitter voltage of the smallest of the two transistors minus the base-emitter voltage of the largest of the two transistors, is of the PTAT (“proportional to absolute temperature”) type.

[0005] Since the base-emitter voltage of the bipolar transistors is additionally of the CTAT (“complementary to absolute temperature”) type, by appropriately dimensioning the bandgap circuit, a temperature-stabilized voltage can be obtained based on the base-emitter voltage difference of the two bipolar transistors and the base-emitter voltage of one of the two bipolar transistors or the base-emitter voltage of the other bipolar transistor of the bandgap circuit.

[0006] However, known bandgap circuits suffer from various disadvantages which would be advantageous to overcome. Summary of the invention

[0007] There is a use for overcoming all or part of the disadvantages of known electronic bandgap circuits and of known devices comprising known bandgap circuits for generating a temperature-stabilized voltage or reference voltage.

[0008] For example, in bandgap circuits of the type described above, such as those implemented in FinFet technology, the value of the temperature-stabilized voltage delivered by the bandgap circuit may differ from the theoretical value for which the bandgap circuit has been sized.

[0009] One embodiment overcomes all or some of the disadvantages of known electronic bandgap circuits and all or some of the disadvantages of known devices including known bandgap circuits for generating a temperature-stabilized voltage.

[0010] For example, one embodiment overcomes all or some of the disadvantages of known electronic bandgap circuits by utilizing the base-emitter voltage difference of a bipolar transistor (eg, NPN type) implemented, for example, in FinFet technology.

[0011] One embodiment provides a correction circuit for a bandgap circuit, the bandgap circuit including a first bipolar transistor and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stabilized DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor, the correction circuit being configured to:

[0012] generating a correction current equal to a difference between a base current of one of the first transistor and the second transistor and a base current of the other of the two transistors; and

[0013] A correction current is injected into an emitter of one of the first and second bipolar transistors to correct an error with respect to a value of a temperature-stabilized voltage caused by a current gain difference between the first and second bipolar transistors.

[0014] Another embodiment provides an apparatus for generating a temperature-stabilized DC voltage, the apparatus comprising:

[0015] a bandgap circuit comprising a first bipolar transistor and a second bipolar transistor and configured to deliver a temperature-stabilized DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and

[0016] Correction circuit as described above.

[0017] According to one embodiment:

[0018] The first bipolar transistor has a smaller size than the second bipolar transistor;

[0019] Bases of the first bipolar transistor and the second bipolar transistor are connected together, and emitters of the first bipolar transistor and the second bipolar transistor are coupled to a first node to which a reference potential is applied; and

[0020] The bandgap circuit includes:

[0021] a first MOS transistor having a source connected to a second node configured to receive a supply potential and a drain coupled, preferably connected, to the collector of the first bipolar transistor, and

[0022] a second MOS transistor, which is identical to the first MOS transistor and has a source, a drain, and a gate, the source being connected to the second node, the drain being coupled, preferably connected, to the collector of the second bipolar transistor, and the gate being connected to the gate of the first MOS transistor, the first MOS transistor and the second MOS transistor being configured to deliver a first current to the first bipolar transistor and to deliver a second current equal to the first current to the second bipolar transistor.

[0023] According to one embodiment, a bandgap circuit comprises:

[0024] a first resistor connected between an emitter of the first bipolar transistor and an emitter of the second bipolar transistor; and

[0025] A second resistor is connected between the emitter of the first bipolar transistor and the first node.

[0026] According to one embodiment, a bandgap circuit comprises:

[0027] a first resistor connected between an emitter of the first bipolar transistor and a first node;

[0028] a second resistor connected between an emitter of the second bipolar transistor and the first node;

[0029] an additional bipolar transistor having a collector connected to the second node;

[0030] an additional MOS transistor having a drain connected to the base of the additional bipolar transistor and coupled to the second node through a current source, a gate connected to the collector of the second bipolar transistor, and a source connected to the first node;

[0031] a capacitive element coupling a drain and a gate of the additional MOS transistor; and

[0032] A third resistor is connected between an emitter of the second bipolar transistor and an emitter of the additional bipolar transistor.

[0033] According to one embodiment, the correction circuit is configured to inject a correction current at a node connecting the first resistor to the first bipolar transistor.

[0034] According to one embodiment, the correction circuit comprises:

[0035] a third MOS transistor and a third bipolar transistor, the third MOS transistor and the third bipolar transistor being connected in series between the first node and the second node;

[0036] A fourth MOS transistor and a fourth bipolar transistor, the fourth MOS transistor and the fourth bipolar transistor are connected in series between the first node and the second node;

[0037] a sixth MOS transistor having a gate connected to a node connecting the third MOS transistor to the third bipolar transistor, a source connected to a base of the third bipolar transistor, and a drain connected to the third node;

[0038] a seventh MOS transistor having a gate connected to a node connecting the fourth MOS transistor to the fourth bipolar transistor, a source connected to a base of the fourth bipolar transistor, and a drain connected to the fourth node;

[0039] a current mirror having a MOS transistor coupling the third node and the fourth node; and

[0040] A voltage source couples the third node or the fourth node to an output of the correction circuit, the output of the correction circuit being configured to deliver a correction current.

[0041] According to one embodiment:

[0042] The third MOS transistor is the same as the first MOS transistor;

[0043] The third bipolar transistor is the same as the first bipolar transistor;

[0044] The fourth MOS transistor is the same as the second MOS transistor;

[0045] The fourth bipolar transistor is identical to the second bipolar transistor; and

[0046] The current ratio of the current mirror is equal to 1.

[0047] According to one embodiment:

[0048] The third MOS transistor is the same as the first MOS transistor;

[0049] The third bipolar transistor is the same as the first bipolar transistor;

[0050] The fourth MOS transistor is N times smaller than the second MOS transistor, where N is a number greater than 1, such as 2;

[0051] The fourth bipolar transistor is N times smaller than the second bipolar transistor; and

[0052] The current mirror includes two MOS transistors, and a size ratio between the two MOS transistors is N.

[0053] According to one embodiment:

[0054] a voltage source coupling the third node to the output; and

[0055] The current mirror is configured to supply a current determined by a base current of the fourth bipolar transistor to the third node.

[0056] According to one embodiment, the output of the correction circuit is connected to the emitter of the first bipolar transistor.

[0057] According to one embodiment, the first bipolar transistor and the second bipolar transistor are of NPN type.

[0058] According to one embodiment, the transistor is implemented in FinFet technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0060] Figure 1 An example of a bandgap circuit is illustrated;

[0061] Figure 2 Another example of a bandgap circuit is illustrated;

[0062] Figure 3 Shown include Figure 1 Embodiments of electronic devices and embodiments of correction circuits for bandgap circuits;

[0063] Figure 4 Shows Figure 3 An embodiment of a correction circuit; and

[0064] Figure 5 Shown include Figure 2 Embodiments of electronic devices and embodiments of correction circuits for bandgap circuits. DETAILED DESCRIPTION

[0065] In the various figures, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, size, and material properties.

[0066] For the sake of clarity, only the steps and elements that are helpful for understanding the described embodiments are detailed and described. In particular, general applications and electronic systems, such as power-on reset (POR) electronic systems, in which a bandgap circuit or a reference voltage generating device including a bandgap circuit can be provided, which are compatible with the described embodiments and variants, are not described in detail.

[0067] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or may be coupled via one or more other elements.

[0068] In the following description, when referring to terms defining absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or terms defining relative positions, such as terms “above”, “below”, “upper”, “lower”, etc., or referring to terms defining directions, such as terms “horizontal”, “vertical”, etc., unless otherwise specified, they refer to the orientation of the drawings.

[0069] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0070] Figure 1 An example of a bandgap circuit 1 is illustrated.

[0071] Circuit 1 includes two bipolar transistors Q1 and Q2. Circuit 1 is configured to deliver a temperature-stable DC voltage Vref, i.e., a voltage Vref having a constant value that is independent of temperature. More specifically, circuit 1 is configured to generate voltage Vref based on a voltage difference DVbe between base-emitter voltages Vbe1 and Vbe2 of transistors Q1 and Q2. More specifically, voltage DVbe is equal to base-emitter voltage Vbe1 of transistor Q1 minus base-emitter voltage Vbe2 of transistor Q2 (DVbe=Vbe1–Vbe2).

[0072] Transistors Q1 and Q2 are, for example, of NPN type. Transistor Q2 is P times larger than transistor Q1, for example, 8 times larger. It is understood that the value of number P can take other values ​​greater than 1 or greater than 8, and these values ​​are not necessarily integer values.

[0073] The bases of the transistors Q1 and Q2 are connected together and the emitters of the transistors Q1 and Q2 are respectively coupled to a node 100 for application of a reference potential GND, for example ground.

[0074] Furthermore, the circuit 1 is configured such that the transistor Q1 receives a collector current Ic1 and the transistor Q2 receives a collector current Ic2 equal to the current Ic1. Therefore, the circuit 1 includes a current mirror 102 configured to deliver the currents Ic1 and Ic2. The current mirror 102 is connected to the collector of the transistor Q1, the collector of the transistor Q2 and a node 104, which is configured to receive a supply potential VDD, for example positive relative to a reference potential GND.

[0075] The current mirror 102 is implemented using MOS (“metal oxide semiconductor”) transistors. More specifically, the current mirror 102 includes a MOS transistor M1 and a MOS transistor M2, the source of which is connected to the node 104, and the drain of which is coupled, preferably connected, to the collector of the transistor Q1, the source of which is connected to the node 104, and the drain of which is coupled, preferably connected, to the collector of the transistor Q2. The gates of the transistors M1 and M2 are connected to each other. As an example, the gate of the transistor M2 is connected to the drain of the transistor M2. As an alternative example, the gate of the transistor M1 is connected to the drain of the transistor M1. The MOS transistors M1 and M2 are identical to each other, or, in other words, have the same size. Therefore, the size ratio of the transistors M1 and M2 is equal to 1, or, in other words, the current ratio of the current mirror 102 is equal to 1. The transistor M1 delivers the current Ic1 to the transistor Q1, and the transistor M2 delivers the current Ic2 to the transistor Q2.

[0076] Circuit 1 includes a resistor R1 and a resistor R2, wherein the resistor R1 is connected between the emitter of transistor Q2 and the emitter of transistor Q1, and the resistor R2 is connected between the emitter of transistor Q1 and a node 100. In other words, one terminal of the resistor R1 is coupled, preferably connected to the collector of transistor Q2, and the other terminal of the resistor R1 is coupled, preferably connected to the collector of transistor Q1, one terminal of the resistor R2 is coupled, preferably connected to the collector of transistor Q2, and the other terminal of the resistor R2 is coupled, preferably connected to the node 100.

[0077] As an example, the buffer circuit 106 is provided between the collector and base of the transistor Q1. Figure 11 , but the buffer circuit comprises, for example, a MOS transistor having its gate connected to the input of the buffer circuit 106, which itself is connected to the collector of a transistor Q1, and having its source connected to the output of the circuit 106, which itself is connected to the bases of transistors Q1 and Q2, the MOS transistor being configured as a follower source, or, in other words, a voltage follower.

[0078] As an alternative example, the buffer circuit may be replaced with a direct connection between the collector and base of transistor Q1. As another alternative example, instead of coupling the collector and base of transistor Q1 with the aid of a buffer circuit or a direct connection, the collector and base of transistor Q2 are coupled to each other with the aid of a buffer circuit or a direct connection, and then the base and collector of transistor Q1 are coupled to each other without the aid of a direct connection or a buffer circuit.

[0079] Ib1 is referred to as the base current of the transistor Q1, and Ib2 is referred to as the base current of the transistor Q2. Furthermore, Ie1 is referred to as the emitter current of the transistor Q1, and Ie2 is referred to as the emitter current of the transistor Q2.

[0080] exist Figure 1 In the circuit 1, a temperature-stabilized voltage Vref is available for the base of the transistor Q2. The voltage Vref is equal to the sum of the voltage Vbe1 and the voltage V2 across the resistor R2.

[0081] Current I2, which is equal to the sum of currents Ie1 and Ie2, flows through resistor R2. Therefore:

[0082] Vref=Vbe1+V2

[0083] Vref=Vbe1+I2*R2.

[0084] If the currents Ie1 and Ie2 are equal, the current I2 in resistor R2 is equal to twice the current Ie2, thus:

[0085] Vref=Vbe1+2*Ie2*R2,

[0086] Vref=Vbe1+2*(DVbe / R1)*R2.

[0087] Since DVbe is equal to (K*T*ln(P)) / q, where K is the Boltzmann constant, q is the electron charge in Coulombs, and T is the temperature in Kelvin, we obtain:

[0088] Vref=Vbe1+2*(R2 / R1)*(K*T / q)*ln(P).

[0089] The voltage Vref then effectively depends on a CTAT type voltage Vbe1 and a PTAT term proportional to the temperature T, whereby by appropriately dimensioning the circuit 1 , e.g. by choosing the values ​​of R1 and / or R2 and / or the number P, a temperature-independent voltage Vref can be obtained.

[0090] Figure 2 Another example of a bandgap circuit 2 is illustrated.

[0091] Like circuit 1, circuit 2 includes components Q1, M1, Q2, M2, and Figure 2 106 in the example of FIG. 1, which are connected together and connected to node 104 in the same manner as circuit 1. Therefore, unless otherwise stated, the combination Figure 1 The description of these components applies to Figure 2 Circuit 2.

[0092] However, circuit 2 does not include resistors R1 and R2.

[0093] Circuit 2 includes a resistor R3 connected between the emitter of transistor Q1 and node 100. For example, one terminal of resistor R3 is coupled, preferably connected, to the emitter of transistor Q1, and the other terminal is coupled, preferably connected, to node 100.

[0094] Circuit 2 includes a resistor R4 connected between the emitter of transistor Q2 and node 100. For example, one terminal of resistor R4 is coupled, preferably connected, to the emitter of transistor Q2, and the other terminal is coupled, preferably connected, to node 100.

[0095] Circuit 2 comprises a bipolar transistor Q3. The collector of transistor Q3 is connected to node 104. Transistor Q3 is of the same type as transistors Q1 and Q2, for example of NPN type.

[0096] Circuit 2 includes a resistor R5 connected between the emitter of transistor Q2 and the emitter of transistor Q3. For example, one terminal of resistor R5 is coupled, preferably connected, to the emitter of transistor Q2, and the other terminal is coupled, preferably connected, to the emitter of transistor Q3.

[0097] Circuit 2 includes a MOS transistor M3, the drain of which is connected to the base of transistor Q3, the source of which is connected to node 100, and the gate of which is connected to the collector of transistor Q2. For example, in this example, transistor M3 has an N channel, where transistors Q1, Q2, and Q3 are NPN bipolar transistors.

[0098] The capacitance element C is connected between the gate and drain of the transistor M3. For example, one terminal of the capacitance element C is connected to the drain of the transistor M3, and the other terminal is connected to the gate of the transistor M3.

[0099] Transistor M3 is biased by a current source connected between the drain of transistor M3 and node 104. The current source couples the drain of transistor M3 to node 104. For example, the bias current source of transistor M3 is implemented by a MOS transistor M4, the source of which is connected to node 104, the drain of which is connected to the drain of transistor M3, and the gate of which is connected to the gates of transistors M1 and M2 of current mirror 102.

[0100] In the same manner as Circuit 1 , the buffer circuit 106 of Circuit 2 may be replaced with a direct connection.

[0101] A temperature-stabilized voltage Vref is present at the base of transistor Q3.

[0102] The voltage Vref is equal to the sum of the voltage V4 across the resistor R4, the voltage V5 across the resistor R5, and the base-emitter voltage Vbe3 of the transistor Q3. Therefore, Vref=V4+V5+Vbe3.

[0103] In circuit 2, voltage V5 is equal to the product of resistor R5 and current I5 flowing through resistor R5. This current I5 is equal to current I4 flowing through resistor R4 minus current Ie2, and current I4 flowing through resistor R4 is equal to the ratio of voltage V4 to resistance R4. Therefore, V5 = R5*((V4 / R4)–Ie2), thus:

[0104] Vref=V4+R5*((V4 / R4)–Ie2)+Vbe3

[0105] Vref=V4*(1+(R5 / R4))–R5*Ie2+Vbe3.

[0106] In circuit 2, voltage V4 is equal to the sum of voltage Dvbe and voltage V3 across resistor 3, which is equal to the product of current Ie1 and resistor R3. Therefore, V4 = DVbe + R3 * Ie1. Result:

[0107] Vref=DVbe*(1+(R5 / R4))+Ie1*R3*(1+(R5 / R4))–R5*Ie2+Vbe3.

[0108] If the currents Ie1 and Ie2 are equal (Ie1=Ie2), and if the value of the resistor R3 is equal to the equal values ​​of the two resistors R4 and R5 connected in parallel, then the terms Ie1*R3*(1+(R5 / R4)) and R5*Ie2 are equal, and we obtain:

[0109] Vref=Dvbe*(1+(R5 / R4))+Vbe3,

[0110] Vref=(1+(R5 / R4))*(((K*T) / q)*ln(P))+Vbe3.

[0111] The voltage Vref then effectively depends on the voltage Vbe3 (which is of CTAT type) and on a PTAT term proportional to the temperature T, whereby, by appropriately dimensioning the circuit 2, e.g. by choosing the value of R4 and / or the value of R5 and / or the value of the number P, a temperature-independent voltage Vref can be obtained.

[0112] There are many other examples of bandgap circuits in which a temperature-stable reference voltage is generated based on the difference Dvbe between the base-emitter voltages of bipolar transistors Q1 and Q2, such as Figure 1 and Figure 2 as described.

[0113] However, in these circuits, the value of the temperature-stabilized voltage Vref may not be the expected value, ie the value of the voltage Vref effectively obtained differs from the theoretical value of the voltage Vref for which the circuit has been sized.

[0114] This stems in particular from the fact that, even if the two transistors Q1 and Q2 receive equal currents Ic1 and Ic2 , if the current gain β1 of transistor Q1 is not equal to the current gain β2 of transistor Q2 , the currents Ie1 and Ie2 are not equal.

[0115] In fact, Ie1 = Ic1 + Ib1 and Ie2 = Ic2 + Ib2, thus Ie1 = Ic1 + Ic1 / β1 and Ie2 = Ic2 + Ic2 / β2. If the gain β1 is different from the gain β2, and the currents Ic1 and Ic2 are equal, the currents Ie1 and Ie2 are different.

[0116] More specifically, when currents Ic1 and Ic2 are equal but gains β1 and β2 are different, then currents Ib1 and Ib2 are not the same, and Ie1 = Ie2 + Ib1 - Ib2, or, in other words, Ie1 + Ib2 - Ib1. The difference between currents Ib1 and Ib2 introduces an error between currents Ie1 and Ie2, which are no longer equal, and therefore introduces an error in the value of the voltage Vref obtained.

[0117] As an example, when a bandgap circuit, such as circuits 1 and 2, is implemented in FinFet technology, transistors Q1 and Q2 have different gains β1 and β2. In fact, in this technology, the inventors have observed that the current gain β of a bipolar transistor depends on the density of the collector current of the transistor. Now, in a bandgap circuit comprising two transistors Q1 and Q2 as described above, the densities of the collector currents of the two transistors Q1 and Q2 are different.

[0118] There is provided herein a method for correcting an error regarding the equality of currents Ie1 and Ie2 by generating a correction current Icorr equal to the difference between currents Ib1 and Ib2, and by injecting the correction current into the emitter of one of transistors Q1 and Q2 to make currents Ie1 and Ie2 equal, or, in other words, correcting an error regarding the value of voltage Vref caused by the current gain difference between transistors Q1 and Q2.

[0119] According to one embodiment, a correction circuit CORR is provided which is configured to generate a correction current Icorr and to inject the correction current Icorr onto the emitter of one of the two transistors Q1 and Q2 .

[0120] According to one embodiment, there is provided a device comprising a bandgap circuit, the bandgap circuit comprising two transistors Q1 and Q2, as previously described, the bandgap circuit being configured to generate a temperature-stabilized voltage, the device further comprising a circuit as described above.

[0121] Figure 3 An embodiment of an electronic device 3 is shown, the electronic device 3 comprising Figure 1 A bandgap circuit 1 and a correction circuit CORR according to an embodiment.

[0122] The device 3 is configured to deliver a temperature-stabilized voltage Vref, which is delivered by the circuit 1 of the device 3 .

[0123] Circuit CORR is configured to deliver a current Icorr. For example, circuit CORR includes an output 304 configured to deliver a current Icorr. In this embodiment, circuit CORR is configured to deliver a current Icorr that is equal to current Ib2 minus current Ib1, or, in other words, Icorr=Ib2−Ib1.

[0124] Furthermore, the circuit CORR is configured to inject a current Icorr into the emitter of one of the transistors Q1 and Q2 of the circuit 1. In this embodiment, since Icorr=Ib2-Ib1, the current Icorr is injected into the emitter of the transistor Q1, or, in other words, into the node connecting the emitter of the transistor Q1 to the resistor R2. In other words, the output 304 of the circuit CORR is connected to the emitter of the transistor Q1. In fact, as previously mentioned, when the gains β1 and β2 are not equal, then Ie1=Ie2+Ib1-Ib2. By injecting the current Icorr into the emitter of the transistor Q1, that is, by adding the current Icorr to the current Ie1, a corrected emitter current Ie1' equal to Ie1+Icorr is delivered to the node where the resistors R1 and R2 are interconnected to each other. Result:

[0125] Ie1'=Ie1+Icorr,

[0126] Ie1'=Ie2+Ib1–Ib2+Ib2–Ib1,

[0127] Ie1'=Ie2.

[0128] Reference combination Figure 1 The calculation described is:

[0129] Vref=Vbe1+I2*R2,

[0130] Vref=Vbe1+(Ie1'+Ie2)*R2,

[0131] Vref=Veb1+2*Ie2*R2, although the currents Ie1 and Ie2 are not equal.

[0132] As an example, the CORR circuit is powered by the voltage VDD. Then, the circuit CORR comprises a terminal 300 connected to the node 100 and a terminal 302 connected to the node 104.

[0133] As an example, the circuit CORR has a terminal 306 connected to the current mirror 102, for example, to the gates of the transistors M1 and M2 of the current mirror 102. Therefore, using MOS transistors assembled as a current mirror using the transistors M1 and M2, the circuit CORR can generate two currents determined by the currents Ic1 and Ic2, and deliver the two currents to the two bipolar transistors, respectively, so that the first of the two bipolar transistors has a base current determined by the current Ib1, and the other of the two bipolar transistors has a base current determined by the current Ib2. The two currents, which are mirrors of the currents Ib1 and Ib2, are then delivered to a current summing node, which is coupled to the output 304 of the circuit CORR, so that the current Icorr is equal to the difference between the currents Ib1 and Ib2. For example, of the two current mirrors, one current mirror is delivered to the summing node by the current mirror, so the resulting current Icorr is equal to the difference between the currents Ib1 and Ib2.

[0134] Combined Figure 3 An embodiment is described in which the circuit CORR delivers a current Icorr equal to Ib2 − Ib1 and this current is thus injected on the emitter of the transistor Q1 .

[0135] In another embodiment, the current Icorr is equal to Ib1-Ib2. In this other embodiment, the current Icorr is then injected into the emitter of transistor Q2. In this other embodiment, the current flowing through resistor R1 is then a current Ie2' which is equal to the sum of the currents Ie2 and Icorr. Result:

[0136] Ie2'=Ie2+Icorr,

[0137] Ie2'=Ie1+Ib2–Ib1+Ib1–Ib2,

[0138] Ie2'=Ie1.

[0139] Reference combination Figure 1 The calculation described is:

[0140] Vref=Vbe1+I2*R2,

[0141] Vref=Vbe1+(Ie1+Ie2')*R2,

[0142] Vref=Vbe1+2*Ie2'*R2, although the currents Ie1 and Ie2 are not equal.

[0143] Replace Ie2' with Dvbe / R1, with:

[0144] Vref=Vbe1+2*(R2 / R1)*DVbe,

[0145] Vref=Vbe1+2*(R2 / R1)*(K*T / q)*ln(P), although the current Ie1 is different from the current Ie2.

[0146] Figure 4 Shows Figure 3 Implementation of the correction circuit.

[0147] In this embodiment, the circuit CORR includes a terminal 306 connected to the current mirror 102 ( Figure 4 102 (not shown), for example, connected to the gates of transistors M1 and M2 of current mirror 102. Circuit CORR also includes a MOS transistor M1' and a bipolar transistor Q1', which are connected in series between terminals 302 and 300 of the circuit, that is, between nodes 104 (VDD) and 102 (GND), which are not connected in series. Figure 4 The circuit CORR further comprises a MOS transistor M2' and a bipolar transistor Q2', which are connected in series between the terminals 302 and 300 of the circuit. The transistors M1' and Q1', M2' and Q2' are respectively configured such that the base current Ib1' of the transistor Q1' and the base current Ib2' of the transistor Q2' are mirror currents of the current Ib1 of the transistor Q1 and the current Ib2 of the transistor Q2.

[0148] Transistors M1' and M2' are assembled as a current mirror with transistors M1 and M2, so that transistor M1' delivers current Ic1' as a mirror of current Ic1, and transistor M2' delivers current Ic2' as a mirror of current Ic2. Transistors M1 and M2 have the same N-type or P-type channels as transistors M1 and M2. For example, the source of transistor M1' is connected to terminal 302, and the gate of transistor M1' is connected to the gates of transistors M1 and M2, the source of transistor M2' is connected to terminal 302, and the gate of transistor M2' is connected to the gates of transistors M1 and M2.

[0149] Transistors Q1' and Q2' are of the same NPN or PNP type as transistors Q1 and Q2. Transistor Q1' is connected to transistor M1'. More specifically, the collector of transistor Q1' is connected to the drain of transistor M1' so as to receive current Ic1'. Symmetrically, transistor Q2' is connected to transistor M2'. More specifically, the collector of transistor Q2' is connected to the drain of transistor M2' so as to receive current Ic2'. Therefore, currents Ib1' and Ib2' are currents that are mirror images of currents Ib1 and Ib2, respectively.

[0150] The emitter of transistor Q1 ′ and the emitter of transistor Q2 ′ are both coupled, preferably connected, to terminal 300 .

[0151] According to one embodiment, transistors M1 and M1 ′ are identical, transistors M2 and M2 ′ are identical, transistors Q1 and Q1 ′ are identical, and transistors Q2 and Q2 ′ are identical, whereby currents Ib1 ′ and Ib2 ′ are equal to respective currents Ib1 and Ib2 .

[0152] The circuit CORR further comprises a transistor M5 , for example having a channel of a type opposite to that of the transistor M1 ′, and a transistor M6 , for example having a channel of a type opposite to that of the transistor M2 ′.

[0153] The gate of transistor M5 is connected to the collector of transistor Q1', and the source of transistor M5 is connected to the base of transistor Q1'. Symmetrically, the gate of transistor M6 is connected to the collector of transistor Q2', and the source of transistor M6 is connected to the base of transistor Q2'.

[0154] Circuit CORR includes a current mirror 400 whose MOS transistors couple the drains of transistors M5 and M6. The drain of one of transistors M5 and M6 has a current summing node function and is coupled to output 304. Current mirror 400 is configured so that the current Icorr supplied by output 304, i.e., the current Icorr supplied by the summing node, is equal to the difference between currents Ib1 and Ib2.

[0155] More specifically, in this embodiment where current Icorr=Ib2-Ib1, the summing node coupled to output 304 is the drain of transistor M5. Current mirror 400 is then configured to deliver current Ib2" to the summing node (the drain of transistor M5) so that current Icorr is equal to Ib2"-Ib1', and Ib2"-Ib1' is equal to Ib2-Ib1.

[0156] According to one embodiment, current mirror 400 has a unity current ratio when transistors M1′, M2′, Q1′, and Q2′ are identical to corresponding transistors M1, M2, Q1, and Q2, and currents Ib1′ and Ib2′ are then equal to corresponding currents Ib1 and Ib2. Figure 4 In the example of , this means that current Ib2" is equal to current Ib2'.

[0157] As an example, the current mirror 400 includes two MOS transistors M7 and M8, for example, having the same type of channels as the channels of the transistors M1' and M2', the gates of the MOS transistors M7 and M8 are connected to each other, and the sources of the MOS transistors M7 and M8 are connected to the terminal 302. The drain of the transistor M7 is connected to the drain of the transistor M5, and the drain of the transistor M8 is connected to the drain of the transistor M6. In this example, the drain of the transistor M8 is connected to the gate of the transistor M8.

[0158] To bias the summing node to a voltage suitable for operation of the MOS transistor current mirror 400, the circuit CORR includes a voltage source 402 connected between the summing node and the output 304. For example, one terminal of the voltage source 402 is connected to the summing node and the other terminal is connected to the output 304.

[0159] As an example, the voltage source 402 is implemented by a MOS transistor having a channel of the same type as that of the transistors M7 and M8, the sources of which are connected to the summing node, the drains of which are connected to the output 304, and the gates of which are connected to the source of the transistor M5 or M6 that is not connected to the summing node.

[0160] An embodiment in which circuit CORR delivers current Icorr=Ib2-Ib1 is described above. In another embodiment in which circuit CORR delivers current Icorr=Ib1-Ib2, the summing node is then the drain of transistor M6, and voltage source 402 couples the drain of transistor M6 to output 304. In addition, current mirror 400 is then configured to deliver current Ib1″ that is a mirror of current Ib1′ at summing node, such that current Icorr is equal to Ib1″-Ib2′ and Ib1″-Ib2′=Ib1-Ib2. In this other embodiment, when transistors M1′, M2′, Q1′, and Q2′ are identical to corresponding transistors M1, M2, Q1, and Q2, and their currents Ib1′ and Ib2′ are then equal to corresponding currents Ib1 and Ib2, current mirror 400 has a unity current ratio such that Ib1″ is equal to Ib1′.

[0161] An embodiment has been described in which transistors M1 ′, M2 ′, Q1 ′, and Q2 ′ are identical to corresponding transistors M1 , M2 , Q1 , and Q2 , such that currents Ib1 ′ and Ib2 ′ are equal to corresponding currents Ib1 and Ib2 .

[0162] In other embodiments, to reduce the size of transistor Q2' compared to the size of transistor Q2, transistor Q2' is different from transistor Q2 and is N times smaller than transistor Q2, N being a number or factor greater than 1, such as equal to 2. In these other embodiments, transistor M2' is then N times smaller than transistor M1', and transistors M7 and M8 have a size ratio equal to N, i.e., transistor M7 is N times larger than transistor M8. Transistors M1' and Q1' remain the same as corresponding transistors M1 and Q1.

[0163] As an example, then Ic1′=Ic1 and Ic2′=(1 / N)*Ic2, hence Ib1′=Ib1 and Ib2′=(1 / N)*Ib2. Because M7 is N times larger than M8, or, in other words, current mirror 400 has a current ratio equal to N when the summing node is the drain of transistor M5, and a current ratio equal to 1 / N when the summing node is the drain of transistor M6. Therefore, Figure 4 In the example of , Ib2″=N*Ib2′=N*(1 / N)*Ib2, thus Icorr=Ib2″−Ib1′=Ib2−Ib1.

[0164] Although combined Figure 3 An embodiment of the device 3 is described in which the circuit CORR is connected to the circuit 1, but the circuit CORR can be used with other bandgap circuits, for example with Figure 2 Used together with circuit 2.

[0165] Figure 5 Shown include Figure 2 The bandgap circuit 2 and Figure 3 An embodiment of the electronic device 5 of the circuit CORR, for example as combined Figure 4 Implemented as described.

[0166] The device 5 is configured to deliver a temperature-stabilized voltage Vref, which is delivered by the circuit 2 of the device 5 .

[0167] Circuit CORR is configured to deliver a current Icorr. For example, circuit CORR includes an output 304 configured to deliver a current Icorr. In this embodiment, circuit CORR is configured to deliver a current Icorr that is equal to current Ib2 minus current Ib1, or, in other words, Icorr=Ib2−Ib1.

[0168] Furthermore, the circuit CORR is configured to inject a current Icorr into the emitter of one of the transistors Q1 and Q2 of the circuit 1. In this embodiment, since Icorr=Ib2-Ib1, the current Icorr is injected into the emitter of the transistor Q1, or, in other words, into the node connecting the emitter of the transistor Q1 to the resistor R3. In other words, the output 304 of the circuit CORR is connected to the emitter of the transistor Q1. By injecting the current Icorr into the emitter of the transistor Q1, i.e., by adding the current Icorr to the current Ie1, a corrected emitter current Ie1' equal to Ie1+Icorr flows through the resistor R3. As a result:

[0169] Ie1'=Ie1+Icorr,

[0170] Ie1'=Ie2+Ib1–Ib2+Ib2–Ib1,

[0171] Ie1'=Ie2.

[0172] Reference combination Figure 2 The calculation described is:

[0173] Vref=DVbe*(1+(R5 / R4))+Ie1'*R3*(1+(R5 / R4))−R5*Ie2+Vbe3, thus:

[0174] Vref = Vref = DVbe*(1+(R5 / R4))+Ie2*(R3*(1+(R5 / R4))-R5)+Vbe3. By setting the value of resistor R3 equal to the equal values ​​of resistors R4 and R5 connected in parallel, the term R3*(1+(R5 / R4)) and -R5 cancel each other and effectively obtain:

[0175] Vref=(1+(R5 / R4))*(K*T / q)*ln(P)+Vbe3, although the currents Ie1 and Ie2 are different.

[0176] In another embodiment, current Icorr is equal to Ib1-Ib2. In this other embodiment, current Icorr is then injected into the emitter of transistor Q2, i.e., into the node connecting resistor R4 to resistor R5. In this other embodiment, current I2 flowing through resistor R4 is then equal to the sum of current Ie2' and current I5, where:

[0177] Ie2'=Ie2+Icorr,

[0178] Ie2'=Ie1+Ib2–Ib1+Ib1–Ib2,

[0179] Ie2'=Ie1.

[0180] Reference combination Figure 2 The calculation described is:

[0181] Vref=DVbe*(1+(R5 / R4))+Ie1*R3*(1+(R5 / R4))−R5*Ie2'+Vbe3, thus:

[0182] Vref = Vref = DVbe*(1+(R5 / R4))+Ie1*(R3*(1+(R5 / R4))-R5)+Vbe3. By setting the value of resistor R3 equal to the equal values ​​of resistors R4 and R5 connected in parallel, the term R3*(1+(R5 / R4)) and -R5 cancel each other out and effectively obtain:

[0183] Vref=(1+(R5 / R4))*(K*T / q)*ln(P)+Vbe3, although the currents Ie1 and Ie2 are different.

[0184] Embodiments of the device 3 and the device 5 comprising the circuit CORR and the bandgap circuit 1 and the circuit CORR and the bandgap circuit 2, respectively, have been described. However, a person skilled in the art is able to provide other devices for generating a temperature-stabilized reference voltage Vref, including:

[0185] a bandgap circuit configured to deliver a voltage Vref based on a difference between a base-emitter voltage Vbe1 of a first bipolar transistor Q1 and a base-emitter voltage Vbe2 of a second bipolar transistor Q2, for example biased by a current mirror 102 as in circuits 1 and 2, and

[0186] A correction circuit CORR, the correction circuit CORR being configured as follows:

[0187] generating a correction current Icorr that is equal to a difference between a base current of one of transistors Q1 and Q2 and a base current of the other of transistors Q1 and Q2; and

[0188] A current Icorr is injected into the emitter of one of the bipolar transistors Q1 and Q2 to correct an error regarding the value of the voltage Vref caused by a difference between the current gains β1 and β2 of the transistors Q1 and Q2, or, in other words, to correct an error in the equality of the emitter currents Ie1 and Ie2 of the transistors Q1 and Q2 caused by a difference between the current gains β1 and β2 of the transistors Q1 and Q2.

[0189] As mentioned before, the difference between the current gains β1 and β2 is caused, for example, by the variation of the current gain β of the bipolar transistor with its collector current density.

[0190] For example, bipolar transistors implemented in FinFet technology show a variation of their current gain β with the density of the collector current.Thus, according to one embodiment, the bipolar and MOS transistors of the device for generating a temperature-stabilized voltage Vref comprising the bandgap circuit and the circuit CORR are all implemented in FinFet technology.

[0191] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0192] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, a person skilled in the art is able to adapt the dimensions of the bandgap circuit configured to generate the voltage Vref.

[0193] A correction circuit (CORR) for a bandgap circuit (1; 2) is summarized as including a first bipolar transistor (Q1) and a second bipolar transistor (Q2), the bandgap circuit being configured to deliver a temperature-stabilized DC voltage (Vref) based on a difference (Dvbe) between a base-emitter voltage (Vbe1) of the first bipolar transistor (Q1) and a base-emitter voltage (Vbe2) of the second bipolar transistor (Q2), the correction circuit being configured to: generate a correction current (Icorr) equal to a difference between a base current (Ib2) of one of the first and second transistors (Q2) and a base current of the other of the two transistors (Q1); and inject the correction current (Icorr) into an emitter of one of the first and second bipolar transistors (Q1) to correct an error with respect to a value of the temperature-stabilized voltage (Vref) caused by a current gain difference between the first and second bipolar transistors (Q1) and (Q2).

[0194] An apparatus (3, 5) for generating a temperature-stabilized DC voltage (Vref) is summarized as comprising: a bandgap circuit (1; 2) comprising a first bipolar transistor (Q1) and a second bipolar transistor (Q2) and configured to deliver a temperature-stabilized DC voltage (Vref) based on a difference (Dvbe) between a base-emitter voltage (Vbe1) of the first bipolar transistor (Q1) and a base-emitter voltage (Vbe2) of the second bipolar transistor (Q2); and a correction circuit (CORR).

[0195] The first bipolar transistor (Q1) has a smaller size than the second bipolar transistor (Q2); the bases of the first bipolar transistor (Q1) and the second bipolar transistor (Q2) are connected together, and their emitters are coupled to a first node (100) to which a reference potential (GND) is applied; and a bandgap circuit (1; 2), the bandgap circuit comprising: a first MOS transistor (M1), the first MOS transistor (M1) having a source and a drain, the source being connected to a second node (104) configured to receive a supply potential (VDD), the drain being coupled, preferably connected, to the collector of the first bipolar transistor (Q1); and a second MOS transistor (M2), which is identical to the first MOS transistor (M1) and has a source, a drain and a gate, the source being connected to the second node (104), the drain being coupled, preferably connected, to the collector of the second bipolar transistor (Q2), and the gate being connected to the gate of the first MOS transistor (M1), the first MOS transistor (M1) and the second MOS transistor (M2) being configured to deliver a first current (Ic1) to the first bipolar transistor (Q1), and to deliver a second current (Ic2) equal to the first current to the second bipolar transistor (Q2).

[0196] The bandgap circuit (1) includes: a first resistor (R1) connected between an emitter of a first bipolar transistor (Q1) and an emitter of a second bipolar transistor (Q2); and a second resistor (R2) connected between the emitter of the first bipolar transistor (Q1) and a first node (100).

[0197] The bandgap circuit (2) comprises: a first resistor (R3) connected between the emitter of the first bipolar transistor (Q1) and a first node (100); a second resistor (R4) connected between the emitter of the second bipolar transistor (Q2) and the first node (100); an additional bipolar transistor (Q3) having a collector connected to the second node (104); an additional MOS transistor (M3) having a drain connected to the additional bipolar transistor ( The invention relates to a MOS transistor (M3) having a base connected to a second node (104) and coupled to the second node (104) through a current source (M4), a gate of the additional MOS transistor (M3) being connected to the collector of the second bipolar transistor (Q2), and a source of the additional MOS transistor (M3) being connected to the first node (100); a capacitive element (C) coupling the drain and gate of the additional MOS transistor (M3); and a third resistor (R5) connected between the emitter of the second bipolar transistor (Q2) and the emitter of the additional bipolar transistor (Q3).

[0198] The correction circuit (CORR) is configured to inject a correction current (Icorr) at a node connecting a first resistor (R1; R3) to a first bipolar transistor (Q1).

[0199] The correction circuit (CORR) comprises: a third MOS transistor (M1') and a third bipolar transistor (Q1'), the third MOS transistor (M1') and the third bipolar transistor (Q1') being connected in series between a first node (100) and a second node (104); a fourth MOS transistor (M2') and a fourth bipolar transistor (Q2'), the fourth MOS transistor (M2') and the fourth bipolar transistor (Q2') being connected in series between the first node (100) and the second node (104); a sixth MOS transistor (M5), the gate of the sixth MOS transistor (M5) being connected to a node connecting the third MOS transistor (M1') to the third bipolar transistor (Q1'), the source of the sixth MOS transistor (M5) being connected to the base of the third bipolar transistor (Q1'), and the sixth MOS transistor (M5) being connected to the gate of the sixth MOS transistor (M5). a transistor (M5) having a drain connected to a third node; a seventh MOS transistor (M6) having a gate connected to a node connecting the fourth MOS transistor (M2') to the fourth bipolar transistor (Q2'), a source connected to the base of the fourth bipolar transistor (Q2'), and a drain connected to the fourth node; a current mirror (400) having MOS transistors (M7, M8) coupling the third node and the fourth node; and a voltage source (402) coupling the third node or the fourth node to an output (304) of a correction circuit (CORR), the output (304) of the correction circuit (CORR) being configured to deliver a correction current (Icorr).

[0200] The third MOS transistor (M1') is the same as the first MOS transistor (M1); the third bipolar transistor (Q1') is the same as the first bipolar transistor (Q1); the fourth MOS transistor (M2') is the same as the second MOS transistor (M2); the fourth bipolar transistor (Q2') is the same as the second bipolar transistor (Q2); and the current ratio of the current mirror (400) is equal to 1.

[0201] The third MOS transistor (M1') is the same as the first MOS transistor (M1); the third bipolar transistor (Q1') is the same as the first bipolar transistor (Q1); the fourth MOS transistor (M2') is N times smaller than the second MOS transistor (M2), where N is a number greater than 1, for example, equal to 2; the fourth bipolar transistor (Q2') is N times smaller than the second bipolar transistor (Q2); and the current mirror includes two MOS transistors (M7, M8), and the size ratio between the two MOS transistors is N.

[0202] A voltage source (402) couples the third node to the output; and the current mirror (400) is configured to supply a current (Ib2') determined by a base current (Ib2) of a fourth bipolar transistor (Q2') to the third node.

[0203] The output (304) of the correction circuit (CORR) is connected to the emitter of the first bipolar transistor (Q1).

[0204] The first bipolar transistor (Q1) and the second bipolar transistor (Q2) are of NPN type.

[0205] The transistors (Q1, Q2, M1, M2, Q1', Q2', M1', M2') are implemented using FinFet technology.

[0206] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0207] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A circuit comprising: A bandgap circuit, the bandgap circuit comprising: a first bipolar transistor; and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stabilized DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and A correction circuit, the correction circuit being configured to: generating a correction current equal to a difference between a base current of one of the first transistor and the second transistor and a base current of the other of the first transistor and the second transistor; and The correction current is injected onto an emitter of one of the first bipolar transistor and the second bipolar transistor to correct an error with respect to a value of the temperature-stabilized voltage caused by a current gain difference between the first bipolar transistor and the second bipolar transistor. 2 . The circuit of claim 1 , wherein the correction circuit comprises a third bipolar transistor and a fourth bipolar transistor.

3. The circuit of claim 2, wherein the correction circuit further comprises: a first metal oxide semiconductor (MOS) transistor, the first MOS transistor being coupled in series to the third bipolar transistor; as well as A second MOS transistor is serially coupled to the fourth bipolar transistor. 4 . The circuit of claim 2 , wherein the third bipolar transistor is smaller than the fourth bipolar transistor.

5. The circuit according to claim 3, further comprising: A third MOS transistor; as well as A fourth MOS transistor, a gate of the fourth MOS transistor is directly coupled to the gate of the third MOS transistor.

6. A device comprising: A bandgap circuit, the bandgap circuit comprising: a first bipolar transistor; and a second bipolar transistor, the bandgap circuit being configured to deliver a temperature-stabilized DC voltage based on a difference between a base-emitter voltage of the first bipolar transistor and a base-emitter voltage of the second bipolar transistor; and A correction circuit is configured to generate a correction current equal to a difference between a base current of one of the first transistor and the second transistor and a base current of the other of the first transistor and the second transistor.

7. The apparatus of claim 6, wherein: The first bipolar transistor has a smaller size than the second bipolar transistor; The bases of the first bipolar transistor and the second bipolar transistor are connected together, and the emitters of the first bipolar transistor and the second bipolar transistor are coupled to a first node to which a reference potential is applied; and The bandgap circuit comprises: a first metal oxide semiconductor (MOS) transistor having a source connected to a second node configured to receive a supply potential and a drain coupled to a collector of the first bipolar transistor; and a second MOS transistor, the second MOS transistor being identical to the first MOS transistor and having: a source connected to the second node; a drain coupled to the collector of the second bipolar transistor; and a gate connected to the gate of the first MOS transistor, the first MOS transistor and the second MOS transistor being configured to deliver a first current to the first bipolar transistor and a second current to the second bipolar transistor, the second current being equal to the first current.

8. The apparatus of claim 7, wherein the bandgap circuit comprises: a first resistor coupled between an emitter of the first bipolar transistor and an emitter of the second bipolar transistor; as well as A second resistor is coupled between an emitter of the first bipolar transistor and the first node.

9. The apparatus of claim 7, wherein the bandgap circuit comprises: a first resistor connected between an emitter of the first bipolar transistor and the first node; a second resistor connected between an emitter of a second bipolar transistor and the first node; a third bipolar transistor having: a collector coupled to the second node; a third MOS transistor having a drain coupled to the base of the third bipolar transistor and coupled to the second node by a current source; a gate coupled to the collector of the second bipolar transistor; and a source connected to the first node; a capacitive element coupling a drain and a gate of the additional MOS transistor; as well as A third resistor is coupled between an emitter of the second bipolar transistor and an emitter of the additional bipolar transistor. 10 . The apparatus of claim 8 , wherein the correction circuit is configured to inject the correction current at a node connecting the first resistor to the first bipolar transistor.

11. A device comprising: A bandgap circuit, the bandgap circuit comprising: a first bipolar transistor; a second bipolar transistor; a first metal oxide semiconductor (MOS) transistor having a source connected to a second node configured to receive a supply potential and a drain coupled to a collector of the first bipolar transistor; and a second MOS transistor having a source connected to the second node, a drain coupled to the collector of the second bipolar transistor, and a gate connected to the gate of the first MOS transistor, the first MOS transistor and the second MOS transistor being configured to deliver a first current to the first bipolar transistor and a second current to the second bipolar transistor, the second current being equal to the first current; and A correction circuit, the correction circuit comprising: A third MOS transistor; a third bipolar transistor, the third bipolar transistor being coupled in series with the third MOS transistor between the first node and the second node; a fourth MOS transistor; a fourth bipolar transistor coupled in series with the fourth MOS transistor between the first node and the second node; and A voltage source couples the third node or the fourth node to an output of the correction circuit, the output of the correction circuit being configured to deliver the correction current.

12. The device according to claim 11, further comprising: a fifth MOS transistor, a gate of the fifth MOS transistor being connected to a node connecting the third MOS transistor to the third bipolar transistor, a source of the fifth MOS transistor being connected to a base of the third bipolar transistor, and a drain of the fifth MOS transistor being connected to a third node; as well as a sixth MOS transistor, a gate of the sixth MOS transistor being connected to a node connecting the fourth MOS transistor to the fourth bipolar transistor, a source of the sixth MOS transistor being connected to a base of the fourth bipolar transistor, and a drain of the sixth MOS transistor being connected to a fourth node.

13. The apparatus of claim 12, further comprising a current mirror including a seventh MOS transistor and an eighth MOS transistor, the seventh MOS transistor and the eighth MOS transistor coupling the third node and the fourth node.

14. The apparatus of claim 11, wherein: The third MOS transistor is the same as the first MOS transistor; The third bipolar transistor is the same as the first bipolar transistor; The fourth MOS transistor is the same as the second MOS transistor; The fourth bipolar transistor is identical to the second bipolar transistor; and The current ratio of the current mirror is equal to 1.

15. The apparatus of claim 13, wherein: The third MOS transistor is the same as the first MOS transistor; The third bipolar transistor is the same as the first bipolar transistor; The fourth MOS transistor is N times smaller than the second MOS transistor, where N is a number greater than 1; The fourth bipolar transistor is N times smaller than the second bipolar transistor; and The current mirror includes two MOS transistors, and a size ratio between the two MOS transistors is N.

16. The apparatus of claim 13, wherein: The voltage source couples the third node to the output; and The current mirror is configured to supply a current to the third node, the current being determined by the base current of the fourth bipolar transistor.

17. The apparatus of claim 16, wherein the output of the correction circuit is connected to an emitter of the first bipolar transistor.

18. The apparatus of claim 11, wherein the first bipolar transistor and the second bipolar transistor are of NPN type.

19. The apparatus of claim 6, wherein the first, second, third, and fourth bipolar transistors, and the first, second, third, and fourth MOS transistors are implemented in FinFET technology.

20. The apparatus of claim 11, wherein the correction circuit is configured to: generating a correction current equal to a difference between a base current of one of the first transistor and the second transistor and a base current of the other of the first transistor and the second transistor; and The correction current is injected onto an emitter of one of the first bipolar transistor and the second bipolar transistor to correct an error with respect to a value of the temperature-stabilized voltage caused by a current gain difference between the first bipolar transistor and the second bipolar transistor.

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