A bandgap reference circuit

Abstract

The present application provides a bandgap reference circuit, relating to the field of integrated circuit technology. The bandgap reference circuit comprises: a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit, and an output circuit. The core circuit is configured to generate a point X voltage, a positive temperature coefficient (PTAT) current without a base current, and a negative temperature coefficient (CTAT) current mixed with a base current. The point X voltage is the base-emitter voltage of a transistor in the core circuit through which the PTAT current flows. The negative temperature current extraction circuit is configured to extract the CTAT current without a base current based on the point X voltage. The high-order modulation processing circuit is configured to generate a bandgap reference current that has undergone high-order modulation and has eliminated the influence of the base current based on the point X voltage and the PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit. The output circuit is configured to convert the bandgap reference current into a bandgap reference voltage for output.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit. Background Art

[0002] Bandgap references provide stable reference voltages and bias currents regardless of temperature and power supply voltage variations. They are widely used in various analog integrated circuits, and their accuracy directly determines the accuracy of the entire system. Design criteria for bandgap references include a low temperature coefficient, high power supply rejection ratio, and minimal dependence on process parameters such as corners. High-performance bandgap references are crucial for the functional implementation of many system modules.

[0003] Most currently designed bandgap reference circuits require amplifiers, which not only increase chip area but also affect the accuracy of the voltage reference due to input offset voltage and noise. Furthermore, current methods for implementing high-order modulated bandgap references are significantly affected by base current, which can easily lead to errors and reduce bandgap reference accuracy.

[0004] Therefore, in order to obtain a high-precision bandgap reference, it is necessary to design a bandgap reference with a high-order modulation, no amplifier structure, and a low temperature coefficient that offsets most of the base current influence. Summary of the Invention

[0005] The purpose of the present application is to provide a high-order modulated, amplifier-free bandgap reference circuit that offsets most of the base current influence and has a low temperature coefficient.

[0006] In order to achieve the above objectives, the technical solutions adopted in this application are as follows:

[0007] The present application provides a bandgap reference circuit, comprising: a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit, and an output circuit;

[0008] The first port of the negative temperature current extraction circuit and the first port of the high-order modulation processing circuit are both connected to point X in the core circuit, the second port and the third port of the high-order modulation processing circuit are connected to the second port of the negative temperature current extraction circuit and the first port of the core circuit respectively, and the output end of the high-order modulation processing circuit is connected to the output circuit;

[0009] The core circuit is used to generate a point X voltage, a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current; wherein the point X voltage is the base-emitter voltage of the transistor in the core circuit through which the PTAT current flows;

[0010] The negative temperature current extraction circuit is used to extract the CTAT current without the base current according to the X point voltage;

[0011] The high-order modulation processing circuit is used to generate a bandgap reference current that has undergone high-order modulation and eliminated the influence of the base current according to the X-point voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit;

[0012] The output circuit is used for converting the bandgap reference current into a bandgap reference voltage and then outputting the converted voltage.

[0013] Furthermore, the core circuit includes: Q0, Q1, Q2, Q3, Q4, PM0, PM1, PM2, PM3, PM23, PM24, PM25, NM4, resistor R0, resistor R1 and a first cascade MOS transistor;

[0014] Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the number of Q0 transistors connected in parallel is greater than the number of Q1 transistors connected in parallel; PM0, PM1, PM2, PM3, PM23, PM24 and PM25 are all PMOS transistors, and NM4 is an NMOS transistor;

[0015] The sources of the PM0, PM1, PM2, PM3, and first cascade MOS transistors are all connected to the power supply; the sources of the PM25, PM24, and PM23 transistors are respectively connected to the drains of the PM3, PM0, and PM2 transistors; the gates of the PM25, PM24, and PM23 transistors are all connected to the gate of the first cascade MOS transistor; the gate of the PM3 transistor, the gate of the PM0 transistor, and the drain of the PM23 transistor are all connected to the gate of the PM2 transistor; wherein the gate of the PM2 transistor serves as the first port of the core circuit;

[0016] The drain of PM25 is connected to the collector of Q3. The drain of PM24 is connected to the gate of PM1 and the collector of Q0. The drain of PM23 is also connected to the drain of NM4. The gate of NM4 is connected to the collector of Q3. The source of NM4 is connected to the base of Q3 and the collector of Q2. The drain of the first cascade MOS tube is connected to the collector of Q4.

[0017] The emitters of tubes Q0, Q1, Q2, Q3, and Q4 are all grounded, the bases of tubes Q1, Q2, and Q4 are all connected to the point X, the collector of tube Q1 is respectively connected to the base of tube Q0 and one end of resistor R0, the other end of resistor R0 is respectively connected to the drain of tube PM1 and the point X, one end of resistor R1 is grounded, and the other end of resistor R1 is connected to point X.

[0018] Furthermore, the negative temperature current extraction circuit includes: a PM4 transistor, a PM5 transistor, a PM6 transistor, a PM30 transistor, a PM31 transistor, an NM0 transistor, an NM1 transistor, an NM2 transistor, an NM3 transistor, a resistor R2, a resistor R3, a resistor R4 and a second cascade MOS transistor;

[0019] Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes;

[0020] The sources of the PM4, PM5, PM6, and second cascade MOS transistors are all connected to the power supply; the drains of the PM4 and PM5 transistors are connected to the sources of the PM30 and PM31 transistors, respectively; the gates of the PM30 and PM31 transistors are both connected to the gate of the second cascade MOS transistor; the gate of the PM4 transistor and the drain of the PM31 transistor are both connected to the gate of the PM5 transistor; wherein the gate of the PM5 transistor serves as the second port of the negative temperature current extraction circuit;

[0021] The drain of the second cascade MOS tube is connected to the drain of the NM3 tube, the drain of the PM6 tube is connected to the drain of the NM0 tube and the gate of the NM0 tube respectively, the drain of the PM30 tube is connected to the gate of the PM6 tube and the drain of the NM1 tube respectively, and the drain of the PM31 tube is also connected to the drain of the NM2 tube;

[0022] The gates of transistors NM3, NM1, and NM2 are all connected to the gate of transistor NM0; the source of transistor NM3 is grounded via resistor R4, the source of transistor NM0 is grounded via resistor R3, the source of transistor NM1 is grounded via resistor R2, and the source of transistor NM2 is connected to point X; wherein the source of transistor NM2 serves as the first port of the negative temperature current extraction circuit.

[0023] Furthermore, the first cascade MOS transistors include: PM32, PM33, PM34 and PM35, and the second cascade MOS transistors include: PM26, PM27, PM28 and PM29.

[0024] Among them, PM32, PM33, PM34, PM35, PM26, PM27, PM28 and PM29 are all PMOS tubes;

[0025] The source of the PM32 transistor is connected to the power supply as the source of the first cascade MOS transistor. The drain of the PM32 transistor is connected to the source of the PM33 transistor. The drain of the PM33 transistor is connected to the source of the PM34 transistor. The drain of the PM34 transistor is connected to the source of the PM35 transistor. The gate of the PM32 transistor, the gate of the PM33 transistor, the gate of the PM34 transistor, the gate of the PM35 transistor, and the drain of the PM35 transistor are connected to serve as the gate of the first cascade MOS transistor. The drain of the PM35 transistor is also connected to the collector of the Q4 transistor.

[0026] The source of transistor PM26 is connected to the power supply as the source of the second cascade MOS transistor, the drain of transistor PM26 is connected to the source of transistor PM27, the drain of transistor PM27 is connected to the source of transistor PM28, and the drain of transistor PM28 is connected to the source of transistor PM29; the gate of transistor PM26, the gate of transistor PM27, the gate of transistor PM28, the gate of transistor PM29, and the drain of transistor PM29 are connected to serve as the gate of the second cascade MOS transistor; the drain of transistor PM29 is also connected to the drain of transistor NM3.

[0027] Furthermore, the high-order modulation processing circuit includes: a resistor R NL , a zero-temperature current generating module, a first Wilson current mirror, and a second Wilson current mirror;

[0028] The first input end of the zero-temperature current generating module is connected to the second port of the negative temperature current extraction circuit, and the second input end of the zero-temperature current generating module is connected to the first port of the core circuit; the first output end of the zero-temperature current generating module is connected to the first port of the first Wilson current mirror, the second output end of the zero-temperature current generating module is connected to the first port of the second Wilson current mirror, the third output end of the zero-temperature current generating module is respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror, and the second port of the second Wilson current mirror is also connected to the output circuit; the resistor R NL One end of the resistor R is connected to the X point in the core circuit. NL The other end is connected to point Z in the first Wilson current mirror;

[0029] The zero temperature current generating module is used to provide a zero temperature coefficient ZTAT current to the first Wilson current mirror and the second Wilson current mirror according to the PTAT current and the CTAT current;

[0030] The resistor R NL for providing a high-order modulation current to the first Wilson current mirror according to the voltage at point X and the voltage at point Z; wherein the voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror through which the ZTAT current flows;

[0031] The first Wilson current mirror and the second Wilson current mirror are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of base current and the influence of transistor current gain reduction at low temperature according to the ZTAT current and the high-order modulation current.

[0032] Furthermore, the zero-temperature current generating module includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube and a PM22 tube;

[0033] Among them, PM7, PM8, PM9, PM10, PM11, PM12, PM17, PM18, PM19, PM20, PM21, and PM22 are all PMOS tubes;

[0034] The number of PM7 tubes in parallel = the number of PM22 tubes in parallel = the number of PM10 tubes in parallel = the number of PM20 tubes in parallel = the number of PM9 tubes in parallel = the number of PM17 tubes in parallel = the number of PM12 tubes in parallel = the number of PM18 tubes in parallel = a, the number of PM8 tubes in parallel = the number of PM21 tubes in parallel = the number of PM11 tubes in parallel = the number of PM19 tubes in parallel = b, where a and b are both positive integers and b>2a;

[0035] The sources of the PM7, PM8, PM9, PM10, PM11, and PM12 transistors are all connected to the power supply; the gates of the PM7, PM8, and PM9 transistors are all connected to the gate of the PM2 transistor; the drains of the PM7, PM8, and PM9 transistors are respectively connected to the sources of the PM22, PM21, and PM17 transistors; and the gates of the PM22, PM21, and PM17 transistors are all connected to the gate of the first cascade MOS transistor.

[0036] The gates of the PM10, PM11, and PM12 transistors are all connected to the gate of the PM5 transistor; the drains of the PM10, PM11, and PM12 transistors are respectively connected to the sources of the PM20, PM19, and PM18 transistors; and the gates of the PM20, PM19, and PM18 transistors are all connected to the gate of the second cascade MOS transistor.

[0037] The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module and are connected to the first port of the first Wilson current mirror. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module and are connected to the first port of the second Wilson current mirror. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module and are respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror.

[0038] Furthermore, the first Wilson current mirror includes: NM5, Q5, Q6, Q11 and Q12; the second Wilson current mirror includes: NM6, Q7, Q8, Q9 and Q10;

[0039] Among them, NM5 and NM6 are NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are NPN transistors;

[0040] The collector of Q12 tube is connected to the first output terminal of the zero-temperature current generating module and the gate of NM5 tube respectively, the drain of NM5 tube is connected to the third output terminal of the zero-temperature current generating module, the source of NM5 tube is connected to the collector of Q6 tube, the base of Q6 tube and the base of Q12 tube respectively, the emitter of Q6 tube is connected to the collector of Q5 tube; the emitter of Q12 tube, the collector of Q11 tube, the base of Q11 tube, the base of Q5 tube and the resistor R NL One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded;

[0041] The drain of the NM6 tube is respectively connected to the third output end of the zero-temperature current generating module and the output circuit, and the source of the NM6 tube is connected to the collector of the Q7 tube; the collector of the Q10 tube is respectively connected to the second output end of the zero-temperature current generating module, the gate of the NM6 tube, the base of the Q10 tube and the base of the Q7 tube; the emitter of the Q10 tube is connected to the collector of the Q9 tube, and the emitter of the Q7 tube is respectively connected to the collector of the Q8 tube, the base of the Q8 tube and the base of the Q9 tube, and the emitters of the Q8 tube and the Q9 tube are both grounded.

[0042] Furthermore, the core circuit further includes a resistor Rs1, and the bandgap reference circuit further includes a startup circuit;

[0043] One end of resistor Rs1 is connected to point X, the other end of resistor Rs1 is respectively connected to the drain of transistor PM1 and the first port of the startup circuit, the second port of the startup circuit is respectively connected to the gate of transistor PM6, the drain of transistor PM30, and the drain of transistor NM1, and the input end of the startup circuit is connected to the power supply.

[0044] Furthermore, the startup circuit includes: a Q13 transistor, an NMs1 transistor, an NMs2 transistor, a resistor Rs2, a resistor Rs3, and a capacitor C1; wherein the Q13 transistor is an NPN transistor, and the NMs1 transistor and the NMs2 transistor are both NMOS transistors;

[0045] One end of resistor Rs3 is connected to the power supply, and the other end of resistor Rs3 is connected to the drain of transistor NMs1, the gate of transistor NMs1, and the gate of transistor NMs2 respectively; the source of transistor NMs1 is connected to the collector of transistor Q13 and the base of transistor Q13 respectively, and the emitter of transistor Q13 is grounded;

[0046] The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1 respectively. The drain of NMs2 is connected to the gate of PM6, the drain of PM30, and the drain of NM1 respectively. The drain of NMs2 is also connected to one end of resistor Rs2. The other end of resistor Rs2 is connected to one end of capacitor C1. The other end of capacitor C1 is grounded.

[0047] When the bandgap reference circuit outputs normally, the NMs2 transistor is turned off and the startup circuit stops running.

[0048] Furthermore, the output circuit includes: a first current mirror, a second current mirror and a resistor R OUT ;

[0049] The first port of the first current mirror is connected to the output end of the high-order modulation processing circuit, the second port of the first current mirror is connected to the third port of the second current mirror, the third port and the fourth port of the first current mirror are both grounded, the first port and the second port of the second current mirror are both connected to the power supply, and the resistor R OUT One end of the resistor R OUT The other end is connected to the fourth port of the second current mirror as the output end of the bandgap reference circuit.

[0050] Compared with the prior art, this application has the following beneficial effects:

[0051] The present application provides a bandgap reference circuit, comprising a core circuit, a negative temperature current extraction circuit, a high-order modulation processing circuit, and an output circuit. The core circuit generates a point X voltage (i.e., the base-emitter voltage of a transistor in the core circuit through which a positive temperature coefficient (PTAT) current flows), a positive temperature coefficient (PTAT) current without a base current, and a negative temperature coefficient (CTAT) current mixed with a base current. The negative temperature current extraction circuit extracts the CTAT current without a base current based on the point X voltage. The high-order modulation processing circuit generates a bandgap reference current that has undergone high-order modulation and eliminates the influence of base current based on the point X voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit. The output circuit converts the bandgap reference current into a bandgap reference voltage for output. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is one of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of the present application;

[0054] Figure 2 A circuit diagram of a core circuit provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of a circuit including a core circuit and a negative temperature current extraction circuit provided in an embodiment of the present application;

[0056] Figure 4 A schematic diagram of a circuit including a core circuit, a negative temperature current extraction circuit, and a startup circuit provided in an embodiment of the present application;

[0057] Figure 5 A second structural diagram of a bandgap reference circuit provided in an embodiment of the present application;

[0058] Figure 6 A circuit diagram of a high-order modulation processing circuit provided in an embodiment of the present application;

[0059] Figure 7 A circuit diagram of an output circuit provided in an embodiment of the present application;

[0060] Figure 8 A circuit diagram of a bandgap reference circuit provided in an embodiment of the present application.

[0061] Icons: 10-bandgap reference circuit; 100-core circuit; 110-first cascade MOS transistor; 200-negative temperature current extraction circuit; 210-second cascade MOS transistor; 300-high-order modulation processing circuit; 310-zero-temperature current generation module; 320-first Wilson current mirror; 330-second Wilson current mirror; 400-output circuit; 410-first current mirror; 420-second current mirror; 500-startup circuit. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0063] In the description of this application, it should be noted that relational terms such as first and second are used solely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. The term "connected" should be understood broadly, for example, it can mean fixed connection, detachable connection, or integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0064] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. The following embodiments and features thereof may be combined with each other unless there is any conflict.

[0065] As mentioned in the background, most existing bandgap reference circuits require amplifiers. These amplifiers not only increase chip area but also affect the accuracy of the voltage reference due to input offset voltage and noise. Furthermore, current methods for implementing high-order modulated bandgap references are significantly affected by base current, which can easily lead to errors and reduce the accuracy of the bandgap reference.

[0066] In view of this, the present application provides a high-order modulated, amplifier-free bandgap reference with a low temperature coefficient that offsets most base current effects. High-order modulation is performed based on the temperature characteristics of the transistor's base-emitter voltage. A negative temperature current extraction circuit and two Wilson current mirrors eliminate the effects of the base current, eliminating the error caused by the reduced current gain β of the transistor at low temperatures, ultimately producing a low-temperature-coefficient bandgap reference voltage.

[0067] See also Figure 1 An embodiment of the present application provides a bandgap reference circuit 10 , including: a core circuit 100 , a negative temperature current extraction circuit 200 , a high-order modulation processing circuit 300 and an output circuit 400 .

[0068] The first port of the negative temperature current extraction circuit 200 and the first port of the high-order modulation processing circuit 300 are both connected to point X in the core circuit 100. The second port and the third port of the high-order modulation processing circuit 300 are connected to the second port of the negative temperature current extraction circuit 200 and the first port of the core circuit 100, respectively. The output of the high-order modulation processing circuit 300 is connected to the output circuit 400.

[0069] The core circuit 100 is configured to generate a point X voltage, a positive temperature coefficient (PTAT) current without a base current, and a negative temperature coefficient (CTAT) current mixed with a base current. The point X voltage is the base-emitter voltage of a transistor in the core circuit 100 through which the PTAT current flows.

[0070] The negative temperature current extraction circuit 200 is used to extract the CTAT current without the base current according to the voltage at point X.

[0071] The high-order modulation processing circuit 300 is used to generate a bandgap reference current I after high-order modulation and eliminating the influence of base current and the influence of transistor β reduction at low temperature based on the X-point voltage and PTAT current provided by the core circuit 100 and the CTAT current provided by the negative temperature current extraction circuit 200. ref .

[0072] The output circuit 400 is used to convert the bandgap reference current I ref Converted to bandgap reference voltage V ref Then output.

[0073] Furthermore, to enable the bandgap reference circuit 10 to escape the degenerate state of zero current, the bandgap reference circuit 10 also includes a startup circuit 500. A first port of the startup circuit 500 is connected to the core circuit 100, a second port of the startup circuit 500 is connected to the negative temperature current extraction circuit 200, and an input terminal of the startup circuit 500 is connected to the power supply VDD. The startup circuit 500 is used to start the core circuit 100 and the negative temperature current extraction circuit 200, and stops operation when the bandgap reference circuit 10 outputs normally.

[0074] In order to better understand the technical solution of the present application, the specific structures and working principles of the core circuit 100, the negative temperature current extraction circuit 200, the startup circuit 500, the high-order modulation processing circuit 300 and the output circuit 400 will be described in turn below.

[0075] See also Figure 2 In the embodiment of the present application, the core circuit 100 includes: Q0, Q1, Q2, Q3, Q4, PM0, PM1, PM2, PM3, PM23, PM24, PM25, NM4, resistor R0, resistor R1 and a first cascade MOS transistor 110.

[0076] Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the number of Q0 transistors connected in parallel is greater than the number of Q1 transistors connected in parallel. Optionally, the number m of Q0 transistors connected in parallel is 8 times the number m of Q1 transistors connected in parallel.

[0077] PM0, PM1, PM2, PM3, PM23, PM24, and PM25 are all PMOS tubes, and NM4 is an NMOS tube.

[0078] The connection relationship between the components of the core circuit 100 is as follows:

[0079] The sources of PM0, PM1, PM2, PM3, and the first cascade MOS transistor 110 are all connected to the power supply VDD. The sources of PM25, PM24, and PM23 are connected to the drains of PM3, PM0, and PM2, respectively. The gates of PM25, PM24, and PM23 are all connected to the gate of the first cascade MOS transistor 110. The gates of PM3, PM0, and PM23 are all connected to the gate of PM2. The gate of PM2 serves as the first port of the core circuit 100.

[0080] The drain of PM25 is connected to the collector of Q3. The drain of PM24 is connected to the gate of PM1 and the collector of Q0. The drain of PM23 is also connected to the drain of NM4. The gate of NM4 is connected to the collector of Q3. The source of NM4 is connected to the base of Q3 and the collector of Q2. The drain of the first cascade MOS transistor 110 is connected to the collector of Q4.

[0081] The emitters of transistors Q0, Q1, Q2, Q3, and Q4 are all grounded. The bases of transistors Q1, Q2, and Q4 are all connected to point X. The collector of transistor Q1 is connected to the base of transistor Q0 and one end of resistor R0, respectively. The other end of resistor R0 is connected to the drain of transistor PM1 and point X, respectively. One end of resistor R1 is grounded, and the other end of resistor R1 is connected to point X.

[0082] Furthermore, the first cascade MOS transistor 110 includes: a PM32 transistor, a PM33 transistor, a PM34 transistor, and a PM35 transistor, wherein the PM32 transistor, the PM33 transistor, the PM34 transistor, and the PM35 transistor are all PMOS transistors.

[0083] The source of transistor PM32 serves as the source of first cascade MOS transistor 110 and is connected to power supply VDD. The drain of transistor PM32 is connected to the source of transistor PM33, the drain of transistor PM33 is connected to the source of transistor PM34, and the drain of transistor PM34 is connected to the source of transistor PM35. The gates of transistor PM32, PM33, PM34, PM35, and PM35 are connected and serve as the gate of first cascade MOS transistor 110. The drain of transistor PM35 is also connected to the collector of transistor Q4.

[0084] The working principle of the core circuit 100 is as follows:

[0085] In the core circuit 100, Q1, Q2, and Q4 form a transistor current mirror, and PM3, PM0, and PM2 form a PMOS transistor current mirror. Ignoring the transistor base current, the transistor collector current and emitter current are equal. At this point, the Q1, Q2, Q4 current mirror and the PM3, PM0, PM2 current mirror make the currents of Q0, Q1, Q2, Q3, and Q4 equal. The number of Q0 connected in parallel is 8 times that of Q1, and the voltage difference V across the resistor R0 is 0. RO = Q0’s base-emitter voltage V be0 and Q1’s base-emitter voltage V be1 The difference, V R0 =V be0 -V be1 =V T ln 8, so the current flowing through R0 Among them, V T= is the thermal voltage, which increases with temperature. Therefore, the current flowing through R0 is the PTAT current. Q4 copies the PTAT current to PM32-PM35 to generate the bias voltage Vb1 required by the MOS transistor current mirror.

[0086] The voltage at point X is unique when the currents of Q0 and Q1 are equal and non-zero. Assuming that the voltage at point X is V1 at this time, analysis shows that: when the voltage at point X is greater than V1, the current of Q0 is less than the current of Q1; when the voltage at point X is less than V1, the current of Q0 is greater than the current of Q1.

[0087] It's important to note that the currents in Q0 and Q1 remain equal, and the voltage at point X remains at V1, thanks to the negative feedback path of PM1. If the voltage at point X is less than V1, the current in Q0 will be greater than the currents in Q1 and Q2, causing the gate voltage of PM1 to drop, increasing the current in PM1 and raising the voltage at point X to V1. Conversely, if the voltage at point X exceeds V1, the negative feedback path of PM1 will also lower the voltage at point X to V1.

[0088] Now consider the base current. Because Q0 draws a base current from the PTAT current flowing through R0, Q3 also draws the same base current from Q2, making Q2's collector voltage equal to Q1's, ensuring accurate replication of the PTAT current. By configuring NM4 to prevent a direct connection between Q3's base and PM2's gate, PM2's gate voltage can vary over a wide range solely with Q2's current, providing freedom for the PM2 current mirror.

[0089] And, since the base-emitter voltage V be Since the voltage has a negative temperature coefficient, connecting resistor R1 between point X and ground will produce a current with a negative temperature coefficient, i.e., the CTAT current. At this point, the PTAT current, the CTAT current, and the quadruple base current (i.e., the base currents of Q0, Q1, Q2, and Q4) will converge at PM1.

[0090] In order to eliminate the influence of the base current, the present application strips off the base current through the negative temperature current extraction circuit 200 , thereby providing a clean CTAT current (ie, a CTAT current without the base current) for the high-order modulation processing circuit 300 .

[0091] The following will be combined Figure 3 The specific structure and working principle of the negative temperature current extraction circuit 200 are described.

[0092] like Figure 3 As shown, in the embodiment of the present application, the negative temperature current extraction circuit 200 includes: PM4 tube, PM5 tube, PM6 tube, PM30 tube, PM31 tube, NM0 tube, NM1 tube, NM2 tube, NM3 tube, resistor R2, resistor R3, resistor R4 and a second cascade MOS tube 210.

[0093] Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes.

[0094] The sources of transistors PM4, PM5, PM6, and the second cascade MOS transistor 210 are all connected to the power supply VDD. The drains of transistors PM4 and PM5 are connected to the sources of transistors PM30 and PM31, respectively. The gates of transistors PM30 and PM31 are both connected to the gate of the second cascade MOS transistor 210. The gate of transistor PM4 and the drain of transistor PM31 are both connected to the gate of transistor PM5. The gate of transistor PM5 serves as the second port of negative temperature current extraction circuit 200.

[0095] The drain of the second cascade MOS transistor 210 is connected to the drain of the NM3 transistor, the drain of the PM6 transistor is connected to the drain of the NM0 transistor and the gate of the NM0 transistor respectively, the drain of the PM30 transistor is connected to the gate of the PM6 transistor and the drain of the NM1 transistor respectively, and the drain of the PM31 transistor is also connected to the drain of the NM2 transistor.

[0096] The gates of transistors NM3, NM1, and NM2 are all connected to the gate of transistor NM0. The source of transistor NM3 is grounded via resistor R4. The source of transistor NM0 is grounded via resistor R3. The source of transistor NM1 is grounded via resistor R2. The source of transistor NM2 is connected to point X. The source of transistor NM2 serves as the first port of negative temperature current extraction circuit 200.

[0097] Furthermore, the second cascade MOS transistor 210 includes: a PM26 transistor, a PM27 transistor, a PM28 transistor, and a PM29 transistor, wherein PM26 transistor, PM27 transistor, PM28 transistor, and PM29 transistor are all PMOS transistors.

[0098] The source of transistor PM26 is connected to power supply VDD, serving as the source of second cascade MOS transistor 210. The drain of transistor PM26 is connected to the source of transistor PM27, the drain of transistor PM27 is connected to the source of transistor PM28, and the drain of transistor PM28 is connected to the source of transistor PM29. The gates of transistor PM26, PM27, PM28, PM29, and PM29 are connected to serve as the gate of second cascade MOS transistor 210. The drain of transistor PM29 is also connected to the drain of transistor NM3.

[0099] Next, Figure 3Explain points L, N, J, Y, and K in the diagram. The gate of PM6, the drain of PM30, and the drain of NM1 are all connected to point L. The gates of PM4, PM5, and PM31 are all connected to point N. The gate of NM3, the gate of NM0, the drain of NM0, the drain of PM6, the gate of NM1, and the gate of NM2 are all connected to point Y. Point J is the source of NM0, and point K is the source of NM1.

[0100] It should be noted that the types and resistance values ​​of resistors R1-R4 are the same. Assuming the resistance value is R C , that is, R1=R2=R3=R4=R C . In addition, PM4-PM6 are equal in size, and NM0-NM3 are equal in size.

[0101] The negative temperature current extraction circuit 200 can copy the voltage at point X to point K and make the current flowing through PM5 fixed to V X / R C The current (i.e. CTAT current excluding base current) is analyzed as follows:

[0102] First assume that the currents of the current mirror are equal, that is, the current mirror can make the currents of NM2, PM5, PM4, and NM1 equal. Because the gate of NM1 is connected to the gate of NM2, the source voltage of NM1 = the source voltage of NM2 = the voltage at point X, so the current of NM1 = V X / R2=V X / R C , and the current of NM2 = V X / R C This requires that the voltage at point Y controlled by NM0 = V X +V gs (Wherein, V gs is the current V X / R C =the gate-source voltage when current flows through NM1). This means that the voltage at point Y changes with the voltage at point X according to this equation. PM6 is designed to maintain this relationship. Considering the channel length modulation effect, the previously assumed equal currents in PM4 and PM5 mean that the voltage at point L equals the voltage at point N. The voltage at point L then serves as the gate voltage for PM6, and the PM6 current = the PM4 current. This allows the NM0 current = the NM1 current = the NM2 current = V X / R C , the voltage at point J also copies the voltage at point X, so the voltage at point Y can always remain equal to V X +V gs Therefore, NM2 can extract V under the assumption that the current mirror current is equal. X / R C Current, that is, the CTAT current excluding the base current.

[0103] Now we no longer assume that the current mirror currents are equal. Assume that the voltage offset at point L causes the voltage at point L to be less than the voltage at point N, meaning that at this point the current mirror's PM5 current is less than the current PM4 current. Then the current at PM6 will be greater than the current in the "assumed" state (that is, when the current mirror currents were assumed to be equal), the voltage at point Y will rise relative to the "assumed" state, and the current in NM2 will increase. If the gate voltage of PM1 remains unchanged at this time, the current in PM1 will remain unchanged, and the voltage at point X will have to rise due to the increase in the voltage at point Y. The voltage at point X will then exceed voltage V1 (that is, the voltage at point X when the currents in Q0 and Q1 are equal and non-zero), and the current in Q0 will be less than that in Q2. This will cause the gate voltage of PM1 to increase and the current in PM1 to decrease. As the voltage at point X increases, the currents in Q1 and R1 both increase, while the current in PM1 decreases, so the current flowing through NM2 will be greater than V at this time. X / R1, that is, greater than V X / R C The current of NM2 will be greater than the current of NM1, the reason is as follows:

[0104] Assumption: NMOS tube

[0105] Then the current I of NM2 NM2 =K N (V Y -V X -V TH,N ) 2 >V X / R C ,

[0106] The current I of NM1 NM1 =K N (V Y -V K -V TH,N ) 2 =V K / R C ,

[0107] After finishing, we can get:

[0108] That is V K >V X , that is, the gate-source voltage of NM1 is smaller than that of NM2, and the current flowing through NM2 will be larger than that of NM1, so the current of PM4 is smaller than that of PM5, PM4 enters the linear region, the voltage at point L rises, and negative feedback is established. Conversely, if the voltage at point L is larger than that at the "assumption time", it will be pulled back to be equal to the voltage at point N due to negative feedback, so that NM2 can extract V fixedly. X / R C electric current.

[0109] That is to say, even if the currents of the current mirrors (PM4-PM5, NM1-NM2) are temporarily unequal due to unknown interference, they will be equal due to negative feedback, and then the voltage at point K will be equal to the voltage at point X, so that NM2 can extract V X / R C Current, that is, the CTAT current excluding the base current.

[0110] NM3 copies the CTAT current to PM26-PM29 to generate the bias voltage Vb required by the current mirror.

[0111] The following combination Figure 4 The specific structure and working principle of the starting circuit 500 are described.

[0112] like Figure 4 As shown, in this embodiment of the present application, core circuit 100 further includes a resistor Rs1. One end of resistor Rs1 is connected to point X, and the other end of resistor Rs1 is connected to the drain of transistor PM1 and the first port of startup circuit 500, respectively. The second port of startup circuit 500 is connected to the gate of transistor PM6, the drain of transistor PM30, and the drain of transistor NM1, respectively. The input of startup circuit 500 is connected to power supply VDD.

[0113] Furthermore, the startup circuit 500 includes: a Q13 transistor, an NMs1 transistor, an NMs2 transistor, a resistor Rs2, a resistor Rs3, and a capacitor C1. The Q13 transistor is an NPN transistor, and the NMs1 transistor and the NMs2 transistor are both NMOS transistors.

[0114] One end of resistor Rs3 is connected to power supply VDD, and the other end is connected to the drain of transistor NMs1, the gate of transistor NMs1, and the gate of transistor NMs2. The source of transistor NMs1 is connected to the collector of transistor Q13 and the base of transistor Q13, respectively. The emitter of transistor Q13 is grounded.

[0115] The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1. The drain of NMs2 is connected to the gate of PM6, the drain of PM30, and the drain of NM1. The drain of NMs2 is also connected to one end of resistor Rs2. The other end of resistor Rs2 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded.

[0116] The operating principle of the startup circuit 500 is as follows:

[0117] By adding resistor Rs1, the source of NMs2 can obtain a voltage higher than V be (i.e., the base-emitter voltage of Q1 and Q2) r , to facilitate the final shutdown of the startup circuit 500.

[0118] When power supply VDD is not zero and startup circuit 500 is not yet operational, the entire bandgap reference circuit 10 has no current, point L is at high voltage, and C1 is energized by VDD. After adding startup circuit 500, the gate voltage of NMs1 increases due to VDD, causing current to flow from point L to point X in NMs2.

[0119] Since PM4 is not turned on yet, the current of NMs2 comes from capacitor C1. As the energy of C1 decreases, the potential of point L is pulled down. PM6 starts to have current, which makes the potential of point Y increase, and the bias circuit of Vb starts to work. At the same time, NM2 starts to flow current, and the current mirror from PM5 to PM4 works. Capacitor C1 gradually no longer needs to bear the current of NMs2. The negative temperature current extraction circuit 200 starts to work, and NM2 extracts V from point X. X / R C electric current.

[0120] The current flowing from NM2 to point X causes the voltage at point X to rise. However, at this point, the voltage at point X is still lower than the stable value. Then, due to the advantage of the parallel number of 8, the current of Q0 will be greater than that of Q2. The gate voltage of PM1 will begin to decrease, and the current required by PM1 will increase. The current required by NM2 will also increase, which will force the potential at point X to rise until it reaches the preset stable state. Before reaching the preset stable state, V r The potential also rises. When it exceeds the turn-on condition of NMs2, NMs2 turns off, and startup circuit 500 turns off. At this point, the current requirements of PM1 and NM2 are still not met, and the voltage at point X continues to increase until it reaches a predetermined steady state, successfully starting bandgap reference circuit 10.

[0121] See also Figure 5 In the embodiment of the present application, the high-order modulation processing circuit 300 includes: a resistor R NL , a zero-temperature current generating module 310 , a first Wilson current mirror 320 and a second Wilson current mirror 330 .

[0122] The first input terminal of the zero-temperature current generation module 310 is connected to the second port of the negative temperature current extraction circuit 200, and the second input terminal of the zero-temperature current generation module 310 is connected to the first port of the core circuit 100. The first output terminal of the zero-temperature current generation module 310 is connected to the first port of the first Wilson current mirror 320, the second output terminal of the zero-temperature current generation module 310 is connected to the first port of the second Wilson current mirror 330, and the third output terminal of the zero-temperature current generation module 310 is connected to the second port of the first Wilson current mirror 320 and the second port of the second Wilson current mirror 330 respectively. The second port of the second Wilson current mirror 330 is also connected to the output circuit 400. The resistor R NL One end of the resistor R is connected to point X in the core circuit 100.NL The other end of is connected to point Z in the first Wilson current mirror 320 .

[0123] The zero temperature current generating module 310 is used to provide a zero temperature coefficient ZTAT current (i.e., I outputted from the first output terminal) to the first Wilson current mirror 320 and the second Wilson current mirror 330 according to the PTAT current and the CTAT current. ZTAT1 , the second output terminal outputs I ZTAT2 and the third output terminal outputs I ZTAT3 ).

[0124] Resistor R NL Provides a high-order modulation current I to the first Wilson current mirror 320 according to the voltage at point X and the voltage at point Z. NL Among them, I NL =(voltage at point X - voltage at point Z) / R NL The voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror 320 through which the ZTAT current flows.

[0125] The first Wilson current mirror 320 and the second Wilson current mirror 330 are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of the base current and the reduction of the transistor current gain β at low temperature according to the ZTAT current and the high-order modulation current.

[0126] In order to better understand the principle of high-order modulation, the formula for the base-emitter voltage of the transistor is first introduced below.

[0127]

[0128] Among them, T r is the reference temperature, V bg (T r ) is T r The bandgap voltage at different temperatures is considered to be a constant. η is a constant that is independent of temperature but is process-dependent. The coefficient x represents the temperature-dependent characteristics of the current flowing through the transistor. If it is a PTAT current, then x = 1. If it is a temperature-independent current (i.e., ZTAT current), then x = 0. It can be seen that the base-emitter voltage V be The first term of (T) is a constant term to be retained, the second term is a first-order term eliminated by the zero-temperature current generation module 310, and the third term is a high-order term that needs to be reduced by high-order modulation.

[0129] The high-order terms can be extracted by taking advantage of the fact that the coefficient x changes with the current characteristics. The difference between the emitter-base voltage of the transistor with PTAT current flowing (i.e., the voltage at point X) and the emitter-base voltage of the transistor with ZTAT current flowing (i.e., the voltage at point Z) is equal to The resistor RNL The current generated on the high-order modulation current is the high-order modulation current

[0130] Further, see Figure 6 The zero-temperature current generating module 310 includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube, and a PM22 tube.

[0131] Among them, PM7 tube, PM8 tube, PM9 tube, PM10 tube, PM11 tube, PM12 tube, PM17 tube, PM18 tube, PM19 tube, PM20 tube, PM21 tube and PM22 tube are all PMOS tubes.

[0132] The number of PM7 tubes connected in parallel = the number of PM22 tubes connected in parallel = the number of PM10 tubes connected in parallel = the number of PM20 tubes connected in parallel = the number of PM9 tubes connected in parallel = the number of PM17 tubes connected in parallel = the number of PM12 tubes connected in parallel = the number of PM18 tubes connected in parallel = a. The number of PM8 tubes connected in parallel = the number of PM21 tubes connected in parallel = the number of PM11 tubes connected in parallel = the number of PM19 tubes connected in parallel = b. Where a and b are both positive integers, and b>2a. Optionally, a=1, b=M, where M is a positive integer greater than 2.

[0133] The sources of transistors PM7, PM8, PM9, PM10, PM11, and PM12 are all connected to the power supply VDD. The gates of transistors PM7, PM8, and PM9 are all connected to the gate of transistor PM2. The drains of transistors PM7, PM8, and PM9 are respectively connected to the sources of transistors PM22, PM21, and PM17. The gates of transistors PM22, PM21, and PM17 are all connected to the gate of first cascade MOS transistor 110.

[0134] The gates of the PM10, PM11, and PM12 transistors are all connected to the gate of the PM5 transistor. The drains of the PM10, PM11, and PM12 transistors are respectively connected to the sources of the PM20, PM19, and PM18 transistors. The gates of the PM20, PM19, and PM18 transistors are all connected to the gate of the second cascade MOS transistor 210.

[0135] The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module 310 and are connected to the first port of the first Wilson current mirror 320. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module 310 and are connected to the first port of the second Wilson current mirror 330. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module 310 and are respectively connected to the second port of the first Wilson current mirror 320 and the second port of the second Wilson current mirror 330.

[0136] Furthermore, the first Wilson current mirror 320 includes transistors NM5, Q5, Q6, Q11, and Q12. The second Wilson current mirror 330 includes transistors NM6, Q7, Q8, Q9, and Q10.

[0137] Among them, NM5 and NM6 are NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are NPN transistors.

[0138] The collector of Q12 is connected to the first output terminal of the zero-temperature current generating module 310 and the gate of NM5, the drain of NM5 is connected to the third output terminal of the zero-temperature current generating module 310, the source of NM5 is connected to the collector of Q6, the base of Q6 and the base of Q12, the emitter of Q6 is connected to the collector of Q5. The emitter of Q12, the collector of Q11, the base of Q11, the base of Q5 and the resistor R are connected. NL One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded.

[0139] The drain of transistor NM6 is connected to the third output terminal of the zero-temperature current generation module 310 and the output circuit 400, respectively. The source of transistor NM6 is connected to the collector of transistor Q7. The collector of transistor Q10 is connected to the second output terminal of the zero-temperature current generation module 310, the gate of transistor NM6, the base of transistor Q10, and the base of transistor Q7, respectively. The emitter of transistor Q10 is connected to the collector of transistor Q9, and the emitter of transistor Q7 is connected to the collector of transistor Q8, the base of transistor Q8, and the base of transistor Q9, respectively. The emitters of transistors Q8 and Q9 are both grounded.

[0140] The working principle of the high-order modulation processing circuit 300 is as follows:

[0141] Since PM7, PM8, and PM9 all form a current mirror with PM2, and PM10, PM11, and PM12 all form a current mirror with PM5, PM7, PM8, and PM9 all copy the PTAT current, and PM10, PM11, and PM12 all copy the CTAT current.

[0142] The PTAT current flowing through PM8 and the CTAT current flowing through PM11 converge at the third output terminal of the zero temperature current generating module 310 to form M times ZTAT current, i.e., I ZTAT3 The PTAT current flowing through PM7 and the CTAT current flowing through PM10 merge at the first output terminal of the zero temperature current generating module 310 to form a ZTAT current, ie, I ZTAT1 Similarly, the second output terminal of the zero temperature current generating module 310 also outputs a ZTAT current, ie, I ZTAT2 Among them, I ZTAT3 =MI ZTAT1 =MI ZTAT2 Since PM7 and PM10 combine to form the ZTAT current (i.e., I ZTAT1 ) flows through Q11, so the voltage at point Z is the base-emitter voltage of Q11.

[0143] The Wilson current mirror used in this application can eliminate most of the base current compared to the ordinary current mirror, but there will still be errors. For example, in the first Wilson current mirror 320, I1 will be larger than I ZTAT1 many The current is due to the following reasons (assuming that there is no resistor R NL , and the following I Q are the collector currents of the transistors, I b1 is the base current of transistor Q11 or Q5, I b2 is the base current of transistor Q12 or Q6):

[0144] I Q11 =I Q5 =βI b1

[0145]

[0146] It can be seen that I1 is larger than I ZTAT1 More When β is large (β = 70 at room temperature), this error has almost no effect. However, at low temperatures, β decreases. For example, at -40°C, β = 30, which results in an error of 4 / 900, which is unacceptable for a bandgap reference.

[0147] In order to eliminate the error caused by the reduction of transistor β at low temperature, the embodiment of the present application adds a second Wilson current mirror 330 which is symmetrical to the first Wilson current mirror 320. Figure 6 This symmetrical circuit structure can offset the error. In addition, Q11 gets the ZTAT current plus the high-order current I NL , and the output requires ZTAT current minus INL , so a current subtraction is required. The specific analysis is as follows:

[0148] As mentioned above, in the absence of resistor R NL In case of:

[0149]

[0150] Then, after adding the resistor R NL In case of:

[0151]

[0152] If we ignore NM5 and NM6, the Q7Q8Q9Q10 structure is the same as the Q5Q6Q11Q12 structure, so:

[0153]

[0154] because and are approximately equal, and:

[0155] I ref =I ZTAT3 -I1-I2

[0156] I ZTAT3 =MI ZTAT1 =MI ZTAT2

[0157] so:

[0158] I ref =I ZTAT3 -I ZTAT1 -I ZTAT2 -I NL =(M-2)*ZTAT current-I NL

[0159] Wherein, M is a positive integer greater than 2. That is, the bandgap reference current I finally output by the high-order modulation processing circuit 300 is ref Equal to (M-2) times the ZTAT current minus the high-order modulation current I NL .in, Since R NL The value of is related to the process constant η, R NL Without reducing I NL In the case of , it is usually designed to be large, and here the M value can be reduced I NL The proportion of the value, the appropriate M value can reduce R NL design value to prevent the resistor from occupying too large a layout area.

[0160] Based on the above design, a bandgap reference current I is obtained after high-order modulation and elimination of the influence of base current and the influence of transistor β reduction at low temperature. ref At this time, it is also necessary to convert it into a bandgap reference voltage V through the output circuit 400 ref Then output.

[0161] See also Figure 7 In the embodiment of the present application, the output circuit 400 includes: a first current mirror 410, a second current mirror 420 and a resistor R OUT .

[0162] The first port of the first current mirror 410 is connected to the output terminal of the high-order modulation processing circuit 300, the second port of the first current mirror 410 is connected to the third port of the second current mirror 420, the third port and the fourth port of the first current mirror 410 are both grounded, and the first port and the second port of the second current mirror 420 are both connected to the power supply VDD. OUT One end of the resistor R is grounded. OUT The other end of is connected to the fourth port of the second current mirror 420 as the output end of the bandgap reference circuit 10.

[0163] Furthermore, the first current mirror 410 includes NM7, NM8, NM9 and NM10, and the second current mirror 420 includes PM13, PM14, PM15 and PM16. NM7, NM8, NM9 and NM10 are all NMOS transistors, and PM13, PM14, PM15 and PM16 are all PMOS transistors.

[0164] The drain of NM7 is connected to the output terminal of the high-order modulation processing circuit 300, the gate of NM7, and the gate of NM8. The source of NM7 is connected to the drain of NM9, the gate of NM9, and the gate of NM10, respectively. The sources of NM9 and NM10 are both grounded. The source of NM8 is connected to the drain of NM10, and the drain of NM8 is connected to the drain of PM15, the gate of PM15, and the gate of PM16, respectively.

[0165] The source of PM15 is connected to the drain of PM13, the gate of PM13 and the gate of PM14 respectively. The source of PM13 and the source of PM14 are both connected to the power supply VDD. The drain of PM14 is connected to the source of PM16. OUT One end is grounded, R OUT The other end is connected to the drain of PM16 as the output end of the bandgap reference circuit 10.

[0166] The bandgap reference current I ref Accurately copy the resistor R OUT On, through ROUT I can ref Converted to bandgap reference voltage V ref Output.

[0167] See also Figure 8 , Figure 8 This is a schematic diagram of the overall circuit of the bandgap reference circuit 10 provided in an embodiment of the present application. The bandgap reference circuit of the aforementioned structure has been verified to exhibit a 675uV output voltage variation of 1.154V at an average temperature range of -40 to 125°C, with a temperature coefficient of 3.4ppm / °C. This means that the bandgap reference circuit 10 provided in an embodiment of the present application can generate a bandgap reference voltage with a low temperature coefficient after undergoing high-order modulation and eliminating the effects of base current and transistor β reduction at low temperatures.

[0168] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0169] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A bandgap reference circuit, characterized in that: include: Core circuit, negative temperature current extraction circuit, high-order modulation processing circuit and output circuit; The first port of the negative temperature current extraction circuit and the first port of the high-order modulation processing circuit are both connected to point X in the core circuit, the second port and the third port of the high-order modulation processing circuit are connected to the second port of the negative temperature current extraction circuit and the first port of the core circuit respectively, and the output end of the high-order modulation processing circuit is connected to the output circuit; The core circuit is used to generate a point X voltage, a positive temperature coefficient PTAT current without a base current, and a negative temperature coefficient CTAT current mixed with a base current; wherein the point X voltage is the base-emitter voltage of the transistor in the core circuit through which the PTAT current flows; The negative temperature current extraction circuit is used to extract the CTAT current without the base current according to the voltage at point X; The high-order modulation processing circuit is used to generate a bandgap reference current that has undergone high-order modulation and eliminated the influence of the base current according to the X-point voltage and PTAT current provided by the core circuit and the CTAT current provided by the negative temperature current extraction circuit; The output circuit is used to convert the bandgap reference current into a bandgap reference voltage and then output it; The core circuit includes: Q0 tube, Q1 tube, Q2 tube, Q3 tube, Q4 tube, PM0 tube, PM1 tube, PM2 tube, PM3 tube, PM23 tube, PM24 tube, PM25 tube, NM4 tube, resistor R0, resistor R1 and a first cascade MOS tube; Among them, Q0, Q1, Q2, Q3 and Q4 are all NPN transistors, and the number of Q0 transistors connected in parallel is greater than the number of Q1 transistors connected in parallel; PM0, PM1, PM2, PM3, PM23, PM24 and PM25 are all PMOS transistors, and NM4 is an NMOS transistor; The sources of the PM0, PM1, PM2, PM3, and first cascade MOS transistors are all connected to the power supply; the sources of the PM25, PM24, and PM23 transistors are respectively connected to the drains of the PM3, PM0, and PM2 transistors; the gates of the PM25, PM24, and PM23 transistors are all connected to the gate of the first cascade MOS transistor; the gate of the PM3 transistor, the gate of the PM0 transistor, and the drain of the PM23 transistor are all connected to the gate of the PM2 transistor; wherein the gate of the PM2 transistor serves as the first port of the core circuit; The drain of PM25 is connected to the collector of Q3. The drain of PM24 is connected to the gate of PM1 and the collector of Q0. The drain of PM23 is also connected to the drain of NM4. The gate of NM4 is connected to the collector of Q3. The source of NM4 is connected to the base of Q3 and the collector of Q2. The drain of the first cascade MOS tube is connected to the collector of Q4. The emitters of tubes Q0, Q1, Q2, Q3, and Q4 are all grounded, the bases of tubes Q1, Q2, and Q4 are all connected to the point X, the collector of tube Q1 is respectively connected to the base of tube Q0 and one end of resistor R0, the other end of resistor R0 is respectively connected to the drain of tube PM1 and the point X, one end of resistor R1 is grounded, and the other end of resistor R1 is connected to point X.

2. The bandgap reference circuit according to claim 1, wherein: The negative temperature current extraction circuit includes: a PM4 tube, a PM5 tube, a PM6 tube, a PM30 tube, a PM31 tube, an NM0 tube, an NM1 tube, an NM2 tube, an NM3 tube, a resistor R2, a resistor R3, a resistor R4 and a second cascade MOS tube; Among them, PM4, PM5, PM6, PM30 and PM31 are all PMOS tubes, and NM0, NM1, NM2 and NM3 are all NMOS tubes; The sources of the PM4, PM5, PM6, and second cascade MOS transistors are all connected to the power supply; the drains of the PM4 and PM5 transistors are connected to the sources of the PM30 and PM31 transistors, respectively; the gates of the PM30 and PM31 transistors are both connected to the gate of the second cascade MOS transistor; the gate of the PM4 transistor and the drain of the PM31 transistor are both connected to the gate of the PM5 transistor; wherein the gate of the PM5 transistor serves as the second port of the negative temperature current extraction circuit; The drain of the second cascade MOS tube is connected to the drain of the NM3 tube, the drain of the PM6 tube is connected to the drain of the NM0 tube and the gate of the NM0 tube respectively, the drain of the PM30 tube is connected to the gate of the PM6 tube and the drain of the NM1 tube respectively, and the drain of the PM31 tube is also connected to the drain of the NM2 tube; The gates of transistors NM3, NM1, and NM2 are all connected to the gate of transistor NM0; the source of transistor NM3 is grounded via resistor R4, the source of transistor NM0 is grounded via resistor R3, the source of transistor NM1 is grounded via resistor R2, and the source of transistor NM2 is connected to point X; wherein the source of transistor NM2 serves as the first port of the negative temperature current extraction circuit.

3. The bandgap reference circuit according to claim 2, wherein: The first cascade MOS transistors include: PM32, PM33, PM34 and PM35; the second cascade MOS transistors include: PM26, PM27, PM28 and PM29; Among them, PM32, PM33, PM34, PM35, PM26, PM27, PM28 and PM29 are all PMOS tubes; The source of the PM32 transistor is connected to the power supply as the source of the first cascade MOS transistor. The drain of the PM32 transistor is connected to the source of the PM33 transistor. The drain of the PM33 transistor is connected to the source of the PM34 transistor. The drain of the PM34 transistor is connected to the source of the PM35 transistor. The gate of the PM32 transistor, the gate of the PM33 transistor, the gate of the PM34 transistor, the gate of the PM35 transistor, and the drain of the PM35 transistor are connected to serve as the gate of the first cascade MOS transistor. The drain of the PM35 transistor is also connected to the collector of the Q4 transistor. The source of transistor PM26 is connected to the power supply as the source of the second cascade MOS transistor, the drain of transistor PM26 is connected to the source of transistor PM27, the drain of transistor PM27 is connected to the source of transistor PM28, and the drain of transistor PM28 is connected to the source of transistor PM29; the gate of transistor PM26, the gate of transistor PM27, the gate of transistor PM28, the gate of transistor PM29, and the drain of transistor PM29 are connected to serve as the gate of the second cascade MOS transistor; the drain of transistor PM29 is also connected to the drain of transistor NM3.

4. The bandgap reference circuit according to claim 2, wherein: The high-order modulation processing circuit includes: a resistor , a zero-temperature current generating module, a first Wilson current mirror, and a second Wilson current mirror; The first input end of the zero-temperature current generating module is connected to the second port of the negative temperature current extraction circuit, and the second input end of the zero-temperature current generating module is connected to the first port of the core circuit; the first output end of the zero-temperature current generating module is connected to the first port of the first Wilson current mirror, the second output end of the zero-temperature current generating module is connected to the first port of the second Wilson current mirror, the third output end of the zero-temperature current generating module is respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror, and the second port of the second Wilson current mirror is also connected to the output circuit; the resistor One end of the resistor is connected to the X point in the core circuit. The other end is connected to point Z in the first Wilson current mirror; The zero temperature current generating module is used to provide a zero temperature coefficient ZTAT current to the first Wilson current mirror and the second Wilson current mirror according to the PTAT current and the CTAT current; The resistor for providing a high-order modulation current to the first Wilson current mirror according to the voltage at point X and the voltage at point Z; wherein the voltage at point Z is the base-emitter voltage of the transistor in the first Wilson current mirror through which the ZTAT current flows; The first Wilson current mirror and the second Wilson current mirror are used to generate a bandgap reference current that has undergone high-order modulation and eliminates the influence of base current and the influence of transistor current gain reduction at low temperature according to the ZTAT current and the high-order modulation current.

5. The bandgap reference circuit according to claim 4, wherein: The zero-temperature current generation module includes: a PM7 tube, a PM8 tube, a PM9 tube, a PM10 tube, a PM11 tube, a PM12 tube, a PM17 tube, a PM18 tube, a PM19 tube, a PM20 tube, a PM21 tube and a PM22 tube; Among them, PM7, PM8, PM9, PM10, PM11, PM12, PM17, PM18, PM19, PM20, PM21, and PM22 are all PMOS tubes; The number of PM7 tubes in parallel = the number of PM22 tubes in parallel = the number of PM10 tubes in parallel = the number of PM20 tubes in parallel = the number of PM9 tubes in parallel = the number of PM17 tubes in parallel = the number of PM12 tubes in parallel = the number of PM18 tubes in parallel = a, the number of PM8 tubes in parallel = the number of PM21 tubes in parallel = the number of PM11 tubes in parallel = the number of PM19 tubes in parallel = b, where a and b are both positive integers, and b>2a; The sources of the PM7, PM8, PM9, PM10, PM11, and PM12 transistors are all connected to the power supply; the gates of the PM7, PM8, and PM9 transistors are all connected to the gate of the PM2 transistor; the drains of the PM7, PM8, and PM9 transistors are respectively connected to the sources of the PM22, PM21, and PM17 transistors; and the gates of the PM22, PM21, and PM17 transistors are all connected to the gate of the first cascade MOS transistor. The gates of the PM10, PM11, and PM12 transistors are all connected to the gate of the PM5 transistor; the drains of the PM10, PM11, and PM12 transistors are respectively connected to the sources of the PM20, PM19, and PM18 transistors; and the gates of the PM20, PM19, and PM18 transistors are all connected to the gate of the second cascade MOS transistor. The drain of the PM22 tube and the drain of the PM20 tube are connected as the first output end of the zero-temperature current generating module and are connected to the first port of the first Wilson current mirror. The drain of the PM17 tube and the drain of the PM18 tube are connected as the second output end of the zero-temperature current generating module and are connected to the first port of the second Wilson current mirror. The drain of the PM21 tube and the drain of the PM19 tube are connected as the third output end of the zero-temperature current generating module and are respectively connected to the second port of the first Wilson current mirror and the second port of the second Wilson current mirror.

6. The bandgap reference circuit according to claim 4, wherein: The first Wilson current mirror includes: NM5 tube, Q5 tube, Q6 tube, Q11 tube and Q12 tube; the second Wilson current mirror includes: NM6 tube, Q7 tube, Q8 tube, Q9 tube and Q10 tube; Among them, NM5 and NM6 are NMOS tubes, and Q5, Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are NPN transistors; The collector of Q12 tube is connected to the first output terminal of the zero-temperature current generating module and the gate of NM5 tube respectively, the drain of NM5 tube is connected to the third output terminal of the zero-temperature current generating module, the source of NM5 tube is connected to the collector of Q6 tube, the base of Q6 tube and the base of Q12 tube respectively, the emitter of Q6 tube is connected to the collector of Q5 tube; the emitter of Q12 tube, the collector of Q11 tube, the base of Q11 tube, the base of Q5 tube and the resistor One end of each is connected to point Z, and the emitters of Q11 and Q5 are grounded; The drain of the NM6 tube is respectively connected to the third output end of the zero-temperature current generating module and the output circuit, and the source of the NM6 tube is connected to the collector of the Q7 tube; the collector of the Q10 tube is respectively connected to the second output end of the zero-temperature current generating module, the gate of the NM6 tube, the base of the Q10 tube and the base of the Q7 tube; the emitter of the Q10 tube is connected to the collector of the Q9 tube, and the emitter of the Q7 tube is respectively connected to the collector of the Q8 tube, the base of the Q8 tube and the base of the Q9 tube, and the emitters of the Q8 tube and the Q9 tube are both grounded.

7. The bandgap reference circuit according to claim 2, wherein: The core circuit further includes a resistor Rs1, and the bandgap reference circuit further includes a startup circuit; One end of resistor Rs1 is connected to point X, the other end of resistor Rs1 is respectively connected to the drain of transistor PM1 and the first port of the startup circuit, the second port of the startup circuit is respectively connected to the gate of transistor PM6, the drain of transistor PM30, and the drain of transistor NM1, and the input end of the startup circuit is connected to the power supply.

8. The bandgap reference circuit according to claim 7, wherein: The startup circuit includes: Q13, NMs1, NMs2, resistor Rs2, resistor Rs3 and capacitor C1; wherein Q13 is an NPN transistor, and NMs1 and NMs2 are both NMOS transistors; One end of resistor Rs3 is connected to the power supply, and the other end of resistor Rs3 is connected to the drain of transistor NMs1, the gate of transistor NMs1, and the gate of transistor NMs2 respectively; the source of transistor NMs1 is connected to the collector of transistor Q13 and the base of transistor Q13 respectively, and the emitter of transistor Q13 is grounded; The source of NMs2 is connected to the drain of PM1 and one end of resistor Rs1 respectively. The drain of NMs2 is connected to the gate of PM6, the drain of PM30, and the drain of NM1 respectively. The drain of NMs2 is also connected to one end of resistor Rs2. The other end of resistor Rs2 is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. When the bandgap reference circuit outputs normally, the NMs2 transistor is turned off and the startup circuit stops running.

9. The bandgap reference circuit according to claim 1, wherein: The output circuit includes: a first current mirror, a second current mirror and a resistor ; The first port of the first current mirror is connected to the output end of the high-order modulation processing circuit, the second port of the first current mirror is connected to the third port of the second current mirror, the third port and the fourth port of the first current mirror are both grounded, the first port and the second port of the second current mirror are both connected to the power supply, and the resistor One end of the resistor is grounded and The other end is connected to the fourth port of the second current mirror as the output end of the bandgap reference circuit.

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