Voltage regulation control method, device and system, MCU and chipset

Abstract

The invention relates to a voltage regulation control method, device and system, an MCU (Microprogrammed Control Unit) and a chipset. The voltage regulation control method comprises the following steps: receiving a voltage identification command VID sent by a CPU (Central Processing Unit) of an SOC (System On Chip); acquiring the current running state of the CPU; determining a target working voltage corresponding to the CPU in the current running state; based on the current running state of the CPU and the target working voltage, the VID command is converted into a serial voltage identification command (SVID) command, and the SVID command triggers a voltage regulation module (VRM) to regulate the working voltage of the CPU. Therefore, the working voltage adaptive to the actual application scene of the CPU can be provided for the CPU.

Description

Technical Field

[0001] The present disclosure relates to the field of power supply control technology, and in particular to a voltage regulation control method, device and system, MCU and chipset. Background Art

[0002] In modern X86 systems, the CPU supports many low-power technologies. Typical low-power technologies include the processor power state (CPU C state) and processor performance state (CPU P state) specified in the Advanced Configuration and Power Interface (ACPI) specification (SPEC). These technologies require dynamic control of the CPU voltage.

[0003] The voltage regulation control method that has been commonly used in chip design is: the CPU sends a voltage regulation request to the serial voltage identification (English: Serial Voltage Identification, abbreviated as: SVID) master controller (English: MaterController); after receiving the voltage regulation request, the SVID master controller converts the voltage regulation request into a command (English: Command) that complies with the SVID protocol (English: Protocol), and then sends it to the voltage regulation module (English: Voltage Regulator Module, abbreviated as: VRM) through the SVID bus (English: Bus); VRM receives the command and cooperates with the external circuit to finally output the CPU operating voltage, namely VDD CPU, to the CPU.

[0004] In actual applications, when the CPU enters / exits the C state and P state, the CPU has different requirements for voltage regulation due to different usage scenarios. Voltage regulation methods include sending SetVID_Fast command, SetVID_Slow command, SetDecay command and Set PS command. However, the existing CPU voltage regulation method may not be compatible with the actual application scenario of the CPU. In some special scenarios, even the VID value in the VID command issued by the CPU may not meet the current working requirements of the CPU. Therefore, the user has the need to dynamically modify the VID value. However, since the CPU and SVID main controller interface signals are fixed in the chip design stage, this greatly limits the CPU's final control over the VRM, and thus cannot flexibly respond to various complex and changeable actual application scenarios. In other words, the VID value in the VID command is not compatible with the actual application scenario of the CPU.

[0005] Therefore, how to provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU is one of the problems that need to be solved urgently. Summary of the invention

[0006] In view of this, the present disclosure proposes a voltage regulation control method, device and system, MCU and chipset, so as to provide a CPU with an operating voltage that is adaptive to the actual application scenario of the CPU.

[0007] According to a first aspect of the present disclosure, a voltage regulation control method is provided, which is applied to an MCU in a chipset of a system on chip (SOC), and the voltage regulation control method includes: receiving a voltage identification command (VID) sent by a CPU of the SOC; obtaining a current operating state of the CPU; determining a target operating voltage corresponding to the current operating state of the CPU; and converting the VID command into a serial voltage identification command (SVID) based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers a voltage regulation module (VRM) to adjust the operating voltage of the CPU.

[0008] In one possible implementation, based on the current operating state of the CPU and the target operating voltage, the VID command is converted into a serial voltage identification command SVID command, including: determining whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if not, converting the VID command into an SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

[0009] In a possible implementation, based on the current operating state of the CPU and the target operating voltage, the VID command is converted into a serial voltage identification command SVID command, including: determining the cause type of mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the cause type includes: a first type used to indicate that it is caused by the VID command type, a second type used to indicate that it is caused by the VID value carried in the VID command, and a third type used to indicate that it is caused by the VID command type and the VID value; for the first type, based on the current operating state of the CPU and the target operating voltage, the VID command is replaced with one or more SVID command sets; for the second type, based on the current operating state of the CPU and the target operating voltage, the VID value is adjusted and the VID command is converted into a SVID command; for the third type, based on the current operating state of the CPU and the target operating voltage, the VID value is adjusted and the VID command is converted into a SVID command, and other SVID commands are added.

[0010] In one possible implementation, after converting the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, the voltage regulation control method further includes: sending the SVID command to the VRM, wherein the MCU is integrated in the SVID main controller in the chipset.

[0011] In one possible implementation, after converting the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, the voltage regulation control method further includes: sending the SVID command to the SVID main controller in the chipset, so as to send the SVID command to the VRM through the SVID main controller, and the MCU and the SVID main controller are separately arranged in the chipset.

[0012] In a possible implementation, acquiring the current running state of the CPU includes: receiving the current running state of the CPU sent by a power management unit PMU in the chipset, wherein the current running state of the CPU is sent by the CPU to the PMU.

[0013] According to a second aspect of the present disclosure, a voltage regulation control device is provided, which is applied to an MCU in a chipset of a system on chip (SOC), and the voltage regulation control device includes: a receiving unit, which is used to receive a voltage identification command (VID) sent by a CPU of the SOC; an acquisition unit, which is used to acquire a current operating state of the CPU; a determination unit, which is used to determine a target operating voltage corresponding to the current operating state of the CPU; and a conversion unit, which is used to convert the VID command into a serial voltage identification command (SVID) based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers a voltage regulation module (VRM) to adjust the operating voltage of the CPU.

[0014] In one possible implementation, the conversion unit is configured to: determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if not, convert the VID command into the SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

[0015] In one possible implementation, the conversion unit is configured to: determine the reason type that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, wherein the reason type includes: a first type used to indicate that it is caused by the VID command type, a second type used to indicate that it is caused by the VID value carried in the VID command, and a third type used to indicate that it is caused by the VID command type and the VID value; for the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; for the second type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage and the VID command is converted into an SVID command; for the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage and the VID command is converted into an SVID command, and other SVID commands are added.

[0016] According to a third aspect of the present disclosure, an MCU in a chipset of a system on chip (SOC) is provided, which includes the above-mentioned voltage regulation control device.

[0017] According to a fourth aspect of the present disclosure, a chipset of a system on chip (SOC) is provided, comprising: the above-mentioned MCU; a serial voltage identification (SVID) main controller, for sending the SVID command received from the MCU to the VRM, wherein the MCU is separately arranged from the SVID main controller, or the MCU is integrated into the SVID main controller.

[0018] In a possible implementation, the chipset further includes: a power management unit PMU, configured to send the current operating status of the CPU received from the CPU to the MCU.

[0019] According to a fifth aspect of the present disclosure, a voltage regulation control system is provided, which includes: a system on chip SOC, which includes a CPU and the above-mentioned chipset; and a voltage regulation module VRM, which is used to receive an SVID command sent by a serial voltage identifier SVID main controller in the chipset, and provide a target operating voltage for the CPU according to the SVID command, wherein the SVID command is obtained by converting the VID command based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

[0020] According to the present disclosure, compared with the existing structure of the SOC chipset, a new MCU is added to the chipset. The MCU converts the VID command (also called voltage adjustment request) sent by the CPU into an SVID command according to the current running state of the SOC CPU and the target operating voltage corresponding to the current running state of the CPU. Since the SVID command is determined according to the current running state of the CPU, the target operating voltage corresponding to the current running state of the CPU and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an operating voltage (i.e., the target operating voltage) that is adaptive to the actual application scenario of the CPU according to the SVID command that is adapted to the actual application scenario of the CPU.

[0021] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0023] Figure 1a It is a block diagram of a voltage regulation control system in the related art.

[0024] Figure 1b is a flow chart of a voltage regulation control method according to an exemplary embodiment.

[0025] Figure 2a is a flow chart of a voltage regulation control method according to an exemplary embodiment.

[0026] Figure 2b A detailed process of a determination step in a voltage regulation control method according to an exemplary embodiment is shown.

[0027] Figure 3 A voltage regulation process of a voltage regulation control system according to an exemplary embodiment.

[0028] Figure 4 is a block diagram of a voltage regulation control system according to an exemplary embodiment.

[0029] Figure 5 is a block diagram of a voltage regulation control system according to an exemplary embodiment.

[0030] Figure 6 is a block diagram of a voltage regulation control apparatus according to an exemplary embodiment. DETAILED DESCRIPTION

[0031] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0034] See also Figure 1aIn the related art, the voltage regulation control system includes a system on chip (SOC) 100 and a VRM 200, wherein the SOC 100 includes a CPU 110 and a chipset 120, the chipset 120 includes a SVID main controller 121, and the VRM 200 is a component that actually physically provides voltage to the CPU. In other words, the VRM 200 for providing the operating voltage to the CPU 110 is located outside the SOC 100, and the SOC 100 is subdivided into a CPU side and a chipset side, the CPU 110 is located at the CPU side, and the SVID main controller 121 is located at the chipset side.

[0035] The CPU 110 sends a voltage adjustment request to the SVID main controller 121 (for example, sends a VID command, and the VID command carries a VID value); the SVID main controller 121 receives the voltage adjustment request, converts the voltage adjustment request into a SVID command and sends the SVID command; the VRM 200 receives the SVID command, performs electrical actions of voltage adjustment and setting the power state (English: PowerState) according to the SVID command, and finally the corresponding voltage change information is fed back to the CPU 110 through the VDD CPU signal, thereby completing the voltage adjustment of the CPU.

[0036] However, as described in the background technology, different usage scenarios may lead to different CPU requirements for voltage regulation methods. However, the above-mentioned voltage regulation control method does not take various usage scenarios into consideration. Therefore, the VID command sent by the CPU may not be compatible with the actual application scenario of the CPU. For example, the VID command sent by the CPU may not be necessary, or it may be difficult to adjust the current operating voltage of the CPU to the target operating voltage that meets the actual application requirements only through the VID command sent by the CPU, and other VID commands may need to be combined. That is, the VID command sent by the CPU may be inappropriate, which may result in the operating voltage provided to the CPU not being compatible with the actual application scenario. Therefore, it is difficult to provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU.

[0037] Moreover, as described in the background technology, in some scenarios, the VID value carried by the VID command sent by the CPU may not meet the current working requirements of the CPU, that is, it may be difficult to adjust the current operating voltage of the CPU to a target operating voltage that meets the actual application requirements via the VID value carried by the VID command, and the VID value needs to be further adjusted, that is, the VID value carried by the VID command may be inappropriate, and it may be necessary to adjust the VID value carried in the voltage adjustment request sent by the CPU, which may result in the operating voltage provided to the CPU not being compatible with the actual application scenario, and therefore it is difficult to provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU.

[0038] To this end, the present disclosure recognizes that the interface signal between the CPU and the SVID main controller is fixed in the chip design stage, which greatly limits the CPU's ultimate control over the VRM, resulting in the inability to flexibly respond to various complex and changeable actual application scenarios, and further making it difficult to provide the CPU with an operating voltage that is adaptive to the CPU's actual application scenarios.

[0039] On this basis, the present disclosure further proposes: adding a microprocessor (MCU) to the chipset, and using the MCU to generate SVID commands that match the actual application scenarios of the CPU, so that the SVID main controller controls the VRM to provide the CPU with an operating voltage that is adaptive to the actual application scenarios of the CPU. The MCU is located at the chipset end. In a possible implementation, please refer to Figure 5 , MCU 422 is integrated in SVID main controller 423 at the chipset 420 end; in another possible implementation, see Figure 4 , the MCU 422 and the SVID main controller 423 are separately located at the chipset 420 end.

[0040] Specifically, the MCU added to the chipset converts the VID command sent by the CPU into an SVID command for triggering the VRM to adjust the operating voltage of the CPU based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU. Since the SVID command is determined based on the current operating state of the CPU, the target operating voltage corresponding to the current operating state of the CPU and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. Therefore, the VRM can naturally provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU (i.e., it can realize adaptive CPU voltage regulation control) based on the SVID command that is adapted to the actual application scenario of the CPU, and thus can flexibly respond to various complex and changeable actual application scenarios, thereby solving the problems mentioned above.

[0041] Based on the above ideas, Figure 1b The voltage regulation control method shown in the figure can be applied to the MCU in the chipset of the SOC. In other words, the voltage regulation control method can be executed by the MCU. Of course, the voltage regulation control method can also be executed by other components of the MCU, such as Figure 6 The voltage regulation control method is executed by the voltage regulation control device 600 included in the MCU shown.

[0042] See also Figure 1b , the voltage regulation control method comprises the following steps:

[0043] In step S110 (receiving step), a voltage identification (English: Voltage Identification) command, ie, a VID command, sent by the CPU of the SOC is received.

[0044] In this embodiment, a VID command sent by the CPU can be received via an interface with the CPU, the VID command carrying a VID value, and the VID information can be transmitted to the VRM through the VID command. In a possible implementation, the CPU will send a VID command when it is in a low power state, and accordingly, the VID command sent by the CPU when it is in a low power state can be received.

[0045] ACPI SPEC stipulates that the VID command includes: the start field Start, which serves as the frame header and indicates the start of VID command sending when the value is "010"; the address field (English: Address Field) ADD[3:0], which indicates the address of each voltage; the command field (English: Command Field) CMD[4:0], which includes the SetVID_XX command and the Get Register command. The SetVID_XX command includes the SetVID_Fast command, the SetVID_Slow command, and the SetDecay command, which are used to inform the VRM of the new VID value; the data field (English: Data Field) CMDDATA[7:0] contains the target (English: target) VID value.

[0046] The SetVID_Fast command (01h) contains the target VID value in the payload byte and the voltage range is defined in the VID table. After receiving this command, the VRM adjusts to the new VID value at a fast slew rate. The SetVID_Slow command (02h) contains the target VID value in the payload byte and the voltage range is defined in the VID table. After receiving this command, the VRM rises to the new VID value at a slow slew rate. The SetDecay command (03h) is the SetVID command with the slowest dynamic conversion rate and is only used for downward conversion of VID values.

[0047] In step S130 (acquisition step), the current operating state of the CPU is acquired.

[0048] In this embodiment, the current operating state of the CPU may include but is not limited to the CPU power state and the CPU performance state. In an example, the CPU performance state may represent a combination of the power supply voltage and frequency of the CPU.

[0049] It should be understood that the CPU power state (English: power state) includes P state and C state. P state is also called processor performance state, and C state is also called processor power state. P state supports changing the processor supply voltage and frequency. Lower voltage and / or frequency is equivalent to lower energy consumption and degraded performance, while higher voltage and / or frequency is equivalent to higher energy consumption and better performance. C state is a different power state that the processor may enter when idle. As C state increases, more power can be saved at the cost of additional waiting time.

[0050] Accordingly, the power state of the CPU currently includes the C state and the P state. ACPI SPEC stipulates that the C state includes C0, C1, C2, C3, ... Cn and other states, wherein the C0 state is the state when the CPU is working normally, which is defined as the runtime state in which the processor operates at high voltage and high frequency. For the X86 CPU, after receiving the HLT (Halt) instruction and turning off the CPU core clock, the C1 state is entered, and the C1 state is defined as the automatic shutdown state in which the core clock is stopped internally. By switching (English: toggle) to stop the clock (English: Stop Clock, abbreviated as: STPCLK), the C2 state is entered, and the C2 state is defined as the stop clock state in which the core clock is stopped externally. C3 is defined as a deep sleep state in which the phase-locked loop (PLL) is turned off to turn off all processor clocks. In the C4 state, the voltage applied to the processor already in the C3 state is reduced to reduce leakage without endangering the state retention in the core and cache. The P state includes P0, P1, P2, ... Pn and other states, wherein the larger the number after P, the more power saving. Different P states correspond to different CPU operating voltages and frequencies. The larger the number, the lower the voltage and frequency.

[0051] In a possible implementation manner, the current running state of the CPU sent by the CPU may be received via an interface with the CPU.

[0052] In another possible implementation, the current operating state of the CPU sent by the CPU may be received via an interface with a power management unit (English: Power Management Unit, abbreviated as: PMU) in the chipset, wherein the PMU receives the current operating state of the CPU sent by the CPU.

[0053] See also Figure 4 and Figure 5A PMU 421 is further added to the chipset 420. An interface is provided between the MCU 422 and the PMU 421, and an interface is provided between the PMU 421 and the CPU 410. The PMU 421 can receive the operating status from the CPU 410 via the interface with the CPU 410, and then can send the operating status to the MCU 422 via the interface with the MCU 422. Thus, the MCU 422 can indirectly obtain the current operating status of the CPU 410 through the interface between the PMU 421 and the CPU 410.

[0054] In step S150 (determination step), the target operating voltage corresponding to the current operating state of the CPU is determined.

[0055] In this embodiment, when the CPU 410 is in a certain CPU current operating state, the CPU 410 may need a target operating voltage corresponding to the CPU current operating state. The target operating voltage corresponding to the CPU current operating state can be determined based on the corresponding relationship between the CPU current operating state and the target operating voltage. Exemplarily, assuming that the CPU current operating state is C4 state, it can be determined that the corresponding target operating voltage in the C4 state is 0.75v.

[0056] In step S170 (conversion step), based on the current operating status of the CPU obtained in step S130 and the target operating voltage determined in step S150, the VID command received in step S110 is converted into an SVID command, wherein the SVID command triggers the VRM to adjust the operating voltage of the CPU.

[0057] In this embodiment, the VID command can be dynamically converted into an SVID command that can adjust the CPU's operating voltage to the target operating voltage corresponding to the CPU's current operating state according to the CPU's current operating state and the target operating voltage corresponding to the CPU's current operating state, so that the VRM can provide the CPU with the target operating voltage according to the VID value carried by the SVID command. The aforementioned conversion may include but is not limited to: adding one or more VID commands on the basis of the VID command, increasing the VID value carried by the VID command, decreasing the VID value carried by the VID command, and any combination of these adjustment methods.

[0058] According to the present disclosure, compared with the existing structure of the SOC chipset, an MCU is newly added to the chipset. The MCU converts the VID command sent by the CPU into an SVID command according to the current running state of the SOC CPU and the target operating voltage corresponding to the current running state of the CPU. Since the SVID command is determined according to the current running state of the CPU, the target operating voltage corresponding to the current running state of the CPU and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an operating voltage (i.e., the target operating voltage) that is adaptive to the actual application scenario of the CPU according to the SVID command that is adapted to the actual application scenario of the CPU, thereby being able to more flexibly control the form of the SVID command finally sent to the VRM, thereby being able to better meet the diverse needs of users and avoid design problems caused by incomplete hardware considerations.

[0059] Figure 2a FIG. 1 is a flow chart of a voltage regulation control method according to an exemplary embodiment. Figure 2a As shown, the voltage regulation control method includes the following steps:

[0060] In step S110 (receiving step), a VID command sent by the CPU of the SOC is received.

[0061] In step S130 (acquisition step), the current operating state of the CPU is acquired.

[0062] In step S150 (determination step), the target operating voltage corresponding to the current operating state of the CPU is determined.

[0063] For details about steps S110, S130 and S150, please refer to the above Figure 1b The description will not be repeated here.

[0064] In step S251, it is determined whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU.

[0065] In this embodiment, if it is determined in step S251 that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, it indicates that the VID command is not suitable for the actual application scenario of the CPU, and the VID command needs to be converted, such as adjusting the VID command (adjusting the number of VID commands), adjusting the VID value carried by the VID command, or adjusting both the VID command and the VID value, so the following step S253 is executed. If it is determined in step S251 that the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU, it indicates that the VID command is suitable for the actual application scenario of the CPU, and there is no need to convert the VID command, so there is no need to adjust the number of VID commands or the VID value carried by the VID command, so the following step S257 is executed.

[0066] In step S253, the VID command is converted into an SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion of the VID command includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

[0067] In this embodiment, whether to adjust the VID command (for example, add at least one VID command) and / or adjust the VID value carried by the VID command (for example, increase / decrease the VID value carried by the VID command) according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU can be determined based on whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU.

[0068] In one possible implementation, Figure 2b As shown, step S253 may include the following steps S2531 to S2537:

[0069] In step S2531, determine the reason type that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, wherein the reason type may include: a first type used to indicate that it is caused by the VID command type, a second type used to indicate that it is caused by the VID value carried in the VID command, and a third type used to indicate that it is caused by the VID command type and the VID value.

[0070] It should be noted that the first type indicates that the type of VID command is inappropriate (it can also be regarded as the number of VID commands is inappropriate) but the VID value carried by the VID command is appropriate, the second type indicates that the type of VID command is appropriate but the VID value carried by the VID command is inappropriate, and the third type indicates that both the type of VID command and the VID value carried by the VID command are inappropriate.

[0071] If it is determined in step S2531 that the reason type that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU is the first type, step S2533 is executed to replace the VID command with one or more SVID command sets according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

[0072] If it is determined in step S2531 that the reason type why the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU is the second type, step S2535 is executed to adjust the VID value according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU and convert the VID command into an SVID command.

[0073] If it is determined in step S2531 that the reason type why the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU is the third type, step S2537 is executed to adjust the VID value according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU and convert the VID command into an SVID command and add other SVID commands.

[0074] In this embodiment, based on the type of reason why the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, it can be decided whether to adjust the type of VID command according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU (such as adding at least one VID command), or to adjust the VID value carried by the VID command (such as increasing / decreasing the VID value carried by the VID command), or to adjust both.

[0075] Example 1: Consider the physical condition of some chips. When adjusting the CPU P state, when the frequency of the P state is relatively low, the corresponding VID value is relatively low (for example, VID value = 0x6F, and the corresponding voltage is 0.8V). At this time, the VID value may not meet the normal working voltage requirements of the CPU of these chips. The MCU can know through the interface between the CPU / PMU that the current system is executing the P state flow (English: P State Flow). For this situation where the VID value is small and not suitable for the chip with poor physical condition, the MCU can process the received original VID value (that is, the VID value carried by the received VID command), such as increasing several VID values ​​(for example, adding 4 VID values ​​on the basis of VID value = 0x6F, at this time VID value = 0x73, and the corresponding voltage is 0.82V), and then notify the VRM of the processed VID value through the SetVID_XX command such as SetVID_Fast / Slow, and the corresponding VRM output voltage will be 0.2v higher than the original voltage.

[0076] It should be understood that for the above example 1, the VID value carried by the VID command sent by the CPU is not suitable for the current application scenario, so it is necessary to change the VID value carried by the VID command sent by the CPU and select the SetVID command suitable for the current application scenario.

[0077] Example 2: Considering the purpose of saving power, when adjusting the CPU P state, the corresponding VID value is lower when the frequency of the P state is relatively low. For example, when the voltage value is less than a certain range, the working current required by the chip CPU will not be too high. The MCU can know that the current system is executing P State Flow through the interface between the CPU / PMU. For such occasions with small VID values, the MCU can send the original VID value received to the VRM without processing it. However, the MCU can consider processing and reissuing the SetPs command later (the PS command value can be debugged to PS1 / 2 according to the voltage value, and this PS command can be slightly delayed to avoid being rejected by the VRM). In this way, for a VID voltage adjustment command sent by the CPU, the two commands VID transmission and SetPSx are finally seen on the SVID Bus. Similarly, when adjusting the CPU P state, when the frequency of the P state is relatively high, the corresponding VID value is higher. The MCU can process the received original VID value, and then send the original VID value to the VRM for processing and resend the SetPs0 command to the VRM to improve the current power supply capability.

[0078] It should be understood that for the above example 2, the VID value carried by the VID command sent by the CPU is not suitable for the current application scenario, so the VID value carried by the VID command sent by the CPU needs to be changed, and the corresponding command needs to be reissued.

[0079] Example 3, taking the moment when C4 just enters as an example, considering the purpose of saving power, the CPU will send a NAP VID (this VID value is generally low, such as VID value = 0x65, and its corresponding voltage value is 0.75v). At this time, the CPU voltage value is very small, so the working current required by the chip CPU will not be too high. The MCU can know that the current system is executing the C state entry process (English: C State Enter Flow) through the interface between the CPU / PMU. For such occasions with small VID values, the MCU can not process the received original CPU VID value, and can freely choose to use the SetVID_Fast command or the SetVID_Slow command to send this VID value.

[0080] It should be understood that for Example 3, the VID value carried by the VID command sent by the CPU is suitable for the current application scenario, so there is no need to change the VID value carried by the VID command sent by the CPU, but only to select the SetVID command suitable for the current application scenario.

[0081] Example 4, taking the C4 exit moment as an example, for some exits caused by periodic timer interrupts, the traditional method is to directly send a SetVID_Fast command or a SetVID_Slow command at the time of exit. For this kind of periodic interrupt, the MCU can control the sending of the exit VID value in stages. In the early stage of the exit stage, the MCU can control the sending of a SetVID_Slow command first. After the CPU voltage climbs in Slow Mode for a period of time, the MCU can control the sending of a SetVID_Fast command in the later stage of the exit, and then climb from this voltage to the final target voltage in Fast Mode.

[0082] Example 5, taking the C4 exit moment as an example, generally a SetVID_Fast command or a SetVID_Slow command is directly sent when exiting. According to the VRM Spec, each time a SetVID_Fast command or a SetVID_Slow command is received, the VRM will return to PS0; if you want to save power better, you need to resend the PSx command. To achieve this requirement, you can consider using the MCU to control the sending of a SetVID_Slow command first, and then refer to the VID value and other conditions when exiting C0 and then resend a PS1 or PS2 command.

[0083] After the SVID command is determined, the process may proceed to step S255 .

[0084] In step S255, the SVID command is sent.

[0085] In this embodiment, after the SVID command is determined, the SVID command may be sent to the VRM in step S255, wherein the MCU is integrated in the SVID main controller in the chipset. Alternatively, after the SVID command is determined, the SVID command may be sent to the SVID main controller in the chipset in step S255, wherein the VRM receives the SVID command from the SVID main controller, and the MCU and the SVID main controller are separately provided in the chipset.

[0086] In step S257, the VID command is sent without adjusting the VID command and the VID value carried by the VID command.

[0087] In this embodiment, after determining that the VID command and the VID value carried by the VID command do not need to be adjusted, the VID command can be sent to the VRM in step S257, wherein the MCU is integrated in the SVID main controller in the chipset. Alternatively, after determining that the VID command and the VID value carried by the VID command do not need to be adjusted, the VID command can be sent to the SVID main controller in the chipset in step S257, wherein the VRM receives the SVID command from the SVID main controller, and the MCU and the SVID main controller are separately provided in the chipset.

[0088] According to the present disclosure, compared with the existing structure of the SOC chipset, an MCU is newly added to the chipset. When the VRM cannot provide the target operating voltage according to the VID command, the MCU decides whether to adjust the type of VID command according to the current operating state of the SOC CPU and the target operating voltage corresponding to the current operating state of the CPU, or to adjust the VID value carried by the VID command, or to adjust both, based on the type of reason why the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, thereby determining the SVID command that can adjust the operating voltage of the CPU to the target operating voltage. Therefore, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with the target operating voltage of the actual application scenario of the adaptive CPU according to the SVID command that is adapted to the actual application scenario of the CPU, so that the form of the SVID command finally sent to the VRM can be more flexibly controlled, thereby better meeting the diverse needs of users and avoiding design problems caused by incomplete hardware considerations.

[0089] Figure 6 FIG. 6 is a block diagram of a voltage regulation control device according to an exemplary embodiment. The voltage regulation control device 600 may be applied to an MCU in a chipset of a system on chip (SOC). In other words, the MCU may include the voltage regulation control device 600. Figure 6 As shown, the voltage regulation control device 600 may include a receiving unit 610, an acquisition unit 620, a determination unit 630 and a conversion unit 640. The receiving unit 610 is used to receive a voltage identification command VID command sent by the CPU of the SOC; the acquisition unit 620 is used to obtain the current operating state of the CPU; the determination unit 630 is connected to the acquisition unit 620, and is used to determine the target operating voltage corresponding to the current operating state of the CPU; the conversion unit 640 is connected to the receiving unit 610, the acquisition unit 620 and the determination unit 630, and is used to convert the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers the voltage regulation module VRM to adjust the operating voltage of the CPU.

[0090] In one possible implementation, the conversion unit 640 can be configured to: determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if not, convert the VID command into SVID according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

[0091] In one possible implementation, the conversion unit 640 may be configured to: determine the cause type of mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the cause type includes: a first type used to indicate that the cause is caused by the VID command type, a second type used to indicate that the cause is caused by the VID value carried in the VID command, and a third type used to indicate that the cause is caused by the VID command type and the VID value; for the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; for the second type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage and the VID command is converted into an SVID command; for the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage and the VID command is converted into an SVID command, and other SVID commands are added.

[0092] In a possible implementation, the voltage regulation control device 60 may further include: a sending unit (not shown) configured to send the SVID command to the VRM, wherein the MCU is integrated in the SVID main controller in the chipset.

[0093] In a possible implementation, the voltage regulation control device 60 may further include: a sending unit (not shown) for sending the SVID command to the SVID main controller in the chipset, so as to send the SVID command to the VRM through the SVID main controller, and the MCU and the SVID main controller are separately arranged in the chipset.

[0094] In a possible implementation, the acquisition unit 620 may be configured to receive the current running state of the CPU sent by the PMU in the chipset, wherein the current running state of the CPU is sent by the CPU to the PMU.

[0095] Figure 4 A block diagram of a voltage regulation control system according to an exemplary embodiment is shown. Figure 4 As shown, the voltage regulation control system may include a SOC 400 and a VRM 500. The SOC 400 includes a CPU 410 and a chipset 420, wherein the chipset 420 includes a PMU 421, an MCU 422 and a SVID main controller 423, and the MCU 422 and the SVID main controller 423 are separately arranged in the chipset 420.

[0096] An interface (English: Interface) for communication between CPU 410 and PMU 421 is provided, and PMU 421 receives the current operating state of CPU 410, such as the current power state of CPU 410 and the performance state of CPU 410, from CPU 410 via the interface. An interface for communication between PMU 421 and MCU 422 is provided, and PMU 421 sends the current operating state of CPU 410 to MCU 422 via the interface, and MCU 422 can receive the current operating state of CPU 410 sent by PMU 421 via the interface.

[0097] An interface for communication between the CPU 410 and the MCU 422 is provided. The CPU 410 sends a VID command to the MCU 422 via the interface, and the MCU 422 can receive the VID command via the interface.

[0098] MCU 422 can determine the target operating voltage corresponding to the current operating state of CPU 410, and convert the VID command received from CPU 410 into an SVID command based on the current operating state of CPU 410 and the target operating voltage received from PMU 421. MCU 422 can include voltage regulation control device 600 to perform Figure 1b or Figure 2a The voltage regulation control method is used to generate SVID commands that are compatible with the actual application requirements of the CPU.

[0099] An interface for communication between the MCU 422 and the SVID main controller 423 is provided. The MCU 422 sends an SVID command to the SVID main controller 423 via the interface, and the SVID main controller 423 can receive the SVID command sent by the MCU 422 via the interface.

[0100] An interface for communication between the SVID main controller 423 and the VRM 500 is provided. The SVID main controller 423 sends an SVID command to the VRM 500 via the interface, and the VRM 500 can receive the SVID command sent by the SVID main controller 423 via the interface. The VRM 500 adjusts the operating voltage of the CPU 410 according to the SVID command to provide the CPU 410 with a target operating voltage that is adapted to the actual application requirements of the CPU. In addition, the VRM 500 can feed back the status of the VRM 500 to the SVID main controller 423 via the interface between itself and the SVID main controller 423, and accordingly, the SVID main controller 423 can feed back the status of the VRM 500 to the MCU 422 via the interface between itself and the MCU 422.

[0101] An interface for communication between the VRM 500 and the CPU 410 is provided, and the VRM 500 outputs VDD CPU to the CPU 410 via the interface to ultimately control the voltage of the CPU 410 .

[0102] Therefore, compared with Figure 1aThe voltage regulation control system shown in the figure, the voltage regulation control system of this embodiment adds an MCU located outside the SVID main controller in the chipset, and the added MCU converts the VID command sent by the CPU into an SVID command according to the current operating state of the CPU of the SOC and the target operating voltage corresponding to the current operating state of the CPU. Since the SVID command is determined according to the current operating state of the CPU, the target operating voltage corresponding to the current operating state of the CPU and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU according to the SVID command that is adapted to the actual application scenario of the CPU.

[0103] Figure 5 A block diagram of a voltage regulation control system according to an exemplary embodiment is shown. Figure 4 and Figure 5 It can be seen that the difference between the voltage regulation control systems may be that the position setting methods of the MCU 422 and the SVID main controller 423 are different. Specifically, Figure 4 The MCU added to the chipset of the voltage regulation control system shown is located outside the SVID main controller. Figure 5 The MCU added to the chipset of the voltage regulation control system shown is located inside the SVID main controller, which can also be referred to as the MCU added to the chipset being integrated inside the SVID main controller.

[0104] Therefore, for the entire SOC side, the SVID main controller is still a separate module, but after the MCU is integrated inside the SVID main controller, the function of the SVID main controller is greatly increased, because at this time the MCU can be intervened by the firmware to flexibly operate to obtain the current power state of the CPU (such as C state / P state) and access the SVID main controller, so that more efficient and real-time voltage regulation control can be performed.

[0105] For ease of understanding, the following combination Figure 3 To illustrate the voltage regulation process of the present disclosure. Figure 3 , the voltage regulation process of the present disclosure may include the following steps:

[0106] In step (1), when CPU 410 is in a low power state, CPU 410 sends a VID command (voltage adjustment request) to MCU 422 via the interface between itself and MCU 422. Accordingly, MCU 422 receives the VID command via the interface between itself and CPU 410.

[0107] In step (2), CPU 410 sends its current operating state (including but not limited to C state / P state) to PMU 421 via the interface between itself and PMU 421. Correspondingly, PMU 421 receives the current operating state via the interface between itself and CPU 410.

[0108] It should be noted that although Figure 3 It is shown that step (1) is performed first and then step (2), but the present disclosure does not limit the order of steps (1) and (2). Step (2) may be performed first and then step (1), or steps (1) and (2) may be performed simultaneously.

[0109] In step (3), the PMU 421 sends the current CPU running status to the MCU 422 via the interface between the PMU 421 and the MCU 422 . Accordingly, the MCU 422 receives the current CPU running status via the interface between the PMU 421 and the MCU 422 .

[0110] In step (4), MCU 422 determines the target operating voltage corresponding to the current operating state of the CPU.

[0111] In step (5), MCU 422 determines whether the current operating state of the CPU is C state or P state; if it is determined that the current operating state of the CPU is C state, then continue to execute the following step (6); if it is determined that the current operating state of the CPU is P state, then continue to execute the following step (7).

[0112] In step (6), MCU 422 converts the VID command sent by CPU 410 into an SVID command based on the C state and the corresponding target operating voltage in the C state. Then, the following step (8) is executed.

[0113] In example one, MCU 422 will combine the VID value (English: Value) carried by the VID command sent by the CPU 410 and the actual application scenario requirements (associated with the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU) to decide which type of SVID command to issue in the process of entering (English: Enter) or exiting (Exit) the CPU C state. The types of SVID commands may include but are not limited to Set VIDFast / Slow / Decay and Set PS, etc., and combinations of these SVID commands, such as Set Decay command + Set PS command, etc.

[0114] In step (7), MCU 422 converts the VID command sent by CPU 410 into an SVID command based on the P state and the corresponding target operating voltage in the P state. Then, the following step (8) is executed.

[0115] In example two, MCU 422 will combine the VID value carried by the received VID command sent by CPU 410 and determine which type of SVID command to issue in the process of entering or exiting the CPU P state according to the requirements of the actual application scenario (associated with the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU). The types of SVID commands may include but are not limited to Set VID Fast / Slow and Set PS, and combinations of these commands, such as Set VID command + Set PS command, etc.

[0116] MCU 422 further determines whether the VID value carried by the VID command sent by CPU 410 meets the requirements of the actual application scenario (that is, determines whether the voltage corresponding to the VID value carried by the VID command sent by CPU 410 (that is, the adjusted operating voltage indicated by the VID command) matches the target operating voltage); if it is determined that the VID value carried by the VID command does not meet the requirements of the actual application scenario, when the VID value carried by the VID command is greater than the VID value required by the actual application scenario (the adjusted operating voltage indicated by the VID command is greater than the target operating voltage), the VID value carried by the VID command can be automatically reduced to adapt to the requirements of the actual application scenario; when the VID value carried by the VID command is less than the VID value required by the actual application scenario (the adjusted operating voltage indicated by the VID command is less than the target operating voltage), the VID value carried by the SVID command can be increased, thereby adapting to the requirements of the actual application scenario.

[0117] In step (8), the MCU 422 sends an SVID command to the SVID master controller 423 via the interface between the MCU 422 and the SVID master controller 423 . Accordingly, the SVID master controller 423 receives the SVID command via the interface between the MCU 422 and the SVID master controller 423 .

[0118] In step (9), the SVID master controller 423 sends a SVID command to the VRM 500 via the SVID bus via the interface between itself and the VRM 500. Accordingly, the VRM 500 receives the SVID command via the interface between itself and the SVID master controller 423 via the SVID bus.

[0119] In step (10), VRM 500 performs electrical actions of adjusting voltage and setting the power state of CPU 410 according to the received SVID command.

[0120] In step (11), VRM 500 outputs a VDD CPU signal to CPU 410 via the interface between itself and CPU 410 to feed back voltage change information to CPU 410. Accordingly, CPU 410 receives the VDD CPU signal via the interface between itself and VRM 500, and CPU 410 controls its own operating voltage to be the target operating voltage according to the VDD CPU signal.

[0121] Thus, the entire voltage regulation process is completed. VRM 500 can naturally provide CPU 410 with an operating voltage that is adaptive to the actual application scenario of CPU 410 according to the SVID command that is adapted to the actual application scenario of CPU 410, so that the form of the SVID command ultimately sent to VRM 500 can be more flexibly controlled, thereby better meeting the diverse needs of users and avoiding design problems caused by incomplete consideration of hardware.

[0122] Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

[0123] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A voltage regulation control method, characterized in that: The voltage regulation control method is applied to an MCU in a chipset of a system on chip (SOC), and includes: Receiving a voltage identification command VID command sent by the CPU of the SOC; Get the current running status of the CPU; Determine the target operating voltage corresponding to the current operating state of the CPU; Based on the current operating state of the CPU and the target operating voltage, the VID command is converted into a serial voltage identification command SVID command, wherein the SVID command triggers a voltage regulation module VRM to regulate the operating voltage of the CPU.

2. The voltage regulation control method according to claim 1, characterized in that: Based on the current operating state of the CPU and the target operating voltage, converting the VID command into a serial voltage identification command SVID command, including: Determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; If there is no match, the VID command is converted into an SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

3. The voltage regulation control method according to claim 2, characterized in that: Based on the current operating state of the CPU and the target operating voltage, converting the VID command into a serial voltage identification command SVID command, including: Determine a reason type that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current running state of the CPU, wherein the reason type includes: a first type for indicating that it is caused by the VID command type, a second type for indicating that it is caused by the VID value carried in the VID command, and a third type for indicating that it is caused by the VID command type and the VID value; For the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; For the second type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage and converting the VID command into an SVID command; For the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command and other SVID commands are added.

4. The voltage regulation control method according to any one of claims 1 to 3, characterized in that: After converting the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, the method further includes: The SVID command is sent to the VRM, wherein the MCU is integrated in a SVID main controller in the chipset.

5. The voltage regulation control method according to any one of claims 1 to 3, characterized in that: After converting the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, the method further includes: The SVID command is sent to the SVID main controller in the chipset, so that the SVID command is sent to the VRM through the SVID main controller, and the MCU and the SVID main controller are separately arranged in the chipset.

6. The voltage regulation control method according to any one of claims 1 to 3, characterized in that: Obtaining the current running state of the CPU includes: The current running state of the CPU sent by a power management unit PMU in the chipset is received, wherein the current running state of the CPU is sent by the CPU to the PMU.

7. A voltage regulating control device, characterized in that: The MCU in the chipset of the system on chip SOC is applied, and the voltage regulation control device comprises: A receiving unit, configured to receive a voltage identification command VID command sent by the CPU of the SOC; An acquisition unit is used to obtain the current running status of the CPU; A determination unit, used to determine a target operating voltage corresponding to the current operating state of the CPU; The conversion unit is used to convert the VID command into a serial voltage identification command SVID command based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers a voltage regulation module VRM to regulate the operating voltage of the CPU.

8. The voltage regulating control device according to claim 7, characterized in that: The conversion unit is configured to: Determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; If there is no match, the VID command is converted into the SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more SVID command sets.

9. The voltage regulating control device according to claim 8, characterized in that: The conversion unit is configured to: Determine a reason type that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current running state of the CPU, wherein the reason type includes: a first type for indicating that it is caused by the VID command type, a second type for indicating that it is caused by the VID value carried in the VID command, and a third type for indicating that it is caused by the VID command type and the VID value; For the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; For the second type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage and converting the VID command into an SVID command; For the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command and other SVID commands are added.

10. An MCU in a chipset of a system on chip (SOC), characterized in that: It comprises a voltage regulating control device according to any one of claims 7 to 9.

11. A chipset for a system on chip (SOC), characterized in that: include: The MCU according to claim 10; A serial voltage identification SVID master controller is used to send the SVID command received from the MCU to the VRM, The MCU is separately arranged from the SVID main controller, or the MCU is integrated into the SVID main controller.

12. The chipset according to claim 11, characterized in that: Also includes: The power management unit PMU is used to send the current operating status of the CPU received from the CPU to the MCU.

13. A voltage regulation control system, characterized in that: include: A system on chip (SOC), comprising a CPU and a chipset according to claim 11 or 12; as well as The voltage regulation module VRM is used to receive the SVID command sent by the serial voltage identification SVID main controller in the chipset, and provide a target operating voltage for the CPU according to the SVID command, wherein the SVID command is obtained by converting the VID command based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

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