Voltage regulation control method, device and system, mcu and chip set

Abstract

The present disclosure relates to a voltage regulation control method, device and system, MCU and chip set, the voltage regulation control method comprising: receiving a voltage identification command (VID command) sent by a CPU of a SOC; obtaining a current running state of the CPU; determining a target working voltage corresponding to the current running state of the CPU; converting the VID command into a serial voltage identification command (SVID command) based on the current running state of the CPU and the target working voltage, wherein the SVID command triggers a voltage regulation module (VRM) to regulate the working voltage of the CPU. Thus, the working voltage adaptive to the actual application scenario of the CPU can be provided for the CPU.

Description

Technical Field

[0001] This disclosure relates to the field of power control technology, and in particular to a voltage regulation control method, device and system, MCU and chipset. Background Technology

[0002] In modern x86 systems, CPUs support many low-power technologies. Typical low-power technologies include the processor power state (CPU C state) and processor performance state (CPU P state) specified in the Advanced Configuration and Power Interface (ACPI) specification. These technologies all require dynamic control of the CPU voltage.

[0003] The commonly used voltage regulation control method in chip design is as follows: The CPU sends a voltage regulation request to the Serial Voltage Identification (SVID) master controller. After receiving the voltage regulation request, the SVID master controller converts the voltage regulation request into a command conforming to the SVID protocol, and then sends it to the voltage regulator module (VRM) through the SVID bus. The VRM receives the command and, in conjunction with external circuitry, ultimately outputs the CPU operating voltage, VDD CPU, to the CPU.

[0004] In practical applications, the CPU's voltage regulation requirements vary depending on the usage scenario when entering / exiting C and P states. These requirements may include sending commands such as SetVID_Fast, SetVID_Slow, SetDecay, and Set PS. However, existing CPU voltage regulation methods may not be suitable for the actual application scenarios. In some special scenarios, even the VID value in the VID command issued by the CPU may not meet the CPU's current operating requirements. Therefore, users need to dynamically modify the VID value. However, since the interface signals between the CPU and the SVID master controller are fixed during the chip design phase, this greatly limits the CPU's final control over the VRM, thus preventing it from flexibly responding to various complex and changing practical application scenarios. In other words, the VID value in the VID command is not compatible with the CPU's actual application scenario.

[0005] Therefore, how to provide the CPU with an adaptive operating voltage for the actual application scenario is one of the problems that urgently needs to be solved. Summary of the Invention

[0006] In view of this, this disclosure proposes a voltage regulation control method, device and system, MCU and chipset, which can provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU.

[0007] According to a first aspect of this disclosure, a voltage regulation control method is provided, applied to an MCU in a chipset of a system-on-a-chip (SoC). The voltage regulation control method includes: receiving a voltage identification command (VID) sent by the CPU of the SoC; obtaining the current operating state of the CPU; determining a target operating voltage corresponding to the current operating state of the CPU; and converting the VID command into a serial voltage identification command (SVID) based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers a voltage regulation module (VRM) to regulate the operating voltage of the CPU.

[0008] In one possible implementation, based on the current operating state of the CPU and the target operating voltage, converting the VID command into a Serial Voltage Identifier (SVID) command includes: determining whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if they do not match, converting the VID command into an SVID command based on the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands.

[0009] In one possible implementation, based on the current operating state of the CPU and the target operating voltage, converting the VID command into a Serial Voltage Identifier (SVID) command includes: determining the type of reason for the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the type of reason includes: a first type indicating a mismatch caused by the type of VID command, a second type indicating a mismatch caused by the VID value carried in the VID command, and a third type indicating a mismatch caused by both the type of VID command and the VID value; for the first type, replacing the VID command with one or more sets of SVID commands based on the current operating state of the CPU and the target operating voltage; for the second type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage and converting the VID command into an SVID command; for the third type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage, converting the VID command into an SVID command, and adding other SVID commands.

[0010] In one possible implementation, after converting the VID command into a serial voltage identifier command (SVID) based on the current operating state of the CPU and the target operating voltage, the voltage regulation control method further includes: sending the SVID command to the VRM, wherein the MCU is integrated into the SVID master controller in the chipset.

[0011] In one possible implementation, after converting the VID command into a serial voltage identifier command (SVID) based on the current operating state of the CPU and the target operating voltage, the voltage regulation control method further includes: sending the SVID command to the SVID master controller in the chipset, so that the SVID command can be sent to the VRM through the SVID master controller, wherein the MCU and the SVID master controller are separately configured in the chipset.

[0012] In one possible implementation, obtaining the current operating state of the CPU includes: receiving the current operating state of the CPU sent by the power management unit (PMU) in the chipset, wherein the current operating state of the CPU is sent by the CPU to the PMU.

[0013] According to a second aspect of this disclosure, a voltage regulation control device is provided, applied to an MCU in a chipset of a system-on-a-chip (SoC). The voltage regulation control device includes: a receiving unit for receiving a voltage identification command (VID) sent by the CPU of the SoC; an acquisition unit for acquiring the current operating state of the CPU; a determination unit for determining a target operating voltage corresponding to the current operating state of the CPU; and a conversion unit for converting the VID command into a serial voltage identification command (SVID) based on the current operating state of the CPU and the target operating voltage, wherein the SVID command triggers a voltage regulation module (VRM) to adjust the operating voltage of the CPU.

[0014] In one possible implementation, the conversion unit is configured to: determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if they do not match, convert the VID command into the SVID command according to the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands.

[0015] In one possible implementation, the conversion unit is configured to: determine the type of cause for the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the type of cause includes: a first type indicating a mismatch caused by the type of VID command, a second type indicating a mismatch caused by the VID value carried in the VID command, and a third type indicating a mismatch caused by both the type of VID command and the VID value; for the first type, replacing the VID command with one or more sets of SVID commands based on the current operating state of the CPU and the target operating voltage; for the second type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage and converting the VID command into an SVID command; for the third type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage, converting the VID command into an SVID command, and adding other SVID commands.

[0016] According to a third aspect of this disclosure, an MCU in a chipset of a system-on-a-chip (SoC) is provided, which includes the voltage regulation control device described above.

[0017] According to a fourth aspect of this disclosure, a chipset for a system-on-a-chip (SoC) is provided, comprising: the aforementioned MCU; and a serial voltage identifier (SVID) master controller for sending SVID commands received from the MCU to the VRM, wherein the MCU and the SVID master controller are separately configured, or the MCU is integrated into the SVID master controller.

[0018] In one possible implementation, the chipset further includes a power management unit (PMU) for sending the current operating state of the CPU received from the CPU to the MCU.

[0019] According to a fifth aspect of this disclosure, a voltage regulation control system is provided, comprising: a system-on-a-chip (SOC) including a CPU and the aforementioned chipset; and a voltage regulation module (VRM) for receiving an SVID command sent by a serial voltage identifier (SVID) master controller in the chipset, and providing a target operating voltage to the CPU according to the SVID command, wherein the SVID command is obtained by converting the VID command based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

[0020] According to this disclosure, compared to the existing structure of the SOC chipset, an MCU is added to the chipset. The MCU converts the VID command (also known as the voltage adjustment request) sent by the CPU into an SVID command based on the current operating state of the CPU of the SOC and the target operating voltage corresponding to the current operating state of the CPU. Since the SVID command is determined based on the current operating state of the CPU, the target operating voltage corresponding to the current operating state of the CPU, and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an adaptive operating voltage (i.e., the target operating voltage) based on the SVID command adapted to the actual application scenario of the CPU.

[0021] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0023] Figure 1a This is a block diagram of a voltage regulation control system in related technologies.

[0024] Figure 1b This is a flowchart of a voltage regulation control method according to an exemplary embodiment.

[0025] Figure 2a This is a flowchart of a voltage regulation control method according to an exemplary embodiment.

[0026] Figure 2b The detailed processing of the determination step in the voltage regulation control method according to an exemplary embodiment is shown.

[0027] Figure 3 This is the voltage regulation process of a voltage regulation control system according to an exemplary embodiment.

[0028] Figure 4 This is a block diagram of a voltage regulation control system according to an exemplary embodiment.

[0029] Figure 5 This is a block diagram of a voltage regulation control system according to an exemplary embodiment.

[0030] Figure 6 This is a block diagram of a voltage regulation control device according to an exemplary embodiment. Detailed Implementation

[0031] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0033] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0034] Please see Figure 1aIn related technologies, the voltage regulation control system includes a System on Chip (SOC) 100 and a VRM 200. The SOC 100 includes a CPU 110 and a chipset 120. The chipset 120 includes an SVID master controller 121. The VRM 200 is the component that physically provides voltage to the CPU. In other words, the VRM 200, which provides the operating voltage to the CPU 110, is located outside the SOC 100. The SOC 100 is internally divided into a CPU side and a chipset side; the CPU 110 is located at the CPU side, and the SVID master controller 121 is located at the chipset side.

[0035] CPU 110 sends a voltage adjustment request (e.g., a VID command with a VID value) to SVID master controller 121; SVID master controller 121 receives the voltage adjustment request, converts it into an SVID command, and sends the SVID command; VRM 200 receives the SVID command and performs electrical actions to adjust the voltage and set the power state according to the SVID command. Finally, the corresponding voltage change information is fed back to CPU 110 through the VDD CPU signal, thereby completing the CPU voltage adjustment.

[0036] However, as explained in the background section, different usage scenarios may lead to different requirements for the voltage regulation method of the CPU. However, the voltage regulation control method mentioned above does not take into account various usage scenarios. Therefore, the VID command sent by the CPU may not be suitable for the actual application scenario of the CPU. For example, the VID command sent by the CPU may not be necessary, or it may be difficult to adjust the current operating voltage of the CPU to the target operating voltage that meets the actual application requirements by the VID command sent by the CPU alone. It may be necessary to combine other VID commands. That is, the VID command sent by the CPU may be inappropriate. This may result in the operating voltage provided to the CPU not being suitable for the actual application scenario. Therefore, it is difficult to provide the CPU with an operating voltage that is adaptive to the actual application scenario of the CPU.

[0037] Moreover, as explained in the background section, in some scenarios, the VID value carried by the VID command sent by the CPU may not meet the current working requirements of the CPU. That is, the VID value carried by the VID command may not be able to adjust the current working voltage of the CPU to the target working voltage that meets the actual application requirements, and further adjustment of the VID value is required. In other words, the VID value carried by the VID command may be inappropriate, and it may be necessary to adjust the VID value carried in the voltage adjustment request sent by the CPU. This may result in the working voltage provided to the CPU not being adapted to the actual application scenario, and therefore it is difficult to provide the CPU with a working voltage that is adaptive to the actual application scenario of the CPU.

[0038] Therefore, this disclosure recognizes that the interface signals between the CPU and the SVID master controller are fixed during the chip design stage, which greatly limits the CPU's final control over the VRM, resulting in an inability to flexibly cope with various complex and ever-changing real-world application scenarios, and consequently, making it difficult to provide the CPU with an operating voltage that adapts to the actual application scenario of the CPU.

[0039] Building upon this, this disclosure further proposes adding a microprocessor (MCU) to the chipset. The MCU generates SVID commands that correspond to the actual application scenario of the CPU. Thus, the VRM, controlled by the SVID master controller, can provide the CPU with an adaptive operating voltage for the CPU's actual application scenario. The MCU is located at the chipset level. For one possible implementation, please refer to [link to relevant documentation]. Figure 5 The MCU 422 is integrated into the SVID master controller 423 on the chipset 420; for another possible implementation, please refer to [link / reference needed]. Figure 4 The MCU 422 and the SVID master controller 423 are located separately on the chipset 420.

[0040] Specifically, the MCU added to the chipset converts the VID command sent by the CPU into an SVID command to trigger the VRM to adjust the CPU's operating voltage, based on the CPU's current operating state and the target operating voltage corresponding to that state. Since the SVID command is determined based on the CPU's current operating state, the target operating voltage corresponding to that state, and the VID command sent by the CPU, it should be adaptable to the CPU's actual application scenario. Therefore, the VRM can provide the CPU with an adaptive operating voltage (i.e., adaptive CPU voltage regulation control) based on the SVID command adapted to the CPU's actual application scenario, thus flexibly responding to various complex and ever-changing application scenarios and solving the problems mentioned above.

[0041] Based on the above concept, the following is proposed Figure 1b The voltage regulation control method shown can be applied to the MCU in the SOC chipset; in other words, the MCU can execute this voltage regulation control method. Of course, other components of the MCU can also execute this voltage regulation control method, such as... Figure 6 The voltage regulation control device 600 included in the MCU shown executes the voltage regulation control method.

[0042] Please see Figure 1b The voltage regulation control method includes the following steps:

[0043] In step S110 (receiving step), the voltage identification (VID) command sent by the CPU of the SOC is received.

[0044] In this embodiment, a VID command sent by the CPU can be received via an interface with the CPU. This VID command carries a VID value and can be used to transmit VID information to the VRM. In one possible implementation, the CPU sends a VID command when it is in a low-power state, and correspondingly, the VID command sent by the CPU when it is in a low-power state can be received.

[0045] ACPI SPEC specifies that VID commands include: a Start field, which serves as the frame header and indicates the start of VID command transmission when its value is "010"; an Address field (ADD[3:0]), which represents the address of each voltage channel; a Command field (CMD[4:0]), which includes the SetVID_XX command and the Get Register command. The SetVID_XX command includes the SetVID_Fast command, the SetVID_Slow command, and the SetDecay command, used to inform the VRM of the new VID value; and a Data field (CMDDATA[7:0]), which contains the target VID value.

[0046] The SetVID_Fast command (01h) includes the target VID value in the payload byte, with the voltage range defined in the VID table. Upon receiving this command, the VRM adjusts to the new VID value at a fast slew rate. The SetVID_Slow command (02h) also includes the target VID value in the payload byte, with the voltage range defined in the VID table. Upon receiving this command, the VRM rises to the new VID value at a slow slew rate. The SetDecay command (03h) has the slowest dynamic slew rate and is only used for down-converting VID values.

[0047] In step S130 (acquisition step), the current operating state of the CPU is acquired.

[0048] In this embodiment, the current operating state of the CPU may include, but is not limited to, the CPU power state and the CPU performance state. In one example, the CPU performance state may represent the combination of the CPU's power supply voltage and frequency.

[0049] It should be understood that CPU power states include P states and C states. P states are also known as processor performance states, and C states are also known as processor power states. P states allow for changes in the processor's supply voltage and frequency; lower voltage and / or frequency corresponds to lower power consumption and degraded performance, while higher voltage and / or frequency corresponds to higher power consumption and better performance. C states are the different power states the processor may enter when idle. As the number of C states increases, more power can be saved at the cost of additional latency.

[0050] Accordingly, the current power states of the CPU include C states and P states. ACPI SPEC specifies that C states include C0, C1, C2, C3, ... Cn, where C0 is the state during normal CPU operation, defined as the running state where the processor operates at high voltage and high frequency. For x86 CPUs, after receiving the HLT (Halt) instruction and shutting down the CPU core clock, it enters the C1 state, defined as an automatic halt state where the internal core clock is stopped. It enters the C2 state by toggling the Stop Clock (STPCLK), defined as a stop clock state where the external core clock is stopped. C3 is defined as a deep sleep state where the phase-locked loop (PLL) is turned off to shut down all processor clocks. In the C4 state, the voltage applied to processors already in C3 is reduced to minimize leakage without jeopardizing state retention in the core and cache. P states include P0, P1, P2, ... Pn, where a larger number after P indicates higher power efficiency. Different P states correspond to different CPU operating voltages and frequencies; the larger the number, the lower the voltage and frequency.

[0051] In one possible implementation, the CPU's current operating status can be received via an interface with the CPU.

[0052] In another possible implementation, the current operating state of the CPU can be received from the CPU via an interface with the power management unit (PMU) in the chipset, whereby the PMU receives the current operating state of the CPU sent by the CPU.

[0053] Please see Figure 4 and Figure 5A PMU 421 is further added to the chipset 420. The MCU 422 has an interface with the PMU 421, and the PMU 421 has an interface with the CPU 410. The PMU 421 can receive the operating status from the CPU 410 through the interface with the CPU 410, and then send the operating status to the MCU 422 through the interface with the MCU 422. Thus, the MCU 422 can indirectly obtain the current operating status of the CPU 410 through the interface between the PMU 421 and the CPU 410.

[0054] In step S150 (determination step), the target operating voltage corresponding to the current operating state of the CPU is determined.

[0055] In this embodiment, when the CPU 410 is in a certain current CPU operating state, the CPU 410 may need a target operating voltage corresponding to that current CPU operating state. The target operating voltage corresponding to the current CPU operating state can be determined based on the correspondence between the current CPU operating state and the target operating voltage. For example, assuming the current CPU operating state is C4, the target operating voltage corresponding to C4 state can be determined to be 0.75V.

[0056] In step S170 (conversion step), based on the current operating state of the CPU obtained in step S130 and the target operating voltage determined in step S150, the VID command received in receiving step S110 is converted into an SVID command, wherein the SVID command triggers the VRM to adjust the operating voltage of the CPU.

[0057] In this embodiment, the VID command can be dynamically converted into an SVID command that adjusts the CPU's operating voltage to the target operating voltage corresponding to the current CPU operating state, based on the CPU's current operating state and the target operating voltage corresponding to that state. Thus, the VRM can provide the target operating voltage to the CPU based on the VID value carried by the SVID command. The aforementioned conversion may include, but is not limited to: adding one or more VID commands to the existing VID command, increasing the VID value carried by the VID command, decreasing the VID value carried by the VID command, and any combination of these adjustment methods.

[0058] According to this disclosure, compared to the existing structure of the SOC chipset, an MCU is added to the chipset. The MCU converts the VID command sent by the CPU into an SVID command based on the current operating state of the SOC CPU and the target operating voltage corresponding to the current operating state of the CPU. Since the SVID command is determined based on the current operating state of the CPU, the target operating voltage corresponding to the current operating state of the CPU, and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an adaptive operating voltage (i.e., target operating voltage) based on the SVID command adapted to the actual application scenario of the CPU. This allows for more flexible control over the form of the SVID command finally sent to the VRM, thereby better meeting the diverse needs of users and avoiding design problems caused by incomplete hardware considerations.

[0059] Figure 2a This is a flowchart of a voltage regulation control method according to an exemplary embodiment. Figure 2a As shown, the voltage regulation control method includes the following steps:

[0060] In step S110 (receiving step), the VID command sent by the CPU of the SOC is received.

[0061] In step S130 (acquisition step), the current operating state of the CPU is acquired.

[0062] In step S150 (determination step), the target operating voltage corresponding to the current operating state of the CPU is determined.

[0063] For details regarding steps S110, S130, and S150, please refer to the previous section on... Figure 1b The description will not be repeated here.

[0064] In step S251, it is determined whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU.

[0065] In this embodiment, if it is determined in step S251 that the adjusted operating voltage indicated by the VID command does not match the target operating voltage corresponding to the current operating state of the CPU, it indicates that the VID command is not suitable for the actual application scenario of the CPU, and the VID command needs to be converted. For example, the VID command can be adjusted (by adjusting the number of VID commands), the VID value carried by the VID command can be adjusted, or both the VID command and the VID value can be adjusted. Therefore, step S253 is executed below. If it is determined in step S251 that the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU, it indicates that the VID command is suitable for the actual application scenario of the CPU, and the VID command does not need to be converted. Therefore, neither the number of VID commands nor the VID value carried by the VID command needs to be adjusted, and step S257 is executed below.

[0066] In step S253, the VID command is converted into an SVID command based on the current operating state of the CPU and the target operating voltage. The conversion of the VID command includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands.

[0067] In this embodiment, the decision to adjust the VID command (e.g., add at least one VID command) and / or adjust the VID value carried by the VID command (e.g., increase / decrease the VID value carried by the VID command) can be made based on whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU.

[0068] In one possible implementation, such as Figure 2b As shown, step S253 may include the following steps S2531 to S2537:

[0069] In step S2531, the cause type of the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU is determined. The cause type may include: a first type indicating the cause caused by the type of VID command, a second type indicating the cause caused by the VID value carried in the VID command, and a third type indicating the cause caused by both the type of VID command and the VID value.

[0070] It should be noted that the first type indicates that the type of VID command is inappropriate (which can also be regarded as the number of VID commands being inappropriate) but the VID value carried by the VID command is appropriate; the second type indicates that the type of VID command is appropriate but the VID value carried by the VID command is inappropriate; and the third type indicates that both the type of VID command and the VID value carried by the VID command are inappropriate.

[0071] If, in step S2531, it is determined that the cause of the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU is of type one, then step S2533 is executed to replace the VID command with one or more sets of SVID commands according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

[0072] If, in step S2531, it is determined that the cause of the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU is of type two, then step S2535 is executed to adjust the VID value according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU and convert the VID command into an SVID command.

[0073] If, in step S2531, it is determined that the cause of the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU is of type three, then step S2537 is executed to adjust the VID value according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU, convert the VID command into an SVID command, and add other SVID commands.

[0074] In this embodiment, the decision can be made based on the type of mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU. This decision can be made to adjust the type of VID command (e.g., add at least one VID command), the VID value carried by the VID command (e.g., increase / decrease the VID value carried by the VID command), or both, according to the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

[0075] Example 1: Considering the inherent limitations of certain chips, when adjusting the CPU P state, the VID value may be low at lower frequencies (e.g., VID = 0x6F, corresponding to a voltage of 0.8V). In this case, the VID value may not meet the normal operating voltage requirements of these chips. The MCU can know through the interface between the CPU and PMU that the current system is executing a P state flow. For situations where the VID value is too low for these chips, the MCU can process the received raw VID value (i.e., the VID value carried by the received VID command). For example, it can increase the VID value by several increments (e.g., adding 4 more VID values ​​to the base VID = 0x6F, resulting in a VID = 0x73, corresponding to a voltage of 0.82V). Then, it can use a SetVID_XX command, such as SetVID_Fast / Slow, to notify the VRM of the processed VID value. The corresponding VRM output voltage will be 0.2V higher than the original voltage.

[0076] It should be understood that, for Example 1 above, the VID value carried by the VID command sent by the CPU is not suitable for the current application scenario. Therefore, it is necessary to change the VID value carried by the VID command sent by the CPU and select a SetVID command that is suitable for the current application scenario.

[0077] Example 2: Considering power saving, when adjusting the CPU P state, the VID value is lower when the frequency of the P state is relatively low, such as when the voltage value is less than a certain range. At this time, the operating current required by the chip CPU will not be too high. The MCU can know that the current system is executing the P State Flow through the interface between the CPU and the PMU. In the case of such a small VID value, the MCU can send the original VID value to the VRM without processing it. However, the MCU can consider processing and resending the SetPs command later (the PS command value can be adjusted according to the voltage value to PS1 / 2. This PS command can be slightly delayed to avoid being rejected by the VRM). In this way, for a VID voltage adjustment command sent by the CPU, what is finally seen on the SVID Bus are two commands: VID transmission and SetPSx. Similarly, when adjusting the CPU P state, the VID value is higher when the frequency of the P state is relatively high. The MCU can process the received raw VID value and then send the raw VID value to the VRM for processing and resending the SetPs0 command to the VRM to improve the current supply capability.

[0078] It should be understood that, in Example 2 above, the VID value carried by the VID command sent by the CPU is not suitable for the current application scenario. Therefore, it is necessary to change the VID value carried by the VID command sent by the CPU, and also to resend the corresponding command.

[0079] Example 3: Taking the moment C4 just enters as an example, considering the purpose of saving power, the CPU will issue a NAP VID (this VID value is generally relatively low, for example, VID value = 0x65, its corresponding voltage value is 0.75V). At this time, the CPU voltage value is very small, so the operating current required by the chip CPU will not be too high. The MCU can know through the interface between the CPU / PMU that the current system is executing the C State Enter Flow. In the case of such a small VID value, the MCU can not process the received raw CPU VID value, and can freely choose to send this VID value using the SetVID_Fast command or the SetVID_Slow command.

[0080] It should be understood that, for Example 3, the VID value carried by the VID command sent by the CPU is adapted to the current application scenario. Therefore, there is no need to change the VID value carried by the VID command sent by the CPU, but only to select the SetVID command that is adapted to the current application scenario.

[0081] Example 4, taking the exit time of C4 as an example, for some exits caused by periodic timer interrupts, the traditional approach is to directly send a SetVID_Fast or SetVID_Slow command at the time of exit. For such periodic interrupts, the MCU can control the sending of the exit VID value in stages. In the early stage of the exit phase, the MCU can control the sending of a SetVID_Slow command first. After the CPU voltage has climbed in Slow Mode for a period of time, in the later stage of the exit, the MCU can control the sending of a SetVID_Fast command first, and then climb from this voltage to the final target voltage in Fast Mode.

[0082] Example 5, taking the exit of C4 as an example, typically a SetVID_Fast or SetVID_Slow command is sent directly upon exit. According to the VRM specification, the VRM will return to PS0 after each SetVID_Fast or SetVID_Slow command is received. If better power saving is desired, a PSx command needs to be resent. To achieve this, one could consider having the MCU control the first SetVID_Slow command, and then, when exiting C0, resent a PS1 or PS2 command based on the VID value and other factors.

[0083] After determining the SVID command, you can proceed to step S255.

[0084] In step S255, the SVID command is sent.

[0085] In this embodiment, after determining the SVID command, the SVID command can be sent to the VRM in step S255, where the MCU is integrated into the SVID master controller in the chipset. Alternatively, after determining the SVID command, the SVID command can be sent to the SVID master controller in the chipset in step S255, where the VRM receives the SVID command from the SVID master controller, and the MCU and SVID master controller are separately configured in the chipset.

[0086] In step S257, the VID command is sent without adjusting the VID command and the VID value carried by the VID command.

[0087] In this embodiment, after determining that no adjustment is needed for the VID command and the VID value carried by the VID command, the VID command can be sent to the VRM in step S257, wherein the MCU is integrated into the SVID master controller in the chipset. Alternatively, after determining that no adjustment is needed for the VID command and the VID value carried by the VID command, the VID command can be sent to the SVID master controller in the chipset in step S257, wherein the VRM receives the SVID command from the SVID master controller, and the MCU and the SVID master controller are separately configured in the chipset.

[0088] According to this disclosure, compared to the existing structure of the SOC chipset, the addition of an MCU to the chipset allows for adjustments based on the cause of the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU. Specifically, the MCU determines whether to adjust the type of VID command, the VID value carried by the VID command, or both, based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU. This determines the SVID command that can adjust the CPU's operating voltage to the target operating voltage. Therefore, this SVID command should be adaptable to the actual application scenario of the CPU. In this way, the VRM can provide the CPU with a target operating voltage that adapts to the actual application scenario of the CPU based on the SVID command adapted to the actual application scenario. This allows for more flexible control over the form of the SVID command ultimately sent to the VRM, thereby better meeting diverse user needs and avoiding design problems caused by incomplete hardware considerations.

[0089] Figure 6 The diagram illustrates a voltage regulation control device 600 according to an exemplary embodiment. This voltage regulation control device 600 can be applied to an MCU within the chipset of a system-on-a-chip (SoC); in other words, the MCU can include the voltage regulation control device 600. Figure 6 As shown, the voltage regulation control device 600 may include a receiving unit 610, an acquisition unit 620, a determining unit 630, and a conversion unit 640. The receiving unit 610 receives a voltage identification command (VID) sent by the CPU of the SOC; the acquisition unit 620 acquires the current operating state of the CPU; the determining unit 630, connected to the acquisition unit 620, determines the target operating voltage corresponding to the current operating state of the CPU; the conversion unit 640, connected to the receiving unit 610, the acquisition unit 620, and the determining unit 630, converts the VID command into a serial voltage identification command (SVID) based on the current operating state of the CPU and the target operating voltage. The SVID command triggers the voltage regulation module (VRM) to adjust the operating voltage of the CPU.

[0090] In one possible implementation, the conversion unit 640 may be configured to: determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; if they do not match, convert the VID command into an SVID based on the current operating state of the CPU and the target operating voltage, wherein the conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands.

[0091] In one possible implementation, the conversion unit 640 may be configured to: determine the type of cause for the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the type of cause includes: a first type indicating a mismatch caused by the type of VID command, a second type indicating a mismatch caused by the VID value carried in the VID command, and a third type indicating a mismatch caused by both the type of VID command and the VID value; for the first type, replacing the VID command with one or more sets of SVID commands based on the current operating state of the CPU and the target operating voltage; for the second type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage and converting the VID command into an SVID command; for the third type, adjusting the VID value based on the current operating state of the CPU and the target operating voltage, converting the VID command into an SVID command, and adding other SVID commands.

[0092] In one possible implementation, the voltage regulation control device 60 may further include: a sending unit (not shown) for sending the SVID command to the VRM, wherein the MCU is integrated in the SVID master controller in the chipset.

[0093] In one possible implementation, the voltage regulation control device 60 may further include: a sending unit (not shown) for sending the SVID command to the SVID master controller in the chipset, so that the SVID command is sent to the VRM through the SVID master controller, wherein the MCU and the SVID master controller are separately disposed in the chipset.

[0094] In one possible implementation, the acquisition unit 620 may be configured to receive the current operating state of the CPU sent by the PMU in the chipset, wherein the current operating state of the CPU is sent by the CPU to the PMU.

[0095] Figure 4 A block diagram of a voltage regulation control system according to an exemplary embodiment is shown, such as... Figure 4 As shown, the voltage regulation control system may include SOC 400 and VRM 500. SOC 400 includes CPU 410 and chipset 420, wherein chipset 420 includes PMU 421, MCU 422 and SVID master controller 423, and MCU 422 and SVID master controller 423 are separately disposed in chipset 420.

[0096] An interface is provided between CPU 410 and PMU 421 for communication. PMU 421 receives information about the current operating status of CPU 410, such as its power supply status and performance status, from CPU 410 via this interface. An interface is also provided between PMU 421 and MCU 422 for communication. PMU 421 sends the current operating status of CPU 410 to MCU 422 via this interface, and MCU 422 receives the current operating status of CPU 410 sent by PMU 421 via this interface.

[0097] An interface is provided between the CPU 410 and the MCU 422 for communication. The CPU 410 sends VID commands to the MCU 422 through this interface, and the MCU 422 can receive VID commands through this interface.

[0098] The MCU 422 can determine the target operating voltage corresponding to the current operating state of the CPU 410. Based on the current operating state of the CPU 410 received from the PMU 421 and the target operating voltage, it converts the VID command received from the CPU 410 into an SVID command. The MCU 422 may include a voltage regulation control device 600 to execute this command. Figure 1b or Figure 2a The voltage regulation control method generates SVID commands that are adapted to the actual application requirements of the CPU.

[0099] An interface is provided between the MCU 422 and the SVID master controller 423 for communication. The MCU 422 sends SVID commands to the SVID master controller 423 through this interface, and the SVID master controller 423 can receive the SVID commands sent by the MCU 422 through this interface.

[0100] An interface is provided between the SVID master controller 423 and the VRM 500 for communication. The SVID master controller 423 sends SVID commands to the VRM 500 through this interface, and the VRM 500 receives the SVID commands sent by the SVID master controller 423 through the same interface. The VRM 500 adjusts the operating voltage of the CPU 410 according to the SVID commands to provide the CPU 410 with a target operating voltage suitable for the actual application requirements. In addition, the VRM 500 can provide feedback on its status to the SVID master controller 423 through its interface with the SVID master controller 423. Similarly, the SVID master controller 423 can provide feedback on the status of the VRM 500 to the MCU 422 through its interface with the MCU 422.

[0101] An interface is provided between the VRM 500 and the CPU 410 for communication. The VRM 500 outputs VDD CPU to the CPU 410 through this interface to ultimately control the voltage of the CPU 410.

[0102] Therefore, compared to Figure 1aThe voltage regulation control system shown in this embodiment adds an MCU located outside the SVID main controller in the chipset. This added MCU converts the VID command sent by the CPU into an SVID command based on the current operating state of the CPU of the SOC and the target operating voltage corresponding to the current operating state of the CPU. Since the SVID command is determined based on the current operating state of the CPU, the target operating voltage corresponding to the current operating state of the CPU, and the VID command sent by the CPU, the SVID command should be able to adapt to the actual application scenario of the CPU. In this way, the VRM can naturally provide the CPU with an adaptive operating voltage based on the SVID command adapted to the actual application scenario of the CPU.

[0103] Figure 5 A block diagram of a voltage regulation control system according to an exemplary embodiment is shown, by comparison Figure 4 and Figure 5 It can be seen that the difference between the two voltage regulation control systems may lie in the different positioning of the MCU 422 and the SVID main controller 423. Specifically, Figure 4 The MCU added to the chipset of the voltage regulation control system shown is located outside the SVID main controller. Relatively speaking, Figure 5 The MCU added to the chipset of the voltage regulation control system shown is located inside the SVID main controller, or it can be said that the MCU added to the chipset is integrated inside the SVID main controller.

[0104] Therefore, for the entire SOC, the SVID master controller is still a separate module. However, since the MCU is integrated inside the SVID master controller, the functionality of the SVID master controller is greatly increased. This is because the MCU can now be flexibly operated by the firmware to obtain the current power state of the CPU (such as C state / P state) and access the SVID master controller. In this way, more efficient and real-time voltage regulation control can be performed.

[0105] For ease of understanding, the following is combined with Figure 3 This will illustrate the voltage regulation process of this disclosure. Please refer to [link / reference]. Figure 3 The voltage regulation process disclosed herein may include the following steps:

[0106] In step (1), when the CPU 410 is in a low power state, the CPU 410 sends a VID command (voltage adjustment request) to the MCU 422 through the interface between itself and the MCU 422. Correspondingly, the MCU 422 receives the VID command through the interface between itself and the CPU 410.

[0107] In step (2), the CPU 410 sends its current running status (including but not limited to C status / P status) to the PMU 421 via the interface between itself and the PMU 421. Correspondingly, the PMU 421 receives the current running status via the interface between itself and the CPU 410.

[0108] It should be noted that, although Figure 3 The illustration shows that step (1) is executed first and then step (2). However, this disclosure does not limit the order of steps (1) and (2). Step (2) can be executed first and then step (1), or steps (1) and (2) can be executed simultaneously.

[0109] In step (3), PMU 421 sends the current CPU operating status to MCU 422 via the interface between itself and MCU 422, and correspondingly, MCU 422 receives the current CPU operating status via the interface between itself and PMU 421.

[0110] In step (4), MCU 422 determines the target operating voltage corresponding to the current operating state of the CPU.

[0111] In step (5), MCU 422 determines whether the current operating state of the CPU is C state or P state; if it determines that the current operating state of the CPU is C state, then continue to execute the following step (6); if it determines that the current operating state of the CPU is P state, then continue to execute the following step (7).

[0112] In step (6), the MCU 422 converts the VID command sent by the CPU 410 into an SVID command based on the C state and the target operating voltage corresponding to the C state. Then, step (8) is performed below.

[0113] Example 1: The MCU 422 combines the VID value carried by the VID command sent by the CPU 410 and the actual application scenario requirements (associated with the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU) to determine which type of SVID command to issue during the process of entering (Enter) or exiting (Exit) the CPU C state. The types of SVID commands may include, but are not limited to, Set VIDFast / Slow / Decay and Set PS, as well as combinations of these SVID commands, such as Set Decay command + Set PS command.

[0114] In step (7), the MCU 422 converts the VID command sent by the CPU 410 into an SVID command based on the P state and the target operating voltage corresponding to the P state. Then, the following step (8) is performed.

[0115] Example 2: The MCU 422 will combine the VID value carried by the VID command sent by the CPU 410 and the actual application scenario requirements (associated with the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU) to determine which type of SVID command to issue during the process of entering or exiting the CPU P state. The types of SVID commands may include, but are not limited to, Set VID Fast / Slow and Set PS, as well as combinations of these commands, such as Set VID command + Set PS command.

[0116] MCU 422 further determines whether the VID value carried by the VID command sent by CPU 410 meets the requirements of the actual application scenario (i.e., whether the voltage corresponding to the VID value carried by the VID command sent by CPU 410 (i.e., the adjusted working voltage indicated by the VID command) matches the target working voltage). If it is determined that the VID value carried by the VID command does not meet the requirements of the actual application scenario, if the VID value carried by the VID command is greater than the VID value required by the actual application scenario (the adjusted working voltage indicated by the VID command is greater than the target working voltage), the VID value carried by the VID command can be automatically reduced to adapt to the requirements of the actual application scenario. If the VID value carried by the VID command is less than the VID value required by the actual application scenario (the adjusted working voltage indicated by the VID command is less than the target working voltage), the VID value carried by the VID command can be increased to adapt to the requirements of the actual application scenario.

[0117] In step (8), the MCU 422 sends an SVID command to the SVID master controller 423 via the interface between itself and the SVID master controller 423. Correspondingly, the SVID master controller 423 receives the SVID command via the interface between itself and the MCU 422.

[0118] In step (9), the SVID master controller 423 sends an SVID command to the VRM 500 via the SVID bus through the interface between itself and the VRM 500, and correspondingly, the VRM 500 receives the SVID command via the SVID bus through the interface between itself and the SVID master controller 423.

[0119] In step (10), VRM 500 performs electrical actions to regulate voltage and set the power state of CPU 410 according to the received SVID command.

[0120] In step (11), VRM 500 outputs a VDD CPU signal to CPU 410 via the interface between itself and CPU 410 to provide feedback on voltage change information to CPU 410. Correspondingly, CPU 410 receives the VDD CPU signal via the interface between itself and VRM 500, and CPU 410 controls its own operating voltage to the target operating voltage according to the VDD CPU signal.

[0121] Thus, the entire voltage regulation process is completed. Based on the SVID command adapted to the actual application scenario of CPU 410, VRM 500 can naturally provide CPU 410 with an adaptive operating voltage for that scenario. This allows for more flexible control over the form of the SVID command ultimately sent to VRM 500, better meeting diverse user needs and avoiding design problems caused by incomplete hardware considerations.

[0122] Regarding the apparatus in the above embodiments, the specific manner in which each unit performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0123] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A voltage regulation control method, characterized in that, An MCU used in a chipset of a system-on-a-chip (SoC), wherein the MCU is located outside the CPU of the SoC, the voltage regulation control method includes: Receive the voltage identification command (VID) sent by the CPU; Get the current operating status of the CPU; Determine the target operating voltage corresponding to the current operating state of the CPU; Based on the current operating state of the CPU and the target operating voltage, the VID command is converted into a serial voltage identifier command (SVID). The SVID command triggers the voltage regulation module (VRM) to adjust the CPU's operating voltage. Specifically, based on the current operating state of the CPU and the target operating voltage, the VID command is converted into a serial voltage identifier command (SVID), including: Determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; If they do not match, the VID command is converted into an SVID command based on the current CPU operating state and the target operating voltage. The conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands. The process of converting the VID command into an SVID command based on the current operating state of the CPU and the target operating voltage includes: Determine the type of reason for the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the type of reason includes: a first type indicating the mismatch caused by the type of VID command, a second type indicating the mismatch caused by the VID value carried in the VID command, and a third type indicating the mismatch caused by both the type of VID command and the VID value; For the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; For the second type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command; For the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command, and other SVID commands are added.

2. The voltage regulation control method according to claim 1, characterized in that, After converting the VID command into a serial voltage identifier command (SVID) based on the current operating state of the CPU and the target operating voltage, the method further includes: The SVID command is sent to the VRM, wherein the MCU is integrated into the SVID master controller in the chipset.

3. The voltage regulation control method according to claim 1 or 2, characterized in that, After converting the VID command into a serial voltage identifier command (SVID) based on the current operating state of the CPU and the target operating voltage, the method further includes: The SVID command is sent to the SVID master controller in the chipset, so that the SVID command can be sent to the VRM through the SVID master controller. The MCU and the SVID master controller are separately set in the chipset.

4. The voltage regulation control method according to claim 1 or 2, characterized in that, Obtaining the current operating state of the CPU includes: The system receives the current operating status of the CPU from the power management unit (PMU) in the chipset, wherein the current operating status of the CPU is sent by the CPU to the PMU.

5. A voltage regulating control device, characterized in that, An MCU used in a chipset of a system-on-a-chip (SoC), the MCU being located external to the CPU of the SoC, the voltage regulation control device comprising: The receiving unit is used to receive the voltage identifier command (VID) sent by the CPU. The acquisition unit is used to acquire the current operating status of the CPU; The determining unit is used to determine the target operating voltage corresponding to the current operating state of the CPU; The conversion unit is used to convert the VID command into a serial voltage identifier command (SVID) based on the current operating state of the CPU and the target operating voltage. The SVID command triggers the voltage regulation module (VRM) to adjust the CPU's operating voltage. The conversion unit is configured as follows: Determine whether the adjusted operating voltage indicated by the VID command matches the target operating voltage corresponding to the current operating state of the CPU; If they do not match, the VID command is converted into the SVID command based on the current CPU operating state and the target operating voltage. The conversion includes: adjusting the VID value carried by the VID command, and / or replacing the VID command with one or more sets of SVID commands. The conversion unit is configured as follows: Determine the type of reason for the mismatch between the adjusted operating voltage indicated by the VID command and the target operating voltage corresponding to the current operating state of the CPU, wherein the type of reason includes: a first type indicating the mismatch caused by the type of VID command, a second type indicating the mismatch caused by the VID value carried in the VID command, and a third type indicating the mismatch caused by both the type of VID command and the VID value; For the first type, the VID command is replaced with one or more SVID command sets based on the current operating state of the CPU and the target operating voltage; For the second type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command; For the third type, the VID value is adjusted based on the current operating state of the CPU and the target operating voltage, and the VID command is converted into an SVID command, and other SVID commands are added.

6. An MCU in a chipset of a System-on-a-Chip (SoC), characterized in that, Includes the voltage regulation control device according to claim 5.

7. A chipset for a System-on-a-Chip (SoC), characterized in that, include: The MCU according to claim 6; The Serial Voltage Identifier (SVID) master controller is used to send the SVID command received from the MCU to the VRM. The MCU and the SVID master controller are set separately, or the MCU is integrated into the SVID master controller.

8. The chipset according to claim 7, characterized in that, Also includes: The power management unit (PMU) is used to send the current operating status of the CPU received from the CPU to the MCU.

9. A voltage regulation control system, characterized in that, include: A system-on-a-chip (SoC) comprising a CPU and a chipset according to claim 7 or 8; as well as The voltage regulation module (VRM) is used to receive the SVID command sent by the serial voltage identifier (SVID) master controller in the chipset, and to provide the target operating voltage to the CPU according to the SVID command. The SVID command is obtained by converting the VID command based on the current operating state of the CPU and the target operating voltage corresponding to the current operating state of the CPU.

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