Memory system, operating method thereof, and computer readable storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method of the memory system and a computer readable storage medium, and the memory system comprises a memory device; the memory controller is coupled with the memory device and is configured to obtain a temperature parameter at a first moment, a temperature parameter at a second moment, a data transmission rate at the first moment and a temperature regulation and control parameter at the first moment; determining a data transmission rate upper limit at a third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment and the temperature regulation and control parameter at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is one moment after the first moment.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] At present, memory systems are usually provided as internal semiconductor integrated circuits in computers or other electronic devices, and are widely used in various fields, including embedded systems such as computers and network interconnection devices, as well as voice, image, and data storage products such as digital cameras and digital recorders. As the speed requirements of these products for a series of access operations (e.g., read operations and write operations) continue to increase, when a series of access operations (e.g., read operations and write operations) are performed quickly to meet user performance requirements, excessive heat may accumulate in the memory system, thereby negatively affecting the performance of the memory system. Summary of the invention

[0003] In view of this, embodiments of the present application provide a memory system and an operating method thereof, and a computer-readable storage medium.

[0004] According to a first aspect of an embodiment of the present application, a memory system is provided, comprising: a memory device; a memory controller coupled to the memory device and configured to: obtain temperature parameters at a first moment and temperature parameters at a second moment, a data transmission rate at the first moment, and a temperature control parameter at the first moment; determine an upper limit of the data transmission rate at a third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameter at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

[0005] In the above scheme, the memory controller is specifically configured to: obtain the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters under the working mode at the first moment; the temperature control parameters in different working modes are different; the temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters; determine the upper limit of the data transmission rate at the third moment according to the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters under the working mode at the first moment; wherein, any two adjacent moments are separated by a preset period.

[0006] In the above scheme, the memory controller is configured to: when the temperature parameter at the first moment exceeds the target control temperature, control the data transmission rate at the third moment to be below the corresponding data transmission rate upper limit so that the temperature parameter approaches the target control temperature.

[0007] In the above scheme, the memory controller is specifically configured to: determine the data rate upper limit of the third moment according to the following calculation formula: V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]}; wherein, V3_limt is the data transmission rate upper limit of the third moment, V2 is the data transmission rate of the first moment, T0 is the temperature parameter of the second moment which is two preset cycles apart from the first moment, T1 is the temperature parameter of the second moment which is one preset cycle apart from the first moment, T2 is the temperature parameter of the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0008] In the above scheme, the memory controller is also configured to: obtain a temperature deviation threshold; when the temperature parameter at the first moment is greater than or equal to the sum of the target control temperature and the temperature deviation threshold, set the data transmission rate upper limit at the third moment to be less than or equal to a preset data transmission rate.

[0009] In the above solution, the preset data transmission rate is the data transmission rate corresponding to 10% of the full power consumption of the memory system.

[0010] In the above solution, the memory controller is configured to: determine the working mode of the memory system at the first moment; and obtain the temperature control parameters corresponding to the working mode at the first moment according to the determined working mode.

[0011] In the above scheme, the memory controller is also configured to: for various working modes of the memory system, respectively obtain the optimal proportional parameters, integral parameters, and differential parameters in the corresponding working mode; generate a mapping table between the various working modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters, and store the mapping table, and trigger a call in the corresponding working mode.

[0012] In the above solution, the memory controller is configured to: obtain multiple temperature measurement data of temperature sensors at different positions included in the memory system, and obtain the temperature parameter by using the multiple temperature measurement data in combination with a temperature composite algorithm.

[0013] According to a second aspect of an embodiment of the present application, a method for operating a memory system is provided, the method comprising: obtaining temperature parameters at a first moment and temperature parameters at a second moment, a data transmission rate at the first moment, and a temperature control parameter at the first moment; determining an upper limit of the data transmission rate at a third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameter at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

[0014] In the above scheme, the operating method also includes: obtaining the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters under the working mode at the first moment; the temperature control parameters in different working modes are different; the temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters; according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters under the working mode at the first moment, determine the upper limit of the data transmission rate at the third moment; wherein, any two adjacent moments are separated by a preset period.

[0015] In the above scheme, the operating method also includes: determining the upper limit of the data transmission rate at the third moment according to the following calculation formula: V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]}; wherein V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter of the second moment which is two preset cycles apart from the first moment, T1 is the temperature parameter of the second moment which is one preset cycle apart from the first moment, T2 is the temperature parameter of the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0016] In the above scheme, the operating method also includes: obtaining a temperature deviation threshold; when the temperature parameter at the first moment is greater than or equal to the sum of the target control temperature and the temperature deviation threshold, setting the data transmission rate upper limit at the third moment to be less than or equal to a preset data transmission rate.

[0017] In the above scheme, the operating method further includes: determining the working mode of the memory system at the first moment; and obtaining the temperature control parameters corresponding to the working mode at the first moment according to the determined working mode.

[0018] In the above scheme, the operating method also includes: for various working modes of the memory system, respectively obtaining the optimal proportional parameters, integral parameters, and differential parameters in the corresponding working mode; generating a mapping table between the various working modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters, and storing the mapping table, and triggering a call in the corresponding working mode.

[0019] According to a third aspect of an embodiment of the present application, a memory system is provided, comprising: a memory device; and a memory controller coupled to the memory device and configured to: within a period of time after a temperature parameter of the memory system exceeds a target control temperature, under different working environments, adjust the data transmission rate of the memory system so that the fluctuation of the data transmission rate of the memory system gradually decreases to a level close to stability and approaches the target control temperature when the temperature parameter is stable.

[0020] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for operating the memory system as described in the second aspect are implemented.

[0021] The embodiment of the present application provides a memory system and its operation method, and a computer-readable storage medium, wherein the memory system includes: a memory device; a memory controller coupled to the memory device and configured to: obtain temperature parameters at a first moment and a temperature parameter at a second moment, a data transmission rate at a first moment, and a temperature control parameter at a first moment; determine the upper limit of the data transmission rate at a third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameter at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment. In this way, the upper limit of the data transmission rate at the next moment is dynamically predicted by the real-time temperature parameters and the data transmission rate, and the memory system can dynamically adjust the upper limit of the data transmission rate at the next moment. This intelligent temperature control strategy allows the memory system to flexibly adjust the real-time data transmission rate according to the actual situation, so as to protect the memory system from high temperature damage to the greatest extent, while providing a good user experience. A balance between the temperature parameters and performance of the memory system is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0023] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0024] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0025] Figure 3 A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0026] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0027] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0028] Figure 6 A schematic diagram of a temperature control curve showing an exemplary temperature control strategy for a memory system;

[0029] Figure 7 Shows Figure 6 The schematic diagram of the temperature control curve when the temperature control strategy is executed multiple times is shown;

[0030] Figure 8 A schematic diagram of a temperature control curve showing another exemplary temperature control strategy for a memory system;

[0031] Fig. 9 A schematic diagram of an implementation flow of an operating method of a memory system provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of a temperature control curve of a temperature control strategy provided in an embodiment of the application;

[0033] Fig.11 A flowchart of an operating method of a memory system provided by an embodiment of the present application;

[0034] Fig.12 A flowchart of an operating method of a memory system provided by another embodiment of the present application;

[0035] Fig.13 A block diagram of a computer-readable storage medium provided for one embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. The described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. It is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0038] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0040] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0043] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0044] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present application is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0045] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0046] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0047] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104.

[0048] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0049] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0050] In such Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 A memory card connector 204 is coupled to the host 108 in the memory card connector.

[0051] In such Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0052] Figure 3 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present application. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0053] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus can store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a two-bit storage cell, Double-Level Cell), three bits per cell (also referred to as a three-bit storage cell (Trinary-Level Cell, TLC)), four bits per cell (also referred to as a four-bit storage cell (Quad-Level Cell, QLC)), five bits per cell (also referred to as a five-bit storage cell (Penta-level cell, PLC)), or more than five bits per cell. Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0054] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: an erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: an erased state and fifteen programming states.

[0055] like Figure 3 As shown in , each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source side selection transistor) at its source terminal and an upper selection transistor (TSG) 312 (also known as a drain side selection transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0056] like Figure 3As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations.

[0057] refer to Figure 3 Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the top selection transistor (TSG) 312).

[0058] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present application. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0059] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0060] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0061] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0062] Return to reference Figure 3, the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0063] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0064] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0065] The control logic 512 may be coupled to each of the other parts in the peripheral circuit described above, and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface (Interface, I / F) 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0066] In order to prevent the memory system from accumulating excessive heat when a large number of access operations are performed quickly, various temperature control (Thermal Throttling) strategies (also known as thermal throttling strategies) are usually adopted.

[0067] Figure 6 A schematic diagram of a temperature control curve of an exemplary temperature control strategy for a memory system is shown. Figure 6As shown, the maximum data transmission rate of the memory system is V_max, and the temperature inside the memory system needs to be detected at regular intervals. After the temperature of the memory system detected at time Q1 exceeds the set temperature threshold T_th, the data transmission rate of the memory system is reduced to the basic data transmission rate V_base, so that the temperature of the memory system gradually stops rising and then falls back to a safe temperature range; after it is detected at time Q2 that the temperature of the memory system has dropped to the safe temperature T_th-△Temp, the memory system returns to normal read and write performance, and the data transmission rate of the memory system is increased to the maximum data transmission rate V_max.

[0068] Here, the set temperature threshold T_th and temperature difference △Temp can be empirical values, or can be default values ​​configured when the memory system is shipped out of the factory, and the default values ​​are obtained through a large number of simulation experiments before the memory system is shipped out of the factory. Exemplarily, the range of the set temperature threshold T_th is set to 70℃-75℃, and the range of the temperature difference △Temp is set to 3℃-5℃. More specifically, the set temperature threshold T_th can be 70℃, 72℃, 75℃, and the temperature difference △Temp can be 3℃, 4℃, 5℃.

[0069] It should be noted that the data transfer rate of a memory system refers to the data transfer rate or read / write data flow between the memory device and the memory controller of the memory system. The data transfer rate table is usually expressed in bits or bytes of data transferred per second (e.g., MB / s). A higher data transfer rate usually means that the memory system has better performance and can meet the needs of high read and write speeds more quickly.

[0070] The above method of controlling the temperature of the memory system by reducing the data transmission rate of the memory system is intended to control the overall temperature of the memory system to prevent overheating. Therefore, the temperature of the memory system is not the temperature of a certain location or a certain component, but the comprehensive temperature of various components inside the memory system. For example, the temperature of the memory system represents the average temperature of components such as the memory controller, the processor, and the memory device.

[0071] exist Figure 6 In the temperature control strategy shown, once the temperature of the memory system reaches or exceeds the set temperature threshold T_th, a single performance reduction measure will be taken, that is, reducing the data transfer rate to reduce heat generation. However, reducing performance immediately when the temperature of the memory system reaches a critical point may cause a sudden drop in performance in high-load tasks, such as large-scale data transmission or complex application running, seriously affecting the user experience.

[0072] Figure 7 Shows Figure 6The temperature control curve diagram when the temperature control strategy is executed multiple times is shown in FIG. Figure 7 As shown, during the entire cycle of the memory system operation, multiple executions Figure 6 After the single-stage temperature control strategy is implemented, the temperature of the memory system and the data transmission rate of the memory system fluctuate periodically over time, and the average data transmission rate of the memory system is relatively low. It is understandable that although the single-stage temperature control strategy can control the temperature of the memory system to a certain extent, its performance stability is poor, which seriously affects the user experience.

[0073] It should be noted that Figure 7 The temperature curves shown are for multiple executions Figure 6 The simplified diagram of the temperature control strategy shown in the figure. For the specific temperature change process, please refer to Figure 6 and related descriptions for understanding.

[0074] Figure 8 A schematic diagram of a temperature control curve of another exemplary temperature control strategy for a memory system is shown. Figure 8 As shown, the maximum data transmission rate of the memory system is V_max. The memory system needs to perform temperature detection at regular intervals. When it is detected that the temperature of the memory system exceeds the set first temperature threshold T_th1, the data transmission rate of the memory system is reduced to the first data transmission rate V_base1. The time at this time is P1. By reducing the data transmission rate of the memory system to the first data transmission rate V_base1, the temperature rise rate of the memory system can be reduced. However, when the ambient temperature is too high, the temperature of the memory system will continue to rise. Therefore, it is necessary to further reduce the data transmission rate of the memory system. Then, when it is detected that the temperature of the memory system exceeds the set second temperature threshold T_th2, the data transmission rate of the memory system is reduced to the second data transmission rate V_base2. The time at this time is P2. When it is detected that the temperature of the memory system exceeds the set maximum temperature threshold T_th+△Temp, the data transmission rate of the memory system is reduced to the minimum data transmission rate V_min. The time at this time is P3.

[0075] Next, after detecting that the temperature of the memory system has dropped to the first temperature threshold T_th1 at time P4, the data transmission rate of the memory system is increased to the first data transmission rate V_base1. Finally, after detecting that the temperature of the memory system has dropped to the safe temperature T_th-△Temp at time P5, the memory system returns to normal read and write performance, and the data transmission rate of the memory system is increased to the maximum data transmission rate V_max.

[0076] Here, the set first temperature threshold T_th1, the set second temperature threshold T_th2, the maximum temperature threshold T_th+△Temp and the safety temperature T_th-△Temp may be empirical values, or may be default values ​​configured when the memory system is shipped from the factory, which are obtained through a large number of simulation experiments before the memory system is shipped from the factory. For example, the maximum temperature threshold T_th+△Temp may be 80°C, the set second temperature threshold T_th2 may be 70°C, the set first temperature threshold T_th1 may be 67°C, and the safety temperature T_th-△Temp may be 65°C.

[0077] Figure 8 The multi-step temperature control strategy shown has multiple temperature thresholds. Figure 6 The single-step temperature control strategy shown can more accurately control the data transfer rate of the memory. Users are less likely to notice a significant drop in memory system performance during high-load tasks, which reduces the adverse impact on user experience to a certain extent. However, the multi-step strategy is more complex and may increase costs.

[0078] In addition, the single-stage temperature control strategy and the multi-step temperature control strategy both use fixed preset values ​​(such as the basic data transmission rate V_base, the second data transmission rate V_base2, etc.) to reduce the data transmission rate during the temperature control process. There is a lack of flexibility in meeting different temperature and performance requirements under different working modes. Moreover, the single-stage temperature control strategy and the multi-step temperature control strategy have limited effects on temperature control when the ambient temperature is high or the ventilation and heat dissipation are poor, which may cause the memory system to work at high temperatures for a long time.

[0079] Based on one or more of the above problems, an embodiment of the present application proposes an operating method of a memory system.

[0080] Fig. 9 A schematic diagram of an implementation flow of an operating method of a memory system provided in one embodiment of the present application.

[0081] like Fig. 9 As shown, the operation method of the memory system specifically includes the following steps:

[0082] Step S10: Acquire the temperature parameters at the first moment and the temperature parameters at the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment.

[0083] Step S20: Determine the upper limit of the data transmission rate at the third moment based on the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

[0084] Here, the structure of the memory system refers to the aforementioned Figure 1 , I will not go into details here.

[0085] In some embodiments, when only one temperature sensor is disposed inside the memory system, the temperature measured by the temperature sensor is the temperature parameter of the memory system.

[0086] In some embodiments, when multiple temperature sensors are provided inside the memory system, obtaining the temperature parameters of the memory system includes: obtaining multiple temperature measurement data of temperature sensors at different positions in the memory system, and using the multiple temperature measurement data in combination with a temperature composite algorithm to obtain the temperature parameters. In this way, the temperature parameters can reflect the overall temperature of the memory system.

[0087] Taking a memory system including a three-dimensional NAND memory and a memory controller as an example, the temperature composite algorithm can be implemented by the following calculation formula: T=max{Tnand, Tcontroller}, where T is a temperature parameter of the memory system, Tnand is a maximum value among multiple temperature measurement data of temperature sensors at multiple positions of the three-dimensional NAND memory, and Tcontroller is a maximum value among multiple temperature measurement data of temperature sensors at multiple positions of the memory controller.

[0088] In some embodiments, the temperature composite algorithm can also be implemented by the following calculation formula: T = (Tcontroller-Tcom+Tnand) / 2. Wherein, T is the temperature parameter of the memory system, Tnand is the maximum value of multiple temperature measurement data of temperature sensors at multiple locations of the three-dimensional NAND memory, and Tcontroller is the maximum value of multiple temperature measurement data of temperature sensors at multiple locations of the memory controller. Tcom is a compensation value used to adjust the impact of the memory controller temperature. The compensation value can be adjusted according to the specific memory system and requirements to meet the performance and temperature management requirements.

[0089] It should be noted that the data transfer rate of a memory system refers to the data transfer rate or read / write data flow between the memory device and the memory controller of the memory system. The data transfer rate table is usually expressed in bits or bytes of data transferred per second (e.g., MB / s). A higher data transfer rate usually means that the memory system has better performance and can meet the needs of high read and write speeds more quickly.

[0090] Fig.10 A schematic diagram of a temperature control curve of a temperature control strategy provided in an embodiment of the application. Fig.11 This is a flowchart of an operation method of a memory system provided in an embodiment of the present application. Fig.10 and Fig.11 Describe in detail the process of determining temperature control.

[0091] When the memory system is powered on, step S201 is executed.

[0092] In step S202, the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters corresponding to the working mode at the first moment are obtained; the temperature control parameters are different in different working modes; the temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters.

[0093] In some embodiments, a preset period is spaced between any two adjacent moments. It is understandable that the temperature detection needs to be performed every preset period inside the memory system. The duration of the preset period ranges from 1s to 5s, and more specifically, the duration of the preset period can be 1s, 3s, or 5s.

[0094] For example, Fig.10 As shown, the temperature parameter T2 at the first moment t2 is obtained, the temperature parameter T0 at the second moment t0 which is two preset periods 2△t apart from the first moment t2, the temperature parameter T1 at the second moment t1 which is one preset period △t apart from the first moment t2, the data transmission rate V2 at the first moment t2, and the temperature control parameters corresponding to the working mode at the first moment t2 are obtained; the temperature control parameters are different under different working modes; the temperature control parameters include: the target control temperature Tsp and the proportional parameter (Proportion, P), the integral parameter (Integral, I), and the differential parameter (Differential, D).

[0095] In some embodiments, determining the operating mode of the memory system at a first moment includes: obtaining a temperature control parameter corresponding to the operating mode at the first moment according to the determined operating mode.

[0096] In some embodiments, for various operating modes of the memory system, the optimal proportional parameters, integral parameters, and differential parameters in the corresponding operating mode are obtained respectively; a mapping table between various operating modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters is generated, and the mapping table is stored and triggered to be called in the corresponding operating mode.

[0097] In some implementations, a large number of simulation experiments are conducted before the memory system leaves the factory, and for various working modes of the memory system, optimal proportional parameters, integral parameters, and differential parameters in corresponding working modes are obtained respectively.

[0098] Exemplarily, the command for adjusting the PID parameters of the interface (e.g., OS interface or debug interface debug) receiving the memory system is implemented through firmware (Firmware, FW) development. The proportional parameter P, integral parameter I, and differential parameter D are adjusted in sequence. Specifically, different workloads and data access modes are simulated, such as read-only, write-only, mixed read-write, etc. Different working modes are representative to simulate actual usage. At the beginning, the proportional parameter P is set to an initial value, usually an empirical value. At this time, the differential parameter D can be set to 0 and the integral parameter I can be set to 0. The fluctuation of the temperature parameter curve of the memory system under different working modes is recorded, and the proportional parameter P is gradually adjusted (the P value is generally adjusted from small to large), and its influence on the temperature parameter curve of the memory system is observed. The temperature parameter curve under different proportional parameters P is analyzed, wherein the optimal proportional parameter P can make the temperature parameter curve change neither oscillate excessively nor lag.

[0099] After determining the optimal proportional parameter under different working modes, the optimal proportional parameter is used, and the differential parameter D is set to 0, and the fluctuation of the curve of the temperature parameter of the memory system under different working modes is recorded, and the integral parameter I is gradually adjusted (the I value is generally adjusted from small to large) to confirm that the integral parameter corresponding to the temperature oscillation period and amplitude in the temperature parameter curve is small is the optimal integral parameter; then, based on the confirmed optimal proportional parameter and optimal integral parameter, the adjustment of the differential parameter D value is increased to confirm that the small-range fluctuation amplitude of the temperature parameter curve is reduced or disappears, and the temperature parameter curve is as smooth as possible, and the corresponding differential parameter is the optimal differential parameter.

[0100] In step S203, the upper limit of the data transmission rate at the third moment is determined according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters corresponding to the working mode at the first moment.

[0101] In some embodiments, Fig.10 As shown, the third moment t3 is separated from the first moment t2 by a preset period Δt.

[0102] In some embodiments, the data transmission rate V2 at the first moment t2 may be a real-time data transmission rate at the first moment t2, or may be an average data transmission rate within a preset period (t1-t2 period) before the first moment t2.

[0103] Exemplarily, the data transmission rate upper limit at the third moment is determined according to the following calculation formula:

[0104] V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]} (1), wherein V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter at the second moment t0 which is two preset periods 2△t apart from the first moment, T1 is the temperature parameter at the second moment t1 which is one preset period △t apart from the first moment, T2 is the temperature parameter at the first moment t2, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0105] In some embodiments, when the differential parameter D in the temperature control parameter corresponding to the working mode at the first moment is 0, the differential parameter D is substituted into the calculation formula (1) to obtain V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]. It can be understood that when the differential parameter D in the temperature control parameter corresponding to the working mode at the first moment is 0, the data transmission rate upper limit V3_limt at the third moment can be determined according to the temperature parameters at the first moment t2 and a second moment t1 before the first moment, the data transmission rate V2 at the first moment t2, and the temperature control parameters at the first moment.

[0106] After executing step S203, execute step S204 and end the operation.

[0107] By executing Fig.11 The operation method of the memory system shown in the figure finally obtains Fig.10 The temperature parameter curve shown ( Fig.10 The solid line curve in the figure) approaches the target control temperature when it is stable. At the same time, the data transfer rate curve of the memory system ( Fig.10 The fluctuation of the dotted curve in FIG. 1 gradually decreases until it approaches stability. In this way, in the process of effectively controlling the temperature of the memory system, the data transmission rate of the memory system can be kept at a high level and relatively stable, effectively improving the performance of the memory system and the user experience.

[0108] Fig.12 This is a flowchart of an operation method of a memory system provided by another embodiment of the present application. Fig.10 and Fig.12 Describe in detail the process of determining temperature control.

[0109] Here, the operation method from step S201 to step S202 has been described before and will not be repeated here.

[0110] In step S205 , a temperature deviation threshold is obtained.

[0111] In step S206, the temperature parameter T2 at the first time t2 is compared with the sum of the target control temperature Tsp and the temperature deviation threshold Toffset to determine whether the temperature parameter T2 at the first time t2 is greater than the sum of the target control temperature Tsp and the temperature deviation threshold Toffset.

[0112] In some embodiments, the target control temperature Tsp is an acceptable upper temperature limit for a memory system to operate. After reaching the target control temperature Tsp, a temperature control strategy can be used to reduce the temperature parameters of the memory system. Under the target control temperature Tsp, the memory system can still continue to operate normally. For example, the target control temperature Tsp is 70°C or 75°C.

[0113] The temperature deviation threshold Toffset is a temperature fluctuation range allowed after reaching the target control temperature Tsp. When the temperature parameter of the memory system is less than or equal to the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, the memory system can still continue to operate normally and no emergency measures will be triggered. The temperature deviation threshold Toffset can be an empirical value or a default value configured when the memory system leaves the factory. For example, the temperature deviation threshold Toffset can be 3°C, 4°C, or 5°C.

[0114] It should be noted that the specific values ​​of the target control temperature Tsp and the temperature deviation threshold Toffset are related to the type and purpose of the memory system. Therefore, the target control temperature Tsp and the temperature deviation threshold Toffset of the memory system need to be set and optimized according to the specific situation to maintain the stability and reliability of the memory system under different uses and environmental conditions.

[0115] When the temperature parameter T2 at the first moment t2 is greater than the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, step 207 is executed to set the upper limit of the data transmission rate at the third moment to be less than or equal to the preset data transmission rate. The preset data transmission rate can be an empirical value or a default value configured when the memory system leaves the factory.

[0116] In some embodiments, the preset data transmission rate is the data transmission rate corresponding to 10% of the full power consumption of the memory system. It is understandable that when the temperature parameter T2 at the first moment t2 is greater than the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, emergency measures are taken to sharply reduce the upper limit of the data transmission rate at the third moment to the preset data transmission rate, which can effectively prevent the memory system from being damaged by high temperature and protect the integrity of the data.

[0117] In some embodiments, the preset data transmission rate is 0 MB / s, which is a more extreme emergency measure that can be executed in more urgent scenarios, such as when the temperature parameter T2 at the first moment t2 is greater than the sum of the target control temperature Tsp and 2 times the temperature deviation threshold Toffset. The memory system will be completely stopped to ensure data security and prevent any potential damage to the memory system caused by high temperature. Once the temperature parameter of the memory system is reduced to a safe range, the data transmission rate of the memory system can be increased to resume normal operation.

[0118] When the temperature parameter T2 at the first moment t2 is less than or equal to the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, execute step S208 to determine the upper limit of the data transmission rate at the third moment based on the temperature parameters at the first and second moments, the data transmission rate at the first moment, and the corresponding temperature control parameters in the working mode at the first moment.

[0119] Exemplarily, the data transmission rate upper limit at the third moment is determined according to the following calculation formula:

[0120] V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]} (1), wherein V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter at the second moment t0 which is two preset periods apart from the first moment, T1 is the temperature parameter at the second moment t1 which is one preset period apart from the first moment, T2 is the temperature parameter at the first moment t2, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0121] In some embodiments, when the differential parameter D in the temperature control parameter corresponding to the working mode at the first moment is 0, the differential parameter D is substituted into the calculation formula (1) to obtain V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]. It can be understood that when the differential parameter D in the temperature control parameter corresponding to the working mode at the first moment is 0, the data transmission rate upper limit V3_limt at the third moment can be determined according to the temperature parameters at the first moment t2 and a second moment t1 before the first moment, the data transmission rate V2 at the first moment t2, and the temperature control parameters at the first moment.

[0122] After executing step S207 or step S208, execute step S209 to end the operation.

[0123] The operating method of the memory system provided in the embodiment of the present application determines the upper limit of the data transmission rate at the third moment after the first moment by obtaining the data transmission rate at the first moment, the temperature control parameters at the first moment, and the temperature parameters of at least one moment before the first moment. In this way, the upper limit of the data transmission rate at the next moment is dynamically predicted by the real-time temperature parameters and data transmission rate, and the memory system can dynamically adjust the upper limit of the data transmission rate at the next moment. This intelligent temperature control strategy allows the memory system to flexibly adjust the real-time data transmission rate according to actual conditions, so as to protect the memory system from high temperature damage to the greatest extent, while providing a good user experience. A balance between the temperature parameters and performance of the memory system is achieved.

[0124] The present application also provides a memory system. Figure 1 As shown, the memory system 102 includes: a memory device 104; a memory controller 106, coupled to the memory device 104 and configured to execute Fig. 9 The following steps are shown in :

[0125] Step S10: Acquire the temperature parameters at the first moment and the temperature parameters at the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment.

[0126] Step S20: Determine the upper limit of the data transmission rate at the third moment based on the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

[0127] In some embodiments, when only one temperature sensor is disposed inside the memory system, the temperature measured by the temperature sensor is the temperature parameter of the memory system.

[0128] In some embodiments, when multiple temperature sensors are provided inside the memory system, obtaining the temperature parameters of the memory system includes: obtaining multiple temperature measurement data of temperature sensors at different positions in the memory system, and using the multiple temperature measurement data in combination with a temperature composite algorithm to obtain the temperature parameters. In this way, the temperature parameters can reflect the overall temperature of the memory system.

[0129] In some embodiments, the memory controller 106 is specifically configured to: obtain temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters corresponding to the working mode at the first moment; the temperature control parameters are different under different working modes; the temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters.

[0130] In some embodiments, a preset period is spaced between any two adjacent moments. It is understandable that the temperature detection needs to be performed every preset period inside the memory system. The duration of the preset period ranges from 1s to 5s, and more specifically, the duration of the preset period can be 1s, 3s, or 5s.

[0131] For example, Fig.10 As shown, the temperature parameter T2 at the first moment t2 is obtained, the temperature parameter T0 at the second moment t0 which is two preset periods 2△t apart from the first moment t2, the temperature parameter T1 at the second moment t1 which is one preset period △t apart from the first moment t2, the data transmission rate V2 at the first moment t2, and the temperature control parameters corresponding to the working mode at the first moment t2 are obtained; the temperature control parameters are different in different working modes; the temperature control parameters include: the target control temperature Tsp and the proportional parameter, the integral parameter, and the differential parameter.

[0132] In some embodiments, the memory controller 106 is configured to: determine the working mode of the memory system at a first moment; and obtain the temperature control parameters corresponding to the working mode at the first moment according to the determined working mode.

[0133] In some embodiments, the memory controller 106 is further configured to: for various operating modes of the memory system, respectively obtain the optimal proportional parameters, integral parameters, and differential parameters in the corresponding operating mode; generate a mapping table between various operating modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters, store the mapping table, and trigger a call in the corresponding operating mode.

[0134] In some implementations, a large number of simulation experiments are conducted before the memory system leaves the factory, and for various working modes of the memory system, optimal proportional parameters, integral parameters, and differential parameters in corresponding working modes are obtained respectively.

[0135] Specifically, different workloads and data access modes are simulated, such as read-only, write-only, mixed read-write, etc. Different working modes are representative to simulate actual usage. At the beginning, the proportional parameter P is set to an initial value, usually an empirical value. At this time, the differential parameter D can be set to 0 and the integral parameter I can be set to 0. Record the fluctuation of the temperature parameter curve of the memory system under different working modes, gradually adjust the proportional parameter P (the P value is generally adjusted from small to large), and observe its impact on the temperature parameter curve of the memory system. Analyze the temperature parameter curve under different proportional parameters P, where the optimal proportional parameter P can make the temperature parameter curve change neither oscillate excessively nor lag.

[0136] After determining the optimal proportional parameter under different working modes, the optimal proportional parameter is used, and the differential parameter D is set to 0, and the fluctuation of the curve of the temperature parameter of the memory system under different working modes is recorded, and the integral parameter I is gradually adjusted (the I value is generally adjusted from small to large) to confirm that the integral parameter corresponding to the temperature oscillation period and amplitude in the temperature parameter curve is small is the optimal integral parameter; then, based on the confirmed optimal proportional parameter and optimal integral parameter, the adjustment of the differential parameter D value is increased to confirm that the small-range fluctuation amplitude of the temperature parameter curve is reduced or disappears, and the temperature parameter curve is as smooth as possible, and the corresponding differential parameter is the optimal differential parameter.

[0137] In some embodiments, the memory controller 106 is configured to: when the temperature parameter at the first moment exceeds the target control temperature, control the data transmission rate at the third moment to be below the corresponding data transmission rate upper limit, so that the temperature parameter approaches the target control temperature. Fig.10 As shown, when the temperature parameter T2 at the first moment t2 exceeds the target control temperature Tsp, the data transmission rate at the third moment t3 is controlled below the corresponding data transmission rate upper limit, so that the temperature parameter approaches the target control temperature Tsp.

[0138] In some embodiments, the memory controller 106 is configured to determine an upper limit of the data transmission rate at the third moment according to temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters in the working mode at the first moment.

[0139] In some embodiments, Fig.10 As shown, the third moment t3 is separated from the first moment t2 by a preset period Δt.

[0140] In some embodiments, the data transmission rate V2 at the first moment t2 may be a real-time data transmission rate at the first moment t2, or may be an average data transmission rate within a preset period (t1-t2 period) before the first moment t2.

[0141] Exemplarily, the data transmission rate upper limit at the third moment is determined according to the following calculation formula:

[0142] V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]}, wherein V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter at the second moment that is two preset cycles apart from the first moment, T1 is the temperature parameter at the second moment that is one preset cycle apart from the first moment, T2 is the temperature parameter at the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0143] In some embodiments, the memory controller 106 is further configured to: obtain a temperature deviation threshold; when the temperature parameter at the first moment is greater than or equal to the sum of the target control temperature and the temperature deviation threshold, set the data transmission rate upper limit at the third moment to be less than or equal to a preset data transmission rate.

[0144] In some embodiments, the target control temperature Tsp is an acceptable upper temperature limit for a memory system to operate. After reaching the target control temperature Tsp, a temperature control strategy can be used to reduce the temperature parameters of the memory system. Under the target control temperature Tsp, the memory system can still continue to operate normally. For example, the target control temperature Tsp is 70°C or 75°C.

[0145] The temperature deviation threshold Toffset is a temperature fluctuation range allowed after reaching the target control temperature Tsp. When the temperature parameter of the memory system is less than or equal to the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, the memory system can still continue to operate normally and no emergency measures will be triggered. The temperature deviation threshold Toffset can be an empirical value or a default value configured when the memory system leaves the factory. For example, the temperature deviation threshold Toffset can be 3°C, 4°C, or 5°C.

[0146] It should be noted that the specific values ​​of the target control temperature Tsp and the temperature deviation threshold Toffset are related to the type and purpose of the memory system. Therefore, the target control temperature Tsp and the temperature deviation threshold Toffset of the memory system need to be set and optimized according to the specific situation to maintain the stability and reliability of the memory system under different uses and environmental conditions.

[0147] When the temperature parameter T2 at the first moment t2 is greater than the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, the upper limit of the data transmission rate at the third moment is set to be less than or equal to the preset data transmission rate. The preset data transmission rate can be an empirical value or a default value configured when the memory system leaves the factory. In some embodiments, the preset data transmission rate is the data transmission rate corresponding to 10% of the full power consumption of the memory system. It can be understood that when the temperature parameter T2 at the first moment t2 is greater than the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, emergency measures are taken to sharply reduce the upper limit of the data transmission rate at the third moment to the preset data transmission rate, which can effectively prevent the memory system from being damaged by high temperature and protect the integrity of the data.

[0148] In some embodiments, when the temperature parameter T2 at the first moment t2 is less than or equal to the sum of the target control temperature Tsp and the temperature deviation threshold Toffset, the data transmission rate upper limit at the third moment is determined based on the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the corresponding temperature control parameters in the working mode at the first moment.

[0149] Exemplarily, the data transmission rate upper limit at the third moment is determined according to the following calculation formula:

[0150] V3_limt=V2-{P*(T2-T1)+I*[(T2+T1) / 2-Tsp]+D*[(T0+T2) / 2-T1]}, wherein V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter at the second moment that is two preset cycles apart from the first moment, T1 is the temperature parameter at the second moment that is one preset cycle apart from the first moment, T2 is the temperature parameter at the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

[0151] The present application also provides a memory system, comprising: a memory device; and a memory controller coupled to the memory device and configured to: within a period of time after a temperature parameter of the memory system exceeds a target control temperature, under different working environments, adjust the data transmission rate of the memory system so that the fluctuation of the data transmission rate of the memory system gradually decreases to a level close to stability (e.g., Fig.10 The dashed curve shown in FIG. 2 ) and the temperature parameters approach the target control temperature when they are stable (as shown in FIG. Fig.10 The solid line curve shown in ).

[0152] Fig.13 A block diagram of a computer-readable storage medium provided in one embodiment of the present application. Fig.13As shown, the computer-readable storage medium 1300 stores a computer program 1310, and when the computer program 1310 is executed by the processor, the operation method of the memory system in the above technical solution can be implemented. The operation method includes: obtaining the temperature parameters at the first moment and the temperature parameters at the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment; according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment, determining the upper limit of the data transmission rate at the third moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

[0153] The methods disclosed in the method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0154] The features disclosed in several device embodiments provided in this application can be arbitrarily combined without conflict to obtain new device embodiments.

[0155] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0156] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory system, characterized in that: include: Memory device; A memory controller is coupled to the memory device and is configured to: Acquire a temperature parameter at a first moment and a temperature parameter at a second moment, a data transmission rate at the first moment, and a temperature control parameter at the first moment; The upper limit of the data transmission rate at the third moment is determined based on the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

2. The memory system according to claim 1, wherein: The memory controller is specifically configured as follows: Acquire temperature parameters at the first moment and the second moment, a data transmission rate at the first moment, and temperature control parameters corresponding to the working mode at the first moment; The temperature control parameters are different in different working modes; The temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters; Determine an upper limit of the data transmission rate at the third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters corresponding to the working mode at the first moment; There is a preset period between any two adjacent moments.

3. The memory system according to claim 2, wherein: The memory controller is configured to: When the temperature parameter at the first moment exceeds the target control temperature, the data transmission rate at the third moment is controlled below the corresponding data transmission rate upper limit, so that the temperature parameter approaches the target control temperature.

4. The memory system according to claim 2, wherein: The memory controller is specifically configured as follows: The data rate upper limit at the third moment is determined according to the following calculation formula: V3_limt=V2-{P*(T2–T1)+I*[(T2+T1) / 2–Tsp]+D*[(T0+T2) / 2–T1]} Among them, V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter of the second moment that is two preset cycles apart from the first moment, T1 is the temperature parameter of the second moment that is one preset cycle apart from the first moment, T2 is the temperature parameter of the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

5. The memory system according to claim 2, wherein: The memory controller is further configured to: Get the temperature deviation threshold; When the temperature parameter at the first moment is greater than or equal to the sum of the target control temperature and the temperature deviation threshold, the upper limit of the data transmission rate at the third moment is set to be less than or equal to a preset data transmission rate.

6. The memory system according to claim 5, characterized in that: The preset data transmission rate is a data transmission rate corresponding to 10% of the full power consumption of the memory system.

7. The memory system according to claim 2, wherein: The memory controller is configured to: Determining an operating mode of the memory system at the first moment; According to the determined working mode, the temperature control parameters corresponding to the working mode at the first moment are obtained.

8. The memory system according to claim 7, characterized in that: The memory controller is further configured to: For various working modes of the memory system, respectively obtain the optimal proportional parameters, integral parameters, and differential parameters in the corresponding working modes; A mapping table between the various working modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters is generated, and the mapping table is stored and triggered to be called in the corresponding working mode.

9. The memory system according to claim 1, wherein: The memory controller is configured to: A plurality of temperature measurement data of temperature sensors at different positions in the memory system are obtained, and the temperature parameters are obtained by using the plurality of temperature measurement data in combination with a temperature compound algorithm.

10. A method for operating a memory system, characterized in that: The operation method comprises: Acquire a temperature parameter at a first moment and a temperature parameter at a second moment, a data transmission rate at the first moment, and a temperature control parameter at the first moment; The upper limit of the data transmission rate at the third moment is determined based on the temperature parameters of the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters at the first moment; wherein the second moment is at least one moment before the first moment, and the third moment is a moment after the first moment.

11. The operating method according to claim 10, characterized in that: The operation method also includes: Acquire temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and temperature control parameters corresponding to the working mode at the first moment; the temperature control parameters are different in different working modes; the temperature control parameters include: target control temperature and proportional parameters, integral parameters, and differential parameters; Determine an upper limit of the data transmission rate at the third moment according to the temperature parameters at the first moment and the second moment, the data transmission rate at the first moment, and the temperature control parameters corresponding to the working mode at the first moment; There is a preset period between any two adjacent moments.

12. The operating method according to claim 11, characterized in that: The operation method also includes: The data transmission rate upper limit at the third moment is determined according to the following calculation formula: V3_limt=V2-{P*(T2–T1)+I*[(T2+T1) / 2–Tsp]+D*[(T0+T2) / 2–T1]} Among them, V3_limt is the upper limit of the data transmission rate at the third moment, V2 is the data transmission rate at the first moment, T0 is the temperature parameter of the second moment that is two preset cycles apart from the first moment, T1 is the temperature parameter of the second moment that is one preset cycle apart from the first moment, T2 is the temperature parameter of the first moment, Tsp is the target control temperature, P is the proportional parameter, I is the integral parameter, and D is the differential parameter.

13. The operating method according to claim 11, characterized in that: The operation method also includes: Get the temperature deviation threshold; When the temperature parameter at the first moment is greater than or equal to the sum of the target control temperature and the temperature deviation threshold, the upper limit of the data transmission rate at the third moment is set to be less than or equal to a preset data transmission rate.

14. The operating method according to claim 11, characterized in that: The operation method also includes: Determining the operating mode of the memory system at the first moment; According to the determined working mode, the temperature control parameters corresponding to the working mode at the first moment are obtained.

15. The operating method according to claim 14, characterized in that: The operation method also includes: For various working modes of the memory system, respectively obtaining optimal proportional parameters, integral parameters, and differential parameters in corresponding working modes; A mapping table between the various working modes and the corresponding optimal proportional parameters, integral parameters, and differential parameters is generated, and the mapping table is stored and triggered to be called in the corresponding working mode.

16. A memory system, characterized in that: include: Memory device; A memory controller is coupled to the memory device and is configured to: within a period of time after the temperature parameter of the memory system exceeds the target control temperature, under different working environments, adjust the data transmission rate of the memory system so that the fluctuation of the data transmission rate of the memory system gradually decreases to a level close to stability and approaches the target control temperature when the temperature parameter is stable.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for operating the memory system according to any one of claims 9 to 15 are implemented.

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