Data access method and device, electronic equipment and storage medium

Abstract

The invention provides a data access method and device, electronic equipment and a storage medium, and the method comprises the steps: responding to an obtained data reading request, determining a first address of to-be-read data carried by the data reading request, transmitting the first row address and a reading instruction to a target storage chip, and transmitting the reading instruction to the target storage chip; and the data reading module is used for reading the candidate data corresponding to the first row address by the target storage chip, acquiring the candidate data read by the target storage chip, and determining to-be-read data corresponding to the first column address from the candidate data according to the first column address. Under the condition that the main processor needs to read data, the main processor obtains all columns of data read by the target storage chip based on the first row address as candidate data, the data volume obtained at a time is increased, and then the to-be-read data corresponding to the first column address is determined from the candidate data, so that the reading efficiency of the main processor is improved, and the reading efficiency of the main processor is improved. And the reading performance of the electronic equipment is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data access method, device, electronic device and storage medium. Background Art

[0002] In electronic devices, the main processor needs to control the reading and writing of data in the memory chip, and the memory chip, such as the Double Data Rate (DDR), needs to be addressed during the reading and writing process, that is, the row address and column address need to be determined respectively before the target address to be read or written can be determined based on the row address or column address, thereby realizing the reading and writing of data. However, this addressing method of the memory chip consumes a lot of time, and at the same time, it is impossible to read a lot of data at a time, so that the amount of data obtained by the main processor is small and inefficient. Summary of the invention

[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the present application proposes a data access method, device, electronic device and storage medium to improve the efficiency of data reading by changing the way data is read.

[0005] In one aspect, an embodiment of the present application provides a data access method, including:

[0006] In response to obtaining a data read request, determining a first address of the data to be read carried by the data read request; wherein the first address includes a first row address and a first column address;

[0007] Sending the first row address and a read instruction to a target memory chip; wherein the read instruction is used by the target memory chip to read candidate data corresponding to the first row address;

[0008] Acquire the candidate data read by the target storage chip;

[0009] The to-be-read data corresponding to the first column address is determined from the candidate data according to the first column address.

[0010] Another aspect of the present application provides a data access method, including:

[0011] In response to obtaining a first row address and a read instruction corresponding to the to-be-read data sent by the main processor, read and obtain candidate data corresponding to the first row address according to the read instruction;

[0012] The candidate data is sent to the main processor; wherein the candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

[0013] Another aspect of the present application provides a data access method and device, including:

[0014] A first determination module, configured to determine, in response to obtaining a data read request, a first address of the data to be read carried in the data read request; wherein the first address includes a first row address and a first column address;

[0015] A sending module, used for sending the first row address and a read instruction to a target memory chip; wherein the read instruction is used for the target memory chip to read the candidate data corresponding to the first row address;

[0016] An acquisition module, used for acquiring the candidate data read by the target storage chip;

[0017] The second determining module is used to determine the to-be-read data corresponding to the first column address from the candidate data according to the first column address.

[0018] Another aspect of the present application provides a data access method and device, including:

[0019] A reading module, configured to respond to obtaining a first row address and a reading instruction corresponding to the data to be read sent by the main processor, and read and obtain candidate data corresponding to the first row address according to the reading instruction;

[0020] A sending module is used to send the candidate data to the main processor; wherein the candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

[0021] Another aspect of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the foregoing method embodiment is implemented.

[0022] Another aspect of the present application is a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the foregoing method embodiment is implemented.

[0023] Another aspect of the present application provides a computer program product having a computer program stored thereon, which implements the method described in the aforementioned method embodiment when the program is executed by a processor.

[0024] The data access method, device, electronic device and storage medium proposed in the present application, in response to obtaining a data read request, determine the first address of the data to be read carried by the data read request, send the first row address and the read instruction to the target memory chip, the read instruction is used for the target memory chip to read the candidate data corresponding to the first row address, obtain the candidate data read by the target memory chip, and determine the data to be read corresponding to the first column address from the candidate data according to the first column address. When the main processor needs to read data, the main processor obtains the data of all columns read by the target memory chip based on the first row address as candidate data, which increases the amount of data obtained at one time, and then determines the data to be read corresponding to the first column address from the candidate data, thereby improving the reading efficiency of the main processor and the reading performance of the electronic device.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A schematic diagram of a data access method provided in an embodiment of the present application;

[0028] Figure 2 A flowchart of another data access method provided in an embodiment of the present application;

[0029] Figure 3 A flowchart of another data access method provided in an embodiment of the present application;

[0030] Figure 4 A flowchart of another data access method provided in an embodiment of the present application;

[0031] Figure 5 A flowchart of another data access method provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of the structure of a data access device provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of another data access device provided in an embodiment of the present application

[0034] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0036] The data access method, device, electronic device and storage medium of the embodiments of the present application are described below with reference to the accompanying drawings.

[0037] Figure 1 A flowchart of a data access method provided in an embodiment of the present application.

[0038] The executor of the data access method of the embodiment of the present application is a data access device, which can be set in a main processor in an electronic device. The main processor is, for example, a Host CPU. The electronic device can be a smart phone, a computer, a pad, a smart wearable device (such as a phone watch), and a device on the vehicle side, etc., which is not limited in this embodiment.

[0039] like Figure 1 As shown, the method may include the following steps:

[0040] Step 101: in response to obtaining a data read request, determining a first address of the to-be-read data carried in the data read request.

[0041] The data to be read may be data corresponding to the scene requirements, and the data to be read is stored in a storage chip, such as a DDR chip. The data read request may be triggered based on a user operation, for example, when the electronic device is turned on, it is necessary to read the boot-up related data from the storage chip to start the electronic device. Or it may be data reading automatically triggered during the operation of the device.

[0042] The first address is the address of the data to be read in the memory chip, and the first address includes a first row address and a first column address.

[0043] Step 102: Send the first row address and the read instruction to the target memory chip.

[0044] The first row address is used by the target memory chip to read candidate data corresponding to the first row address.

[0045] In an embodiment of the present application, when the target memory chip obtains a read instruction, the data corresponding to the first row address in the target memory chip can be read as candidate data according to the first row address, wherein the candidate data can be data of all columns, or data of set columns among all columns, thereby achieving that in the storage unit, the data of all columns can be read at once by parsing the first row address obtained, thereby improving the reading efficiency.

[0046] As an example, the main processor bit width is 64 bits (8 bytes). In the related art, the target memory chip needs to decode the row address first and then decode the column address through addressing. The addressing is performed according to the decoded row address and column address. The addressing time is long, and based on the addressing, a maximum of 256 bytes (32x64 / 8) can be read at a time. In this application, the target memory chip only needs to parse the row address, and based on the row address, the data of all column addresses corresponding to the row address can be read at one time, that is, the data of 1024-bit column addresses (8K Bytes, 1024x64 / 8), which reduces the addressing time, improves the performance of data reading, and improves the reading efficiency.

[0047] Step 103: Acquire candidate data read by the target storage chip.

[0048] In one implementation of the embodiment of the present application, the candidate data read by the target storage chip may be obtained based on the DDR bus.

[0049] Step 104 : determining the to-be-read data corresponding to the first column address from the candidate data according to the first column address.

[0050] Among them, the candidate data is the data in the set column corresponding to the first row address read by the storage chip. The data in the set column may not be all the data that the main processor needs to read. Therefore, it is needed to be used as candidate data to further determine the target data, that is, the data to be read, from the candidate data.

[0051] As an implementation method, the main processor can determine the data to be read corresponding to the first column address from the candidate data corresponding to the set column according to the first column address in the first address corresponding to the data to be read, so that after the main processor obtains all the column data of a row, it can obtain the data corresponding to the required target column from all the columns based on demand. When the system and stored data of the electronic device continue to increase, all the data of a row are read at a time through the target storage chip, and then the main processor selects the target data corresponding to the first column address from the data of all the columns corresponding to a row, that is, the data to be read, thereby improving the reading efficiency and the performance of the electronic device.

[0052] In the data access method of the embodiment of the present application, in response to obtaining a data read request, the first address of the data to be read carried by the data read request is determined, the first row address and the read instruction are sent to the target memory chip, the read instruction is used for the target memory chip to read the candidate data corresponding to the first row address, obtain the candidate data read by the target memory chip, and determine the data to be read corresponding to the first column address from the candidate data according to the first column address. When the main processor needs to read data, the main processor obtains the data of all columns read by the target memory chip based on the first row address as candidate data, which increases the amount of data read at one time, and then determines the data to be read corresponding to the first column address from the candidate data, thereby improving the reading efficiency of the main processor and improving the reading performance of the electronic device.

[0053] Based on the above embodiments, Figure 2 A flow chart of another data access method provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the method comprises the following steps:

[0054] Step 201 : in response to obtaining a data read request, determining a first address of the to-be-read data carried in the data read request.

[0055] Among them, step 201 can refer to the explanation in the above-mentioned embodiment, and the principle is the same, which will not be repeated here.

[0056] Step 202, obtaining the state of the control pin.

[0057] Among them, the control pin can be selected from pins with special functions in the main processor, such as G5, E6, J10, and P10. Of course, a pin can also be added separately as a control pin. The specific setting method is not limited in this disclosure.

[0058] Step 203: determining a target memory chip from the first memory chip and the second memory chip according to the state of the control pin.

[0059] In an embodiment of the present application, when the electronic device is turned on, the main processor reads the power-on startup data from the storage chip. If there is only one storage chip, when the data in one storage chip is abnormal and cannot be read, it will cause the device to fail to turn on, reducing the user experience.

[0060] In an embodiment of the present application, multiple storage chips are provided, including a first storage chip and a second storage chip. The two storage chips store the same data and can back up each other, or one of them can be a main storage chip and the other can be a backup storage chip. By providing multiple storage chips, it is possible to avoid the situation where data cannot be read or stored when one storage chip is abnormal. Therefore, a control pin is set on the main processor. When data reading is required, the state of the control pin is obtained, and the target storage chip is determined from the first storage chip and the second storage chip according to the state of the control pin for data reading.

[0061] As an implementation method, a control pin is connected to a button, and a target storage chip is selected from a first storage chip and a second storage chip according to the state of the control pin, including: when the first level signal on the control pin is a low level signal, the first storage chip is selected as the target storage chip; or, when the first level signal on the control pin is a high level signal, the second storage chip is selected as the target storage chip, and the storage chip selected by the user is obtained for access through the user's operation of the button.

[0062] Among them, the button in this embodiment can be used as an emergency switch. In one scenario, if the current electronic device is restarted or powered on, if the power-on data stored in a storage chip read by the main controller is abnormal and cannot be powered on, the user needs to manually trigger the button to change the state of the control pin, so that the main processor can read the power-on data stored in other storage chips, realize dynamic selection, realize power-on or restart, and avoid the problem of failure to boot.

[0063] As another implementation method, when the control pin is connected to a selection tool, wherein the selection tool is, for example, a selection switch, a digital selection tool, for example, selection number 1 corresponds to a first storage chip, and selection number 2 corresponds to a second storage chip, when the control pin receives a first selection signal sent by the selection tool, the first storage chip is used as the target storage chip; or, when the control pin receives a second selection signal sent by the selection tool, the second storage chip is used as the target storage chip.

[0064] Step 204: Send the first row address and the read instruction to the target memory chip.

[0065] Step 205: Acquire candidate data read by the target storage chip.

[0066] Step 206 : Determine the to-be-read data corresponding to the first column address from the candidate data according to the first column address.

[0067] Among them, step 204 to step 206 can refer to the explanation in the above-mentioned embodiment, and the principles are the same, so they will not be repeated here.

[0068] In the data access method of the embodiment of the present application, a control pin is set on the main processor, so that the user can control the signal of the control pin by pressing a button or selecting a tool, so that the main processor selects the target storage chip according to the signal of the control pin, and realizes data storage by dynamic selection. In addition, if the system update of the electronic device uses the first storage chip, once the update fails or other reasons cause the data of the first storage chip to be damaged and the main processor, that is, the host central processing unit, cannot be turned on, the second storage chip can be selected by pressing a button or selecting a tool to perform a rescue boot, thereby improving the reliability of the system and the user experience.

[0069] Based on the above embodiments, the present application provides another data access method. Figure 3 A flowchart of another data access method provided in an embodiment of the present application specifically illustrates how to write data to improve the writing efficiency, such as Figure 3 As shown, the method comprises the following steps:

[0070] Step 301: In response to obtaining a data write request, determine the to-be-written data carried in the data write request and a second address corresponding to the to-be-written data.

[0071] The second address includes a second row address and a second column address. The second address is the address of the data to be written in the memory chip. Since the address in the memory chip corresponding to the data to be written and the address in the memory chip corresponding to the data to be read may be different, in order to distinguish them, they are called the first address and the second address, so the row address and the column address included in the second column address are called the second row address and the second column address.

[0072] Step 302: Generate first mask data corresponding to the second row address according to the data to be written.

[0073] The first mask data includes mask data and non-mask data, and the non-mask data is the data to be written. The non-mask data corresponds to the second column address, that is, the non-mask data needs to be written into the target storage unit corresponding to the second row address and the second column address in the target storage chip.

[0074] As an implementation method, according to the number of columns corresponding to a row of data in the target storage unit, unmasked first data is generated according to the data to be written, and then according to the position of the second column address in the column, the data corresponding to the second column address in the first data is not masked, and the data corresponding to the columns other than the second column address is masked to obtain the first mask data, so as to identify the validity of the second column address data in the first mask data.

[0075] Step 303: Send the first mask data and the second row address to the target memory chip.

[0076] The first mask data is used for the target storage chip to store the non-masked data block in the first data to the target storage unit corresponding to the second row address and the second column address.

[0077] In an embodiment of the present application, the data to be written includes data of a set column in the second row address of the target memory chip. For example, there are 6 columns of data in a row of the target memory chip, that is, the data of the row corresponding to the second row address includes data from the 1st to the 6th row, and the data to be written is the data in the 2nd, 3rd and 4th columns in the row corresponding to the second row address. Before sending the data to be written to the target memory chip, it is necessary to mask the data corresponding to the columns that do not need to be written in a row through a data mask, that is, a Data Mask mechanism, to obtain a whole row of data, that is, the first mask data, the first mask data includes data of all columns in the row corresponding to the second row address, and the nth data in the first mask data corresponds to the nth column in the row corresponding to the second row address, wherein each mask data indicates that the data does not need to be stored in the row corresponding to the second row address of the target memory chip; each non-masked data indicates that the data needs to be stored in the storage unit corresponding to the second row address and the second column address of the target memory chip.

[0078] As an example, row A corresponding to the second row address of the target memory chip includes 6 columns of data, and the first mask data is [mask, X1, X2, X3, mask, mask]. Therefore, the first data, the fifth data and the sixth data in the first mask data do not need to be stored in the first column, the fifth column and the sixth column in row A of the target memory chip, while the second data, the third data and the fourth data in the first mask data are stored in the second column, the third column and the fourth column in row A of the target memory chip, thereby realizing that in the process of the main processor generating the first mask data corresponding to the second row address according to the data to be written, based on the second column address, it is determined which data in the first mask data needs to be masked and which data does not need to be masked, so that the first mask data carries the information of the second column address corresponding to the second row address in the target memory chip, and the information of the column address does not need to be decoded, and data storage can be realized, thereby improving storage efficiency.

[0079] In the data access method of the embodiment of the present application, when the main processor generates the first mask data corresponding to the second row address according to the data to be written, it determines which data in the first mask data needs to be masked and which data does not need to be masked based on the second column address, so that the first mask data carries the information of the second column address corresponding to the second row address in the target memory chip, realizes the storage of data without decoding the column address information, and improves the storage efficiency.

[0080] Based on the aforementioned embodiment, in the case where there are multiple memory chips, before sending the first data and the second row address to the target memory chip, it is necessary to first determine the target memory chip from the multiple memory chips, wherein the method for determining the target memory chip from the multiple memory chips can refer to the explanation in the aforementioned reading scenario, the principle is the same and will not be repeated here.

[0081] It should be noted that whether writing or reading is required is determined according to the needs of the business scenario, thereby determining whether to perform data reading of steps 101 to 104 or data writing of steps 301 to 303.

[0082] Based on the above embodiments, the present application provides another data access method. Figure 4 A flowchart of another data access method provided in an embodiment of the present application is shown, wherein the execution subject is a target storage chip among multiple storage chips, such as Figure 4 As shown, the following steps are included:

[0083] Step 401 , in response to obtaining a first row address and a read instruction corresponding to the to-be-read data sent by a main processor, read and obtain candidate data corresponding to the first row address according to the read instruction.

[0084] The first row address is the first address of the data to be read determined from the data carried in the data read request when the main processor obtains the data read request. Then, the main processor generates a read instruction and sends the read instruction to the target memory chip.

[0085] The target memory chip of the embodiment of the present application only needs one row decoding for address decoding, and data can be output without waiting for column decoding, which shortens the overall address decoding time by half. At the same time, 1024 consecutive column addresses on the same row address can be directly read and written at one time. Compared with the original operation range of 16 / 32 consecutive addresses, the data range that can be read and written at one time is increased by 32 times. At the same time, this simplified addressing method can also help the memory chip save the circuit of column address addressing and reduce the size and cost of the chip.

[0086] Step 402, sending the candidate data to the main processor.

[0087] The candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

[0088] It should be understood that the memory chip of the embodiment of the present application can be a memory chip that supports only decoding of row addresses. This memory chip can save the decoding circuit of the column address, thereby saving costs; or it can be achieved by modifying the storage logic of a conventional memory chip, that is, only the row address needs to be decoded to output the data of a positive row, without waiting for the column address to be addressed before outputting.

[0089] The explanations in the aforementioned embodiments are also applicable to this embodiment, and the principles are the same, which will not be repeated here.

[0090] In the data access method of the embodiment of the present application, when the main processor needs to read data, the main processor sends the first row address and the read instruction to the target memory chip. The target memory chip reads the candidate data corresponding to the first row address according to the read instruction, and sends the candidate data to the main processor, thereby eliminating the need for column addressing, reducing the time required for column addressing, and improving the data reading efficiency of the target memory chip. At the same time, the target memory chip can read the candidate data corresponding to all columns corresponding to the first row address based on the read instruction and the first row address, thereby simplifying the addressing method, obtaining data of all columns at one time, and improving the data reading efficiency of the target memory chip. In turn, the efficiency of the main processor in obtaining data is improved, and the reading performance of the electronic device is improved.

[0091] Based on the above embodiments, the present application provides another data access method. Figure 5 A flowchart of another data access method provided in an embodiment of the present application is shown, wherein the execution subject is a target storage chip among multiple storage chips, such as Figure 5 As shown, the following steps are included:

[0092] Step 501, in response to obtaining a second row address and first mask data corresponding to the data to be written sent by the main processor, storing non-masked data in the first mask data into a target storage unit corresponding to the second row address and the second column address.

[0093] The first mask data includes mask data and non-mask data; the non-mask data corresponds to the second column address.

[0094] The first mask data is the first mask data corresponding to the second row address generated by the main processor in response to obtaining the data write request, determining the data to be written carried in the data write request and the second address corresponding to the data to be written, according to the data to be written. The second address includes the second row address and the second column address.

[0095] Among them, the explanations and beneficial effects in the aforementioned embodiments are also applicable to this embodiment, and the principles are the same, so they will not be repeated here.

[0096] In order to implement the above embodiment, the embodiment of the present application further proposes a data access device.

[0097] Figure 6 A schematic diagram of the structure of a data access device provided in an embodiment of the present application.

[0098] like Figure 6 As shown, the device may include:

[0099] A first determination module 61 is used to determine, in response to obtaining a data read request, a first address of the data to be read carried in the data read request; wherein the first address includes a first row address and a first column address;

[0100] A sending module 62, configured to send the first row address and a read instruction to a target memory chip; wherein the read instruction is used by the target memory chip to read candidate data corresponding to the first row address;

[0101] An acquisition module 63, used for acquiring the candidate data read by the target storage chip;

[0102] The second determining module 64 is configured to determine the to-be-read data corresponding to the first column address from the candidate data according to the first column address.

[0103] Furthermore, in an implementation of the embodiment of the present application, the device further includes a writing module, the writing module being configured to:

[0104] In response to obtaining a data write request, determining the data to be written carried by the data write request and a second address corresponding to the data to be written; wherein the second address includes a second row address and a second column address;

[0105] Generate first mask data corresponding to the second row address according to the data to be written; wherein the first mask data includes mask data and non-mask data; the non-mask data corresponds to the second column address;

[0106] The first mask data and the second row address are sent to the target storage chip; wherein the first mask data is used by the target storage chip to store the non-masked data block in the first data to the target storage unit corresponding to the second row address and the second column address.

[0107] In an implementation of the embodiment of the present application, a control pin is set on the main processor, and the device further includes:

[0108] The selection module is used to obtain the state of the control pin; and determine the target storage chip from the first storage chip and the second storage chip according to the state of the control pin.

[0109] In one implementation of the embodiment of the present application, when the control pin is connected to the button, the selection module is also used to select the first storage chip as the target storage chip when a first level signal is generated on the control pin; or to select the second storage chip as the target storage chip when a second level signal is generated on the control pin.

[0110] In one implementation of the embodiment of the present application, when the control pin is connected to the selection tool, the selection module is also used to use the first storage chip as the target storage chip when the control pin receives a first selection signal sent by the selection tool; or to use the second storage chip as the target storage chip when the control pin receives a second selection signal sent by the selection tool.

[0111] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and will not be repeated here.

[0112] The data access device proposed in the present application, in response to obtaining a data read request, determines the first address of the data to be read carried by the data read request, sends the first row address and the read instruction to the target memory chip, and the read instruction is used for the target memory chip to read the candidate data corresponding to the first row address, obtain the candidate data read by the target memory chip, and determine the data to be read corresponding to the first column address from the candidate data according to the first column address. When the main processor needs to read data, the main processor obtains the data of all columns read by the target memory chip based on the first row address as candidate data, which increases the amount of data read at one time, and then determines the data to be read corresponding to the first column address from the candidate data, thereby improving the reading efficiency of the main processor and the reading performance of the electronic device.

[0113] In order to implement the above embodiment, the embodiment of the present application further proposes a data access device.

[0114] Figure 7 A schematic diagram of the structure of a data access device provided in an embodiment of the present application.

[0115] like Figure 7 As shown, the device may include:

[0116] The reading module 71 is used for, in response to obtaining a first row address and a reading instruction corresponding to the to-be-read data sent by the main processor, reading and obtaining candidate data corresponding to the first row address according to the reading instruction.

[0117] The sending module 72 is used to send the candidate data to the main processor; wherein the candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

[0118] In one implementation of the embodiment of the present application, the device also includes a write module, which is used to respond to obtaining a second row address and first mask data corresponding to the data to be written sent by the main processor; the first mask data includes mask data and non-mask data; the non-mask data corresponds to the second column address; and the non-mask data in the first mask data is stored in the target storage unit corresponding to the second row address and the second column address.

[0119] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and will not be repeated here.

[0120] In the data access device of the embodiment of the present application, when the main processor needs to read data, the main processor sends the first row address and the read instruction to the target memory chip. The target memory chip reads the candidate data corresponding to the first row address according to the read instruction, and sends the candidate data to the main processor, thereby eliminating the need for column addressing, reducing the time required for column addressing, and improving the data reading efficiency of the target memory chip. At the same time, the target memory chip can read the candidate data corresponding to all columns corresponding to the first row address based on the read instruction and the first row address, thereby obtaining data from all columns at one time, improving the data reading efficiency of the target memory chip, and further improving the efficiency of the main processor in obtaining data and improving the reading performance of the electronic device.

[0121] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in the above method embodiments is implemented.

[0122] In order to implement the above embodiments, the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above method embodiments is implemented.

[0123] In order to implement the above embodiments, the present application also proposes a computer program product on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiments is implemented.

[0124] Figure 8This is a block diagram of an electronic device provided in an embodiment of the present application. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0125] Reference Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0126] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0127] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0128] The power component 806 provides power to the various components of the electronic device 800. The power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0129] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0130] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0131] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0132] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0133] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0134] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0135] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by a processor 820 of an electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0136] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0137] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0138] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0139] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0140] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0141] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0142] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0143] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A data access method, characterized in that: Applicable to main processors, including: In response to obtaining a data read request, determining a first address of the data to be read carried by the data read request; wherein the first address includes a first row address and a first column address; Sending the first row address and a read instruction to a target memory chip; wherein the read instruction is used by the target memory chip to read candidate data corresponding to the first row address; Acquire the candidate data read by the target storage chip; The to-be-read data corresponding to the first column address is determined from the candidate data according to the first column address.

2. The method according to claim 1, characterized in that The method further comprises: In response to obtaining a data write request, determining the data to be written carried by the data write request and a second address corresponding to the data to be written; wherein the second address includes a second row address and a second column address; Generate first mask data corresponding to the second row address according to the data to be written; wherein the first mask data includes mask data and non-mask data; the non-mask data corresponds to the second column address; The first mask data and the second row address are sent to the target storage chip; wherein the first mask data is used by the target storage chip to store the non-masked data block in the first mask data to the target storage unit corresponding to the second row address and the second column address.

3. The method according to claim 1, characterized in that The main processor is provided with a control pin, and before sending the first row address and the read instruction to the target memory chip, the method further includes: Get the status of the control pin; A target memory chip is determined from the first memory chip and the second memory chip according to the state of the control pin.

4. The method according to claim 3, characterized in that When the control pin is connected to the button, determining the target storage chip from the first storage chip and the second storage chip according to the state of the control pin includes: When a first level signal is generated on the control pin, the first storage chip is selected as the target storage chip; or when a second level signal is generated on the control pin, the second storage chip is selected as the target storage chip.

5. The method according to claim 3, characterized in that: When the control pin is connected to the selection tool, determining the target memory chip from the first memory chip and the second memory chip according to the state of the control pin includes: When the control pin receives a first selection signal sent by the selection tool, the first storage chip is used as the target storage chip; Alternatively, when the control pin receives the second selection signal sent by the selection tool, the second storage chip is used as the target storage chip.

6. A data access method, characterized in that: Applied to target memory chips, including: In response to obtaining a first row address and a read instruction corresponding to the to-be-read data sent by the main processor, read and obtain candidate data corresponding to the first row address according to the read instruction; The candidate data is sent to the main processor; wherein the candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

7. The method according to claim 6, characterized in that include: In response to obtaining the second row address and first mask data corresponding to the data to be written sent by the main processor, the non-mask data in the first mask data is stored in the target storage unit corresponding to the second row address and the second column address; wherein the first mask data includes mask data and non-mask data; the non-mask data corresponds to the second column address.

8. A data access device, characterized in that: include: A first determination module, configured to determine, in response to obtaining a data read request, a first address of the data to be read carried in the data read request; wherein the first address includes a first row address and a first column address; A sending module, used for sending the first row address and a read instruction to a target memory chip; wherein the read instruction is used for the target memory chip to read the candidate data corresponding to the first row address; An acquisition module, used for acquiring the candidate data read by the target storage chip; The second determining module is used to determine the to-be-read data corresponding to the first column address from the candidate data according to the first column address.

9. A data access device, characterized in that: include: A reading module, configured to respond to obtaining a first row address and a reading instruction corresponding to the data to be read sent by the main processor, and read and obtain candidate data corresponding to the first row address according to the reading instruction; A sending module is used to send the candidate data to the main processor; wherein the candidate data is used by the main processor to determine the data to be read corresponding to the first column address from the candidate data according to the first column address corresponding to the data to be read.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method according to any one of claims 1 to 5 is implemented, or the method according to any one of claims 6 to 7 is implemented.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented, or the method according to any one of claims 6 to 7 is implemented.

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