Multi-thread dynamic binary translation method, device, equipment and product

Abstract

The invention discloses a multi-thread dynamic binary translation method, device, equipment and product. The method comprises the following steps: respectively establishing a cache table and a prediction table; the execution thread searches whether the address of the code block needing to be translated is recorded in the cache table or not, if the address of the code block needing to be translated is recorded, the corresponding translated code block is executed, and if the address of the code block needing to be translated is not recorded, the translating thread translates the code block needing to be translated and then the translated code block is executed by the execution thread; and further selecting the target code block recorded in the prediction table to translate according to a preset condition. According to the method, multi-thread binary translation can be realized through mutual cooperation of the execution thread and the translation thread; the same code block is prevented from being repeatedly translated by means of the immediately updated cache table, and waste of computing resources is reduced; by means of the immediately updated prediction table, the target code block with high skipping frequency can be translated in advance, so that the overall binary translation efficiency is improved, the program starting time is shortened, and the requirements of different hardware platforms are better met.

Description

Technical Field

[0001] The present invention belongs to the field of dynamic binary translation, and in particular relates to a multi-threaded dynamic binary translation method, device, equipment and product. Background Art

[0002] In the current computer field, the x86 architecture has established a mature and large software ecosystem with its wide application in the desktop and server markets. This ecosystem includes a large number of efficient and stable software developed and optimized for the x86 architecture. However, with the rapid development of embedded devices, the Internet of Things, and mobile computing, other architectures such as ARM and RISC-V have gradually gained attention. These emerging architectures have promoted their application in low-power and high-performance scenarios with their low-power and high-performance characteristics. However, since the software ecosystem of these emerging architectures is not yet mature, the widespread use of emerging architectures and the improvement of user experience are severely restricted.

[0003] The emergence of dynamic binary translation technology provides an important means to solve the above problems. By dynamically translating the binary code of the x86 architecture into the machine code of the target architecture when the program is running, the software can be compatible and run on different hardware platforms. This technology not only protects existing software investments, but also significantly reduces the migration cost of new hardware architectures, greatly improving cross-platform compatibility. However, in actual applications, the existing dynamic binary translation technology has the problem of repeatedly translating the same code blocks, wasting a lot of computing resources and significantly extending the program startup time. At the same time, it fails to effectively allocate translation tasks, there are problems such as uneven load or resource contention between threads, and the hardware parallel processing capabilities cannot be fully utilized. Summary of the invention

[0004] In view of this, the present invention aims to overcome the defects in the prior art and proposes a multi-threaded dynamic binary translation method, device, equipment and product.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows: In a first aspect, the present invention discloses a multi-threaded dynamic binary translation method, comprising: Establishing a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; The execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table. According to preset conditions, the target code block recorded in the prediction table is selected for translation, and the address of the translated target code block and the address of the corresponding translated code block are recorded in the cache table.

[0006] In another embodiment of the present invention, the method further includes: establishing a sorting table, the sorting table is used to instantly record the execution time sorting of the translated code blocks, when the cache table records are full, sorting according to the execution time, deleting the records of the translated code blocks that have not been executed for the longest time, and synchronously releasing the corresponding storage space.

[0007] In another embodiment of the present invention, selecting a target code block recorded in a prediction table for translation according to a preset condition includes: determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table.

[0008] In another embodiment of the present invention, the target code block to be translated is determined according to the jump times of the target code block recorded in the prediction table, including: translating the target code blocks with the highest jump times in descending order.

[0009] In another embodiment of the present invention, the method further comprises: translating adjacent code blocks of the currently translated code block to be translated, and recording addresses of the adjacent code blocks and addresses of corresponding translated code blocks in a cache table.

[0010] In another embodiment of the present invention, the execution thread updates the records in the prediction table.

[0011] In another embodiment of the present invention, according to a preset condition, before selecting the target code block recorded in the prediction table for translation, the method further includes: if the address of the target code block has been recorded in the cache table, the corresponding target code block is not translated.

[0012] In a second aspect, the present invention discloses a multi-threaded dynamic binary translation device, the device comprising: A table establishment module, used to establish a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; An execution module, used for executing a thread to search whether the address of the code block to be translated has been recorded in the cache table, and if it has been recorded, executing the corresponding translated code block; if it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table; The pre-translation module is used to select the target code block recorded in the prediction table for translation according to preset conditions, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table.

[0013] In a third aspect, the present invention discloses an electronic device, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the above method.

[0014] In a fourth aspect, the present invention discloses a computer program product, including a computer program, which implements the above method when executed by a processor.

[0015] Compared with the prior art, the present invention has the following advantages: The present invention discloses a multi-threaded dynamic binary translation method, device, equipment and product, including: establishing a cache table and a prediction table respectively; the execution thread searches whether the address of the code block to be translated has been recorded in the cache table, if it has been recorded, the corresponding translated code block is executed, if it has not been recorded, the translation thread translates the code block to be translated, and then the execution thread executes it; further, according to preset conditions, the target code block recorded in the prediction table is selected for translation, and the address of the translated target code block and the address of the corresponding translated code block are recorded in the cache table. The multi-threaded dynamic binary translation method, device, equipment and product disclosed by the present invention can realize multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; with the help of the cache table updated in real time, the repeated translation of the same code block is avoided, and the waste of computing resources is reduced; with the help of the prediction table updated in real time, the target code block with high jump frequency can be translated in advance, thereby improving the efficiency of the overall binary translation, reducing the time of program startup, and better adapting to the needs of different hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0017] In the attached picture: Figure 1 A schematic diagram of an application scenario of a multi-threaded dynamic binary translation method according to an embodiment of the present invention; Figure 2 A schematic diagram of a multi-threaded dynamic binary translation method according to an embodiment of the present invention; Figure 3 A schematic diagram of releasing space in a cache table according to a multi-threaded dynamic binary translation method according to an embodiment of the present invention; Figure 4A schematic diagram of adjacent code blocks translated by a multi-threaded dynamic binary translation method according to an embodiment of the present invention; Figure 5 A schematic diagram of a multi-threaded dynamic binary translation device according to an embodiment of the present invention; Figure 6 The present invention is a schematic diagram of an electronic device for multi-threaded dynamic binary translation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0020] In the description of the present invention, it should be further explained that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] The application scenarios of the multi-threaded dynamic binary translation method, device, equipment and product disclosed in the present invention are as follows: Figure 1As shown, under the existing technical conditions, the existing dynamic binary translation technology has the problem of repeatedly translating the same code block, wasting a lot of computing resources, greatly extending the program startup time, and failing to give full play to the hardware parallel processing capabilities. The present invention discloses a multi-threaded dynamic binary translation method, device, equipment and product, including establishing a cache table and a prediction table respectively; at the same time, it can select the target code block recorded in the prediction table for translation according to preset conditions, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table. The present invention discloses a multi-threaded dynamic binary translation method, device, equipment and product, which can realize multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; with the help of the cache table that is updated in real time, the repeated translation of the same code block is avoided, and the waste of computing resources is reduced; with the help of the prediction table that is updated in real time, the target code block with a high jump frequency can be translated in advance, thereby improving the efficiency of the overall binary translation, reducing the time of program startup, and improving the fluency of program operation.

[0022] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0023] In one embodiment of the present invention, Figure 2 As shown, a multi-threaded dynamic binary translation method includes: Step S201, respectively establishing a cache table and a prediction table, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of jumps from the translated code block to the target code block; In this embodiment, the cache table and the prediction table are both hash tables, the key of the prediction table is the address of the current translated code block, and the value is the list of target code blocks to which the translated code block is to jump.

[0024] Step S202, the execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table; In this embodiment, during the dynamic binary translation process, the execution thread searches the translated program one by one in units of code blocks according to the program flow to see whether the addresses of the code blocks to be translated have been recorded in the cache table.

[0025] In this embodiment, if the address of the code block to be translated has been recorded in the cache table, the corresponding translated code block is directly executed to achieve non-repeated translation of the code block.

[0026] The execution thread updates the records in the prediction table.

[0027] Step S203: According to preset conditions, select the target code block recorded in the prediction table for translation, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table.

[0028] In this embodiment, multiple translation threads are provided, which can translate several target code blocks in parallel and simultaneously, and cooperate with the code blocks to be translated to achieve multi-threaded simultaneous translation, which significantly improves the startup speed and operation of the program.

[0029] In this embodiment, before step S203, the following further includes: if the address of the target code block has been recorded in the cache table, the corresponding target code block is not translated.

[0030] This embodiment can realize multi-threaded binary translation through the cooperation between the execution thread and the translation thread; with the help of the real-time updated cache table, it can avoid repeated translation of the same code block and reduce the waste of computing resources; with the help of the real-time updated prediction table, it can translate the target code block with high jump frequency in advance, thereby improving the efficiency of the overall binary translation and reducing the time of program startup.

[0031] Based on the previous embodiment, in another embodiment of the present invention, Figure 3 As shown, the multi-threaded dynamic binary translation method also includes: establishing a sorting table, the sorting table is used to instantly record the execution time sorting of the translated code blocks, when the cache table records are full, sorting according to the execution time, deleting the records of the translated code blocks that have not been executed for the longest time, and synchronously releasing the corresponding storage space.

[0032] In this embodiment, the sorting table is a bidirectional linked list. Each executed translated code block is inserted into the head of the linked list, indicating the latest executed translated code block, while the tail indicates the translated code block that has not been executed for the longest time.

[0033] This embodiment can immediately release the storage space corresponding to the cache table, implement dynamic management of the cache, and reduce redundancy and storage space occupation.

[0034] Based on the previous embodiment, in another embodiment of the present invention, Figure 2 As shown, in step S203, according to a preset condition, a target code block recorded in the prediction table is selected for translation, including: determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table.

[0035] Furthermore, in this embodiment, the target code blocks with the first several bits in descending order of the number of jumps are translated.

[0036] Exemplarily, the number of the first several digits can be set as needed, for example, the first three digits.

[0037] This embodiment can translate the target code blocks with high jump frequency in advance according to the setting situation, and can freely adjust the selection range of the target code blocks translated in advance, thereby improving the efficiency of the overall binary translation and reducing the time of program startup.

[0038] Based on the previous embodiment, in another embodiment of the present invention, Figure 4 As shown, the method further includes: translating adjacent code blocks of the currently translated code block to be translated, and recording the addresses of the adjacent code blocks and the addresses of the corresponding translated code blocks in a cache table.

[0039] In this example, adjacent code blocks can be translated using independent translation threads.

[0040] In this embodiment, there are multiple translation threads. Exemplarily, one translation thread is used to translate adjacent code blocks, and the other multiple translation threads respectively perform one-to-one parallel translation on multiple target code blocks.

[0041] The translation of adjacent code blocks reflects the principle of spatial locality. The target code block reflects the activity level of future code blocks. Both adjacent code blocks and target code blocks are independently translated in advance using translation threads. The two work together to effectively improve the overall efficiency of binary translation and reduce the time for program startup.

[0042] For example, an ELF file of an x86 application needs to be run on a RISC-V platform and needs to be translated. According to the program entry in the ELF file, the execution thread starts from the code block 0x1000 to be translated, and searches whether the address of the code block 0x1000 to be translated has been recorded in the cache table. If it has been recorded, the translated code block corresponding to the code block 0x1000 to be translated is directly executed; If it is not recorded, the execution thread notifies the translation thread to translate the code block 0x1000 to be translated; After the translation thread completes the translation, it sends the address of the translated code block to the execution thread for execution. At the same time, the address of the code block 0x1000 to be translated and the address of the corresponding translated code block are recorded in the cache table, and the address of the code block 0x1000 to be translated is inserted into the head of the sorting table, indicating that it has been used recently for execution; The cache table is updated to include the address of the code block 0x1000 to be translated and the address of the corresponding translated code block, and the header of the sorting table is updated to the address of the code block 0x1000 to be translated.

[0043] Another translation thread translates the adjacent blocks of the current code block 0x1000 to be translated, such as 0x1010 and 0x1020, and records the addresses of the corresponding translated code blocks into the cache table at the same time, and further inserts the addresses of the code blocks 0x1010 and 0x1020 to be translated into the head of the sorting table; The cache table is updated to include the code blocks 0x1000, 0x1010 and 0x1020 to be translated and the addresses of the corresponding translated code blocks, and the sorting table is updated to have the code block 0x1020 to be translated at the head, the code block 0x1010 to be translated next, and the code block 0x1000 to be translated at the tail.

[0044] The prediction table records show that the historical jump targets of the code block 0x1000 to be translated are the code blocks 0x2000 (jump 5 times), 0x3000 (jump 3 times) and 0x4000 (jump 2 times) to be translated. In addition, multiple translation threads translate the code blocks 0x2000, 0x3000 and 0x4000 to be translated in parallel, record them in the cache table, and update the sort table header.

[0045] The cache table is updated to include the code blocks to be translated 0x1000, 0x1010, 0x1020, 0x2000, 0x3000, 0x4000 and the addresses of the corresponding translated code blocks, and the sorting table is updated to have the code block 0x4000 to be translated at the head, followed by the code blocks 0x3000, 0x2000, 0x1020, 0x1010 and 0x1000 to be translated.

[0046] When the cache table is full and a new record of the code block 0x5000 to be translated is needed, the record of the code block 0x1000 to be translated at the end of the sort table is deleted, the record of 0x1000 is removed from the cache table, and the corresponding storage space is released synchronously.

[0047] The cache table is updated to include the code blocks to be translated: 0x5000, 0x4000, 0x3000, 0x2000, 0x1020, 0x1010; the sort table is updated to have the head at 0x5000 and the tail at 0x1010; like Figure 5 As shown, the present invention also discloses a multi-threaded dynamic binary translation device, comprising: A table establishment module 501 is used to establish a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of jumps from the translated code block to the target code block; An execution module 502 is used for the execution thread to search whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table; The pre-translation module 503 is used to select the target code block recorded in the prediction table for translation according to preset conditions, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table.

[0048] The present invention also discloses an electronic device, such as Figure 6 As shown, an embodiment is disclosed, which is a block diagram of an electronic device suitable for the above-mentioned multi-threaded dynamic binary translation.

[0049] The electronic device 60 of this embodiment includes a processor 601, which can perform various appropriate actions and processes according to the program stored in the ROM 602 or the program loaded from the storage part 608 to the RAM 603. The processor 601 may include, for example, a general-purpose microprocessor, an instruction set processor and / or a related chipset and / or a dedicated microprocessor, etc. The processor 601 may also include an onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0050] In RAM603, various programs and data required for the operation of electronic device 60 are stored. Processor 601, ROM602 and RAM603 are connected to each other through bus 604, and processor 601 performs various operations of the method flow according to the embodiment of the present invention by executing the program in ROM602 and / or RAM603. It should be noted that the program can also be stored in one or more memories other than ROM602 and RAM603, and processor 601 can also perform various operations of the method flow according to the embodiment of the present invention by executing the program stored in one or more memories.

[0051] According to an embodiment of the present invention, the electronic device 60 may further include an I / O interface 605, which is also connected to the bus 604. The electronic device 60 may further include one or more of the following components connected to the I / O interface 605: an input portion 606 including a keyboard, a mouse, etc.; an output portion 607 including a cathode ray tube, a liquid crystal display, and a speaker; a storage portion 608 including a hard disk, etc.; and a communication portion 609 including a network interface card such as a LAN card, a modem, etc. The communication portion 609 performs communication processing via a network such as the Internet. A drive 6010 is also connected to the I / O interface 605 as needed. A removable medium 6011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 6010 as needed, so that a computer program read therefrom is installed into the storage portion 608 as needed.

[0052] The present invention also provides a computer-readable storage medium.

[0053] The computer-readable storage medium may be included in the electronic device / device system described in the above embodiment; or it may exist independently without being assembled into the electronic device / device. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present invention is implemented.

[0054] According to an embodiment of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include but is not limited to: a portable computer disk, a hard disk, a random access memory RAM, a read-only memory ROM, an erasable programmable read-only memory EPROM or a flash memory, a portable compact disk read-only memory CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, apparatus, or device.

[0055] Embodiments of the present invention also include a computer program product.

[0056] The computer program product includes a computer program, which contains program codes for executing the method provided by the embodiment of the present invention. When the computer program product runs on an electronic device, the program codes are used to enable the electronic device to implement the method provided by the embodiment of the present invention.

[0057] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium. The program code included in the computer program may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0058] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written by any combination of one or more programming languages, and specifically, these computing programs can be implemented using high-level process and / or object-oriented programming languages. Programming languages ​​include but are not limited to programming languages ​​such as Java, C++, python, C language or similar. The program code can be executed completely on the user computing device, partially on the user device, partially on the remote computing device, or completely on the remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network or a wide area network, or can be connected to an external computing device.

[0059] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways, even if such a combination or combination is not explicitly recorded in the present invention. In particular, without departing from the spirit and teaching of the present invention, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present invention.

[0060] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination. The scope of the present invention is limited by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A multi-threaded dynamic binary translation method, characterized in that: include: Establishing a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; The execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the corresponding address of the translated code block are recorded in the cache table. According to a preset condition, the target code block recorded in the prediction table is selected for translation, and the address of the translated target code block and the corresponding address of the translated code block are recorded in the cache table.

2. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The method further includes: establishing a sorting table, the sorting table being used to instantly record the execution time sorting of the translated code blocks, and when the cache table records are full, deleting the records of the translated code blocks that have not been executed for the longest time according to the execution time sorting, and synchronously releasing the corresponding storage space.

3. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The selecting the target code block recorded in the prediction table for translation according to a preset condition includes: determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table.

4. A multi-threaded dynamic binary translation method according to claim 3, characterized in that: Determining the target code block to be translated according to the number of jumps of the target code block recorded in the prediction table includes: translating the target code blocks that are ranked first in descending order of the number of jumps.

5. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The method further includes: translating adjacent code blocks of the currently translated code block to be translated, and recording addresses of the adjacent code blocks and corresponding addresses of the translated code blocks in the cache table.

6. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The execution thread updates the records in the prediction table.

7. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: Before selecting the target code block recorded in the prediction table for translation according to the preset condition, the method further includes: if the address of the target code block has been recorded in the cache table, the corresponding target code block is not translated.

8. A multi-threaded dynamic binary translation device, characterized in that: The device comprises: A table establishment module, used to establish a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; An execution module, configured to execute a thread to search whether the address of the code block to be translated has been recorded in the cache table, and if so, to execute the corresponding translated code block; if not, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table; The pre-translation module is used to select the target code block recorded in the prediction table for translation according to preset conditions, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table.

9. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are caused to perform the method according to any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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