A low-power single-issue out-of-order execution RISC-V processor and instruction processing method

Abstract

This invention discloses a low-power single-issue out-of-order execution RISC-V processor, comprising a seven-stage pipeline architecture, namely: an instruction fetch unit, an instruction buffer unit, a decoding unit, a single-instruction issue unit, a physical register file, a parallel out-of-order execution unit, and a retirement unit. The instruction fetch unit serves as the front end of the RISC-V processor; the five-stage pipeline architecture consisting of the decoding unit, the issue unit, the physical register file, the execution unit, and the retirement unit serves as the back end of the RISC-V processor. Through the above technical solution, this invention provides a microarchitecture that is more balanced in performance and power consumption, thereby improving the applicability of the processor core in high-computation-demand and power-sensitive scenarios.

Description

Technical Field

[0001] This invention belongs to the field of computer architecture and integrated circuit technology, and particularly relates to a low-power single-issue out-of-order execution RISC-V processor and instruction processing method. Background Technology

[0002] RISC-V is short for Reduced Instruction Set Computing (RISC), the fifth generation of instruction sets. Its main characteristics are simplification, open source, modularity, and scalability. The RISC-V instruction set includes various instruction architectures. The basic instruction set includes the 32-bit integer instruction set RV32I and the 64-bit integer instruction set RV64I; the extended instruction set includes 32-bit multiplication and division RV32M, 32-bit single-precision floating-point arithmetic RV32F, and 64-bit multiplication and division RV64M, etc. Names containing both the basic and extended instruction sets can be combined; for example, RV32IM indicates that the current instruction set includes both 32-bit integer and multiplication / division instructions.

[0003] Currently, processor core designs based on the RISC-V instruction set architecture mainly focus on two directions: low-power designs for embedded scenarios such as mobile devices and edge computing; and high-performance designs for servers, artificial intelligence, and other applications requiring significant computing resources. In terms of low-power implementation, processors typically employ fewer pipeline stages and a sequential execution architecture to reduce hardware resource consumption and meet low-power requirements. However, due to the overly simple processor structure, this design is relatively inefficient, with more clock cycles of pipeline stalls caused by data conflicts, wasting more computation time. Such designs may fail to meet real-time requirements due to low computational efficiency. In scenarios with both timeliness and computational power requirements, such as autonomous driving and edge computing, insufficient processor performance may lead to malfunctions. In terms of high-performance implementation, some existing processors employ superscalar technology, using complex microarchitectures with multiple issues and out-of-order execution to improve instruction parallelism and thus enhance processor efficiency. However, existing designs significantly increase hardware resource and energy consumption, resulting in higher core resource consumption and power consumption. In power- and cost-sensitive applications such as edge computing, how to improve processor computing efficiency with less hardware resources and lower power consumption has become an urgent problem to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a low-power single-issue out-of-order execution RISC-V processor microarchitecture. While improving processor instruction parallelism and processing efficiency, it fully considers the low-power design of the microarchitecture. By developing a microarchitecture that is more balanced in performance and power consumption, the applicability of the processor core in high-computation and power-sensitive scenarios is improved, thereby solving the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides a low-power single-issue out-of-order execution RISC-V processor, comprising a seven-stage pipeline architecture, which are, in order: an instruction fetch unit, an instruction buffer unit, a decoding unit, a single-instruction issue unit, a physical register file, a parallel out-of-order computation execution unit, and a retirement unit.

[0006] In addition, the present invention also provides an instruction processing method for the RISC-V instruction set, including processing input RISC-V instructions based on the seven-stage pipeline architecture of the RISC-V processor described above.

[0007] Compared with the prior art, the present invention has the following advantages and technical effects:

[0008] This invention employs various techniques, including clock gating, input gating, and glitches optimization, to successfully reduce overall core power consumption while maintaining efficient processor execution, thus achieving a better balance between processor performance and energy efficiency. These optimizations play a crucial role in core power management, enabling the processor to maintain low power consumption while operating efficiently. Attached Figure Description

[0009] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0010] Figure 1 This is a diagram of the overall microarchitecture of the RISC-V processor core according to an embodiment of the present invention;

[0011] Figure 2 This is an internal architecture diagram of the instruction fetching unit according to an embodiment of the present invention;

[0012] Figure 3 This is a flowchart of a method for predicting the execution branch of the instruction fetch unit according to an embodiment of the present invention;

[0013] Figure 4 This is an internal architecture diagram of a register renaming unit according to an embodiment of the present invention;

[0014] Figure 5 This is a logical operation structure diagram of a priority arbitration tree according to an embodiment of the present invention;

[0015] Figure 6 This is a flowchart illustrating one method of register renaming according to an embodiment of the present invention.

[0016] Figure 7 This is an internal structural diagram of the transmitting unit according to an embodiment of the present invention;

[0017] Figure 8 This is an internal architecture diagram of the memory access path for accessing peripheral devices to load and store data, according to an embodiment of the present invention.

[0018] Figure 9 This is a schematic diagram comparing the Coremark scores of the kernel in this embodiment of the invention and existing kernels;

[0019] The attached diagrams are labeled as follows: 10, Instruction Fetch Unit; 11, Dynamic Branch Predictor; 12, Program Counter; 13, Level 1 Tightly Coupled Instruction Cache Unit; 20, Instruction Buffer Unit; 30, Decoding Unit; 31, Decoding Logic Circuit; 32, Register Renaming Unit; 321, Physical Register Free List; 322, Predictive Renaming Map; 323, Physical Register Ready List; 324, Register Allocation Logic Circuit; 325, First Priority Arbitration Tree; 326, Physical Register Free List. Checkpoints; 327. Architecture renaming mapping table; 40. Issue unit; 41. Dispatch logic; 411. Issue ready logic; 412. Allocation logic; 413. Age arbitration tree; 50. Physical register file; 60. Execution unit; 61. Arithmetic logic unit (ALU); 62. Multiplication and division unit (MDU); 63. Memory access unit (LSU); 64. First-level tightly coupled data cache unit; 70. Retirement unit; 71. Reorder cache; 80. Cache bus; 90. AXI interface. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0022] For applications in embedded, mobile, and edge devices where hardware resources and energy are limited but computational performance requirements are high, this invention aims to design a low-power, single-issue, dynamically scheduled, out-of-order execution processor based on the RISC-V instruction set that achieves a better balance between performance and power consumption and higher execution efficiency. This invention primarily focuses on two key issues in processor design: first, how to improve processor performance and processing efficiency, and enhance instruction parallelism to adapt to scenarios with increasing computational demands; and second, how to reduce processor power consumption so that it can operate efficiently in mobile and embedded environments with limited hardware resources and power consumption. To address the aforementioned problems, the objective of this invention is to improve processor instruction parallelism and processing efficiency while fully considering low-power microarchitecture design, thereby enhancing the applicability of the processor core in high-computational-demand and power-sensitive scenarios by developing a microarchitecture that achieves a more balanced performance and power consumption.

[0023] This invention proposes a pipelined microarchitecture scheme for processors that achieves a better balance between performance and power consumption, improving processor instruction parallelism while also ensuring low power consumption of the microarchitecture.

[0024] like Figure 1 As shown, the low-power single-issue out-of-order execution RISC-V processor provided by the present invention includes a seven-stage pipeline architecture, which are as follows: instruction fetch unit 10, instruction buffer unit 20, decoding unit 30, single-instruction issue unit 40, physical register file 50, parallel out-of-order computation execution unit 60, and retirement unit 70.

[0025] The instruction fetch unit 10 serves as the front end of the RISC-V processor; the five-stage pipeline architecture consisting of the decoding unit 30, the issue unit 40, the physical register file 50, the execution unit 60, and the retirement unit 70 serves as the back end of the RISC-V processor.

[0026] The instruction fetch unit 10 is used to read the corresponding RISC-V instruction from the off-chip memory according to the PC value of the current cycle and send it to the instruction buffer unit 20; it is also used to predict the PC value of the next cycle through the dynamic branch predictor 11. Specifically, the PC value refers to the output value of the program counter 12 (PC) in the processor. The PC value points to the storage address of the instruction to be executed in the current cycle in the off-chip memory, so the PC value is also the read address of the off-chip memory storing the instruction to be executed, so as to retrieve the RISC-V instruction to be executed in the current cycle. In this embodiment, the RISC-V instruction to be processed is stored off-chip (i.e., outside the processor), which helps to reduce the hardware resource consumption and chip area of ​​the RISC-V processor itself; however, there is usually a certain cost of read clock. Therefore, in order to reduce clock latency and achieve efficient off-chip memory instruction fetching, this embodiment of the invention further sets up a tightly coupled instruction cache unit 13 in the instruction fetch unit 10.

[0027] The first-level tightly coupled instruction cache unit 13 is used to access RISC-V instructions in the off-chip memory through the cache bus 80 and AXI interface 90 according to the PC value of the current cycle, and read out and cache multiple RISC-V instructions corresponding to the PC value of the current cycle and the PC value of the adjacent cycle.

[0028] The first-level tightly coupled instruction cache unit 13 is also used to check whether it has cached the corresponding RISC-V instruction based on the PC value of the current cycle; if so, it will send the RISC-V instruction inside that corresponds to the PC value of the current cycle to the instruction buffer unit 20; otherwise, it will access the off-chip memory through the cache bus 80 and the AXI interface 90, send the RISC-V instruction corresponding to the PC value of the current cycle to the instruction buffer unit 20, and read out and cache multiple RISC-V instructions corresponding to the PC values ​​of adjacent cycles.

[0029] The instruction buffer unit 20 is used to receive RISC-V instructions from the instruction fetch unit 10 in sequence, forming an instruction buffer queue to isolate the front-end computing and back-end computing of the RISC-V processor.

[0030] The five-stage pipeline architecture at the back end of the RISC-V processor is used to sequentially decode RISC-V instructions, issue single instructions, read and write physical register file 50, execute out of order, and retire operations, implementing register data path and memory access path. The register data path and memory access path share the same three-stage pipeline path (instruction fetch, instruction buffer, and decoding), but differ in the four-stage pipeline path (issue, read / write physical register file 50, execution, and retirement), as detailed below. Figure 1As shown. The core difference between the memory access path and the register data path is that the memory access path is used to execute load and store instructions. It reads and writes physical register file 50 through an independent memory access issue queue, and reads and writes off-chip data through an independent execution unit 60, namely memory access unit LSU63.

[0031] In most cases, the PC value automatically increments as instructions are executed, ensuring that the program executes sequentially. However, the RISC-V instruction set contains unconditional jump instructions JAL (Jump Link) and J (Direct Jump), as well as conditional jump instructions such as beq (jump if equal), bne (jump if unequal), and blt (jump if less than). Therefore, the RISC-V processor designed in this embodiment needs to be able to adapt to the execution of these branch instructions (also known as jump instructions or branch jump instructions). When the RISC-V processor provided in this embodiment encounters branch instructions (including conditional jumps and unconditional jumps), the designed dynamic branch predictor 11 predicts and modifies the final PC value based on the jump address (jump target PC) in the instruction, thereby changing the program execution flow. In practical implementation, since it is impossible to know whether an instruction is a jump instruction before executing the instruction of the current cycle, branch prediction is required for the PC value corresponding to each instruction to be executed during the instruction fetch stage. Whether the PC value prediction was successful can be determined during the decoding or execution stage. If successful, execution of the next cycle's instruction can proceed quickly; if unsuccessful, the processor's pipeline at each stage needs to be restored. The RISC-V processor provided in this embodiment of the invention possesses the above-mentioned fast branch prediction and branch prediction failure recovery functions.

[0032] In a preferred embodiment, one circuit implementation architecture of the dynamic branch predictor 11 in the instruction fetching unit 10 is as follows: Figure 2 As shown. Specifically, the dynamic branch predictor 11 includes: a predictive global history register (P-GHR), a query circuit ( Figure 2 (Not shown in the text) Mode History Table (PHT), Saturation Counter (SC), Branch Target Buffer (BTB), Return Address Stack (RAS), and Jump Arbiter (JA).

[0033] Each address space in the Pattern History Table (PHT) stores a saturation count value indicating whether a jump has occurred; the Branch Target Buffer (BTB) records the PC value of the branch instruction that has jumped and its jump address; the Return Address Stack (RAS) stores the function call target address corresponding to the function return instruction.

[0034] The query circuit is used to perform logical operations on the PC value of the current period and the global jump history prediction value output by the Predictive Global History Register (P-GHR) to obtain an index address, and query the Pattern History Table (PHT) according to the index address to determine whether the PC value of the current period has jumped.

[0035] The saturation counter (SC) is used to update the corresponding saturation counter value in the pattern history table (PHT) based on the jump state of the PC value in the current cycle. In this embodiment, a 2-bit saturation counter is preferably used to predict and represent the jump state ("jump" or "no jump") of the instruction, that is, the generated saturation counter value is a 2-bit binary value from 00 to 11. When the saturation counter value is 00, it indicates that the current instruction is predicted to be strongly non-jump (SNT), indicating that the historical execution results show that the instruction almost never jumps; 01 is weakly non-jump (WNT), indicating that the historical execution results show that the instruction sometimes jumps and sometimes does not jump; similarly, 10 is weakly jump (WT), and 11 is strongly jump (ST). Although the saturation counter is a 2-bit counter with four output states, in this invention, when the saturation counter value is 00 and 01, the instruction in the current cycle is predicted to be non-jump; when the saturation counter value is 10 and 11, the instruction in the current cycle is predicted to jump. This has the advantage of improving the accuracy of branch prediction. When the saturation counter is working, if the current instruction is predicted to be a jump, the saturation counter value is incremented by 1, and the current saturation counter value moves one step towards ST (00→01→10→11). If the jump continues, it remains at 11. If the current instruction is predicted not to jump, the saturation counter value is decremented by 1, and it moves one step towards SNT (11→10→01→00). If the jump continues, it remains at 00. The advantages of using this 2-bit saturation counter to predict the PC value are its simplicity, low hardware overhead, and ability to effectively improve the efficiency of the instruction pipeline, reducing pipeline stalls caused by branch prediction errors. Furthermore, compared to a 1-bit saturation counter, it is more adaptable and accurate, and can adaptively adjust the prediction result according to the program's execution. The saturation counter (SC) maintains a separate count value for each branch instruction, stored in the Pattern History Table (PHT). Therefore, by querying the value in the PHT memory space pointed to by the corresponding address, the prediction result of whether the current instruction will jump can be obtained.

[0036] The PHT lookup address can be implemented using the PC value output by the program counter. However, since the PC value of each instruction is quite long (e.g., the PC value of the RV32I instruction set is 32 bits long), and the off-chip memory for storing instructions is usually stored byte by byte (8 bits), each instruction requires k = 4 bytes. Therefore, when querying the PHT to obtain the jump prediction result of the corresponding instruction, only the second bit (the 0th and 1st bits are meaningless) and above bits are used as the lookup address. In this embodiment, since the processor's hardware resources are limited, the PHT storage space cannot be increased indefinitely. Therefore, only the PHT with a certain storage space is used to reuse the prediction result of the PC value, and a portion of the PC value is used as the corresponding lookup address. For example, when the PHT storage depth is 1024, only 10 bits of the PC[11:2] value need to be truncated as the PHT lookup address. As long as the PC values ​​of [2] to

[11] are the same, the corresponding saturation count value is used to predict the jump state of the current instruction. However, the accuracy of instruction jump prediction results obtained by such query may be low. Therefore, this embodiment of the invention further combines the global jump history predicted by the Predictive Global History Register (P-GHR) to improve the accuracy of branch prediction.

[0037] Unlike the Pattern History Table (PHT), which uses a saturation counter (SC) to maintain a separate count for each branch instruction, the Predictive Global History Register (P-GHR) predicts the jump behavior of all branch instructions, requiring only a globally shared history of jumps. However, in practical designs, due to the limited hardware resources of the processor, the length of the P-GHR is necessarily finite, making it impossible to store all jump prediction results in a register. Therefore, this embodiment uses a shift register to implement the P-GHR, recording only the predicted jump results of the most recently executed branch instructions, forming a bit vector. For example, a 6-bit shift register is used to record the jump direction ("jump" or "no jump," represented by 0 or 1 respectively) of the most recent 6 instructions. Preferably, as... Figure 2 As shown, in order to improve the prediction accuracy of branch instructions, this embodiment combines the prediction of global jump history information to search for prediction results. In specific implementation, P-GHR is XORed with a portion of the PC value of the current branch instruction (e.g., the local 6-bit PC value: PC[12:7]) to obtain an index value, and then the prediction result of whether to jump is found in PHT according to the index value.

[0038] Preferably, the instruction fetch unit 10 further includes an Architecture Global History Register (A-GHR). The Architecture Global History Register (A-GHR) records the accurate global jump history value after instruction execution. In the event of branch prediction failure, the accurate global jump history value is used to overwrite the predicted global jump history value in the Predicted Global History Register in the next cycle. The global branch history table includes the Architecture Global History Register (A-GHR) and the Predicted Global History Register (P-GHR). The A-GHR is updated during the retirement phase by the retirement unit 70, and the P-GHR is updated during the instruction fetch phase by the instruction fetch unit 10. When a branch prediction failure occurs, the A-GHR is used to overwrite and restore the information in the Predicted Global Branch History Table in the P-GHR. Then, the global jump history (also called the global branch history table) in the P-GHR is XORed with a partial value of the PC, and combined with other partial values ​​of the PC, a jump information index is provided to the Pattern History Table PHT. Based on this jump information index, the Pattern History Table PHT is addressed to obtain the jump direction of whether the current PC has jumped. Since the instruction jump results stored in the P-GHR are also prediction results, prediction errors or failures are possible. However, the success or failure of the prediction can only be determined when the current instruction reaches the execution stage. Therefore, when obtaining all instruction information after the current instruction is executed, it is necessary to update and record the prediction information of the preceding multi-stage pipeline in a timely manner to ensure that the execution of each instruction (including the instruction jump direction) is correct. Specifically, for global jump history prediction, after the instruction execution is completed and retirement is committed, the correct jump results need to be returned to the A-GHR and Branch Target Buffer (BTB) in the instruction fetch stage. The A-GHR records the correct jump results ("jump" or "no jump") of the most recently executed branch instructions; the BTB records the PC value and corresponding jump address of all branch instructions executed up to the current time. Therefore, when branch prediction is successful, it is only necessary to record the corresponding jump information after the branch instruction retires in A-GHR (at this time, the contents of A-GHR and P-GHR are the same) and BTB in a timely manner; when branch prediction fails, A-GHR can be used to overwrite P-GHR in one cycle, so that the instructions executed in the previous cycle can be re-predicted.

[0039] The jump arbitrator (JA) is used to predict the PC value for the next period based on the jump state of the PC value in the current period, including:

[0040] If a jump occurs, it is determined whether the PC value of the current cycle hits any branch instruction in the Branch Target Cache (BTB). If it does, it is further determined whether the hit branch instruction is a function return instruction. If it is a function return instruction, the corresponding function call target address in the Return Address Stack (RAS) is predicted as the jump address of the PC value in the next cycle. If it is not a function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the PC value in the next cycle.

[0041] If no jump occurs, or if a jump occurs but no branch instruction in the Branch Target Cache (BTB) is hit, the jump address for the next cycle's PC value is predicted as PC+k; PC is the PC value of the current cycle, and k is a user-defined constant. Typically, for the RV32I instruction set, since the instruction width is 32 bits, the constant k is set to 4 when each byte in off-chip memory is 8 bits; similarly, for the RV64I instruction set, the instruction width is 64 bits, so the constant k is set to 8.

[0042] BTB and RAS are used to predict the jump address or function return address of branch instructions. In this embodiment, when a branch instruction is executed and a jump occurs, a new jump address is obtained. At this time, the PC and its jump address are synchronously updated in BTB. Therefore, BTB records the PC of the branch instruction that has jumped and its corresponding jump address. However, there is a special case in the jump branch instruction: when the instruction that jumps is a function call (return) instruction, the information on whether the current PC is a function return is also synchronously updated in BTB. Therefore, the PC value of all items in BTB is searched using the PC value of the current cycle that is determined to be a jump. If the PC of any item in BTB is equal to the PC of the current cycle, it is determined that the PC is hit. Then, it is further determined whether the PC is recorded as a function return in BTB. If so, the corresponding address popped from the return address stack RAS is used as the branch prediction result, that is, the predicted function return address; if not, the target address of the hit in BTB is taken as the branch jump address of the current PC. If there is no PC in BTB that is equal to the PC of the current period, then sequential index fetching is still performed, that is, the prediction result of PC is PC+k.

[0043] Therefore, the dynamic branch predictor provided in this embodiment of the invention is a two-stage adaptive branch predictor. The global history register of this invention is used to record this global branch jump information, serving as the first-stage branch history of the branch predictor in this design; the second stage uses PHT, BTB, and RAS to predict the branch jump direction and jump address. In a program, the jump direction of a branch instruction may be related to the result of the previous branch jump, therefore, GHR (including A-GHR and P-GHR) is needed to record this jump information of the preceding and following branch instructions as the basis for branch prediction; while the saturation counter in PHT can further predict the probability of whether the instruction pointed to by the current PC will jump in this cycle. The two-stage adaptive branch predictor provided in this embodiment can make predictions quickly within one cycle, preventing the processor front-end pipeline from becoming too long while also ensuring the accuracy of branch prediction.

[0044] In one feasible approach, the PHT is a 2-bit saturated counter table with a depth of 1024 entries. The lookup address of the PHT is the concatenation of the 6-bit middle PC value and the 6-bit P-GHR output value by XOR operation, and then the concatenation with the lower 4 bits of PC[5:2], i.e.: {{PC[11:6](XOR)P-GHR[5:0]},PC[5:2]}; the BTB is constructed in the form of a 32-entry fully associative cache, which can make predictions quickly within one cycle, preventing the processor front-end pipeline from being too long while also ensuring the accuracy of branch prediction.

[0045] like Figure 3 The flowchart shown is an implementation flowchart of the branch prediction method provided in an embodiment of the present invention. Specifically, the specific steps of branch prediction in the instruction fetching stage are as follows:

[0046] Step S301: Read the program counter 12 of the PC value to be predicted, obtain the output PC value, and take only a portion of the bit width value (6th to 11th bits of PC [11:6]);

[0047] Step S302: Read the global jump history prediction value from the Predictive Global History Register (P-GHR);

[0048] Step S303: Using the partial width value of PC and the global jump history prediction value, generate the read address for finding PHT. That is, XOR PC[11:6] with the 6-bit P-GHR output value and then concatenate it with the lower 4 bits of PC[5:2] to generate a 10-bit query address or index that incorporates branch history jump information: Addr_read={{PC[11:6](XOR)P-GHR[5:0]},PC[5:2]}. Directly using PC or P-GHR to generate the index may lead to conflicts, especially when different branch instructions share the same PC lower bits or have the same history pattern. By XORing a portion of the width of the middle bits of PC (such as bits 6 to 11) with P-GHR, the generated index can effectively combine the information of these two, reducing such conflicts. The PC corresponding to the branch instruction is often relatively fixed in the low bits. For example, the alignment requirement of 4 bytes for each 32-bit PC makes the lowest two bits unchanged. However, directly using the high bits may not fully reflect historical information. Therefore, this embodiment selects the middle bits such as 6 to 11 bits and XORs them with P-GHR to ensure a more uniform index distribution and reduce prediction table conflicts caused by address similarity.

[0049] Step S304: Use the 10-bit query address Addr_read to read the pattern history table (PHT) with a depth of 1024. Based on the query result of the PHT, determine whether the PC value corresponding to the instruction to be executed in the next cycle should jump. If it jumps, proceed to step S305. If it does not jump, proceed to step S306.

[0050] Step S305: Search the BTB (Branch Targeting Library) to check if there is a record information for the PC value predicted as a jump. If no match is found, proceed to step S306. If any PC value in the BTB is equal to the PC of the current cycle, it means that the PC value matches an item in the BTB. However, since the BTB also records the call record of the return function, which has a higher priority, if the current PC matches an item in the BTB, step S307 needs to be executed to determine whether it is a return instruction. Specifically, the BTB includes 32 items, each of which stores the PC of a branch instruction that has previously jumped, the jump address corresponding to that PC, and whether it is a function return. The PC value of the current cycle is compared with the PC of each item in the BTB. If the PC value of one item is equal to the PC value of the current cycle, it is determined that the PC value of the current cycle matches the content of the BTB.

[0051] Step S306: Predict the result of PC as PC+4. Therefore, if either PHT or BTB misses, it is predicted that there is no jump, and the pointer is fetched sequentially, i.e., PC is incremented by k=4 each time.

[0052] Step S307: Determine whether the instruction hit by the PC in BTB is a return instruction; if not, proceed to step S308; if yes, proceed to step S309.

[0053] Step S308: Use the target address recorded in the hit item in BTB as the jump address (prediction result) of the current PC;

[0054] Step S309: Pop the target address of the return address stack RAS, i.e. the function return address, as the prediction result.

[0055] RAS (Recursive Branch Analyzer) is a hardware architecture specifically designed for predicting function calls and returns, aiming to accelerate branch prediction, particularly for function calls and returns. Its architecture is closely related to the "call" and "return" instructions. When the processor encounters a function call instruction (such as `call`), it pushes the return address (the address of the instruction following the called function) onto the RAS. This address represents the location where the program should return after the function execution is complete. Simultaneously, the processor jumps to the called function based on the target address of the function call. When the processor encounters a function return instruction (such as `return`), it checks if a return address is available in the RAS. If so, the RAS pops the address from the top of the stack as the predicted address for the return instruction. This return address is used as the predicted address for the next instruction to be executed (i.e., the program returns to the call point). The main purpose of RAS is to improve the accuracy of function call and return predictions. The RAS architecture ensures that whenever a function returns, the processor can quickly and accurately obtain the return address, avoiding performance penalties caused by incorrect function return predictions.

[0056] In summary, based on the prediction results of the dynamic branch predictor 11, the processor selects the instruction address to fetch in the next cycle. If a jump to the current PC is predicted, the processor looks up the target jump address in the associated BTB record or the return address of the RAS as the target address, and the fetch address for the next cycle is this target address. If a jump to the PC is predicted not to occur, the fetch address is the next sequential address of the current PC (PC+k). Through this mechanism, the processor can start fetching instructions in advance without being completely certain whether a branch jump will occur, thereby reducing pauses in the instruction execution pipeline. If the prediction is incorrect, the processor will discard the instructions on the incorrect path and start again from the correct address. This optimization can significantly improve the efficiency of the pipeline of this invention and improve overall performance.

[0057] In this embodiment, the second-stage pipeline architecture is the instruction buffer stage, which mainly includes an instruction buffer unit 20. Preferably, the instruction buffer unit 20 adopts a sequential, uncompressed, first-in-first-out architecture to buffer the RISC-V instructions sent from the RISC-V processor front end, in order to adapt to the difference in computing speed between the front end and the back end.

[0058] Specifically, such as Figure 1 As shown, the present invention employs a first-in, first-out (FIFO) cache of depth d (preferably d=8 or d=16) in the instruction buffer unit 20. This FIFO queue divides the processor into a front-end and a back-end. The front-end is responsible for generating program calculations and fetching instructions, while the back-end is responsible for processing the fetched instructions, executing them, and committing the results (write-back and retirement). A FIFO setting of depth 8 or 16 is a compromise, providing sufficient instruction capacity to handle the speed differences between the front-end and back-end and the need for out-of-order execution, while avoiding excessive increases in hardware resources and complexity. Using an instruction buffer decouples the front-end and back-end of the processor. Since the front-end and back-end have many states, using a single control logic to control both would result in a large control logic, becoming a critical path in the kernel. By decoupling the front-end and back-end, the control logic of each can be implemented independently, simplifying the control modules and enabling faster frequencies. On the other hand, due to the inconsistent processing capabilities and speeds of the front-end and back-end, the back-end may experience blocking due to various factors (such as excessively long clock cycles required for front-end instruction fetching to access external memory, or the back-end's issue queue becoming full due to multi-cycle instruction execution). Instruction buffering can address this speed inconsistency, allowing the front-end to continue running even when the back-end is blocked, thus improving pipeline throughput. Even if the back-end is blocked, if the instruction buffer is not full, the front-end can still fetch instructions normally. This decoupling simplifies the design of the control modules and improves pipeline throughput.

[0059] Furthermore, unlike existing FIFO structures, this embodiment employs an uncompressed first-in-first-out (FIFO) architecture for the instruction buffer unit 20. Each time an instruction is input, it is not necessary to move all bytes of data in the instruction buffer unit 20. Instead, a free space is first searched within the instruction buffer unit 20, and then the newly entered instruction is written into that free space. When removing an instruction from the queue, the oldest instruction in the queue is pushed to the next stage of the pipeline according to its age, thus achieving the FIFO mechanism. The advantages of using an uncompressed architecture for the instruction buffer unit 20 are fast data access, ensuring timely access to instructions, avoiding delays caused by decompression, and higher data integrity, making it less prone to data corruption or loss.

[0060] As some embodiments, in the third-level pipeline architecture, which is the decoding and register renaming stage, a decoding unit 30 is mainly provided. The decoding unit 30 includes a decoding logic circuit 31, which is used to parse the RISC-V instructions obtained from the instruction buffer unit 20, obtain the control information required for instruction execution, and jointly encode the control information using one-hot codes and binary codes.

[0061] To simplify the representation of the instruction information parsed and translated by the decoding logic circuit 31, so as to facilitate rapid operation of subsequent pipeline architectures, this embodiment of the invention re-encodes the decoded information, mainly using a combination of partial one-hot code and partial binary code for instruction encoding. Since the calculations involved in the RISC-V instruction set are mainly single-cycle arithmetic logic operations (instruction architecture is mainly RV32I), multi-cycle multiplication and division (instruction architecture is RV32M), and memory access instructions (mainly load instructions and store instructions; for accessing external devices, multiple cycles are usually required to complete the instruction execution), the sixth-stage pipeline execution unit 60 is also equipped with three parallel and independently executed functional units, namely the arithmetic logic unit ALU61 (the branch instruction unit BRU is also implemented through the ALU), the multiplication and division calculation unit MDU62, and the memory access unit LSU63.

[0062] Specifically, the decoding stage uses a combination of partial one-hot encoding and partial binary encoding to generate the control information for the subsequent pipeline. In this embodiment, the control information for the subsequent pipeline preferably uses a shared 17-bit information encoding. Two bits are used to classify the operation types of the three instructions using binary encoding: arithmetic logic operations using the ALU61 are encoded as 00, instructions using the MDU62 are encoded as 01, and instructions requiring memory access by the LSU63 are encoded as 10. Then, a 15-bit encoding is used for different instruction operations (various instruction operations under each instruction operation type, such as addition, subtraction, AND, OR, XOR, etc. in the RV32I instruction set; multiplication and division, etc. in the RV32M instruction set; load or store). Each bit of control information is different for different instruction operation types. Therefore, all instruction operations in the RV32IM instruction set can be encoded using a shared 17-bit overall encoding via a multiplexer to achieve the encoded representation of the decoding information. Other standard instruction sets may have different instruction counts, thus requiring adaptive modifications to the joint code length. The main reason for using joint encoding is that while one-hot encoding can increase the frequency of subsequent decoding, using longer one-hot codes increases the demand on subsequent registers, leading to increased power consumption and area. By using a combined architecture that mixes one-hot codes and binary codes, the register requirements of subsequent pipelines are reduced. If one-hot code encoding is used alone without a multiplexed architecture, more than 40 bits of information are needed for subsequent pipeline control for the standard RV32I instruction set. Although binary encoding only requires about 10 bits for encoding, the subsequent stage still needs about 10 bits of decoder to decode the information, increasing the critical path length of the subsequent pipeline. The joint encoding architecture of one-hot codes and binary codes provided in this embodiment of the invention is superior to full one-hot code encoding in terms of area and power consumption, while also exhibiting higher performance than full binary encoding, thus achieving a better balance between the frequency, area, and power consumption of the overall decoding circuit.

[0063] The decoding unit 30 further includes a register renaming unit 32, used to dynamically map the logical registers involved in the RISC-V instruction set to physical registers, generating access control information for the physical register file 50 to avoid read / write conflicts in the register data path. Logical registers refer to the general-purpose logical registers of the RISC-V instruction set, which are registers directly used in the instructions; physical registers are the actual hardware registers existing inside the processor. For the RV32IM instruction set, it has 32 logical registers x0 to x31. When multiple RISC-V instructions enter the pipeline, data conflicts can occur. WAR (WriteAfter Read) conflicts occur when a preceding instruction needs to read a register, and a subsequent instruction needs to write to the same register; the subsequent instruction must wait for the preceding instruction to finish reading before writing, otherwise the preceding instruction will read incorrect data. WAW (WriteAfter Write) conflicts occur when both a preceding and subsequent instruction need to write to the same register; the subsequent instruction must wait for the preceding instruction to finish writing before writing, otherwise the preceding instruction will overwrite the value written by the subsequent instruction, causing a calculation error. Because the RV32IM instruction set has a limited number of logical registers, frequent WAW and WAR conflicts are likely to occur. These conflicts arise because the same register is used. To resolve this, the number of processor registers must be increased, and different register names must be used; this solution is also known as register renaming. Therefore, this embodiment introduces register renaming technology. When renaming registers, only the register name needs to be changed, mapping the logical register number to a different physical register number. However, the renamed physical registers actually exist in the processor's physical register file 50. Specifically, register renaming allows the number of physical registers to exceed the number of logical registers defined by the instruction set. Through dynamic hardware management, the logical register of each operation is mapped to the actual physical register, ensuring that no race conditions occur during execution. This embodiment preferably sets 64 physical registers in the physical register file 50 to support pipelined operations and register renaming. After the same instruction is executed twice consecutively, the physical register occupied during the first execution (the previous destination physical register) is released after the second execution is completed and the instruction retires, thus allowing for the cyclical reuse of the register space in the physical register file 50. This approach not only improves instruction parallelism but also effectively reduces performance loss due to data dependencies with lower hardware resource consumption.

[0064] like Figure 4The diagram shown is a schematic diagram of an implementation structure of a register renaming unit provided in an embodiment of the present invention. The register renaming used in this embodiment is explicit renaming, i.e., a unified register renaming method. Preferably, the register renaming unit 32 includes: a physical register free list 321, a predictive renaming mapping table 322, a physical register ready list 323, and a register allocation logic circuit 324. The input information of the register renaming unit 32 includes branch information, the source logic register rs1 to be renamed, the source logic register rs2 to be renamed, and the destination logic register rd to be renamed. Different instructions may contain different numbers of source logic registers and destination logic registers. The output information of the register renaming unit 32 includes the corresponding renamed physical register 1 and its ready state, physical register 2 and its ready state, the destination physical register, and the previous destination physical register.

[0065] The physical register free list 321 is used to mark the free status of each physical register. When a physical register is free, its corresponding free status is set to "1", and when it is not free, it is set to "0".

[0066] The predictive rename mapping table 322 is used to record the dynamic mapping relationship between logical registers and physical registers. The 32 logical registers of the instruction are dynamically mapped to the 64 physical registers in the physical register file 50. Whenever an instruction enters the rename stage of the pipeline, the register allocation logic circuit 324 allocates an empty physical register for the destination logical register of the instruction; while the source logical register can obtain the corresponding physical register simply by querying the predictive rename mapping table 322.

[0067] Specifically, the register allocation logic circuit 324 is used to detect whether the physical register free list 321 is available when the instruction executes to write the destination logical register; if not, it waits for the subsequent pipeline operation to complete before releasing the physical register; if so, it arbitrates a free physical register in the physical register free list 321 through the first priority arbitration tree 325, allocates it as the destination physical register to the destination logical register to be written, and updates the corresponding mapping relationship between logical registers and physical registers in the predictive renaming mapping table 322.

[0068] The register allocation logic circuit 324 is further configured to, when an instruction executes to read a source logical register, look up the corresponding source physical register number in the predictive renaming mapping table 322, and, based on the source physical register number, look up the corresponding source physical register's ready state in the physical register ready list 323. When an instruction reads data from a physical register, it must use a data dependency detection mechanism to determine the physical register's ready state to ensure that no data dependency issues occur during the read operation. The physical register ready list 323 proposed in this invention records the ready state of all physical registers: when a register is ready, the corresponding bit is set to 1; when not ready, it is 0. Therefore, the physical register ready list 323 is actually a 64-bit binary sequence, and updating this physical register ready list 323 manages the data ready state of physical registers. When a physical register is in a ready state, it means that no instruction needs to write the result back to the register, so its data can be read by subsequent instructions without data conflict. However, if the physical register is in a not-ready state, a data conflict will occur when reading its value. It is necessary to wait for the previous instruction to be executed and write the result back to the register in order to obtain the correct value.

[0069] The register allocation logic circuit 324 is also used to integrate the destination physical register number, source physical register number, and the ready state of the source physical register corresponding to the current instruction into the access control information for output. The state of an unready physical register is passed from the renaming stage to the issue stage. If the physical register required by the instruction is not ready, the instruction cannot be issued or executed until the relevant register is written back and becomes ready again. The update of the physical register ready list 323 occurs during the renaming and instruction execution stages. After the instruction is renamed, it occupies the corresponding physical register, but because it has not yet been executed, the result has not yet been written back, and at this time, the register state is unready. Therefore, its ready state needs to be updated to 0 to reflect its unready state. After the instruction is executed and written back, the occupied physical register is released, and the result in the physical register has been updated. Subsequent instructions will not encounter data conflicts when reading the physical register, so the state of the corresponding item in the physical register ready list 323 is updated to 1, becoming ready.

[0070] Preferably, the unified register renaming technology adopted in this invention expands the 32 logical registers x0 to x31 defined in the RV32IM instruction set into 64 physical registers, forming a unified physical register file 50 for renaming. The physical address indices of the renamed source and destination logical registers correspond one-to-one with the specific physical register numbers in the physical register file 50. The operation results obtained from subsequent pipelines are uniformly written back to the unique physical register file 50. Compared with renaming using a reorder cache (RoB) and renaming by expanding logical registers, this renaming method changes the mapping relationship between logical registers and physical registers by changing the predictive renaming mapping table 322. Data only needs to be written back to the physical register file 50 once, which can greatly reduce data movement and reduce kernel power consumption.

[0071] Preferably, the arbitration of the physical register free list 321 is implemented using a priority arbitration tree architecture with fixed priority, that is, the first priority arbitration tree 325 is a compare-multiplexed arbitrator with fixed low-order bits as priority. A specific structure of the priority arbitration tree provided in this embodiment of the invention is as follows: Figure 5 As shown. Since the physical register file 50 contains 64 physical registers, the physical register free list 321 only needs to use 64-bit binary numbers to mark the free status of the corresponding physical registers. For example, "R=1" is marked when free, and "R=0" is marked when not free. Therefore, a system like this can be designed... Figure 5 The low-order priority arbitration tree shown is indicated by the 64-bit marker information R0~R in the physical register free list 321. n-1 From the least significant bit to the most significant bit in the (n=64) array, find the free physical register that is first set to "1". Therefore, the 64-bit flag information can be used as the selection signals R0~R n-1 (n=64), physical register numbers I0~I n-1 As Figure 5 Arbitrate the input signal of the priority arbitration tree, and find the first bit of R from the least significant bit to the most significant bit from the 64-bit tag information. x =1 corresponds to the physical register I x . Figure 5 The core design principle of the provided priority arbitration tree is: the maximum value comparator MAX uses the tag information R in two physical registers. 左 and R 右 The comparison is performed between the two values ​​to find the largest R value. Since the R value only takes values ​​between 0 and 1, the R value with a value of "1" is selected. If the input flags on both sides are 1, the logic of MAX is low-order priority, meaning the rightmost R value is always selected. 右The value is output; if both are 0, it means that the physical registers represented by the two input flag signals are not idle. In this case, it is preferable to use the higher number for output, that is, take the leftmost R value. 左 The value is output. Therefore, when the R value and the paired physical register number I are input into the priority arbitration tree, the R value obtained from the current comparison can be used as the selection signal of the "two-to-one" selector MUX, which will select the number or index I of the first free physical register from right to left. x Arbitration is completed. The priority arbitration tree routes the arbitration data path (input physical register numbers I0~I1). n-1 ) and control paths (selection signals R0~R n-1 It is coupled into a balanced tree, and while generating an arbitration selection signal, it performs multiplexing on each item (physical register number) in the physical register free list 321, which can quickly arbitrate the free items in the physical register free list 321.

[0072] Specifically, the physical register free list 321 has a 64-bit width, with each bit corresponding to the free state of a physical register. For example, bit 0 of the physical register free list 321 corresponds to the free state of physical register number 0, bit 1 corresponds to the free state of physical register number 1, and so on. When a physical register is free, the corresponding bit is 1; when it is not free, it is 0. Therefore, it can be quickly utilized... Figure 5 The priority arbitration tree shown selects the first 1 value from the least significant bit to the most significant bit in the physical register free list 321, thus selecting the corresponding physical register as the free physical register and assigning it to the destination physical register for the current instruction's write operation. The physical register free list 321 is updated when an instruction enters the renaming phase and when an instruction commits for retirement. After an instruction allocates a free physical register during the renaming phase, the number of free entries in the physical register free list 321 decreases. When an instruction retires and subsequent instructions no longer use the physical register, its free state is restored, thus increasing the number of free entries in the free list. In this embodiment, the mechanism for determining whether a physical register can be vacated is as follows: The previous destination physical register is saved. When an instruction and a subsequent instruction both write to the same destination logical register, and the subsequent instruction commits for retirement, the physical register corresponding to the destination logical register of the preceding instruction will no longer be used. Therefore, it is necessary to record the previous destination physical register for each instruction so that the corresponding entry in the physical register free list 321 can be released during retirement.

[0073] Furthermore, the register renaming unit 32 is also provided with: a physical register free list checkpoint 326, and an architecture renaming mapping table 327. In this embodiment, in addition to using the physical register free list 321 to allocate free physical registers, the renaming logic also tracks the mapping relationship between each logical register and physical register through the renaming mapping table (including the architecture renaming mapping table 327 and the predictive renaming mapping table 322). After the instruction enters the renaming stage, the physical register numbers corresponding to all the logical registers of the instruction after renaming can be obtained by querying the predictive renaming mapping table 322. The physical registers obtained from the lookup tables of the two source logical registers of the instruction will be used in the subsequent physical register file read stage, while the physical register obtained from the lookup table of the destination logical register will serve as the previous destination physical register.

[0074] The physical register free list checkpoint 326 is used to mark the current RISC-V instruction as a branch instruction, generate a branch number, and back up the physical register free list 321 when the current RISC-V instruction is a branch instruction. In this embodiment of the invention, only the physical register free list 321 corresponding to the branch instruction needs to be backed up. Other non-branch instructions do not have branch prediction error problems and are fetched sequentially, therefore, backing up the physical register free list 321 is not required.

[0075] The register renaming unit 32 is further configured to, in the next cycle, restore the contents of the physical register free list 321 using the physical register free list checkpoint 326 corresponding to the branch number, and restore the contents of the prediction renaming mapping table 322 using the architecture renaming mapping table 327, when branch prediction fails. In this embodiment, fast branch prediction recovery is performed during the register renaming phase using the physical register free list checkpoint 326 and the architecture renaming mapping table 327. The renaming mapping table includes the prediction renaming mapping table 322 and the architecture renaming mapping table 327. The prediction renaming mapping table 322 records the predicted renaming mapping relationship, and the architecture renaming mapping table 327 records the correct architecture renaming mapping relationship. When branch prediction fails, the architecture renaming mapping table 327 overwrites the renaming mapping relationship of the prediction renaming mapping table 322 in one cycle based on the correct renaming mapping relationship. When branch prediction fails, the contents of the physical register free list 321 are overwritten in one cycle using the backup information of the physical register free list with the corresponding number in the physical register free list checkpoint 326.

[0076] Furthermore, the register allocation logic circuit 324 also includes register wake-up logic. This register wake-up logic is used to detect whether there is an early wake-up signal returned from the transmitting unit 40 when the source physical register to be read by the current instruction is not ready; if so, it compares the register number carried in the early wake-up signal with the source physical register number to be read by the current instruction; if they are the same, it updates the source physical register to be read by the current instruction to a ready state; if they are different or there is no early wake-up signal, it checks whether the write address of the execution unit 60 to the physical register file 50 is consistent with the source physical register number to be read by the current instruction; if they are consistent, it updates the source physical register to be read by the current instruction to a ready state; if they are inconsistent, it waits for the source physical register to complete execution.

[0077] The physical register file 50 is used to perform write operations on an idle destination physical register or read operations on a ready source physical register according to the access control information.

[0078] As some embodiments, for branch instructions, the branch instruction flag is marked as 1 by the physical register free list checkpoint 326, a branch instruction number is generated and provided to the physical register free list 321, and the physical register free list is backed up. If it is not a branch instruction, the input instruction is directly provided to the physical register free list 321. The physical register free list 321 selects the register according to the input instruction or branch instruction number through the first priority arbitration tree 325 to generate the destination physical register number. For renaming the source register, the source logic register obtains the source register renaming mapping number by looking up the predictive renaming mapping table 322, and further determines whether the two source physical registers are ready by looking up the physical register ready list 323. If they are ready, all the decoded control information and the information of the renamed source physical register and destination physical register are stored in the ready register and transmitted to the next pipeline emitter unit 40. If they are not ready, but the physical register stack address written back in the current cycle happens to be consistent with the physical index of the two renamed source registers, the corresponding not-ready physical register is woken up.

[0079] Figure 6 This describes the steps of a specific implementation method for register renaming. Its core process mainly includes:

[0080] 1) Check if the physical register free list 321 and physical register free list checkpoint 326 are available. If they are full, wait for the subsequent pipeline to release resources.

[0081] 2) Instruction decoding: Determine if the instruction is a branch instruction. If it is a branch instruction, mark the current instruction as a branch, set the branch instruction flag to 1, and use physical register free list checkpoint 326 to generate a branch number and back up physical register free list 321 for quick recovery in case of subsequent branch prediction failure.

[0082] 3) The physical register free list 321 generates the destination physical register number. For the source register, the source logical register obtains the rename mapping number through the address prediction rename mapping table 322, which serves as the physical address index of the renamed source physical register. The number generated in the table is then looked up in the physical register ready list 323 to check whether one or two source physical registers (the number of source registers depends on the current instruction content) are ready. If the address that the execution unit 60 needs to write back to the physical register file 50 in the current cycle happens to match the physical index of the two renamed source physical registers, then the corresponding ready source physical register is woken up. In addition, if the physical register number returned by the issuer unit 40 is the same as the source physical register number to be read, the corresponding physical register can also be woken up.

[0083] 4) Integrate all the decoded control information, renamed source physical register information, and destination physical register information into a single output signal and send it to the next stage of the pipeline.

[0084] Furthermore, this invention designs a fast branch prediction recovery circuit architecture for handling branch prediction failures. In dynamically scheduled processors, when a branch prediction failure occurs, due to out-of-order instruction execution, younger instructions than the jump instruction that caused the branch prediction failure may have already affected the processor's state. In this case, processor state recovery is required to restore the processor to the position where the branch instruction prediction error occurred. Various components in the register renaming stage, such as the prediction renaming mapping table 322 which records the processor's renaming mapping relationships, and the physical register free list 321 which records free registers, are crucial components that require state recovery after a branch prediction failure. Failure to recover will lead to processor errors. On the other hand, the recovery time of the renaming stage after a branch prediction failure also affects processor performance. A long recovery cycle can cause subsequent instructions to be blocked, inserting more "bubbles" into the pipeline and affecting pipeline throughput. Therefore, fast branch prediction recovery significantly improves processor performance.

[0085] like Figure 4As shown, the branch prediction failure recovery circuit architecture adopted in this invention is configured with two renaming mapping tables. The predictive renaming mapping table 322 is used to record the speculative renaming mapping relationship and is in a speculative state; the architecture renaming mapping table 327 is used to record the accurate architecture renaming mapping relationship and is in a determined state, which is updated after the instruction is executed and submitted for retirement. When branch prediction fails, this invention quickly recovers by overwriting the speculative predictive renaming mapping table 322 with the accurate architecture renaming mapping table 327. During recovery, the registers in the architecture renaming mapping table 327 are used as inputs to the registers in the predictive renaming table, and the register numbers correspond one-to-one. During recovery, only one clock cycle is needed to restore the erroneous predictive renaming mapping table 322 to the accurate mapping table, quickly restoring the mapping relationship of the renaming mapping table. The physical register free list 321 used to allocate renaming numbers is designed as a backup, such as... Figure 4 As shown in the physical register free list checkpoint 326, the number of backup circuits for physical register free list checkpoint 326 set in this invention is 4. When a branch instruction enters the renaming stage in the pipeline, Figure 4 One of the four backup circuits at the checkpoint performs a quick backup, recording the free list state before the current branch instruction. When branch prediction fails, the backup free list is used to overwrite the previous one. The recovery cost for a failed branch prediction is only one clock cycle, eliminating the need for multiple data reads and writes to restore the kernel state. Both renaming the mapping table and restoring the free list require only one clock cycle, achieving rapid processor state recovery, improving kernel performance while reducing power consumption.

[0086] Furthermore, during the launch phase, launches are conducted using different launch queue architectures. Specifically, such as... Figure 1 and Figure 7 As shown, the issuing unit 40 includes three independent parallel issuing queues: a logic operation issuing queue, a multiplication and division issuing queue, and a memory access issuing queue; each issuing queue is an uncompressed and non-data capture queue. The instructions in each queue will be issued to the arithmetic logic unit ALU61, the multiplication and division calculation unit MDU62, and the memory access unit LSU63 in the execution unit 60 for calculation and processing, respectively.

[0087] The launch unit 40 also includes distribution logic 41, which includes launch ready logic 411, allocation logic 412, and age arbitration tree 413. In specific implementation, a distribution logic 41 can be set up independently for the three launch queues, with independent launch ready logic 411, allocation logic 412, and age arbitration tree 413; or a single distribution logic 41 can be shared. Figure 7The implementation scheme shown sets up a distribution logic 41 for each queue, and uses independent launch ready logic 411, allocation logic 412 and age arbitration tree 413 to arbitrate and distribute each queue separately.

[0088] The issue-ready logic 411 is used to determine whether the current RISC-V instruction obtained from the decoding unit 30 is issue-ready. When all source physical registers involved in the current RISC-V instruction are awakened, the current RISC-V instruction is determined to be issue-ready, and the issue-ready RISC-V instruction is distributed to one of the issue queues according to its instruction type. If the current instruction is an arithmetic logic operation instruction or a branch jump instruction, it is sent to the logic operation issue queue; if it is a multiplication, division, or modulo instruction in the RV32M or RV64M instruction architecture, it is sent to the multiplication and division issue queue; if it is a memory access instruction such as load or store, it is sent to the memory access issue queue.

[0089] The allocation logic 412 finds an empty entry in the corresponding launch queue through the second priority arbitration tree and writes the launch-ready instruction into it. In specific implementations, the second priority arbitration tree can adopt a method similar to... Figure 5 The first priority arbitration tree shown is implemented in the same way, but its architecture should be adjusted according to the different bit width n of the input signal, so that the number of comparison stages in the priority arbitration tree can be adjusted accordingly.

[0090] The age arbitration tree 413 is used to sort the instructions in each launch queue by age and arbitrate the oldest instruction in each of the three launch queues for parallel launch.

[0091] Specifically, the transmit-ready logic 411 of the logic operation transmit queue in this embodiment also includes early wake-up logic, which is used to release the source physical register involved in the instruction after it is transmitted, return the associated source physical register number, and compare it with the source physical register involved in the instruction of the next cycle. When the returned source physical register is the same as the source physical register involved in the instruction of the next cycle, the source physical register corresponding to the instruction of the next cycle can be woken up in advance; if the instruction of the next cycle includes two source physical registers, they need to be woken up one by one, and the transmit-ready signal is issued only when all physical registers involved in the instruction of the next cycle are woken up. The specific implementation circuit structure can adopt... Figure 7The circuit implementation scheme is shown in the upper left corner. It should be noted that this embodiment takes into account the following characteristics: only instructions in the arithmetic logic operation (ALU) issue queue can be executed within one clock cycle in the ALU61. The multiplication and division calculation unit MDU62 and the memory access unit LSU63 require multiple cycles to execute instructions. Therefore, this invention can issue an early wake-up signal after the instructions in the ALU issue queue are issued, waking up the source physical registers involved in the instructions of the next cycle in advance; otherwise, the source physical registers can only wait until the current cycle's instructions are completed and the register information is written back (i.e.,...). Figure 7 Only when tags 1 and 2 (located in the upper left corner) are further compared with the relevant source physical registers of the next cycle's instruction to determine whether to wake up the physical registers. Since the latter requires waiting for multiple clock cycles, it results in lower processor execution efficiency. It should be noted that the number of source and destination logic registers in basic RISC-V instructions is standardized by the RISC-V instruction set; therefore, the number of source and destination physical registers involved in different RISC-V instructions may vary.

[0092] In practice, during the launch phase, such as Figure 7 As shown, the issue queue in this embodiment differs from existing single, compressed, and data-driven issue queues. This embodiment designs a distributed, uncompressed, and non-data-capture issue queue architecture. Specifically, the distributed issue queue divides the traditional single issue queue into three queues based on instruction type characteristics: a logic operation issue queue, a multiplication and division issue queue, and a memory access issue queue. This distributed design effectively avoids the complex design of multiple read / write ports in traditional long issue queues, significantly improves power consumption, and can distinguish between the issue logic of single-cycle instructions and multi-cycle instructions, supporting early wake-up of the source physical register for the next cycle instruction.

[0093] Furthermore, each launch queue in this embodiment employs an uncompressed launch architecture design. This design reduces unnecessary data changes within the queue, with each data item undergoing only one read / write operation during enqueueing and one during dequeueing. Traditional compressed queues operate similarly to a standard FIFO, where subsequent commands entering the queue are moved forward after an instruction is launched, forming a "latest-oldest" order. This means that multiple instruction items within the queue undergo read / write operations during each launch. In contrast, with an uncompressed launch queue, the positions of other instructions remain unchanged when an instruction leaves the current cycle; unlaunched instructions retain their original positions. When an instruction from the next cycle enters the queue, a priority arbitration tree is used to find an available position for writing. Therefore, the launch enqueue selection circuit of the uncompressed queue can shorten the timing path of the arbitration logic by arbitrarily selecting data. It should be noted that, unlike the sequential FIFO instruction queue of instruction buffer unit 20, all three launch queues are out-of-order FIFO queues. This ensures that instructions in the launch queue can be executed out of order according to their readiness status and required execution cycle, improving instruction execution efficiency.

[0094] Furthermore, each transmit queue in this embodiment is a non-data capture queue architecture. The non-data capture queue architecture does not need to record the internal storage data of the required physical registers, but only needs to record their corresponding physical register numbers or tags. Since the temporarily stored data typically has a large bit width, while the register tag bit width is very small, the data bit width for data calculation in the transmit pipeline and subsequent pipeline stages is also reduced, thereby reducing the demand on processor storage space and reducing area and power consumption. Figure 7 As shown, this invention employs an "older-first" transmit arbitration allocation mechanism. The oldest instruction is selected from the transmit-ready list via the age arbitration tree 413 for transmission, prioritizing the resolution of subsequent data dependency issues. In the wake-up design of the transmit queue, when the transmit arbitration for the logic operation transmit queue is selected, the physical registers of items in the relevant queue are activated; however, early wake-up is not supported for the multiplication / division transmit queue and the memory access transmit queue. By simplifying the wake-up circuit architecture, the fan-out of the wake-up logic is lower, enabling the overall transmit unit 40 circuit architecture to achieve higher frequencies and lower power consumption.

[0095] As one embodiment, the execution unit 60 is used to receive the decoding information of one or more RISC-V instructions transmitted by the transmission unit 40 using an input gating circuit, assign them to the corresponding functional units for calculation, and submit the calculation results to the register data path or memory access path.

[0096] like Figure 1As shown, the functional unit includes an independent arithmetic logic unit (ALU) 61, a multiplication and division unit (MDU) 62, and a memory access unit (LSU) 63. The ALU 61 is used to process single-cycle arithmetic operation instructions and branch jump instructions. The MDU 62 is used to process instructions from the M-type extended instruction set. The LSU 63 is used to process load instructions and store instructions. It should be noted that since logical operations and branch jump operations only involve simple arithmetic logic operations, the ALU 61 can also directly implement the function of the branch jump unit (BRU) required for branch jumps.

[0097] In practical implementation, the execution unit 60 adopts an input-gated circuit architecture, which can isolate data and fix the operand to zero when the input signal is disabled. Furthermore, although this invention employs a low-power dynamic scheduling scheme, the overall core power consumption is still relatively high. To further optimize core power consumption, this invention uses various register-transfer-level (RTL) low-power design methods to comprehensively optimize core power consumption. Specifically, the entire RISC-V processor core uses gated clock technology, and power consumption at each stage of the pipeline is optimized, including input-gated design for functional units during the execution stage. The clock signal's flip-flop frequency in the chip is very high, which is the main cause of most dynamic power consumption. By using gated clock technology, this invention ensures that the register clock at each stage is only turned on when enabled, significantly reducing the power consumption of registers at each stage of the pipeline. This design is particularly significant in optimizing overall core power consumption, greatly reducing unnecessary power waste.

[0098] Specifically, for the execution phase, this invention employs an input gating design for the functional units (such as the arithmetic logic unit ALU61 and the multiplication and division calculation unit MDU62) in the execution unit 60. When the input operand is in an disabled state, it is fixed to a constant value, thereby isolating the operand and reducing the number of toggles in subsequent related combinational logic gate circuits. This significantly reduces power consumption during the execution phase and further improves the processor's energy efficiency.

[0099] Furthermore, this invention optimizes the problem of unnecessary switching caused by glitch in combinational logic. Glitches are transient unstable states caused by delay differences in combinational logic circuits; these unnecessary signal switchings lead to additional power consumption. To address this, this invention performs a balanced design of the cascaded circuits in the overall architecture. By improving the multi-stage cascaded two-to-one selector into a tree structure, not only is the critical path of the combinational logic shortened, but the glitch problem caused by delay is also effectively avoided, thereby preventing further increases in power consumption.

[0100] Furthermore, the execution unit 60 reuses a large number of circuits with the same function to reduce the area of ​​the logic circuit. For example, addition and subtraction operations reuse the same adder, and comparison and XOR operations reuse the same XOR circuit. By using different configurations, a single logic circuit can implement multiple logic functions, thereby eliminating the need to set up separate circuits for different logic functions and saving resource consumption.

[0101] Furthermore, such as Figure 8 As shown, the memory access path includes an uncompressed load queue and a first-in-first-out storage queue; the storage instruction is used to write data to an external device through the memory access path; the load instruction is used to read data from an external device into the physical register file through the memory access path.

[0102] The memory access unit LSU63 is used to sequentially execute store instructions in the storage queue, and to execute load instructions in the load queue whose age is greater than that of the store instructions to be retired out of order.

[0103] Preferably, the memory access path further includes a first-level tightly coupled data cache unit 64. The first-level tightly coupled data cache unit 64 is used to cache the data to be read by the load instruction in the load queue or the data to be written by the storage instruction in the storage queue.

[0104] In this embodiment of the invention, the memory access path adopts a partially out-of-order memory access circuit design. That is, the memory queue strictly performs memory access in sequence, and when the retirement enable signal of the retirement unit 70 is received, the instructions in the memory queue are retired in a first-in-first-out order. Since the load instruction reads data from the peripheral device without affecting the peripheral device data, multiple load instructions can be executed out of order and in parallel. Therefore, the load queue adopts out-of-order memory access. Specifically, for the load instruction between two store instructions, one or more load instructions are allowed to perform memory access operations out of order. The specific implementation method is to broadcast the age of the oldest store instruction to be retired in the memory queue to the load queue. When the age in the load queue item is greater than the age broadcast from the memory queue, it indicates that the data to be written to the peripheral device does not conflict with the older load instruction, and the item in the load queue can be loaded and accessed. This invention manages all memory access instructions through load and store queues. All memory access operations communicating with external systems are not halted by cache hits but continue to be written to the load-store queue, awaiting subsequent resource release, thus forming a non-blocking, partially out-of-order memory access mechanism. This load-store queue-based memory access design has significant advantages. First, it achieves higher instruction parallelism with a smaller area overhead, thereby significantly improving the overall performance of the kernel. Second, the non-blocking design avoids memory access bottlenecks caused by insufficient cache hits, ensuring smooth instruction execution and further enhancing processor efficiency. Furthermore, due to the presence of a tightly coupled data cache unit 64, multiple adjacent data entries can be read from the peripheral device into the tightly coupled data cache unit 64 at once during each write or read operation, or multiple adjacent data entries to be written to the peripheral device can be stored in the tightly coupled data cache unit 64. When executing the store or load instruction to write or read from a peripheral device, the system first checks if there is any matched data in the first-level tightly coupled data cache unit 64. If so, the load instruction can quickly write the data back to the physical register file 50 and the reorder cache 71; the store instruction can continuously and directly write the data in the cache to the peripheral device.

[0105] In some embodiments, the retirement unit 70 is equipped with a first-in-first-out (FIFO) reordering cache 71, branch prediction failure recovery logic, and interruption exception detection logic. Branch prediction failure recovery and interruption exception detection functions are implemented during the retirement phase. Specifically, a circular FIFO queue is used during the retirement phase to detect branch prediction failures and interruption exceptions at the FIFO read address.

[0106] The retirement unit 70 is used to retire instructions entering the reordering cache 71 sequentially, return the accurate global jump history value of the retired instructions to the instruction fetch unit 10, and return the physical register numbers and register mapping relationships released by the retired instructions to the decoding unit 30. Specifically, it returns the accurate global jump history value to the architecture global history register (A-GHR) in the instruction fetch unit 10, returns the corresponding instruction jump information and its corresponding jump address to the BTB for recording, and returns the physical register numbers and register mapping relationships to the architecture renaming mapping table 327 of the decoding unit 30.

[0107] The retirement unit 70 is also used to perform branch prediction failure detection and interrupt exception detection at the dequeue pointer of the reordering cache 71 using the branch prediction failure recovery logic and interrupt exception detection logic, and to flush the pipeline architecture of each stage of the RISC-V processor when a branch prediction failure or interrupt exception occurs, and to perform computation recovery on the RISC-V processor using the accurate value of the global jump history and the correct register mapping relationship.

[0108] Specifically, the reordering cache 71 in the retirement phase uses a circular queue and a first-in, first-out (FIFO) design. Furthermore, it employs a design that performs branch prediction failure recovery and interrupt exception recovery at the retirement point. This recovery mechanism allows for unified processor state recovery upon retirement, requiring only branch prediction failure and interrupt exception detection at the dequeue pointer (FIFO read address), eliminating the need for additional exception detection logic, thus simplifying the recovery logic and reducing circuit power consumption. On the other hand, since previous stages, such as the register renaming stage, have included backup recovery circuitry for rapid kernel recovery, the recovery cost is only one cycle. This combination of a simple detection mechanism and fast recovery circuitry simplifies the logic design for branch prediction failure recovery, reducing the overall power consumption of the kernel architecture.

[0109] In summary, to achieve a better balance between processor performance and power consumption, this invention optimizes the processor core by modifying the core architecture pipeline and employing different configuration strategies at each pipeline stage. The design of each pipeline stage not only focuses on performance improvement but also emphasizes low power consumption. Balanced design is used in many technical aspects, simplifying logic and reducing data changes in the data path while ensuring functionality, thus achieving a more ideal balance between overall processor performance and power consumption.

[0110] The entire processor core microarchitecture employs dynamic scheduling technology to achieve out-of-order instruction execution, while fully considering low-power design requirements. Compared to traditional sequential pipelines, dynamic scheduling adds a significant amount of circuitry to handle data conflicts in the processor pipeline, preventing pipeline stalls and bubble insertions caused by data conflicts, thereby ensuring improved instruction parallelism. However, while dynamic scheduling can improve core performance, the additional circuitry it introduces increases chip area and power consumption. Therefore, in dynamic scheduling, the selection of renaming schemes, issue schemes, and branch prediction and recovery schemes significantly impacts the overall performance, power consumption, and area of ​​the core microarchitecture. Therefore, this invention, after careful consideration, selects an implementation scheme that achieves a better balance between performance and power consumption, and optimizes some circuitry, particularly excelling in power efficiency.

[0111] The optimized configurations employed in this invention, such as unified register renaming, non-compressed, non-data-captured, distributed issue queues, and unified branch prediction and interrupt exception recovery mechanisms at retirement points, simplify the implementation of dynamic scheduling. This configuration not only ensures out-of-order execution of instructions but also significantly reduces the frequent data flips required for dynamic scheduling in the pipeline, thereby greatly reducing the power consumption of the processor core.

[0112] In summary, this invention utilizes various techniques, including clock gating, input gating, and glitches optimization, to successfully reduce overall core power consumption while maintaining efficient processor execution, thus achieving a better balance between processor performance and energy efficiency. These optimizations play a crucial role in core power management, enabling the processor to maintain low power consumption while operating efficiently.

[0113] Based on the same inventive concept as the above embodiments, this embodiment also provides an embodiment of an instruction processing method based on the RISC-V instruction set, which processes input RISC-V instructions based on the seven-stage pipeline architecture of the RISC-V processor described in any of the above claims, including:

[0114] Combination Figure 1 As shown, specifically, this embodiment describes a low-power single-issue out-of-order execution RISC-V processor, which includes a seven-stage pipeline architecture, namely: instruction fetch unit 10, instruction buffer unit 20, decoding unit 30, single-instruction issue unit 40, physical register file 50, parallel out-of-order computation execution unit 60, and retirement unit 70.

[0115] Based on the seven-stage pipelined architecture of the aforementioned processor and using the same logical concept, this embodiment of the invention provides an instruction processing method for the RISC-V instruction set. This method processes input RISC-V instructions for implementation based on the seven-stage pipelined architecture of the RISC-V processor described above. It should be noted that the specific structure of the seven-stage pipelined architecture of the RISC-V processor in this embodiment and the specific instruction processing method for the input RISC-V instructions have been described and demonstrated in the corresponding embodiments of the RISC-V processor. Those skilled in the art can implement the instruction processing method for the RISC-V instruction set based on the structure of the seven-stage pipelined architecture and the instruction processing method described above; further details are omitted here.

[0116] The beneficial effects achievable by this invention are as follows: This invention proposes a low-power embedded processor core microarchitecture based on dynamic scheduling, which supports out-of-order instruction execution and exhibits strong instruction parallelism. By employing a low-power dynamic scheduling design and a series of register-transfer level low-power technologies, the low-power characteristics of the core microarchitecture are ensured, achieving a good balance between processor performance and power consumption.

[0117] This invention takes the RV32IM instruction architecture as an example. Its core microarchitecture was prototyped on an FPGA, and the chip's frequency, power consumption, and area were evaluated based on a 40nm process.

[0118] On the ZYNQ-7020 core board's FPGA chip platform (model XC7Z020CLG400-2), the processor core's maximum operating frequency is 95MHz. At this frequency, such as Figure 9 As shown, the processor achieved a Coremark score of 3.6 Coremark / MHz in the Coremark benchmark test, outperforming most sequentially executing processor cores.

[0119] Using a 40nm CMOS integrated circuit process, and after comprehensive optimization, the processor core achieves a maximum operating frequency of 588MHz, a dynamic power consumption of only 14.36μW / MHz, and an area of ​​0.063mm². 2 Detailed experimental results are shown in Table 1. Compared with most sequential processor cores using the same process technology, this invention has significant advantages in frequency and power consumption, although the area is slightly larger than that of sequentially executing cores due to the increased logic circuitry caused by the dynamic scheduling design. Experimental results show that the low-power embedded processor core microarchitecture designed in this invention exhibits excellent performance and power consumption, making it particularly suitable for applications with high computational demands and power sensitivity.

[0120] Table 1

[0121]

[0122] Specifically, the first column of Table 1 shows the ASIC implementation results of the core microarchitecture of this invention using a 40nm process. The ASIC implemented using this invention in a 40nm process has significant performance advantages, with a maximum operating frequency of 588.23MHz. At this frequency, the chip area is 0.063mm². 2 Its dynamic power consumption is only 14.36μW / MHz. Furthermore, it achieved a CoreMark benchmark score of 3.6CoreMark / MHz, demonstrating excellent computational efficiency. Figure 9 The performance of the processor core microarchitecture of this invention was compared with that of other embedded processors in the CoreMark benchmark. The results show that the benchmark score of this invention is significantly better than most embedded processors, which proves the superior performance of the processor provided by this invention on embedded platforms and its ability to meet the computing power requirements of such platforms.

[0123] Table 1 also presents a comprehensive comparison of the present invention with several existing processors at the 40nm process node in terms of performance, frequency, area, and power consumption. It can be seen that the highest frequency of the present invention exceeds that of other processor cores, thanks to its optimized critical path design. Due to the use of dynamic scheduling out-of-order instruction execution technology, the core of the present invention requires more logic circuitry to complete complex control functions, resulting in a slightly larger area than some sequentially executing processors. However, through the combination of a low-power out-of-order scheduling scheme and a series of optimized designs, even when operating at a maximum frequency close to 600MHz, the core's dynamic power consumption remains at 14.36μW / MHz, which is superior to most sequential processor cores.

[0124] Experimental results further demonstrate that the processor core of this invention has significant advantages in frequency and power consumption, thanks to the low-power dynamic scheduling scheme, optimized circuit configuration, and a series of low-power design methods for the microarchitecture. The processor core of this invention combines high frequency, high performance, and low power consumption, making it particularly outstanding in power-sensitive applications with high processor performance requirements.

[0125] Overall, this invention presents a low-power embedded processor core microarchitecture based on the RISC-V instruction set and employing dynamic scheduling technology, achieving a good balance between performance and power consumption. It is particularly suitable for scenarios with high requirements for both power consumption and performance.

[0126] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-power single-issue out-of-order execution (RISC-V) processor, comprising: The seven-stage pipeline architecture comprises, in sequence, a fetch unit, an instruction buffer unit, a decoding unit, a single-instruction emission unit, a physical register file, a parallel out-of-order calculation execution unit, and a retirement unit; The fetch unit is a front end of a RISC-V processor; and the five-stage pipeline architecture of the decoding unit, the emission unit, the physical register file, the execution unit, and the retirement unit is a back end of the RISC-V processor; The fetch unit is configured to read a corresponding RISC-V instruction in an off-chip memory according to a PC value of a current cycle and deliver the corresponding RISC-V instruction to the instruction buffer unit; and the fetch unit is further configured to predict a PC value of a next cycle by using a dynamic branch predictor. The instruction buffer unit is configured to sequentially receive RISC-V instructions from the fetch unit, form an instruction buffer queue, and isolate front-end calculation from back-end calculation of the RISC-V processor. The five-stage pipeline architecture of the RISC-V processor back end is configured to sequentially perform decoding, single-instruction emission, read-write operation on the physical register file, out-of-order execution, and retirement operation on RISC-V instructions, so as to realize register data path and memory access path. The dynamic branch predictor in the fetch unit comprises a prediction global history register, a query circuit, a pattern history table, a saturation counter, a branch target buffer, a return address stack, and a jump arbiter. Each address space in the pattern history table stores a saturation count value indicating whether to jump; the branch target buffer records a PC value of a branch instruction that has jumped and a jump address; and the return address stack stores a function call target address corresponding to a function return instruction. The query circuit is configured to perform logical operation on a PC value of a current cycle and a global jump history prediction value output by the prediction global history register to obtain an index address, and query the pattern history table according to the index address to determine whether the PC value of the current cycle jumps. The saturation counter is configured to update a corresponding saturation count value in the pattern history table according to a jump state of the PC value of the current cycle. The jump arbiter is configured to predict a PC value of a next cycle according to a jump state of the PC value of the current cycle. The fetch unit further comprises an architecture global history register. The architecture global history register records a global jump history accurate value after instruction execution, and is configured to use the global jump history accurate value to cover a global jump history prediction value in the prediction global history register in a next cycle when branch prediction fails. The decoding unit comprises a register renaming unit configured to dynamically map a logical register involved in a RISC-V instruction set to a physical register, generate access control information of the physical register file, and avoid read-write conflict of the register data path. The register renaming unit is provided with a physical register free list, a predicted renaming mapping table, a physical register free list checkpoint, and an architecture renaming mapping table; The physical register free list is used to mark the free state of each physical register; The predicted renaming mapping table is used to record the dynamic mapping relationship between a logical register and a physical register; The physical register free list checkpoint is used to mark the current RISC-V instruction as a branch instruction, generate a branch number, and backup the physical register free list when the current RISC-V instruction is a branch instruction; The register renaming unit is further used to restore the content of the physical register free list using the physical register free list checkpoint corresponding to the branch number in the next cycle when the branch prediction fails, and restore the content of the predicted renaming mapping table using the architecture renaming mapping table.

2. The low power single-issue out-of-order (OOO) RISC-V (RISC Five) processor of claim 1, wherein, The jump arbiter is used to predict the PC value of the next cycle according to the jump state of the PC value of the current cycle, including: If a jump occurs, it is determined whether the PC value of the current cycle hits any branch instruction in the branch target buffer, if it does, it is further determined whether the hit branch instruction is a function return instruction; if it is a function return instruction, the function call target address corresponding in the return address stack is predicted as the jump address of the PC value of the next cycle; if it is not a function return instruction, the jump address corresponding to the hit branch instruction is predicted as the jump address of the PC value of the next cycle; If no jump occurs, or a jump occurs but the PC value of the current cycle does not hit any branch instruction in the branch target buffer, the jump address of the PC value of the next cycle is predicted as PC+k; k is a user-defined constant.

3. The low power single-issue out-of-order (OOO) RISC-V (RISC Five) processor of claim 1, wherein, The instruction fetching unit further includes a first tightly coupled instruction cache unit; The first tightly coupled instruction cache unit is used to access the RISC-V instructions in the off-chip memory through the cache bus and the AXI interface according to the PC value of the current cycle, read out and cache a plurality of RISC-V instructions corresponding to the PC value of the current cycle and the PC value of the adjacent cycle, and deliver the RISC-V instructions corresponding to the PC value of the current cycle in the first tightly coupled instruction cache unit to the instruction buffer unit. The first tightly coupled instruction cache unit is further used to search whether the corresponding RISC-V instructions are cached in the first tightly coupled instruction cache unit according to the PC value of the current cycle; if yes, the RISC-V instructions corresponding to the PC value of the current cycle in the first tightly coupled instruction cache unit are delivered to the instruction buffer unit; otherwise, the RISC-V instructions corresponding to the PC value of the current cycle are delivered to the instruction buffer unit through the cache bus and the AXI interface, and a plurality of RISC-V instructions corresponding to the PC value of the adjacent cycle are read out and cached.

4. The low-power single-shot out-of-order execution RISC-V processor of claim 1, wherein The instruction buffer unit adopts a non-compressed first-in-first-out architecture, and is used to buffer the RISC-V instructions sent by the front end of the RISC-V processor to adapt to the difference in calculation speed between the front end and the back end.

5. The low-power single-issue out-of-order (OOO) RISC-V processor of claim 1, wherein the decode unit comprises a decode logic circuit configured to parse the RISC-V instruction fetched from the instruction buffer unit to obtain control information required for execution of the RISC-V instruction, and jointly encode the control information using one-hot encoding and binary encoding. The register renaming unit is provided with a physical register ready list and a register allocation logic circuit.

6. The low-power single-issue out-of-order (OOO) RISC-V (RISC-five) processor of claim 1, wherein, The register allocation logic circuit is configured to, when a RISC-V instruction executes a write-destination logical register, detect whether the physical register free list is available; if not, wait for a physical register to be released after a subsequent pipeline operation is completed; if yes, arbitrate an idle physical register from the physical register free list through a first priority arbitration tree, and allocate the idle physical register as a destination physical register to the write-destination logical register, and update the mapping relationship between the corresponding logical register and the physical register in the prediction renaming mapping table. The register allocation logic circuit is further configured to, when a RISC-V instruction executes a read-source logical register, find the corresponding source physical register number in the prediction renaming mapping table, and find the ready state of the corresponding source physical register in the physical register ready list according to the source physical register number. The register allocation logic circuit is further configured to integrate the destination physical register number, the source physical register number, and the ready state of the source physical register corresponding to the current RISC-V instruction into the access control information for output. The register allocation logic circuit further comprises a register wake-up logic.

7. The low-power single-issue out-of-order (OOO) RISC-V (RISC-five) processor of claim 1, wherein, The register wake-up logic is configured to, when a source physical register to be read by a current RISC-V instruction is not ready, detect whether there is an early wake-up signal returned from the execution unit; if yes, compare the register number carried in the early wake-up signal with the source physical register number to be read by the current RISC-V instruction; if the same, update the source physical register to be read by the current instruction to a ready state; if not the same or there is no early wake-up signal, detect whether the write address of the physical register stack by the execution unit is consistent with the source physical register number to be read by the current instruction; if consistent, update the source physical register to be read by the current RISC-V instruction to a ready state; if not consistent, wait for the source physical register to be executed. The physical register stack is configured to perform a write operation on an idle destination physical register or a read operation on a ready source physical register according to the access control information. The first priority arbitration tree is a fixed low-priority comparison multiplexing merging arbiter.

8. The low-power single-issue out-of-order (OOO) RISC-V (RISC-five) processor of claim 6, wherein, The issue unit comprises three independent and parallel issue queues: a logical operation issue queue, a multiplication and division issue queue, and a memory access issue queue; each issue queue is a non-compressed and non-data capture queue.

9. The low-power single-issue out-of-order (OOO) RISC-V (RISC-five) processor of claim 1, wherein, The issue unit further comprises a distribution logic, and the distribution logic comprises an issue ready logic, an allocation logic, and an age arbitration tree. ​ The emission readiness logic is configured to determine whether a current RISC-V instruction obtained from the decoding unit is emission ready, and determine that the current RISC-V instruction is emission ready when all source physical registers involved in the current RISC-V instruction are woken up, and distribute the emission ready RISC-V instruction to one of the emission queues according to the instruction type of the RISC-V instruction. The allocation logic is configured to find an idle item of the corresponding emission queue through the second priority arbitration tree, and write the emission ready RISC-V instruction into the idle item. The age arbitration tree is configured to age sort the RISC-V instructions in the respective emission queues, and arbitrate the oldest instructions in the three emission queues respectively for parallel emission.

10. The low-power single emission out-of-order execution RISC-V processor according to claim 1, wherein the execution unit is configured to receive decoding information of one or more RISC-V instructions emitted by the emission unit through an input gating circuit, assign the decoding information to a corresponding functional unit for calculation, and submit a calculation result to a register data path or a memory access path. The functional unit includes an independent arithmetic logic operation unit, a multiplication division calculation unit and a memory access unit; the arithmetic logic operation unit is configured to process calculation of single-cycle arithmetic operation instructions and branch jump instructions; the multiplication division calculation unit is configured to process instruction calculation of the M-type extension instruction set; and the memory access unit is configured to process calculation of load instructions and store instructions. The memory access path includes a non-compressed load queue and a first-in-first-out store queue; the store instructions are configured to write data into an external device through the memory access path; and the load instructions are configured to read data from the external device into the physical register stack through the memory access path.

11. The low-power single-issue out-of-order (OOO) RISC-V (RISC Five) processor of claim 10, wherein, The memory access unit is configured to sequentially execute the store instructions in the store queue, and out-of-order execute the load instructions in the load queue whose age is greater than that of a to-be-retired store instruction. The memory access path further includes a one-level tightly coupled data cache unit; the one-level tightly coupled data cache unit is configured to cache data read in by the load instructions in the load queue or data written out by the store instructions in the store queue.

12. The low-power single-issue out-of-order (OOO) RISC-V (RISC Five) processor of claim 11, wherein, 13. The low-power single emission out-of-order execution RISC-V processor according to claim 1, wherein the retirement unit is provided with a first-in-first-out reordering cache, branch prediction failure recovery logic and interrupt exception detection logic. The retirement unit is configured to retire instructions entering the reordering cache in sequence, return a global jump history accurate value of the retired instructions to the instruction fetching unit, and return a physical register number and register mapping relationship released by the retired instructions to the decoding unit. ​ ​ The retirement unit is further configured to perform branch misprediction detection and interrupt exception detection at the dequeue pointer of the reorder buffer using the branch misprediction recovery logic and the interrupt exception detection logic, and flush all stages of the pipelined architecture of the RISC-V processor and perform computation recovery of the RISC-V processor using the global jump history accurate value and the correct register mapping relationship when a branch misprediction or an interrupt exception occurs.

14. A method of processing instructions oriented to a RISC-V instruction set, the method comprising: The RISC-V processor is configured to process input RISC-V instructions based on the seven-stage pipelined architecture of the RISC-V processor according to any one of claims 1-13.

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