Bandwidth Allocation Method, Module, Server, Electronic Device, Medium and Product

Abstract

The present application discloses a bandwidth allocation method, module, server, electronic device, medium and product, relating to the technical field of servers, including: in response to the platform controller hub writing a strobe signal to the switch chip, controlling the output end of the switch chip to be conducted with the input end of the switch chip corresponding to the target root port of the central processing unit; wherein, the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit; obtaining the output end signal of the switch chip through the input-output interface of the platform controller hub, and allocating bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port. The bandwidth allocation method provided by the present application can implement the bandwidth allocation function of the CPU PCIe port with fewer input-output interfaces.

Description

Technical Field

[0001] This application relates to the technical field of servers, and in particular, to a bandwidth allocation method, a bandwidth allocation module, a server, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU (Central Processing Unit) and various expansion cards, such as graphics cards, sound cards, network adapters, etc. The bandwidth of PCIe is closely related to its version and the number of lanes. For example, the theoretical maximum bandwidth of a PCIe x1 slot is 1GB / s, suitable for devices with low data transfer requirements; the theoretical maximum bandwidth of a PCIe x4 slot is 4GB / s, suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of a PCIe x8 slot is 8GB / s, suitable for devices with higher data transfer speed requirements; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s and is widely used to connect high-performance graphics cards.

[0003] The PICe interfaces on the server motherboard generally use PCIe x8 slots or PCIe x16 slots, which is convenient for plugging in different types of expansion cards later. Even if the gold fingers on the expansion card are x2 or x4, they can still be plugged into the PCIe x8 slot or PCIe x16 slot. However, currently, the CPU directly provides the maximum bandwidth to the PCIe x8 slot and the PCIe x16 slot. That is, when a PCIe device with a small number of lanes is inserted, the PCIe device cannot be recognized, and the CPU still allocates the maximum bandwidth, resulting in waste of PCIe resources and loss of CPU functions.

[0004] But in the related art, when allocating the bandwidth of the CPU RootPort (root port), generally multiple GPIOs (General Purpose Input / Output) are set for each CPU root port to achieve automatic bandwidth allocation, resulting in a large amount of GPIO resources being used. Summary of the Invention

[0005] This application provides a bandwidth allocation method, module, server, electronic device, medium, and product to at least solve the problem of using a large amount of GPIO resources when automatically allocating bandwidth in the related art.

[0006] In a first aspect, this application provides a bandwidth allocation method, including:

[0007] In response to the platform controller hub writing a strobe signal to the switch chip, control the conduction between the output terminal of the switch chip and the input terminal of the switch chip corresponding to the target root port of the central processing unit; wherein, the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the bandwidth allocation signal lines of the input terminal of the switch chip and the root port of the central processing unit are connected;

[0008] Obtain the output terminal signal of the switch chip through the input / output interface of the platform controller hub, and perform bandwidth allocation for the root port according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

[0009] In a second aspect, the present application further provides a bandwidth allocation module, including:

[0010] A BIOS storage device, a platform controller hub, a switch chip, and a central processing unit;

[0011] The BIOS storage device is configured to store a bandwidth allocation program;

[0012] The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, control the conduction between the output terminal of the switch chip and the input terminal of the switch chip corresponding to the target root port of the central processing unit in response to the platform controller hub writing a strobe signal to the switch chip; and obtain the output terminal signal of the switch chip through the input / output interface of the platform controller hub, and perform bandwidth allocation for the root port according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port;

[0013] wherein, the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the bandwidth allocation signal lines of the input terminal of the switch chip and the root port of the central processing unit are connected.

[0014] In a third aspect, the present application further provides a server, including the bandwidth allocation module as described in the second aspect.

[0015] In a fourth aspect, the present application further provides an electronic device, including:

[0016] A memory for storing a computer program;

[0017] A processor for implementing the steps of the bandwidth allocation method as described in the first aspect when executing the computer program.

[0018] In a fifth aspect, the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program implements the steps of the bandwidth allocation method as described in the first aspect when being executed by a processor.

[0019] In a sixth aspect, the present application further provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the bandwidth allocation method described in the first aspect.

[0020] In the present application, since each input end of the switch chip corresponds to each root port of the central processing unit, and the input end of the switch chip is connected to the bandwidth allocation signal line of the corresponding root port of the central processing unit, the input end of the switch chip can receive the bandwidth allocation signal line information of the corresponding root port of the central processing unit. The central processing unit can respond to the platform controller hub writing a strobe signal to the switch chip. Different strobe signals control different input ends of the switch chip to conduct with the output end of the switch chip, and different input ends of the switch chip correspond to different root ports of the central processing unit. Furthermore, it can control the output end of the switch chip to conduct with the input end of the switch chip corresponding to the target root port of the central processing unit. Therefore, the signal at the output end of the switch chip obtained through the input / output interface of the platform controller hub is the bandwidth allocation signal line information of the target root port of the selected central processing unit. The central processing unit can then find the bandwidth corresponding to the bandwidth allocation signal line information according to the bandwidth allocation relationship between the signal at the output end of the switch chip and the root port, so as to allocate bandwidth to this root port. Compared with the prior art where multiple input / output interfaces need to be set for each PCIe root port of the central processing unit to achieve bandwidth allocation, for each root port of the central processing unit in the present application, a set of input / output interfaces can be used to provide strobe signals, and in a polling manner through the control of the strobe signals, the bandwidth of each root port can be allocated. Therefore, it is not necessary to set multiple input / output interfaces for each root port as in the prior art to perform bandwidth allocation. The bandwidth allocation method provided in the present application can achieve the bandwidth allocation function of the CPU PCIe port with fewer input / output interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic diagram of a bandwidth allocation framework provided by an embodiment of the present application;

[0023] Figure 2 It is a flowchart of a bandwidth allocation method provided by an embodiment of the present application;

[0024] Figure 3 It is another schematic diagram of a bandwidth allocation framework provided by an embodiment of the present application;

[0025] Figure 4 Another schematic diagram of the bandwidth allocation framework provided by the embodiment of the present application;

[0026] Figure 5 Another schematic diagram of the bandwidth allocation framework provided by the embodiment of the present application;

[0027] Figure 6 Another schematic diagram of the bandwidth allocation framework provided by the embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of a switching chip provided by the embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of a server provided by the embodiment of the present application;

[0030] Figure 9 A schematic diagram of the structure of an electronic device provided by the embodiment of the present application. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0032] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0033] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0034] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU and various expansion cards, such as graphics cards, sound cards, and network adapters, etc.

[0035] PCIe has made fundamental changes in the bus structure, mainly reflected in two aspects: one is the change from a parallel bus to a serial bus; the other is the use of point-to-point interconnection. It has changed a bus connecting devices under the bridge in the original parallel bus structure into a link. A link can contain one or more lanes, and each lane consists of two pairs of differential signal lines to form a full-duplex serial transmission channel. There are no dedicated data, address, control, and clock lines, and various transactions on the bus are organized into information packets for transmission. Another feature of PCIe that breaks through the traditional bus is the use of point-to-point interconnection method. Each device is connected by an independent link and enjoys exclusive bandwidth, which is an effective solution to improve the transmission rate. The PCIe bus structure regards a link as a bus, thus maintaining compatibility with the traditional PCI bus in terms of address space, configuration mechanism, and software. A PCIe device occupies one bus (link), so there are many bridges and buses in a PCIe-based computer. Traditional PCI devices can also run on the PCIe platform. Through a PCIe-to-PCI (or PCI-X) bridge, a PCI (or PCI-X) bus can be led out, and traditional PCI devices can be integrated into the PCI Express structure by hanging on such a bus.

[0036] The following are the detailed information of different versions of PCIe and their bandwidths:

[0037] PCIe 1.0: The bit transmission rate on the line is 2.5 Gb / s, using 8 / 10 encoding. Therefore, the bandwidth of PCIe 1.0x1 is 250 MB / s.

[0038] PCIe 2.0: The bit transmission rate on the line doubles to 5 Gb / s, using 8 / 10 encoding. Therefore, the bandwidth of PCIe 2.0x1 is 500 MB / s.

[0039] PCIe 3.0: The bit transmission rate on the line is 8 Gb / s, using 128 / 130 encoding. Therefore, the bandwidth of PCIe 3.0x1 is 1 GB / s.

[0040] PCIe 4.0: The bit transmission rate on the line is increased to 16 GT / s.

[0041] PCIe 5.0: The highest bit transmission rate on the line can reach 32 GT / s.

[0042] In addition, the bandwidth of PCIe is also related to the number of its lanes. For example, the theoretical maximum bandwidth of a PCIe x1 slot is 1GB / s, which is suitable for devices with low requirements for data transmission; the theoretical maximum bandwidth of a PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of a PCIe x8 slot is 8GB / s, which is suitable for devices with higher requirements for data transmission speed; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s and is widely used to connect high-performance graphics cards.

[0043] The PICe interfaces on the server motherboard generally use PCIe x8 slots and PCIe x16 slots, which facilitate the later plugging of different types of expansion cards. Even if the gold fingers on the expansion card are x2 or x4, they can still be plugged into the PCIe x8 slot or the PCIe x16 slot. However, currently, the bandwidth directly provided by the CPU to the PCIe x8 slot and the PCIe x16 slot is the maximum bandwidth, resulting in ineffective recognition when inserting expansion cards with a small number of lanes. The CPU still allocates the maximum bandwidth, leading to waste of PCIe resources and loss of CPU functions. For example, two PCIe x8 devices are inserted into two PCIe x16 slots, but it is impossible to support two x8 devices in one x16 slot; automatic recognition and bandwidth allocation of PCIe cannot be achieved.

[0044] Currently, when automatically allocating bandwidth for the CPU root port in related technologies, multiple GPIOs (General Purpose Input / Output) are generally set for each CPU root port to achieve automatic bandwidth allocation, resulting in a large amount of GPIO resources being used.

[0045] The embodiments of the present application provide a bandwidth allocation method. Hereinafter, a specific application environment architecture or a specific hardware architecture on which the execution of the bandwidth allocation method depends will be described.

[0046] The present application uses a switch chip and combines a bandwidth allocation program stored in a BIOS storage device to achieve automatic recognition and allocation of the CPU PCIe port bandwidth. Figure 1 A schematic diagram of a bandwidth allocation framework is shown. As Figure 1 shown, the server includes a central processing unit (i.e., CPU), a PCH (Platform Controller Hub), a BIOS storage device, and a switch chip. Among them, the input end of the switch chip can receive the bandwidth allocation signal line information of the root port of the central processing unit. Each group of input ends of the switch chip corresponds to a root port of the central processing unit. Each root port of the central processing unit corresponds to two bandwidth allocation signal lines.Figure 1 In the example, the central processing unit (CPU) includes 4 root ports, namely CPU0 PE0, CPU0 PE1, CPU0 PE2, and CPU0 PE3. Each root port corresponds to two bandwidth allocation signal lines. Figure 1 In the example, the switch chip includes 4 groups of input terminals: the first group of input terminals U1Y0, U2Y0; the second group of input terminals U1Y1, U2Y1; the third group of input terminals U1Y2, U2Y2; the fourth group of input terminals U1Y3, U2Y3. Among them, the first group of input terminals U1Y0, U2Y0 corresponds to CPU0 PE3; the second group of input terminals U1Y1, U2Y1 corresponds to CPU0 PE2; the third group of input terminals U1Y2, U2Y2 corresponds to CPU0 PE1; the fourth group of input terminals U1Y3, U2Y3 corresponds to CPU0 PE0. The bandwidth allocation signal line information of each root port can be preset.

[0047] The PCH can write a strobe signal to the switch chip through the input / output interface. The switch chip selects which group of input terminals is conducted with the output terminal of the switch chip according to the strobe signal. Then, the output terminal of the switch chip can transmit the bandwidth allocation signal line information of the corresponding root port received by the selected input terminal to the PCH through the output terminal. Figure 1 U1Z and U2Z in it are the output terminals of the switch chip. S0, S1, and S2 are the terminals in the switch chip that receive the strobe signal. In terms of software, a bandwidth allocation program is stored in the BIOS storage device. The bandwidth allocation program is used to design the bandwidth allocation program for the root port. The CPU can read the bandwidth allocation program stored in the BIOS storage device. After the server is powered on, the PCH loads the bandwidth allocation program into the memory, and the CPU executes the bandwidth allocation program. Specifically, determine the strobe signal corresponding to the root port, write the strobe signal to the switch chip through the input / output interface of the platform controller hub. The switch chip controls the output terminal of the switch chip to be conducted with the input terminal of the switch chip corresponding to the target root port of the central processing unit according to the strobe signal. Then, read the data of the output terminals U1Z, U2Z of the switch chip, and find the bandwidth required to be allocated to the root port based on the read data of U1Z, U2Z and the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port, and allocate the bandwidth to the root port according to the found bandwidth.

[0048] Figure 2 It is a flowchart of a bandwidth allocation method provided by an embodiment of the present application. The bandwidth allocation method provided by the embodiment of the present application can be applied to a central processing unit. Figure 2FIG. 0 is a flowchart of a bandwidth allocation method according to an embodiment of the present invention. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here. As Figure 2 shown, the bandwidth allocation method provided by the present application includes:

[0049] S101. In response to the platform controller hub writing a strobe signal to the switch chip, control the output terminal of the switch chip to conduct with the input terminal of the switch chip corresponding to the target root port of the central processing unit.

[0050] The BIOS storage device stores a bandwidth allocation program designed for the root port. After the server is powered on, the PCH loads the bandwidth allocation program into the memory, and the CPU executes the bandwidth allocation program. Specifically, the CPU determines the strobe signal corresponding to the root port. In response to the platform controller hub writing a strobe signal to the switch chip, control the output terminal of the switch chip to conduct with the input terminal of the switch chip corresponding to the target root port of the central processing unit. Figure 1 In FIG., S0 and S1 are terminals in the switch chip that receive the strobe signal. After the CPU writes the strobe signal to the switch chip through the input / output interface of the PCH, it can further control the switch chip to select which group of input terminals to conduct with the output terminal of the switch chip according to the strobe signal. Then, the output terminal of the switch chip can transmit the corresponding root port bandwidth allocation signal line information received by the selected input terminal to the PCH through the output terminal. Figure 1 In FIG., U1Z and U2Z are the output terminals of the switch chip. E represents the enable signal terminal of the switch chip.

[0051] Among them, the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal. As introduced in the above Figure 1 frame schematic diagram, the input terminal of the switch chip is connected to the bandwidth allocation signal line of the central processing unit's shadow root port. For example, when the strobe signal is "LLL", the root port of the central processing unit corresponding to the strobe signal is CPU0 PE3, that is, the input terminal of the switch chip corresponding to the root port CPU0 PE3 conducts with the output terminal of the switch chip. Where "L" represents a low level.

[0052] Since the input terminal of the switch chip is connected to two bandwidth allocation signal lines of the corresponding root port, and the bandwidth allocation signal line information of each root port can be preset, the output terminal of the switch chip can output the root port bandwidth allocation signal line information selected by the strobe signal to the PCH.

[0053] S102. Obtain the output signal of the switch chip through the input / output interface of the platform controller hub, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output signal of the switch chip and the root port.

[0054] In step S101, the central processing unit (CPU) selects the root port that needs to be configured with bandwidth through the strobe signal. For example, when the strobe signal "LLL" is selected in the above distance, the input end of the switch chip corresponding to the root port CPU0 PE3 is conducted with the output end of the switch chip, that is, the bandwidth of the root port CPU0 PE3 is allocated this time. In this application, there is a bandwidth allocation relationship between the output signal of the switch chip and the root port, that is, there is a certain correlation between the output signal of the switch chip and the bandwidth of the root port. The output signal of the switch chip is the information of the root port bandwidth allocation signal line selected by the switch chip according to the strobe signal. Therefore, the central processing unit can determine the bandwidth corresponding to the received output signal of the switch chip according to the bandwidth allocation relationship between the output signal of the switch chip and the root port, and allocate the found bandwidth as the bandwidth of the currently selected root port.

[0055] In this application, for each root port of the central processing unit, a set of input / output interfaces can be used to provide strobe signals, and the bandwidth of each root port can be allocated by polling in a controlled manner through the strobe signal. It can allocate the required bandwidth to each root port of the CPU, avoiding waste of PCIe resources. At the same time, since there is no need to set multiple input / output interfaces for each root port as in the prior art to allocate bandwidth. The bandwidth allocation method provided by this application can implement the bandwidth allocation function of the CPU PCIe port with fewer input / output interfaces.

[0056] In some optional embodiments, the above step S101 "in response to the platform controller hub writing a strobe signal to the switch chip, controlling the output end of the switch chip to be conducted with the input end of the switch chip corresponding to the target root port of the central processing unit" may specifically include:

[0057] Query the switch chip strobe truth table, and in response to the platform controller hub polling and writing the strobe signals corresponding to each root port to the switch chip, control the output end of the switch chip to be conducted with the input end of the switch chip corresponding to the target root port of the central processing unit.

[0058] Among them, the switch chip strobe truth table includes the corresponding relationship between the conduction conditions of different input and output ends of the switch chip and the level of the strobe signal.

[0059] In this embodiment, a truth table for gating the switch chip can be preset. The truth table for gating the switch chip includes the correspondence between the conduction conditions of different input and output terminals of the switch chip and the levels of the gating signals. Table 1 is a specific example of a truth table for gating the switch chip provided in the embodiment of the present application. As shown in Table 1, "L" represents a low level, and "H" represents a high level. Taking Figure 1 the shown framework as an example, the conduction of "U1Y0, U2Y0" and "U1Z, U2Z" means that the first group of input terminals U1Y0, U2Y0 of the switch chip are conducted with the output terminals U1Z, U2Z. Since the first group of input terminals U1Y0, U2Y0 are connected to two bandwidth signal lines of the root port CPU0 PE3, when the first group of input terminals U1Y0, U2Y0 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root port CPU0 PE3 can be output. The conduction of "U1Y1, U2Y1" and "U1Z, U2Z" means that the second group of input terminals U1Y1, U2Y1 of the switch chip are conducted with the output terminals U1Z, U2Z. Since the second group of input terminals U1Y1, U2Y1 are connected to two bandwidth signal lines of the root port CPU0 PE2, when the second group of input terminals U1Y1, U2Y1 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root port CPU0 PE2 can be output. The conduction of "U1Y2, U2Y2" and "U1Z, U2Z" means that the third group of input terminals U1Y2, U2Y2 of the switch chip are conducted with the output terminals U1Z, U2Z. Since the third group of input terminals U1Y2, U2Y2 are connected to two bandwidth signal lines of the root port CPU0 PE1, when the third group of input terminals U1Y2, U2Y2 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root port CPU0 PE1 can be output. The conduction of "U1Y3, U2Y3" and "U1Z, U2Z" means that the fourth group of input terminals U1Y3, U2Y3 of the switch chip are conducted with the output terminals U1Z, U2Z. Since the fourth group of input terminals U1Y3, U2Y3 are connected to two bandwidth signal lines of the root port CPU0 PE0, when the fourth group of input terminals U1Y3, U2Y3 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root port CPU0 PE0 can be output. Through the truth table for gating the switch chip, a gating signal can be selected to gate which root port of the CPU the signals on the two bandwidth allocation signal lines at the output terminal of the switch chip are output.

[0060]

[0061] In some alternative embodiments, the above step S102 "obtain the signal at the output terminal of the switch chip through the input / output interface of the platform controller hub, and perform bandwidth allocation for the root port according to the bandwidth allocation relationship between the signal at the output terminal of the switch chip and the root port" may specifically include:

[0062] The output signal of the switch chip is obtained through the input and output interface of the platform controller center, the bandwidth allocation table is queried, the root port bandwidth corresponding to the output signal of the switch chip is determined, and the bandwidth of the root port is configured according to the determined root port bandwidth.

[0063] The bandwidth allocation table includes the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

[0064] Table 2 is an example of a bandwidth allocation table provided in an embodiment of the present application. As shown in Table 2, the bandwidth allocation table includes the bandwidth allocation relationship between the output signal of the switch chip and the root port. The output signal of the switch chip is the signal of the input end of the switch chip selected by the selection signal, and the signal of the input end of the switch chip selected by the selection signal is the signal of the bandwidth allocation signal line of the corresponding CPU root port. The present application can pre-set the level signal of the bandwidth allocation signal line of each root port. Figure 1 Taking the framework shown as an example, in Table 2, the level signal of the bandwidth allocation signal line of the root port CPU0 PE0 is 00, the level signal of the bandwidth allocation signal line of the root port CPU0 PE1 is 01, the level signal of the bandwidth allocation signal line of the root port CPU0 PE2 is 10, and the level signal of the bandwidth allocation signal line of the root port CPU0 PE3 is 11. After the central processing unit CPU obtains the output signal of the switch chip through the input and output interface of the platform controller center PCH, it can query the bandwidth allocation table to determine the root port bandwidth corresponding to the output signal of the switch chip, and configure the bandwidth of the root port according to the determined root port bandwidth. For example, if the output signal of the switch chip is 00, it means that the switch chip input terminals U1Y3 and U2Y3 corresponding to the CPU root port are connected to the output terminal of the switch chip, and the corresponding output is the level signal of the bandwidth allocation signal line of the root port CPU0 PE0. By looking up the table, it can be seen that the bandwidth of the root port CPU0 PE0 corresponding to the output signal 00 of the switch chip is x8x8, so the bandwidth of the root port CPU0 PE0 can be configured according to the determined bandwidth x8x8 of the root port CPU0 PE0.

[0065]

[0066] In the prior art, 16 GPIOs are required for a single-channel processor (CPU includes 4 root ports). This application can only set 1 enable signal terminal (E), 2 output terminals (U1Z, U2Z), and 2 selection signal terminals (S0, S1) for a single-channel processor, a total of 5 GPIOs. Therefore, the occupied resources of GPIO can be significantly reduced.

[0067] It should be noted that, for the convenience of description, the signals transmitted in this application, and the terminals or interfaces for sending and receiving the signals use the same figure marks.

[0068] In some alternative embodiments, before controlling the output terminal of the switch chip to conduct with the input terminal of the switch chip corresponding to the target root port of the central processing unit in response to the platform controller hub writing a strobe signal to the switch chip, it may include:

[0069] Configure the bandwidth of each root port in the central processing unit to the maximum bandwidth.

[0070] In the actual use process, there may be some CPU root ports that do not participate in bandwidth configuration. Before performing bandwidth configuration in the embodiments of the present application, the bandwidth of each root port in the central processing unit is first default-configured to the maximum bandwidth, so that all root ports have corresponding bandwidths. And since the unused root ports adopt the maximum bandwidth, it can also keep the hardware resource allocation logic simple, without the need for dynamic channel splitting or recombination, reducing the overhead of logic circuits, simplifying state management and reducing physical layer complexity, and reducing the overall resource occupancy. In addition, initially default-configuring the bandwidth of each root port in the central processing unit to the maximum bandwidth can also avoid further operations when the bandwidth of the root port corresponding to the output terminal signal of the switch chip cannot be found. For example, before writing a strobe signal to the switch chip through the input / output interface of the platform controller hub, the central processing unit CPU sets the default x16 bandwidth for each root port.

[0071] In some alternative embodiments, the bandwidth allocation method provided by the present application may further include:

[0072] Obtain the output terminal signal of the switch chip through the input / output interface of the platform controller hub, and determine the root ports that do not participate in bandwidth allocation based on the bandwidth allocation relationship between the output terminal signal of the switch chip and the root ports, and configure the bandwidth of the root ports that do not participate in bandwidth allocation to the maximum bandwidth.

[0073] After obtaining the output terminal signal of the switch chip through the input / output interface of the platform controller hub (PCH), if the bandwidth of the root port corresponding to the output terminal signal cannot be found based on the bandwidth allocation relationship between the output terminal signal of the switch chip and the root ports, it indicates that the CPU root port corresponding to the output terminal signal is a root port that does not participate in bandwidth allocation. In the embodiments of the present application, when it is determined that there are root ports that do not participate in bandwidth allocation in the above manner, the bandwidth of the root ports that do not participate in bandwidth allocation is configured to the maximum bandwidth.

[0074] In some alternative embodiments, before controlling the output terminal of the switch chip to conduct with the input terminal of the switch chip corresponding to the target root port of the central processing unit in response to the platform controller hub writing a strobe signal to the switch chip, it further includes:

[0075] Write an enable signal to the switch chip through the input / output interface of the platform controller hub.

[0076] Reference Figure 1 The input / output interface of the platform controller hub includes an enable signal terminal E. The platform controller hub writes an enable signal to the switch chip through the enable signal terminal. In some embodiments, it can be configured that when the output of the enable signal terminal E is at a low level, the switch chip is enabled and starts to work. When the enable signal terminal E receives a high level, other pins of the switch chip are not connected. Figure 1 In [reference], the switch chip is also correspondingly provided with an enable signal terminal for receiving the enable signal, which is represented by the same reference numeral "E".

[0077] In some alternative embodiments, in the relationship between the output signal of the switch chip and the bandwidth allocation of the root port, the minimum combined bandwidth is 4 channels.

[0078] In the embodiments of the present application, the signal level combinations of two bandwidth signal lines are used to represent different bandwidth modes. The levels of the two bandwidth signal lines are output through the output terminal of the switch chip. Therefore, the level combinations of the GPIO pins at the output terminal of the switch chip (00, 01, 10, 11 as shown in Table 2) represent different bandwidth modes. If a smaller bandwidth unit is used, it will lead to a huge number of combinations, resulting in an increase in complexity, exceeding the range that can be represented by the GPIO pin level combinations.

[0079] In the embodiments of the present application, to avoid introducing more GPIO pins or more complex coding, the minimum combined bandwidth in the relationship between the output signal of the switch chip and the bandwidth allocation of the root port is set to 4 channels, which can simplify the circuit design and status management, and avoid the increase in the number of bandwidth combinations and hardware complexity caused by introducing a finer-grained bandwidth (such as x2).

[0080] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0081] The embodiments of the present application also provide a bandwidth allocation module, including: a platform controller hub, at least one switch chip, and at least one central processing unit.

[0082] The BIOS storage device is configured to store a bandwidth allocation program.

[0083] The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, and in response to the platform controller hub writing a strobe signal to the switch chip, control the conduction between the output end of the switch chip and the input end of the switch chip corresponding to the target root port of the central processing unit, and obtain the output end signal of the switch chip through the input / output interface of the platform controller hub. According to the bandwidth allocation relationship between the output end signal of the switch chip and the root port, bandwidth allocation is performed on the root port.

[0084] The target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

[0085] The framework and data interaction of the bandwidth allocation module provided by the embodiment of the present application in the server are similar to Figure 1 that shown and the corresponding explanations. The embodiment of the present application will not elaborate on this.

[0086] Figure 1 The switch chip in Figure 1 is a device with a strobe function. The form of the switch chip can be a single chip similar to Figure 3 shown, or it can be in the form of two chips according to the selected device function. For example, Figure 3 as shown, the switch chip includes a sub-first switch chip U1 and a second switch chip U2. Multiple input ends of the switch chip correspond to multiple root ports one by one. The input ends of the switch chip include the input pins of the first switch chip and the input pins of the second switch chip. For example, the input ends U1Y3, U2Y3 of the switch chip include the input pin Y3 of the first switch chip U1 and the input pin Y3 of the second switch chip U2. The input pins of the first switch chip and the input pins of the second switch chip at the input end of the switch chip are connected to two bandwidth allocation signal lines of the corresponding root port one by one. The input pin Y3 of the first switch chip U1 and the input pin Y3 of the second switch chip U2 are connected to two bandwidth allocation signal lines of the root port CPU0 PE0 one by one. The first switch chip U1 and the second switch chip U2 multiplex the strobe signal. Figure 3 Through the first switch chip U1 and the second switch chip U2 jointly controlling which input end is conducted with the output end according to the strobe signal, it is realized that the signal of the bandwidth allocation signal line of which root port of CPU0 is output to the output end.

[0087] It should be noted that Figure 1 the exemplary display in

[0088] In some alternative embodiments, the bandwidth allocation module provided by the embodiments of the present application can also be used in a dual-processor. The bandwidth allocation module applicable to a dual-processor includes a dual-processor bandwidth allocation unit. The dual-processor bandwidth allocation unit includes a first central processing unit, a second central processing unit, a first switch chip, and a second switch chip.

[0089] The switch chips include a first switch chip and a second switch chip; multiple input ends of the switch chips correspond to multiple root ports one by one; the input ends of the switch chips include input pins of the first switch chip and input pins of the second switch chip; the input pins of the first switch chip and the input pins of the second switch chip at the input ends of the switch chips are respectively and correspondingly connected to two bandwidth allocation signal lines of the corresponding root ports; the first switch chip and the second switch chip multiplex the gating signal.

[0090] Figure 4 It is a schematic diagram of another bandwidth allocation framework provided by the embodiments of the present application. As Figure 4 shown, the bandwidth allocation module includes a dual-processor bandwidth allocation unit. The dual-processor bandwidth allocation unit includes a first central processing unit CPU0, a second central processing unit CPU1, a first switch chip U1, and a second switch chip U2. The switch chips include a first switch chip U1 and a second switch chip U2. Multiple input ends of the switch chips correspond to multiple root ports one by one.

[0091] Figure 4 Exemplarily, it is set that the first central processing unit CPU0 includes 4 root ports, namely CPU0 PE0, CPU0 PE1, CPU0 PE2, and CPU0 PE3. The second central processing unit CPU1 includes 4 root ports, namely CPU1 PE0, CPU1 PE1, CPU1 PE2, and CPU1 PE3.

[0092] The multiple input terminals of the switch chip include the first group of input terminals U1Y0, U2Y0; the second group of input terminals U1Y1, U2Y1; the third group of input terminals U1Y2, U2Y2; the fourth group of input terminals U1Y3, U2Y3; the fifth group of input terminals U1Y4, U2Y4; the sixth group of input terminals U1Y5, U2Y5; the seventh group of input terminals U1Y6, U2Y6; the eighth group of input terminals U1Y7, U2Y7. The first group of input terminals U1Y0, U2Y0 corresponds to CPU0 PE3; the second group of input terminals U1Y1, U2Y1 corresponds to CPU0 PE2; the third group of input terminals U1Y2, U2Y2 corresponds to CPU0 PE1; the fourth group of input terminals U1Y3, U2Y3 corresponds to CPU0 PE0. The fifth group of input terminals U1Y4, U2Y4 corresponds to CPU1 PE0; the sixth group of input terminals U1Y5, U2Y5 corresponds to CPU1 PE1; the seventh group of input terminals U1Y6, U2Y6 corresponds to CPU1 PE2; the eighth group of input terminals U1Y7, U2Y7 corresponds to CPU1 PE3.

[0093] Each input terminal of the switch chip corresponds to two pins, including the input pin of the first switch chip and the input pin of the second switch chip. The input pin of the first switch chip and the input pin of the second switch chip of the input terminal of the switch chip are respectively and correspondingly connected to two bandwidth allocation signal lines of the corresponding root port to obtain the signals of the two bandwidth allocation signal lines of the corresponding root port.

[0094] For example, the first group of input terminals U1Y0, U2Y0 includes the input pin Y0 of the first switch chip U1 and the input pin Y0 of the second switch chip U2. The second group of input terminals U1Y1, U2Y1 includes the input pin Y1 of the first switch chip U1 and the input pin Y1 of the second switch chip U2. The third group of input terminals U1Y2, U2Y2 includes the input pin Y2 of the first switch chip U1 and the input pin Y2 of the second switch chip U2. The fourth group of input terminals U1Y3, U2Y3 includes the input pin Y3 of the first switch chip U1 and the input pin Y3 of the second switch chip U2. The fifth group of input terminals U1Y4, U2Y4 includes the input pin Y4 of the first switch chip U1 and the input pin Y4 of the second switch chip U2. The sixth group of input terminals U1Y5, U2Y5 includes the input pin Y5 of the first switch chip U1 and the input pin Y5 of the second switch chip U2. The seventh group of input terminals U1Y6, U2Y6 includes the input pin Y6 of the first switch chip U1 and the input pin Y6 of the second switch chip U2. The eighth group of input terminals U1Y7, U2Y7 includes the input pin Y7 of the first switch chip U1 and the input pin Y7 of the second switch chip U2.

[0095] Such as Figure 4As shown, the first switch chip U1 and the second switch chip U2 both include three gating signal terminals S0, S1, and S2. The first switch chip U1 and the second switch chip U2 share the gating signals, that is, the first switch chip U1 and the second switch chip U2 use the same set of gating signals, and the first switch chip U1 and the second switch chip U2 are connected to the same gating signal GPIO pins of the PCH. This setting can reduce the number of GPIO pins used.

[0096] Figure 4 The bandwidth allocation module shown includes two CPUs, a total of 8 root ports, and only two GPIOs ( Figure 4 U1Z and U2Z in it) are required to implement the bandwidth allocation function of the CPU root ports of the dual-server. The input ends of the two switch chips receive the information on the bandwidth allocation signal lines of the 8 root ports of the two CPUs.

[0097]

[0098] In this embodiment, the gating truth table of the switch chip can be preset. The gating truth table of the switch chip includes the corresponding relationship between the conduction conditions of different input and output ends of the switch chip and the levels of the gating signals. Table 3 is for Figure 4Specific example of the gating truth table of the switching chip for the shown bandwidth allocation framework. As shown in Table 3, "L" represents low level and "H" represents high level. The conduction of "U1Y0, U2Y0" and "U1Z, U2Z" means that the first group of input terminals U1Y0, U2Y0 of the first switching chip U1 are conducted with the output terminals U1Z, U2Z. Since the first group of input terminals U1Y0, U2Y0 are connected to the two bandwidth signal lines of the root port CPU0 PE3, when the first group of input terminals U1Y0, U2Y0 are conducted with the output terminals U1Z, U2Z, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE3 can be output. The conduction of "U1Y1, U2Y1" and "U1Z, U2Z" means that the second group of input terminals U1Y1, U2Y1 of the switching chip CPU0 are conducted with the output terminals U1Z, U2Z. Since the second group of input terminals U1Y1, U2Y1 are connected to the two bandwidth signal lines of the root port CPU0 PE2, when the second group of input terminals U1Y1, U2Y1 are conducted with the output terminals U1Z, U2Z, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE2 can be output. The conduction of "U1Y2, U2Y2" and "U1Z, U2Z" means that the third group of input terminals U1Y2, U2Y2 of the switching chip CPU0 are conducted with the output terminals U1Z, U2Z. Since the third group of input terminals U1Y2, U2Y2 are connected to the two bandwidth signal lines of the root port CPU0 PE1, when the third group of input terminals U1Y2, U2Y2 are conducted with the output terminals U1Z, U2Z, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE1 can be output. The conduction of "U1Y3, U2Y3" and "U1Z, U2Z" means that the fourth group of input terminals U1Y3, U2Y3 of the switching chip CPU0 are conducted with the output terminals U1Z, U2Z. Since the fourth group of input terminals U1Y3, U2Y3 are connected to the two bandwidth signal lines of the root port CPU0 PE0, when the fourth group of input terminals U1Y3, U2Y3 are conducted with the output terminals U1Z, U2Z, the corresponding signals of the two bandwidth signal lines of the root port CPU0 PE0 can be output. The conduction of "U1Y4, U2Y4" and "U1Z, U2Z" means that the fifth group of input terminals U1Y4, U2Y4 of the switching chip CPU1 are conducted with the output terminals U1Z, U2Z. Since the fifth group of input terminals U1Y4, U2Y4 are connected to the two bandwidth signal lines of the root port CPU1 PE0, when the fifth group of input terminals U1Y4, U2Y4 are conducted with the output terminals U1Z, U2Z, the corresponding signals of the two bandwidth signal lines of the root port CPU1 PE0 can be output.The conduction of “U1Y5, U2Y5” and “U1Z, U2Z” indicates that the sixth group of input terminals U1Y5, U2Y5 of the switch chip CPU1 are conducted with the output terminals U1Z, U2Z. Since the sixth group of input terminals U1Y5, U2Y5 are connected to two bandwidth signal lines of the root port CPU1 PE1, when the sixth group of input terminals U1Y5, U2Y5 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root terminal CPU1 PE1 can be output. The conduction of “U1Y6, U2Y6” and “U1Z, U2Z” indicates that the seventh group of input terminals U1Y6, U2Y6 of the switch chip CPU1 are conducted with the output terminals U1Z, U2Z. Since the seventh group of input terminals U1Y6, U2Y6 are connected to two bandwidth signal lines of the root port CPU1 PE2, when the seventh group of input terminals U1Y6, U2Y6 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root terminal CPU1 PE2 can be output. The conduction of “U1Y7, U2Y7” and “U1Z, U2Z” indicates that the eighth group of input terminals U1Y7, U2Y7 of the switch chip CPU0 are conducted with the output terminals U1Z, U2Z. Since the eighth group of input terminals U1Y7, U2Y7 are connected to two bandwidth signal lines of the root port CPU1 PE3, when the eighth group of input terminals U1Y7, U2Y7 are conducted with the output terminals U1Z, U2Z, the signals corresponding to the two bandwidth signal lines of the root terminal CPU1 PE3 can be output.

[0099] Enable signal terminals E are provided on the switch chips CPU0 and CPU1. When the signal received by the enable signal terminal E is the low level “L”, the switch chips are enabled and start to work. When the enable signal terminal E receives the high level “H”, the other pins of the switch chips are not connected, and “X” in Table 3 indicates that the corresponding pins are not connected.

[0100] In this embodiment, a bandwidth allocation table can be preset, and the bandwidth allocation table includes the bandwidth allocation relationship between the output terminal signals of the switch chip and the root port. Table 4 is a specific example of the bandwidth allocation table for the Figure 4 frame of the bandwidth allocation shown. As shown in Table 4, the level signals of the bandwidth allocation signal lines of the root port CPU0 PE0 are 00, the level signals of the bandwidth allocation signal lines of the root port CPU0 PE1 are 01, the level signals of the bandwidth allocation signal lines of the root port CPU0 PE2 are 10, the level signals of the bandwidth allocation signal lines of the root port CPU0 PE3 are 11, the level signals of the bandwidth allocation signal lines of the root port CPU1 PE2 are 10, and the level signals of the bandwidth allocation signal lines of the root port CPU1 PE3 are 11.

[0101]

[0102] After the central processing unit (CPU) obtains the output signal of the switch chip through the input / output interface of the platform controller hub (PCH), it can query the bandwidth allocation table to determine the root port bandwidth corresponding to the output signal of the switch chip, and configure the bandwidth of the root port according to the determined root port bandwidth. For example, if the output signal of the switch chip is 00, it means that the input terminals U1Y3 and U2Y3 of the switch chip corresponding to the CUP root port are conducted with the output terminal of the switch chip, and the level signal of the bandwidth allocation signal line of the root port CPU0 PE0 is output correspondingly. By looking up the table, it can be known that the root port bandwidth corresponding to the output signal 00 of the switch chip is x8x8. Therefore, the bandwidth of the root port CPU0 PE0 can be configured according to the determined root port bandwidth x8x8. In Table 4, the output signals of the switch chips corresponding to the root ports CPU1 PE0 and CPU1 PE1 are "NC", indicating that the root ports CPU1 PE0 and CPU1 PE1 do not participate in the bandwidth configuration, and the root ports CPU1 PE0 and CPU1 PE1 are default set to x16.

[0103] In some alternative embodiments, the platform controller hub includes an enable signal terminal for writing an enable signal to the switch chip. The first switch chip and the second switch chip are connected to the same enable signal terminal.

[0104] See Figure 4 , when implementing the bandwidth allocation of the dual-processor in the embodiment of the present application, the first switch chip and the second switch chip are set to be connected to the same enable signal terminal of the platform controller hub. Under the same enable signal, different input and output conduction selections are realized through the level combination of the gating signals S0, S1, and S2, which can reduce the number of PCH GPIO pins.

[0105] In some alternative embodiments, the bandwidth allocation module includes a four-processor bandwidth allocation unit, and the four-processor bandwidth allocation unit includes two dual-processor bandwidth allocation units, namely the first dual-processor bandwidth allocation unit and the second dual-processor bandwidth allocation unit; the first dual-processor bandwidth allocation unit and the second dual-processor bandwidth allocation unit are connected to different enable signal terminals; the first dual-processor bandwidth allocation unit and the second dual-processor bandwidth allocation unit multiplex the gating signals.

[0106] In the prior art, a dual-processor (both CPUs include 4 root ports) requires 32 GPIOs. While adopting the method of the present application, by setting the bandwidth of the bandwidth signal line of the CPU root port to achieve automatic bandwidth configuration, while avoiding PCIe resource waste, for a dual-processor, only 1 enable signal terminal (E), 2 output terminals (U1Z, U2Z), and 3 strobe signal terminals (S0, S1, S2) can be set, a total of 6 GPIOs. Therefore, the occupied resources of GPIOs can be significantly reduced.

[0107] The embodiment of the present application can be applied to the bandwidth allocation of a quad-processor. Figure 5 It is a schematic diagram of another bandwidth allocation framework provided by the embodiment of the present application. As Figure 5 shown, the quad-processor bandwidth allocation unit includes two dual-processor bandwidth allocation units, namely the first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2. The first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2 can refer to the above Figure 4 and the corresponding structure and principle introduction, which will not be elaborated in the embodiment of the present application. The first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2 are connected to different enable signal terminals of the PCH. Figure 5 For the enable signal terminal of the PCH, the first dual-processor bandwidth allocation unit A1, and the second dual-processor bandwidth allocation unit A2, the ports corresponding to the same enable signal are represented by the same reference numerals. The enable signal terminal E1 of the first dual-processor bandwidth allocation unit A1 receives the enable signal of the enable signal terminal E1 of the PCH, and the enable signal terminal E2 of the second dual-processor bandwidth allocation unit A2 receives the enable signal of the enable signal terminal E2 of the PCH. The output terminals of the switch chip in the first dual-processor bandwidth allocation unit A1 are represented by U1Z, U1Z, and the output terminals of the switch chip in the second dual-processor bandwidth allocation unit A2 are represented by U3Z, U4Z. The two central processors of the first dual-processor bandwidth allocation unit A1 are represented by CPU0 and CPU1, and the two central processors of the second dual-processor bandwidth allocation unit A2 are represented by CPU2 and CPU3. The first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2 multiplex the strobe signals, that is, the first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2 both receive the same set of strobe signals from the PCH. For example Figure 5 the first dual-processor bandwidth allocation unit A1 and the second dual-processor bandwidth allocation unit A2 in [reference] are connected to 3 GPIO pins of the PCH for inputting the strobe signals S0, S1, and S2.

[0108] In some alternative embodiments, the bandwidth allocation module includes a four-way processor bandwidth allocation unit, and the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit is connected to the enable signal terminal of the platform controller hub; the second dual-way processor bandwidth allocation unit is connected to the enable signal terminal connected by the first dual-way processor bandwidth allocation unit through an inverter; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit share the gating signal.

[0109] The embodiments of the present application are also applicable to the bandwidth allocation of four-way processors. Figure 6 It is a schematic diagram of another bandwidth allocation framework provided by the embodiments of the present application. As Figure 6 shown, the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit A1 and a second dual-way processor bandwidth allocation unit A2. The first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 can refer to the above Figure 4 and the corresponding structure and principle introduction, which will not be elaborated in the embodiments of the present application. The first dual-way processor bandwidth allocation unit A1 is connected to the enable signal terminal E of the PCH, Figure 6 and the enable signal terminal of the first dual-way processor bandwidth allocation unit A1 is marked as E1 in the figure. The enable signal terminal E2 of the second dual-way processor bandwidth allocation unit A2 is connected to the enable signal terminal connected by the first dual-way processor bandwidth allocation unit through an inverter B, and the enable signal terminal of the second dual-way processor bandwidth allocation unit A2 is marked as E2. The output terminals of the switch chips in the first dual-way processor bandwidth allocation unit A1 are represented by U1Z and U1Z, and the output terminals of the switch chips in the second dual-way processor bandwidth allocation unit A2 are represented by U3Z and U4Z. The two central processing units of the first dual-way processor bandwidth allocation unit A1 are represented by CPU0 and CPU1, and the two central processing units of the second dual-way processor bandwidth allocation unit A2 are represented by CPU2 and CPU3. The first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit 2 share the gating signal, that is, both the first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 receive the same set of gating signals from the PCH. For example, Figure 6 in the figure, the first dual-way processor bandwidth allocation unit A1 and the second dual-way processor bandwidth allocation unit A2 are connected to 3 GPIO pins of the PCH for inputting gating signals S0, S1, and S2.

[0110] In the embodiment of the present application, the first dual-processor bandwidth allocation unit A1 is connected to the enable signal terminal E of the PCH, and the second dual-processor bandwidth allocation unit A2 is connected to the enable signal terminal connected by the first dual-processor bandwidth allocation unit A1 through an inverter B, which can further save the number of CPIO pins of the PCH.

[0111] In some alternative embodiments, the bandwidth allocation module may further include i four-processor bandwidth allocation units; different four-processor bandwidth allocation units are connected to different enable signal terminals; different four-processor bandwidth allocation units multiplex the strobe signals. Wherein, i is a positive integer greater than 1.

[0112] The embodiment of the present application can be applicable to the case of 8-way or more processors. For example, when the bandwidth allocation module further includes 2 four-processor bandwidth allocation units, it can be applicable to 8-way processors. For the specific structure and implementation principle of the four-processor bandwidth allocation unit, reference can be made to the introduction in the above embodiments and architectures similar to Figure 5 or Figure 6 the architecture. Different four-processor bandwidth allocation units are connected to different enable signal terminals of the PCH to implement the enable polling configuration of each CPU root port.

[0113] In the prior art, 32 GPIOs of the PCH are used for dual processors. Currently, the PCH may still provide enough GPIOs for its use. However, for four-processor cases, since the number of GPIOs of the PCH is limited, the prior art uses a GPIO expansion chip to expand the GPIOs to provide GPIOs for the bandwidth allocation of four-processor cases. Therefore, in the prior art, for four-processor or more processors, not only does a GPIO expansion chip need to be involved, but also corresponding programs need to be configured for reading, so it is relatively complex and has poor stability.

[0114] In the prior art, if bandwidth allocation is performed for a single-processor case, for example, the root port CPU0 PE0 is configured using GPIO5~GPIO8. If another motherboard design is used, this root port may be replaced with another set of GPIOs. Once the CPU root port changes, the configuration program needs to be rewritten. For multi-processor cases, the prior art also needs to add a GPIO expansion chip. The GPIOs expanded by the expansion chip corresponding to a certain root port of a certain CPU are not fixed. For different CPUs and different root ports, corresponding programs need to be rewritten, while the read configuration of the present application can be fixed and universal. Even if the server model changes (such as different motherboard or system designs), and even if the connection form of the server CPU root port changes, the same BIOS program can still be used for the bandwidth allocation of the CPU root port.

[0115] In some alternative embodiments, the bandwidth allocation module further includes a bandwidth signal line level configuration circuit. The bandwidth signal line level configuration circuit is electrically connected to the input end of the switch chip and is used to configure the level signal of the input end of the switch chip.

[0116] The bandwidth signal line level configuration circuit includes, for example, a pull-up resistor, a pull-down resistor, etc. Connecting to the ground is a low level, and connecting to the power supply is a high level. The specific circuit composition of the bandwidth signal line level configuration circuit in the embodiments of the present application is not limited. The level information of the bandwidth allocation signal line is set through the bandwidth signal line level configuration circuit, so as to configure the level signal of the input end of the switch chip.

[0117] In some alternative embodiments, the bandwidth signal line level configuration circuit is disposed on the main board or the expansion card.

[0118] For the case where there are fixed slots on the server main board, the level information of the bandwidth allocation signal line can be set by setting the bandwidth signal line level configuration circuit on the main board.

[0119] For the case of setting an expansion card in the general slot on the main board, the level information of the bandwidth allocation signal line can be set through the bandwidth signal line level configuration circuit on the expansion card.

[0120] In some alternative embodiments, the platform controller hub includes n strobe signal input / output interfaces for writing strobe signals to the switch chip; the number n of the strobe signal input / output interfaces satisfies: 2 n = m; where m is the number of root ports.

[0121] In the embodiments of the present application, the number of PCH strobe signal input / output interfaces can be flexibly set according to the number of root ports to provide strobe signals to the switch chip. In the present application, the PCH strobe signal input / output interfaces can also be referred to as GPIO pins.

[0122] For example Figure 3 In the case of a single-way server shown including 4 root ports, the number of root ports m = 4, the number n of the strobe signal input / output interfaces is set to 2, and the PCH provides strobe signals to the switch chip through two GPIO pins.

[0123] For example Figure 4 In the case of a two-way server shown including 8 root ports, the number of root ports m = 8, the number n of the strobe signal input / output interfaces is set to 3, and the PCH provides strobe signals to the switch chip through three GPIO pins.

[0124] In some alternative embodiments, the switch chip may include, for example, a logic level conversion module and a decoder. As Figure 7As shown, the switch chip includes a logic level conversion module and a decoder. Among them, the logic level conversion module is used to convert the level of the input signal into a level suitable for the internal circuit to work. It can include multiple inverters and buffers, etc. Through the cascading of inverters and buffers, signal amplification and shaping can be achieved to ensure the stability and integrity of the signal. The logic level conversion module includes input terminals S0, S1, S2, and E. The input terminals S0, S1, S2 are used to receive the strobe signals, and the input terminal E is used to receive the enable signal. The output terminal of the logic level conversion module is connected to the decoder module. The logic level conversion module also includes power terminals: Vcc and GND. If taking Figure 4 the switch chip with the architecture shown, the decoder of the switch chip decodes the 3-bit binary address signal into 8 independent output signals, and only one of the output signals is at a high level, and the rest of the output signals are at a low level. When the input address signal changes, only one of the output signals is at a high level, and the rest of the output signals are at a low level. The decoder is usually composed of multiple AND gates and OR gates to achieve the decoding function. The input terminals C1, C2, C3, C4 of the decoder are connected to the output terminal of the logic level conversion module. The output terminals D0, D1, D2, D3, D4, D5, D6, D7 of the decoder control which input terminal (Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7) of the switch chip is conducted with the output terminal Z of the switch chip. The logic level conversion module and the decoder inside the switch chip jointly implement the function of an 8-channel analog multiplexer / demultiplexer. The logic level conversion module ensures the stability and integrity of the input signal, and the decoder realizes the decoding of the input address signal, thus realizing the functions of multiplexing and demultiplexing.

[0125] This embodiment also provides a server, as Figure 8 shown. The server includes the bandwidth allocation module in any of the above embodiments. The bandwidth allocation module includes a BIOS storage device, a platform controller hub (PCH), a switch chip, and a central processing unit (CPU). The BIOS storage device is configured to store a bandwidth allocation program; the central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, and in response to the platform controller hub writing a strobe signal to the switch chip, control the input terminal of the switch chip corresponding to the target root port of the central processing unit to be conducted with the output terminal of the switch chip, and obtain the output terminal signal of the switch chip through the input / output interface of the platform controller hub, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port. Among them, the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the bandwidth allocation signal lines of the input terminal of the switch chip and the root port of the central processing unit are connected.

[0126] The functional descriptions of the BIOS storage device, platform controller hub, switch chip, and central processing unit in this server are the same as those in the corresponding foregoing embodiments, and will not be elaborated herein.

[0127] An embodiment of this application further provides an electronic device. As Figure 9 shown, it is a schematic structural diagram of the electronic device provided by the embodiment of this application. The electronic device includes a memory 100 and a processor 200. Among them, the memory 100 is used to store a computer program; the processor 200 is used to implement the steps of the bandwidth allocation method provided in any of the foregoing embodiments when executing the computer program.

[0128] The electronic device provided by the embodiment of this application is used to execute the bandwidth allocation method provided in the foregoing embodiment, and its implementation manner and principle are the same, and will not be elaborated herein.

[0129] An embodiment of this application further provides a computer-readable storage medium, in which a computer program is stored. Among them, the computer program is set to execute the steps in any of the foregoing embodiments of the bandwidth allocation method when running.

[0130] In an exemplary embodiment, the foregoing computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0131] An embodiment of this application further provides a computer program product. The foregoing computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the foregoing embodiments of the bandwidth allocation method.

[0132] An embodiment of this application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the foregoing embodiments of the bandwidth allocation method.

[0133] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the foregoing description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0134] The above has introduced in detail a bandwidth allocation method provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A bandwidth allocation method, characterized in that: include: In response to the platform controller center polling and writing a strobe signal to the switch chip, the output end of the switch chip is controlled to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit; wherein the target root port of the central processing unit is the root port of the central processing unit corresponding to the strobe signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit; The output terminal signal of the switch chip is obtained through the input and output interface of the platform controller center, and the bandwidth of the root port is allocated according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port.

2. The bandwidth allocation method according to claim 1, characterized in that: The method of controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor in response to the platform controller center polling the switch chip to write a strobe signal comprises: Query the switch chip gating truth table, respond to the platform controller center polling and writing the gating signal corresponding to each root port to the switch chip, and control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processor; The switch chip gating truth table includes the corresponding relationship between the conduction conditions of different input terminals and output terminals of the switch chip and the levels of the gating signal.

3. The bandwidth allocation method according to claim 1, characterized in that: The step of acquiring the output terminal signal of the switch chip through the input and output interface of the platform controller center, and allocating bandwidth to the root port according to the bandwidth allocation relationship between the output terminal signal of the switch chip and the root port, comprises: Obtaining the output end signal of the switch chip through the input and output interface of the platform controller center, querying the bandwidth allocation table, determining the root port bandwidth corresponding to the output end signal of the switch chip, and configuring the bandwidth of the root port according to the determined root port bandwidth; The bandwidth allocation table includes a bandwidth allocation relationship between an output terminal signal of a switch chip and a root port.

4. The bandwidth allocation method according to claim 1, characterized in that: Before the step of responding to the platform controller center polling the switch chip to write a strobe signal and controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor, the step includes: The bandwidth of each of the root ports in the central processor is configured to be the maximum bandwidth.

5. The bandwidth allocation method according to claim 1, characterized in that: Also includes: The output signal of the switch chip is obtained through the input and output interface of the platform controller center, and the root port not participating in the bandwidth allocation is determined based on the bandwidth allocation relationship between the output signal of the switch chip and the root port, and the bandwidth of the root port not participating in the bandwidth allocation is configured as the maximum bandwidth.

6. The bandwidth allocation method according to claim 1, characterized in that: Before the step of responding to the platform controller center polling the switch chip to write a strobe signal and controlling the output end of the switch chip to be connected to the input end of the switch chip corresponding to the target root port of the central processor, the step further includes: The enable signal is written to the switch chip through the input and output interface of the platform controller center.

7. A bandwidth allocation module, characterized in that: include: BIOS storage devices, platform controller hub, switch chips and central processing units; The BIOS storage device is configured to store a bandwidth allocation program; The central processing unit is configured to read the bandwidth allocation program stored in the BIOS storage device, and in response to the platform controller center polling and writing a selection signal to the switch chip, control the output end of the switch chip to be connected with the input end of the switch chip corresponding to the target root port of the central processing unit; and obtain the output end signal of the switch chip through the input and output interface of the platform controller center, and allocate bandwidth to the root port according to the bandwidth allocation relationship between the output end signal of the switch chip and the root port; The target root port of the central processing unit is the root port of the central processing unit corresponding to the selection signal; the input end of the switch chip is connected to the bandwidth allocation signal line of the root port of the central processing unit.

8. The bandwidth allocation module according to claim 7, characterized in that: It also includes a bandwidth signal line level configuration circuit; the bandwidth signal line level configuration circuit is electrically connected to the input end of the switch chip and is used to configure the level signal of the input end of the switch chip.

9. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth signal line level configuration circuit is arranged on the main board.

10. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth signal line level configuration circuit is arranged on the expansion card.

11. The bandwidth allocation module according to claim 8, characterized in that: The platform controller center includes n selection signal input and output interfaces for writing selection signals to the switch chip; the number n of the selection signal input and output interfaces satisfies: 2n=m; wherein m is the number of root ports.

12. The bandwidth allocation module according to claim 8, characterized in that: The bandwidth allocation module includes a dual-path processor bandwidth allocation unit; the dual-path processor bandwidth allocation unit includes a first central processing unit, a second central processing unit, a first switch chip and a second switch chip; the switch chip includes the first switch chip and the second switch chip; the multiple input ends of the switch chip correspond one-to-one to the multiple root ports; the input end of the switch chip includes an input pin of the first switch chip and an input pin of the second switch chip; the input pin of the first switch chip and the input pin of the second switch chip at the input end of the switch chip are connected one-to-one to two bandwidth allocation signal lines of the corresponding root port; the first switch chip and the second switch chip multiplex the selection signal.

13. The bandwidth allocation module according to claim 12, characterized in that: The platform controller center includes an enable signal terminal for writing an enable signal to the switch chip; the first switch chip and the second switch chip are connected to the same enable signal terminal.

14. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module includes a four-way processor bandwidth allocation unit, and the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit are connected to different enable signal terminals; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

15. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module includes a four-way processor bandwidth allocation unit, and the four-way processor bandwidth allocation unit includes two dual-way processor bandwidth allocation units, namely a first dual-way processor bandwidth allocation unit and a second dual-way processor bandwidth allocation unit; the first dual-way processor bandwidth allocation unit is connected to the enable signal end of the platform controller center; the second dual-way processor bandwidth allocation unit is connected to the enable signal end connected to the first dual-way processor bandwidth allocation unit through an inverter; the first dual-way processor bandwidth allocation unit and the second dual-way processor bandwidth allocation unit multiplex the selection signal.

16. The bandwidth allocation module according to claim 13, characterized in that: The bandwidth allocation module comprises i four-way processor bandwidth allocation units; different four-way processor bandwidth allocation units are connected to different enable signal terminals; different four-way processor bandwidth allocation units multiplex the selection signal; Wherein, i is a positive integer greater than 1.

17. A server, characterized in that: Comprising a bandwidth allocation module as described in any one of claims 7 to 16.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bandwidth allocation method according to any one of claims 1 to 6 when executing the computer program.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the bandwidth allocation method according to any one of claims 1 to 6.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the bandwidth allocation method according to any one of claims 1 to 6 are implemented.

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