Double-bit input characteristic optimized DCIM circuit based on SRAM

Abstract

The invention discloses a double-bit input characteristic optimized DCIM circuit based on an SRAM, and belongs to the technical field of electronic circuits. Comprising an input preprocessing module, an SRAM (Static Random Access Memory) memory array, a split adder tree, a result correction module and an uninterrupted accumulator, wherein the input preprocessing module is used for supporting feature optimization of multiple groups of double-bit data; the low sparseness input data is inverted to increase sparseness, and the resulting computational errors will be subsequently corrected. And after rarefaction, two groups of input data with lower average inversion rate are recombined. The sparseness can be obviously improved and the inversion rate can be reduced through feature optimization. The hybrid computing unit and the split adder tree embedded in each SRAM unit in the SRAM memory array are used for completing multiplication and addition operation of input data and weights after recombination. The uninterrupted accumulator completes accumulation with a minimum period. The circuit aims at improving the operation energy efficiency and the data throughput of the DCIM architecture for the edge AI equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a DCIM circuit with double-bit input characteristic optimization based on SRAM. Background Art

[0002] Artificial intelligence (AI) edge devices offer significant advantages for AI tasks, including enhanced privacy, reduced latency, and increased bandwidth, but are often limited by power consumption. However, the separation of on-chip / off-chip memory and processing elements (PEs) in the traditional von Neumann architecture leads to a "memory wall" bottleneck. When using a von Neumann-based processor to perform neural network model operations in AI tasks, a large number of weight parameters in the model need to be frequently moved from the storage device to the computing unit, which will greatly limit the energy efficiency and latency of the processor when performing such tasks. Unlike traditional von Neumann-based systems, the CIM architecture can significantly improve the throughput and energy efficiency of multiplication and addition operations, making it a better solution for AI edge devices.

[0003] Computation-in-memory (CIM) based on static random access memory (SRAM) has attracted more attention due to its high speed and high reliability. The analog computation-in-memory scheme (ACIM) based on SRAM has advantages in terms of wiring resources and energy efficiency. However, PVT (process, voltage, temperature) and signal tolerance have a great impact on the accuracy of analog CIM. In contrast, the digital computation-in-memory scheme (DCIM) based on SRAM has the advantage of being insensitive to PVT, and the computational accuracy in the digital domain is higher and more stable, which enables it to have higher computational accuracy when facing neural network tasks. However, DCIM faces three major challenges: (1) As the input data inversion rate increases, the energy consumption of DCIM will increase significantly. (2) The large-scale adder tree used for partial product summation will result in considerable energy consumption. (3) The computational parallelism of DCIM is limited by wiring resources, resulting in its low throughput.

[0004] Many works are devoted to improving the energy efficiency of DCIM, especially for the optimization of adder trees and local computing units. For example, Chih et al. used a 14 / 28T hybrid adder tree to improve the energy efficiency by 30%. Wang et al. used bitwise OR logic operations to replace the addition operations of non-overlapping partial multiplications to improve the energy efficiency of DCIM. Guo et al. reduced the energy efficiency of DCIM by reducing the number of adders by approximating partial products. How to further reduce the energy efficiency of DCIM on the basis of the above is the problem to be solved in this application. Summary of the invention

[0005] In view of the above, the present invention proposes a DCIM circuit with dual-bit input feature optimization based on SRAM, which is aimed at edge AI computing and adopts a high-efficiency, high-throughput MAC operation mechanism. It can optimize the key characteristics of input data (including sparsity and inversion rate), improve the computing energy efficiency of DCIM and alleviate the limitations of DCIM on wiring resources.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention discloses a DCIM circuit based on SRAM with dual-bit input feature optimization, wherein the DCIM circuit is applied to multiplication and addition operations of neural network input data and neural network weights;

[0008] The DCIM circuit adopts a dual-bit data serial computing model: it has an input preprocessing module that supports feature optimization of multiple groups of dual-bit data, an SRAM storage array and a split adder tree that supports dual-bit parallel computing, a result correction module, and an uninterrupted accumulator;

[0009] The input preprocessing module includes an input data sparsification module and an input reorganization module; the input data sparsification module determines the sparsity of the neural network input data through a delay mechanism, and inverts the input data with low sparsity bit by bit, keeps the input data with high sparsity unchanged, and generates an inversion flag signal; the input reorganization module reorganizes the double-bit input data processed by the input data sparsification module into a left input and a right input with a lower average inversion rate, and generates a shift control signal;

[0010] The SRAM storage array pre-calculates and stores the weights of the neural network and the sum of the weights. The hybrid computing unit embedded in each SRAM unit in the SRAM storage array completes the dot product of the left input, the right input and the weight respectively to obtain two groups of partial products; the partial products are shifted according to the shift control signal; the two groups of partial products are summed by a split adder tree divided into two to obtain two partial sums, which are corrected by a result correction module using the sum of the weights stored in the SRAM storage array to calculate the corrected intermediate sum, and then the continuous accumulator completes the accumulation and outputs the final multiplication and addition result.

[0011] Preferably, the input data sparsification module includes an input sparsity detection unit and an input inversion control unit, and the input sparsity detection unit includes an input control delay link and a reference delay link composed of a buffer delay unit; the double-bit input data is sampled, and a delay controlled by the sampled input data is generated through the input control delay link, and the size of the delay is negatively correlated with the number of "1"s in the sampled input data; the input control signal of the reference delay link is set to have 50% "1"; if the input delay is less than the reference delay, the sparsity of the input data is less than 50%, and a corresponding input inversion flag signal P=1 is generated at this time, and the input data is bit-inverted through the input inversion control unit; otherwise P=0, and the input data remains unchanged.

[0012] Preferably, the input inversion control unit includes a two-stage inverter and a 2-to-1 multiplexer, the selection signal of the multiplexer is P, and the two input signals of the multiplexer are the outputs of the two-stage inverters respectively; when P=1, the logical function of the input inversion control unit is an inverter, and when P=0, the logical function of the input inversion control unit is a buffer.

[0013] Preferably, the calculation of the input recombination module includes:

[0014] When IN[i+1] is a non-sign bit, INL=IN[i]&IN[i+1], INR=IN[i]|IN[i+1], and the original input data is reorganized into a sparser left input INL and a denser right input INR; wherein the bit weight of INL is 2, and the bit weight of INR is 1; and when IN[i]=0, IN[i+1]=1, the input reorganization module generates a shift signal SHIFT=1, otherwise SHIFT=0;

[0015] When IN[i+1] is the sign bit, INR=IN[i]|IN[i+1]; wherein the bit weight of INL is 2, and the bit weight of INR is -1.

[0016] Preferably, the hybrid computing unit embedded in each SRAM unit in the SRAM storage and computing array includes two independent computing modules, which are respectively used to calculate the dot product of the left input and the weight, and the dot product of the right input and the weight, to obtain two sets of partial products;

[0017] The computing module for processing the left input is a 3T structure based on transmission logic, including a transmission gate and a grounded NMOS tube. The transmission gate is turned on when the neural network weight is 1, and the input data is transmitted to the split adder tree; the transmission gate is closed when the neural network weight is 0, the NMOS tube is turned on, and the output signal is 0;

[0018] The calculation module for processing the right input is a NOR logic gate, which is calculated by the formula Calculate the right input INR i With weight w i The dot product of .

[0019] Preferably, the split adder trees are respectively located on both sides of the SRAM storage array, including a left adder tree and a right adder tree, and two groups of partial products output by the SRAM storage array are connected to the left adder tree and the right adder tree by cross wiring.

[0020] Preferably, the calculation of the result correction module includes:

[0021] (1) Correcting the sign bit of the right-hand partial sum generated by the sign bit of the input data: When the bit weight of the right-hand input is -1, the right-hand partial sum after the partial product generated by the right-hand input is summed through the split adder tree is negative, and the right-hand partial sum after the sign bit is corrected is obtained; when the bit weight of the right-hand input is not -1, the right-hand partial sum does not need to be corrected;

[0022] (2) Shift the left partial sum by one position and add it to the corrected right partial sum to obtain the middle sum;

[0023] (3) When the input inversion flag signal P=1, determine whether the double-bit input data contains a sign bit. If so, select the weight sum in the negative SRAM storage array minus the intermediate sum to obtain the final intermediate sum result; if not, select the weight sum in the 3 times SRAM storage array minus the intermediate sum to obtain the final intermediate sum result;

[0024] When the input inversion flag signal P = 0, the intermediate sum does not need to be corrected;

[0025] (4) Output the final intermediate sum as the output result of the result correction module.

[0026] Preferably, the sum of the weights in the 3 times SRAM storage array and the negative sum of the weights in the SRAM storage array are pre-calculated and stored in the SRAM storage array.

[0027] Preferably, the uninterrupted accumulator accumulates the intermediate sum output by the result correction module; when the double-bit input data is the highest bit and the second highest bit of a round of multi-bit input data, at the next clock rising edge, the accumulator outputs the accumulation result of the previous round of multi-bit input data, and sets the intermediate accumulation result to zero; and completes the initial accumulation of the intermediate sum of the highest bit and the second highest bit of the current input data within the next clock cycle.

[0028] In a second aspect, the present invention discloses a high-parallel double-bit multiplication-addition calculation method based on the above-mentioned DCIM circuit, comprising the following steps:

[0029] 1) In the weight write mode, multiple groups of multi-bit weights are written into the SRAM storage array by column, and at the same time, the pre-calculated sum of 3 times the weight and the negative sum of the weight are written into the SRAM unit attached to the SRAM storage array;

[0030] 2) In the calculation mode, the input data is input in the manner of highest bit first and double-bit serial input. The input preprocessing module detects the sparsity of a group of multiple double-bit input data. If the sparsity is higher than 50%, the original input data is inverted and the inversion flag signal P is set to 1, otherwise P is set to 0; then, the input data is reorganized into left input and right input, and a shift control signal corresponding to the right input is generated;

[0031] 3) The hybrid computing unit embedded in each SRAM unit in the SRAM storage and computing array calculates two groups of partial products corresponding to the left input and the right input respectively, performs a shift operation on the non-partial products corresponding to the right input according to the shift control signal, and then sums them by the left adder tree and the right adder tree respectively to obtain the left partial sum and the right partial sum;

[0032] 4) The result correction module calculates the two-step correction:

[0033] In the first step, when the bit weight of the right input is -1, the right partial sum is negative; when the bit weight of the right input is not -1, the right partial sum does not need to be corrected;

[0034] Shift the left partial sum by one position and add it to the corrected right partial sum to get the middle sum;

[0035] The second step is to calculate the final intermediate sum result according to the inversion flag signal P:

[0036] When the double-bit input data contains a sign bit, PS2 = -P∑w i +(1-2P)PS1;

[0037] When the double-bit input data does not contain the sign bit, PS2 = 3P∑w i +(1-2P)PS1;

[0038] Among them, PS1 is the intermediate sum, ∑w i is the sum of the neural network weights, and PS2 is the corrected intermediate sum;

[0039] 5) The uninterrupted accumulator accumulates the intermediate sum PS2 calculated from the multi-bit input data. After the highest bit and the second highest bit of the next round of multi-bit input data are input into the DCIM circuit, the accumulator outputs the multiplication and addition result of the previous round of multi-bit input data and the neural network weight at the rising edge of the clock in the next cycle.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] By adopting a dual-bit data parallel computing mode and utilizing an uninterrupted accumulator, the throughput of DCIM operations is significantly improved; by optimizing the features of the input data, including sparse processing and reorganization, the sparsity of the input data is increased and the inversion rate of the input data is greatly reduced, which significantly improves the energy efficiency of DCIM in performing multiplication and addition operations; the present invention has significant advantages in computing energy efficiency and throughput, and can better adapt to the low-power and high-parallel computing needs of edge AI devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the circuit architecture of a DCIM macro circuit provided by the present invention;

[0043] Figure 2 It is a schematic diagram of the principle of input data sparseness and reorganization provided by the present invention;

[0044] Figure 3 is a circuit diagram of the IPM provided by the present invention;

[0045] Figure 4 It is a schematic diagram of the SAT circuit and HSCU circuit structure and the PSUM correction process provided by the present invention;

[0046] Figure 5 The present invention provides a circuit structure and a schematic diagram of a working waveform of a non-stop accumulator. DETAILED DESCRIPTION

[0047] The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment in this application may be combined accordingly without conflicting with each other.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein are only for the purpose of describing the present invention and are not intended to limit the present invention.

[0049] The present invention is further described below in conjunction with the accompanying drawings and specific examples.

[0050] The DCIM circuit of the present invention has multiple identical CIM arrays. Figure 1As shown, in an optional embodiment of the present invention, the DCIM circuit of the present invention includes an input preprocessing module (IPM), 32 CIM arrays, a clock control module, a word line (WL) decoder, a bit line (BL) driver, an input and output cache SRAM, and an input and output serial port (SPI). Each CIM array contains 256×4 hybrid SRAM computing-in-memory units (HSCU), a split adder tree (SAT), a result correction model (RCM), a non-interrupted accumulator, and 7×4 SRAM units for storing weight sums. The SAT includes two split sub-adder trees (ATL and ATR). The word line decoder and the bit line driver control the writing and reading of the neural network weights in the SRAM array, the input SPI writes the serial input neural network input data in parallel to the input cache SRAM, and writes the calculated output results in parallel to the output cache SRAM, the output SPI serially outputs the calculated results read in parallel from the output cache SRAM, and the clock control module uses the external clock signal to generate a control clock signal for controlling the reading and writing of the SRAM. The DCIM circuit of the present invention is applied to the multiplication and addition operation of the neural network input data and the neural network weights, and the weights stored in the SRAM unit are the neural network weights.

[0051] In calculation mode, 256 sets of double-bit input data are transmitted from the input cache SRAM to the input pre-processing module for sparseness and reorganization. The low-sparse input data is bit-inverted and further converted into the left input (input left, INL) and right input (input right, INL) with a lower average inversion rate. HSCU includes two independent calculation modules, which are used to calculate the dot product of INL and the weight, and the dot product of INR and the weight, respectively. After the calculation is completed, two independent sets of partial products are generated. The partial product generated by INR is shifted under the control of the shift signal SHIFT of the input reorganization module. When SHIFT=1, the partial product generated by the corresponding INR is controlled to shift one bit to the left. When SHIFT=0, no shift is required. Two sub-adder trees: the left adder tree (ATL) and the right adder tree (ATR) sum the two sets of partial products respectively and output two partial sums (PSUM) to RCM; RCM corrects the sign bit of the PSUM generated by ATR and shifts the PSUM generated by ATL one bit to the left, and then adds the two processed PSUMs to get the intermediate PSUM. Finally, under the control of the input inversion flag signal P, RCM uses the weighted sum (3 times the weighted sum 3∑w in the SRAM storage array) to calculate the sum of the weights. i or negative SRAM storage array weights -∑w i ) Correct the calculation error caused by input inversion. The sum of the weights in the 3x SRAM storage array and the sum of the weights in the negative SRAM storage array are pre-calculated and written into the SRAM storage array together when writing the weights, and can be used at any time during the calculation process.

[0052] In an optional embodiment of the present invention, the input data sparseness and reorganization principle is as follows: Figure 2 As shown. The principle of input data sparseness is as follows:

[0053] A set of low-sparse original inputs can be converted into a set of all-1 inputs and the difference between the inverted inputs; and the multiplication and addition result of the all-1 inputs and the weights is the sum of the weights. Therefore, the multiplication and addition result of the inverted inputs and the weights can be calculated first, and then the multiplication and addition result of the original inputs and the weights can be obtained by subtracting this result from the sum of the weights. For the non-sign bit of the double-bit input, the sum of the weights should be adjusted to 3 times the sum of the weights; for the double-bit input containing the sign bit, a negative sum of the weights should be used.

[0054] The input reorganization principle is as follows: the input reorganization module reorganizes the original input data into INL and INR through the logical operations of INL=IN[i]&IN[i+1], INR=IN[i]|IN[i+1]. The bit weight of INL is 2, and the bit weight of INR is 1. In the bit serial input mode, standardizing the sparsity characteristics of INL and INR can significantly reduce the average inversion rate of the two groups of inputs. At the same time, the relationship between the input inversion rate and the DCIM power consumption has a logarithmic form, so reducing the inversion rate has a significant effect on reducing power consumption. In addition, in order to ensure the accuracy of the calculation after input reorganization, when IN[i]=0, IN[i+1]=1, the original input data is 2, and it is 1 after reorganization; therefore, the input reorganization module generates a shift signal SHIFT=1 to control the partial product generated by the corresponding INR to shift one bit to the left, and this shift process can be implemented in the shift controller. When IN[i+1] is a sign bit, the encoding method of INL is changed to The bit weight of INL is 2, and the bit weight of INR is -1. The & symbol here represents the AND operation: the result is 1 only when both are 1; the | symbol represents the OR operation: the result is 0 only when both are 0.

[0055] In an optional embodiment of the present invention, the circuit structure of the IPM is as follows: Figure 3 As shown, it includes an input sparsification module and an input reorganization module; wherein the input sparsification module includes an input sparsity detection unit and an input inversion control unit. The input sparsity detection unit includes an input control delay link and a reference delay link composed of buffer delay units, and uses timing information to detect whether the sparsity of the input data is higher than the set threshold. Each delay unit on the delay link is controlled by part of the input data obtained by sampling. The delay chain composed of buffer delay units with adjustable delay has different delays under the control of different input signals; the total delay of the continuous inversion signal DEN in the delay link is negatively correlated with the "1" in the control data. The delay controlled by the input data is obtained by controlling each delay unit on the delay link through 32-bit input data obtained by sampling from the input data. The control signal in the delay link that provides the reference delay has 50% "1" (DEF0, DEF1, ...DEF 30 ,DEF 31 =1,0…1,0). By comparing the two delays, it can be determined whether the delay of the input data is higher than the set threshold (50%). When the sparsity of the input data is lower than 50%, the inversion control signal P is set to 1, and the input inversion control unit completes the inversion of the input data. As shown in the operation waveform, when the sparsity of the sampled 32-bit input data is greater than 50%, the output signal DREF of the 32nd delay unit in the reference delay chain is 31 The output signal DOUT of the 32nd delay unit in the input controlled delay chain will be31 The reference delay link output signal PB0 is fixed to 0. If P0 is pulled high earlier, the reference delay link output signal PB0 is fixed to 0. The enable signal of the output latch is (P0|PB0) & DEN, which ensures that P does not change before the next set of valid input signals arrives.

[0056] The input inversion control unit includes a two-stage inverter (two inverters connected in series) and a 2-to-1 multiplexer. The selection signal of the multiplexer is P. The two input signals of the multiplexer are the outputs of the two-stage inverters. When P=1, the logic function of the input inversion control unit is an inverter. When P=0, the logic function of the input inversion control unit is a buffer. Therefore, when P is 1, the inversion control unit inverts the input data. Otherwise, the input data remains unchanged. Finally, the reorganization module uses AND gates and OR gates to complete the input data reorganization: INL=IN[i]&IN[i+1], INR=IN[i]|IN[i+1], for the sign bit At the same time, a shift control signal SHIFT is output.

[0057] In an optional embodiment of the present invention, the SAT circuit and HSCU circuit structure and PSUM correction process are as follows: Figure 4 As shown. Among them, HSCU embeds two independent computing modules in an SRAM unit, which are used to calculate the dot product of the left input and the weight, and the dot product of the right input and the weight, respectively, to obtain two sets of partial products; the computing module for processing the left input INL is a 3T structure based on transmission logic, including a transmission gate and a grounded NMOS tube. The transmission gate is turned on when the weight is 1, and the input data is transmitted to the split adder tree; the transmission gate is closed when the weight is 0, the NMOS tube is turned on, and the output signal is 0, so as to reduce energy consumption and area overhead without losing voltage. The computing module for processing the right input INR uses a NOR logic gate, through the formula Calculate input INR i With weight w i to ensure the drive shift logic.

[0058] The adder tree is divided into two sub-adder trees, including ATL and ATR. Both adder trees use 28T and 14T full adders in an interleaved arrangement to reduce power consumption. The partial products generated by INL are summed by ATL, while the partial products generated by INR are summed by ATR to obtain two partial sums. Since the sparsity and inversion rates of INL and INR are different, calculating their partial products separately can reduce the energy consumption of the adder tree, where the partial products generated by INR are shifted by the shift controller under the control of the shift control signal SHIFT.

[0059] After the inverted two-bit input data completes the multiplication and addition operation with the weight, an intermediate PSUM is generated. The intermediate PSUM is corrected by pre-calculating and writing the sum of the weights of the SRAM array to obtain an accurate multiplication and addition result. For two-bit input data containing a sign bit, the negative sum of the weights is used to subtract the intermediate PSUM; for two-bit input data not containing a sign bit, the sum of the weights is 3 times the sum of the weights to subtract the intermediate PSUM.

[0060] Specifically, for the sign bit of the input data (when the bit weight of INR is -1), the PSUM calculated by ATR is first converted to its opposite number in the result correction module, and then added to the shifted PSUM of ATL to obtain the intermediate sum PSUM, recorded as PS1. Finally, under the control of the sign bit flag signal (Sign), the result correction module RCM obtains the accurate final sum PSUM through the following formula, recorded as PS2:

[0061] PS2=-P∑w i +(1-2P)PS1

[0062] Wherein, P is the value of the inversion flag signal P of the input data sparsification module;

[0063] For the remaining non-sign bits of the input data (when the bit weight of INR is not -1), the PSUM calculated by ATR is directly added to the shifted PSUM of ATL to obtain the intermediate sum PSUM, recorded as PS1. Finally, under the control of the sign bit flag signal (Sign), the result correction module RCM obtains the precise final sum PSUM through the following formula, recorded as PS2:

[0064] PS2=3P∑w i +(1-2P)PS1

[0065] If P is 0, the input data is not inverted and PSUM does not need to be corrected by the sum of weights.

[0066] In an optional embodiment of the present invention, the uninterrupted accumulator circuit structure is as follows: Figure 5As shown. The uninterrupted accumulator accumulates the PS2 calculated from the multi-bit input data. First, the accumulator extends the sign bit of the input PS2. When the input double-bit data is the highest bit (MSB) and the second highest bit (MSB-1) of a certain round of multi-bit input data, the calculation completion signal is pulled high. At the next rising edge of the clock, the accumulator outputs the accumulation result of the previous round of multi-bit input data, and sets the intermediate accumulation result to zero. The initial accumulation of the PSUM of the highest bit and the second highest bit data of the current input is completed in the next clock cycle. Therefore, unlike the existing accumulator, after completing the accumulation of the PSUM results of a round of input data, the uninterrupted accumulator does not require an additional cycle to output the results of the previous round of calculations and reset the intermediate accumulation state. In an optional embodiment of the present invention, the CIM array supports 4-bit or 8-bit weight modes, such as Figure 4 As shown; in the 4-bit weight mode, after the accumulator calculation is completed, the calculation result is directly output; in the 8-bit mode, the calculation results of the two CIM arrays are shifted and added to obtain the multiplication and addition result in the 8-bit weight mode.

[0067] The steps of implementing the method for parallel computing of dual-bit input data streams using the above energy-efficient DCIM circuit are as follows:

[0068] 1) Multiple groups of double-bit data are input into the IPM from the input buffer SRAM for sparse processing, and the processed data are reorganized into INL and INR again;

[0069] 2) INL and INR are simultaneously input into HSCU, and the 3T calculation module based on the transmission gate and the grounded NMOS completes the dot product of INL and the weight, and the calculation module based on the NOR logic gate completes the dot product of INR and the weight; two sets of independent partial products are generated; for the partial product generated by INR, a shift operation is performed according to the shift control signal, and a shift is required when SHIFT=1, and no shift is required when SHIFT=0;

[0070] 3) The split adder trees located on both sides of the SRAM storage array sum the multiple groups of partial products generated by INL and the multiple groups of partial products generated by INR, respectively, to generate two independent partial sums, including PSUML and PSUMR;

[0071] 4) RCM corrects the sign bit of PSUMR, shifts PSUML one bit to the left and adds it to PSUMR to obtain the intermediate PSUM; then, under the control of the input inversion flag signal P, the intermediate PSUM is corrected using the sum of weights to obtain an accurate multiplication and addition result;

[0072] 5) The non-stop accumulator accumulates the accurate multiplication and addition results calculated from the multi-bit input data. After the highest and second highest bits of the next round of multi-bit input data are input to the DCIM macro, the accumulator outputs the accumulation result of the previous round of multi-bit input data at the rising edge of the next clock cycle, and sets the intermediate accumulation result to zero. The initial accumulation of the PSUM of the highest and second highest bits of the current input data is completed in the next clock cycle.

[0073] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those of ordinary skill in the art, and the general principles defined in this application may be applied to other embodiments without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown in this application, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A DCIM circuit with dual-bit input feature optimization based on SRAM, which is applied to the multiplication and addition operation of neural network input data and neural network weights; It is characterized in that The DCIM circuit adopts a dual-bit data serial computing model: it has an input preprocessing module that supports feature optimization of multiple groups of dual-bit data, an SRAM storage array and a split adder tree that supports dual-bit parallel computing, a result correction module, and an uninterrupted accumulator; The input preprocessing module includes an input data sparseness module and an input reorganization module; The input data sparsification module determines the sparsity of the neural network input data through a delay mechanism, and inverts the input data with low sparsity bit by bit, keeps the input data with high sparsity unchanged, and generates an inversion flag signal; the input reorganization module reorganizes the double-bit input data processed by the input data sparsification module into left input and right input with a lower average inversion rate, and generates a shift control signal; The SRAM storage array pre-calculates and stores the weights of the neural network and the sum of the weights. The hybrid computing unit embedded in each SRAM unit in the SRAM storage array completes the dot product of the left input, the right input and the weight respectively to obtain two groups of partial products; the partial products are shifted according to the shift control signal; the two groups of partial products are summed by a split adder tree divided into two to obtain two partial sums, which are corrected by a result correction module using the sum of the weights stored in the SRAM storage array to calculate the corrected intermediate sum, and then the continuous accumulator completes the accumulation and outputs the final multiplication and addition result.

2. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 1, characterized in that: The input data sparsification module includes an input sparsity detection unit and an input inversion control unit, wherein the input sparsity detection unit includes an input control delay link and a reference delay link composed of a buffer delay unit; sampling of double-bit input data, generating a delay controlled by the sampled input data through the input control delay link, the size of the delay being negatively correlated with the number of "1"s in the sampled input data; setting the input control signal of the reference delay link to have 50% "1"; if the input delay is less than the reference delay, the sparsity of the input data is less than 50%, at which time a corresponding input inversion flag signal P=1 is generated, and the input data is bit-inverted through the input inversion control unit; otherwise P=0, and the input data remains unchanged.

3. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 2, characterized in that: The input inversion control unit includes a two-stage inverter and a 2-to-1 multiplexer, the selection signal of the multiplexer is P, and the two input signals of the multiplexer are the outputs of the two-stage inverters respectively; when P=1, the logic function of the input inversion control unit is an inverter, and when P=0, the logic function of the input inversion control unit is a buffer.

4. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 1, characterized in that: The calculation of the input recombination module includes: When IN[i+1] is a non-sign bit, INL=IN[i]&IN[i+1], INR=IN[i]|IN[i+1], and the original input data is reorganized into a sparser left input INL and a denser right input INR; wherein the bit weight of INL is 2, and the bit weight of INR is 1; and when IN[i]=0, IN[i+1]=1, the input reorganization module generates a shift signal SHIFT=1, otherwise SHIFT=0; When IN[i+1] is the sign bit, INR=IN[i]|IN[i+1]; wherein the bit weight of INL is 2, and the bit weight of INR is -1.

5. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 1, characterized in that: The hybrid computing unit embedded in each SRAM unit in the SRAM storage and computing array includes two independent computing modules, which are respectively used to calculate the dot product of the left input and the weight and the dot product of the right input and the weight to obtain two sets of partial products; The computing module for processing the left input is a 3T structure based on transmission logic, including a transmission gate and a grounded NMOS tube. The transmission gate is turned on when the neural network weight is 1, and the input data is transmitted to the split adder tree; the transmission gate is closed when the neural network weight is 0, the NMOS tube is turned on, and the output signal is 0; The calculation module for processing the right input is a NOR logic gate, which is calculated by the formula Calculate the right input INR i With weight w i The dot product of .

6. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 5, characterized in that: The split adder trees are respectively located on both sides of the SRAM storage array, including a left adder tree and a right adder tree. The two groups of partial products output by the SRAM storage array are connected to the left adder tree and the right adder tree in a cross wiring manner.

7. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 1, characterized in that: The calculation of the result correction module includes: (1) Correcting the sign bit of the right-hand partial sum generated by the sign bit of the input data: When the bit weight of the right-hand input is -1, the right-hand partial sum after the partial product generated by the right-hand input is summed through the split adder tree is negative, and the right-hand partial sum after the sign bit is corrected is obtained; when the bit weight of the right-hand input is not -1, the right-hand partial sum does not need to be corrected; (2) Shift the left partial sum by one position and add it to the corrected right partial sum to obtain the middle sum; (3) When the input inversion flag signal P=1, determine whether the double-bit input data contains a sign bit. If so, select the weight sum in the negative SRAM storage array minus the intermediate sum to obtain the final intermediate sum result; if not, select the weight sum in the 3 times SRAM storage array minus the intermediate sum to obtain the final intermediate sum result; When the input inversion flag signal P = 0, the intermediate sum does not need to be corrected; (4) Output the final intermediate sum as the output result of the result correction module.

8. The DCIM circuit with double-bit input characteristic optimization based on SRAM according to claim 7, characterized in that: The sum of the weights in the 3 times SRAM storage array and the negative sum of the weights in the SRAM storage array are pre-calculated and stored in the SRAM storage array.

9. The DCIM circuit with optimized dual-bit input characteristics based on SRAM according to claim 1, characterized in that: The uninterrupted accumulator accumulates the intermediate sum output by the result correction module; when the double-bit input data is the highest bit and the second highest bit of a certain round of multi-bit input data, at the next clock rising edge, the accumulator outputs the accumulation result of the previous round of multi-bit input data and sets the intermediate accumulation result to zero; and completes the initial accumulation of the intermediate sum of the highest bit and the second highest bit of the current input data within the next clock cycle.

10. A high parallel double-bit multiplication and addition calculation method based on the DCIM circuit according to any one of claims 1 to 9, characterized in that: The following steps are involved: 1) In the weight write mode, multiple groups of multi-bit weights are written into the SRAM storage array by column, and at the same time, the pre-calculated sum of 3 times the weight and the negative sum of the weight are written into the SRAM unit attached to the SRAM storage array; 2) In the calculation mode, the input data is input in the manner of highest bit first and double-bit serial input. The input preprocessing module detects the sparsity of a group of multiple double-bit input data. If the sparsity is higher than 50%, the original input data is inverted and the inversion flag signal P is set to 1, otherwise P is set to 0; Afterwards, the input data is reorganized into a left input and a right input, and a shift control signal corresponding to the right input is generated; 3) The hybrid computing unit embedded in each SRAM unit in the SRAM storage and computing array calculates two groups of partial products corresponding to the left input and the right input respectively, performs a shift operation on the non-partial products corresponding to the right input according to the shift control signal, and then sums them by the left adder tree and the right adder tree respectively to obtain the left partial sum and the right partial sum; 4) The result correction module calculates the two-step correction: In the first step, when the bit weight of the right input is -1, the right partial sum is negative; when the bit weight of the right input is not -1, the right partial sum does not need to be corrected; Shift the left partial sum by one position and add it to the corrected right partial sum to get the middle sum; The second step is to calculate the final intermediate sum result according to the inversion flag signal P: When the double-bit input data contains a sign bit, PS2 = -P∑w i +(1-2P)PS1; When the double-bit input data does not contain the sign bit, PS2=3PΣw i +(1-2P)PS1; Among them, PS1 is the intermediate sum, ∑w i is the sum of the neural network weights, and PS2 is the corrected intermediate sum; 5) The uninterrupted accumulator accumulates the intermediate sum PS2 calculated from the multi-bit input data. After the highest bit and the second highest bit of the next round of multi-bit input data are input into the DCIM circuit, the accumulator outputs the multiplication and addition result of the previous round of multi-bit input data and the neural network weight at the rising edge of the clock in the next cycle.

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