52 results about "Accumulator (computing)" patented technology

The invention discloses a double-bit input characteristic optimized DCIM circuit based on an SRAM, and belongs to the technical field of electronic circuits. Comprising an input preprocessing module, an SRAM (Static Random Access Memory) memory array, a split adder tree, a result correction module and an uninterrupted accumulator, wherein the input preprocessing module is used for supporting feature optimization of multiple groups of double-bit data; the low sparseness input data is inverted to increase sparseness, and the resulting computational errors will be subsequently corrected. And after rarefaction, two groups of input data with lower average inversion rate are recombined. The sparseness can be obviously improved and the inversion rate can be reduced through feature optimization. The hybrid computing unit and the split adder tree embedded in each SRAM unit in the SRAM memory array are used for completing multiplication and addition operation of input data and weights after recombination. The uninterrupted accumulator completes accumulation with a minimum period. The circuit aims at improving the operation energy efficiency and the data throughput of the DCIM architecture for the edge AI equipment.

The invention relates to a near-memory computing device, method and equipment, the device comprises a data arrangement unit, a computing normal form unit and a reconfigurable computing unit, the data arrangement unit is used for continuously storing key vectors corresponding to newly generated texts into preset lines of a memory storage unit, and the computing normal form unit is used for computing the newly generated texts; and / or splitting a value vector corresponding to the newly generated text and then dispersing and storing the value vector into a plurality of storage units of the memory; the calculation normal form unit is used for quoting different calculation normal forms according to different data arrangements of the key cache and the value cache; the reconfigurable calculation unit is used for executing inner product calculation and / or outer product calculation according to different calculation normal forms; the inner product calculation refers to internal accumulation of data read out through an adder tree, and the outer product calculation refers to accumulation of calculation results of matrix data read out multiple times through an accumulator. Therefore, the bandwidth waste in the data preparation stage can be completely eliminated, and the integrated bandwidth of the near memory architecture is fully utilized in the calculation stage.

The invention relates to a digital circuit (10) for calculating a scalar product between two vectors and . The digital circuit comprises a multiplier (11), an accumulator (12) comprising at least one adder (13) and a register (14), as well as a control circuit (15) for the accumulator. At a clock tick of index , the multiplier is configured to calculate the result of the multiplication , and the accumulator is configured to add with the current value of the register. The result of the addition is then stored in the register. The control circuit is configured to control the accumulator so as to perform the addition approximately for at least one addition among the additions of the calculation of the scalar product. The digital circuit is in particular intended to be used in an electronic device implementing a cryptographic algorithm based on a "learning with errors" (LWE) technology. Figure for the abstract: Fig. 1

Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.

Embodiments of the invention provide a memory system, a memory device, and a method of operating the memory device. A memory device includes an encoder circuit, a memory array, and an accumulator circuit. An encoder circuit converts the first bit of each weight to a sign bit according to flag data to generate an encoded weight. The memory array includes memory cells. The memory cells arranged in the same column store bits of encoding weights and flag data having the same index number. The memory array performs an in-memory computation (CIM) operation on the encoding weight and the input to generate a plurality of CIM results. Each of the plurality of CIM results corresponds to a column of the memory array. The accumulator circuit decodes the CIM result according to the flag data to generate a decoded CIM result.

Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

Methods and apparatuses for performing deep learning operations are provided. The computing apparatus includes an adder-tree-based tensor kernel and a multiplier-accumulator (MAC)-based vector kernel. The adder-tree-based tensor kernel is configured to perform tensor operations, and the multiplier-accumulator (MAC)-based vector kernel is configured to perform vector operations using the output of the tensor kernel as input.

A digital circuit for including a scalar product between two vectors (a0, a1, . . . , ai, . . . , aN-1) and (s0, s1, . . . , si, . . . , sN-1). The digital circuit includes a multiplier, an accumulator including at least one adder and a register, as well as a control circuit of the accumulator. At a clock tick of index i, the multiplier is configured to compute the result ri of the multiplication ai×si, and the accumulator is configured to add ri with the current value of the register. Afterwards, the result of the addition is memorised in the register. The control circuit is configured to control the accumulator so as to perform the addition in an approximate manner for at least one addition amongst the N additions of the computation of the scalar product. In particular, the digital circuit is intended to be used in an electronic device implementing a cryptographic algorithm based on a “Learning With Errors” (LWE) technology.

The invention belongs to the technical field of block chains and cloud computing, and provides a data processing task result verification method and system.The data processing task result verification method based on the smart contract comprises the steps that an execution device receives auxiliary information sent by a block chain and responds to decryption operation executed by an executor, and the execution device sends the auxiliary information to the block chain; and processing the CPABE ciphertext based on the decryption operation to obtain a decryption set, calculating according to the decryption set and the auxiliary information to obtain a solution proving set, receiving an accumulator value sent by the block chain by the execution device, responding to a verification operation executed by an executor, performing verification according to the accumulator value and the solution proving set to obtain a verification result, and sending the verification result to the execution device. Therefore, the reliability of the data processing task result is improved.

The invention discloses a multiply-accumulator based on unary calculation, which is characterized by comprising a sequence generation unit, a signal processing unit, a signal processing unit, a signal processing unit, a signal processing unit and a signal processing unit, wherein the sequence generation unit is used for converting a fixed-point decimal between 0 / -1 and 1 into a unary sequence; the unary calculation multiply-accumulate unit is fused with the sequence generation unit; and the probability estimation unit is used for converting a unary calculation result obtained by the unary calculation multiply-accumulate unit back to the fixed-point decimal. The method has the following beneficial effects: a unary sequence generation unit with lower hardware overhead is provided, and the problem that the energy efficiency of unary calculation is reduced in a high-precision scene is solved; a novel low-delay unary calculation multiply-accumulate unit which is high in energy efficiency and can be terminated in advance is provided, and the problem that the energy efficiency of unary calculation is reduced under large-scale calculation is solved.

The embodiment of the application provides a kind of in-memory computing device of parallel vector multiplier-accumulator and electronic equipment, it is related to in-memory computing technical field, can improve the computing speed.The in-memory computing device of parallel vector multiplier-accumulator, comprising: L multiplication module, each multiplication module includes q multiplication unit and an adder, q>1, L>1;Multiplication unit includes memory and multiplication circuit;The adder includes q addition input, the output of the a multiplication unit is electrically connected to the a addition input, a is 1, 2, …, q;Shift accumulator, shift accumulator includes L accumulation input, the output of the b multiplication module is electrically connected to the b accumulation input, b is 1, 2, …, L;Each accumulation input has corresponding weight value, and shift accumulator is used for carrying out shift accumulation calculation based on the weight value corresponding to each accumulation input value of L accumulation input.

The application discloses a double-bit input feature optimization DCIM circuit based on SRAM and belongs to the technical field of electronic circuits. The circuit comprises an input preprocessing module, an SRAM memory and computing array, a split adder tree, a result correction module and an uninterrupted accumulator, supports feature optimization of multiple groups of double-bit data, reverses low-sparse input data to improve sparsity, and corrects calculation errors generated in the subsequent correction. After sparsification, the input data is reorganized into two groups of input data with lower average reversal rate. Feature optimization can significantly improve sparsity and reduce reversal rate. The hybrid computing unit and the split adder tree embedded in each SRAM unit of the SRAM memory and computing array are used to complete the multiplication and addition operation of the reorganized input data and weights. The uninterrupted accumulator completes accumulation in the least period. The circuit aims to improve the operation energy efficiency and data throughput of the DCIM architecture for edge AI devices.

The invention provides a near-memory convolution operation circuit, a convolutional neural network and a chip system. The near storage convolution operation circuit is used for executing multiply-accumulate operation; the digital near storage convolution operation circuit comprises a logic control circuit, a memory array, a register group and a multiply-accumulate calculation unit, the multiply-accumulate calculation unit comprises a multiplier and an accumulator; the memory array comprises a magnetic random access memory sub-array and a static random access memory sub-array; the multiply-accumulate calculation unit is arranged on one side close to the memory array; and the register group is positioned between the multiply-accumulate calculation unit and the memory array.

A memory device may include a memory array, a first computing unit, and a second computing unit. The memory array may include a plurality of memory cells for storing weights for a neural network. The first computing unit may be configured to receive the stored weights from the plurality of memory cells and generate a first partial sum according to the stored weights. The second computing unit may be configured to receive the stored weights from the plurality of memory cells and the first partial sum and generate a second partial sum according to the stored weights and the first partial sum. The second computing unit may be sequentially connected to the first computing unit.

A kind of matrix computing device, method, system, circuit, chip and equipment, compressed format matrix can be directly calculated, so as to improve the computing efficiency of compressed format matrix.Matrix computing device includes: vector outer product processing engine and accumulator, matrix computing device is based on vector outer product and carries out the calculation of compressed format first matrix and second matrix, in the process of calculation, vector outer product processing engine carries out vector outer product calculation to the first column vector of the row coordinate reserved and the second column vector of the column coordinate reserved, then accumulator is based on the index of position coordinate, and the third element value of the same position coordinate is accumulated, to obtain the result matrix of two compressed format matrixes for calculating, relative to the method that compressed format matrix needs to be decompressed first in traditional, then matrix calculation is carried out to the decompressed matrix, the matrix computing device provided in the embodiment of the application can effectively improve the computing efficiency of compressed format matrix.

The invention discloses a convolutional neural network accelerator based on a lookup table and in-memory computation, which comprises an on-chip main memory and a plurality of operation processing units, and is characterized in that each operation processing unit comprises a data preprocessing unit, an in-memory computation array unit, a first summator and an accumulator which are connected in sequence; serial input based on bit feature values is adopted, and an input feature value sequence is compressed; the data preprocessing unit is used for decompressing the compressed feature value sequence and the compressed weight, and matrix multiplication based on a lookup table form is carried out in the in-memory calculation array unit through an in-memory calculation macro module; the first adder is used for adding a first part and a result output by each column of in-memory computing macro-module in the in-memory computing array unit to obtain a second part and a result, and the accumulator is used for calculating the second part and the result to obtain a multiply-accumulate result corresponding to the characteristic value data stream; and high sparseness caused by unstructured pruning can be effectively utilized.

A chiplet-based architecture may quantify or reduce the number of bits at various levels of a data path in an artificial intelligence processor. The architecture may utilize quantizing synergy between multiple dimensions together to greatly reduce memory usage and data path bandwidth. The internal weights may be statically quantified after the training procedure. The accumulator bits and the activation bits may be dynamically quantified during an inference operation. The new hardware logic may be configured to quantify the output of each operation directly from the core or other processing node prior to storing the tensor in the memory. Quantization may use statistics from a previous tensor for a current output tensor while also calculating statistics to be used on a subsequent output tensor. In addition to quantization based on statistics, bits may be further quantized using a Kth percentile truncation operation.

In the field of programmable in-memory computing devices for performing vector-matrix multiplication, an accumulator circuit for a charge-redistribution based vector-matrix multiplier is provided. The accumulator circuit provides column summation output voltages, which are linearized as a function of the capacitances of the matrix memory components associated with the summation charge storage component of a given column, by eliminating a non-linearity caused by the parallel connection of capacitances of the summation charge storage component and its associated matrix memory components in the column.

An ear-mounted device may include a neural network chip. A neural network chip may include a plurality of computing units arranged in a computing unit array, each computing unit including a memory, a plurality of multiply-accumulator circuits (MACs), and a routing circuit. The memory of each computing unit may be configured to store a portion of elements of a matrix A including weights of the neural network. Each computing unit may be configured to receive and store elements of an activation vector X, wherein the activation vector X is derived from an input audio signal. All or a subset of the plurality of computing units may be configured to perform matrix vector multiplication AX by performing multiplication and accumulation sub-operations in parallel between all or a subset of the plurality of computing units. Routing circuitry for computing cells in the array of computing cells may be configured to combine the results of the multiply and accumulate sub-operations.

The invention relates to a data processing method and device in sparse matrix multiplication, equipment and a storage medium. The method comprises the following steps: determining the number of non-zero elements in a processing unit of a first sparse matrix; determining the type of the accumulator according to the number of the non-zero elements; the types of the accumulators comprise a direct index accumulator, a hash accumulator and a dense accumulator; accumulatively summing the product of the number of the non-zero elements in the processing units and the number of the non-zero elements in the corresponding processing units in the second sparse matrix by adopting an accumulator of the type to obtain a sum value; performing intermediate process storage on the sum value; and after performing intermediate process storage on the sum value, inputting the sum value into a third sparse matrix. According to the method, the calculation performance of the SpGEMM is remarkably improved. And the problem of performance bottleneck of the accumulator caused by sparse diversity of the sparse matrix is solved. And a suitable accumulator is dynamically determined for each processing unit in a lightweight manner, so that the problem of non-ideal performance caused by unreasonable design of the accumulators is solved.

This application provides a data processing method, apparatus, chip, device, and storage medium. The apparatus deploys a computing unit array, which includes multiple depthwise separable convolutional computing units. Each depthwise separable convolutional computing unit includes: multiple multiply-accumulate units, multiple intermediate result accumulators, and a multiplexer. The output of each multiply-accumulate unit is connected to the input of an intermediate result accumulator, and the input of the multiplexer is connected to the outputs of both the multiple multiply-accumulate units and the multiple intermediate result accumulators. The multiple multiply-accumulate units perform multiply-accumulate operations on multiple convolutional window data within a single channel of input feature data. The multiple intermediate result accumulators accumulate the intermediate results generated by their respective multiply-accumulate units. The multiplexer selects to output either the result of each multiply-accumulate unit or the accumulated result of each intermediate result accumulator.

An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.

The invention discloses a storage and calculation integrated and physical unclonable function hardware architecture and an implementation method, and the architecture comprises a physical unclonable function generator, an encryption and decryption unit, a voltage-current converter and a multiplication accumulator. The physical unclonable function generator comprises a first memory, a second memory and an SR trigger; the second memory is connected with the multiplication accumulator; the first memory and the second memory are connected with the SR trigger; the first memory, the SR trigger and the voltage-current converter are connected with the encryption and decryption unit; the voltage-current converter is connected with the first memory; wherein the thickness of the free layer of the second memory is different from that of the free layer of the first memory. The circuit can be widely applied to the technical field of electronic circuits.

This neural network circuit includes a convolution operation circuit that performs a convolution operation on input data and a weight. The input data is a tertiary or higher tensor having elements in an x-axis direction, a y-axis direction, and a c-axis direction. The convolution operation circuit includes: a multiplier that multiplies divided input data obtained by dividing the input data by a predetermined number of elements in the c-axis direction and the corresponding weight; and an accumulator circuit that adds multiplication operation results of the multiplier. The accumulator circuit includes a register that records an addition operation result obtained by cumulatively adding the multiplication operation results from the divided input data contiguous in the c-axis direction, and outputs the addition operation result from the divided input data contiguous in the c-axis direction and recorded in the register.

One embodiment provides a computing device for performing machine learning operations, the device comprising: a decoding unit for decoding a single instruction into a decoded instruction that specifies a plurality of operands including an input value and a quantized weight value associated with a neural network; an arithmetic logic unit that includes a barrel shifter, an adder, and an accumulator register, wherein, to execute the decoded instruction, the barrel shifter shifts the input value by the quantized weight value to generate a shifted input value, and the adder adds the shifted input value to the value stored in the accumulator register and updates the value stored in the accumulator register.

The present invention discloses a storage and calculation architecture of a basic linear algebra subroutine and an implementation method thereof, wherein the storage and calculation architecture comprises a plurality of processing engines PE interconnected by an H-tree, each processing engine comprises a plurality of processing units CU interconnected by an H-tree, each processing unit comprises a plurality of arrays, each array comprises a set of input registers and index registers, an index calculation unit, a delay unit and a non-volatile memory-based Crossbar array equipped with a set of peripheral components. The present invention designs corresponding data flows and execution mechanisms for each BLAS function, breaks through the fixed operator limitation of the traditional storage and calculation integrated architecture, expands the potential of the existing peripheral modules, and maps complex operations such as matrix transposition, subtraction and division to shift accumulators without the need for additional module hardware support, which can efficiently meet the needs of scientific computing.

An activation function unit is capable of calculating an activation function calculated by Taylor series approximation. The activation function unit may include a plurality of computing elements. Each computing element may include two multipliers and an accumulator. The first multiplier may calculate an intermediate product using an activation, such as an output activation of the DNN layer. The second multiplier may calculate terms of the Taylor series of the approximate calculation activation function based on the intermediate product from the first multiplier and coefficients of the Taylor series. The accumulator may compute a partial sum of terms as an output of an activation function. The number of terms may be determined based on a predetermined accuracy of the output of the activation function. The activation function unit may process a plurality of activations. Different activations may be input into different computing elements in different clock cycles. The activation function unit can calculate activation functions with different precisions.

The invention discloses a reconfigurable digital filter based on an FPGA (Field Programmable Gate Array), which comprises an FPGA chip, and the FPGA chip comprises an ROM (Read Only Memory) module, an RAM (Random Access Memory) module, a multiplier, an accumulator, a pulse counter, a filtering control module and a reconfiguration interface, the inertial device comprises at least one gyroscope and an accelerometer, and the gyroscope and the accelerometer both output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts count values of the N channels into floating-point numbers after the counting period is ended, and stores the floating-point numbers into the RAM module; the filtering control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, multiplexes the same group of computing resources to process signals of N channels in series, and completes filtering calculation according to an IIR filter algorithm; the reconfiguration interface can adjust the order and coefficient of the IIR filter online. The filter replaces DSP filtering, the FPGA resource utilization rate is increased, the chip cost is reduced, the execution efficiency of an inertial navigation system is improved, and online reconstruction can be carried out to adapt to different filtering requirements.