Multiply-accumulator based on unary calculation

Abstract

The invention discloses a multiply-accumulator based on unary calculation, which is characterized by comprising a sequence generation unit, a signal processing unit, a signal processing unit, a signal processing unit, a signal processing unit and a signal processing unit, wherein the sequence generation unit is used for converting a fixed-point decimal between 0 / -1 and 1 into a unary sequence; the unary calculation multiply-accumulate unit is fused with the sequence generation unit; and the probability estimation unit is used for converting a unary calculation result obtained by the unary calculation multiply-accumulate unit back to the fixed-point decimal. The method has the following beneficial effects: a unary sequence generation unit with lower hardware overhead is provided, and the problem that the energy efficiency of unary calculation is reduced in a high-precision scene is solved; a novel low-delay unary calculation multiply-accumulate unit which is high in energy efficiency and can be terminated in advance is provided, and the problem that the energy efficiency of unary calculation is reduced under large-scale calculation is solved.

Description

Technical Field

[0001] The present invention relates to an approximate multiplication and accumulation device based on unary calculation, belonging to the technical field of high-performance and high-energy-efficiency calculation. Background Art

[0002] Applications such as scientific computing and machine learning models require numerous matrix multiplications. Traditional methods often use floating-point and integer operations, which typically consume considerable time and energy. As the complexity of the problems increases, these negative effects become increasingly pronounced. Unary computing, which uses a serial sequence of 0s and 1s to implement the most basic multiplication-accumulation function in these matrix multiplications, significantly reduces energy and hardware overhead by processing single bits in a simple manner.

[0003] In unary calculation, a fixed arrangement of 0 / 1 serial sequences is used to represent numerical values, and the numerical value is the same as the ratio of 1 in the sequence. By taking advantage of this feature, simple logic gates can be used to implement complex functions by bitwise operations. For example, an AND gate can be used to implement unary calculation multiplication. When two sequences are independent of each other, according to the principle of probability theory, the probability of 1 in the result sequence after AND is the product of the probabilities of 1 in the two input sequences. Although the calculation circuit is simple, the current unary calculation is limited by the calculation accuracy and the problem of adapting to the data expression format of the traditional computing system. The accuracy of unary calculation is related to the length of the 0 / 1 sequence, so it often takes a lot of time to perform high-precision calculations; in addition, in order to be compatible with the current computing system, before performing unary calculations, the original data needs to be converted into unary sequence encoding, and after the calculation, the result needs to be converted back to the traditional data expression format. The following literature [1], [2], [3], [4] proposed some optimization methods to solve the corresponding problems, but there are still problems such as high conversion overhead or limited application areas.

[0004] Reference [1] Ren Yifan, Peng Xiaofeng, Xiong Haifei, Ju Chunhui, Li Jun, Zhou Gongming, et al. A random calculator based on Sobol random numbers. CN Patent CN117270815B, filed Aug 22, 2023, and issued Oct 29, 2024. A unary sequence conversion unit based on Sobol sequence is proposed. Compared with the Sobol sequence conversion unit based on storage direction vector, it uses the Sobol random number one-hot encoding form and replaces a large number of AND gate arrays with addition and selectors to reduce hardware overhead. However, the disadvantage is that a complex finite state machine is required. In addition, random multiplication requires two independent random number generators, and this design still has the problem of large hardware overhead when multiple independent random number sources are required.

[0005] Reference [2] "Sim H, Lee JA New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks [C]. ACM, 2017.". A counter-based early termination mechanism for random multiplication and a finite state machine-based unary sequence conversion unit are proposed. The work shows that in the dual sequences of random calculations, all 1s in one sequence can be sorted to the front of the sequence without affecting the accuracy of the random calculation. Based on this, the generation unit of one set of unary sequences can be simplified and optimized to use a counter to control the counting of the number of random bits generated by the other set of unary sequences. However, a large amount of hardware overhead is still required when multiple random number sources are required.

[0006] Reference [3] "Wu D, Li J, Yin R, et al. uGEMM: unary computing architecture for GEMM applications [C] / / ACM / IEEE 47th Annual International Symposium on Computer Architecture (ISCA). ACM, 2020." A unary computing universal matrix multiplication unit architecture is proposed. The bit value of one set of unary sequences is used as the enable signal to turn on another set of unary sequence conversion units. Based on this, the number of unary sequence conversion units required in a universal matrix multiplication is significantly reduced. However, this work did not propose optimization of the unary sequence conversion unit, so the hardware overhead is still large and the running time is long.

[0007] Reference [4] "Nair H, Vellaisamy P, Chen A, et al. tuGEMM: Area-Power-EfficientTemporal Unary GEMM Architecture for Low-Precision Edge AI[J]. IEEE, 2024.". A unary general matrix multiplication unit architecture with a reordering coding method is proposed. By performing AND operations on all bits in the unary sequence participating in the multiplication calculation, the accurate result is obtained by full combination accumulation. However, the disadvantage of this work is the large delay caused by the need to generate the unary sequence bits serially and perform full combination AND operations. The time required for this architecture to perform a multiplication calculation increases quadratically with the length of the unary sequence, and higher accuracy is achieved by sacrificing delay time. Summary of the Invention

[0008] The technical problem to be solved by the present invention is that the traditional unary matrix operation circuit has low calculation accuracy and large conversion overhead.

[0009] In order to solve the above technical problems, the technical solution of the present invention is to provide a multiplication and accumulation device based on unary calculation, which is characterized by comprising:

[0010] A sequence generation unit that converts a fixed-point decimal between 0 / -1 and 1 into a unary sequence;

[0011] Unary multiplication and accumulation unit implemented by fusion with sequence generation unit;

[0012] A probability estimation unit that converts the unary calculation result obtained by the unary calculation multiplication and accumulation unit back into a fixed-point fraction.

[0013] Preferably, the unary sequence generation unit includes a random number generator capable of simultaneously generating a two-dimensional Hammersley sequence, the random number generator including only one counter (since the second-dimensional random number is generated by inverting the first dimension, a shared incrementing counter is used for generation), wherein:

[0014] (1) When generating the first-dimensional sequence, the counter generates the first-dimensional random number. The valid bits of the corresponding generated unary sequence are at the front. Therefore, this feature can be used to skip the subsequent invalid bit 0 operation to terminate early.

[0015] (2) When generating the second-dimensional sequence, a bit order reversal operation is performed through additional wiring, so that the second-dimensional sequence is generated by reversing the bits of the first-dimensional sequence and comparing it with the second multiplier.

[0016] Preferably, for a number of N Hammersley sequences, the first-dimensional sequence is generated by Hammersley[i]=i / N, and the second-dimensional sequence is generated by the formula Produced, where i is a non-negative integer, It is the binary inverted form of i.

[0017] Preferably, the traditional unary calculation obtains the proportion of 1s in the two sequences as an estimate of the product by bitwise AND. Since the logical result of 1 and any bit is the bit itself, the logical result of 0 and any bit is 0. Therefore, during unary multiplication, 0 has no effect on the result, while the unary bit ANDed with 1 retains its own value. According to this principle, the multiplication operation of two columns of unary calculation sequences can be simplified to selecting the bits of the second unary calculation sequence according to the first unary calculation sequence. The unary calculation sequence corresponding to the first multiplier in the unary sequence generation unit preferentially generates X 1s, and the first X bits in the other operand sequence will be selected as the result after the sequence is bitwise ANDed, and then the probability estimation unit will count the number of 1s to obtain an estimate of the operation result. If more pairs of data need to be multiplied and accumulated, the data are input in order and the above process is repeated. Therefore, the steps when the unary calculation multiplication and accumulation unit is executed are as follows:

[0018] Step S1: Generate a first-dimensional Hammersley sequence, and obtain a second-dimensional Hammersley sequence by reversing the binary form of the first-dimensional Hammersley sequence;

[0019] Step S2: generating a unary calculation sequence corresponding to the second multiplier based on the second-dimensional Hammersley sequence comparison, and determining whether generation of valid bit 1 has ended based on the first-dimensional Hammersley sequence, and terminating the bitwise AND operation;

[0020] Step S3: When the generation is completed, the corresponding unary sequence is passed to the probability estimator as the unary multiplication result to count the number of 1s and accumulate it with the result of the previous operand pair;

[0021] If there are more operand pairs that need to be multiplied and accumulated, steps S1 to S3 are repeated.

[0022] Preferably, the effective bits of the counter when generating the first-dimensional Hammersley sequence are determined by the size of the first multiplier (ie, the operand). The count value is terminated when it reaches the first multiplier, thus completing the multiplication calculation of the random field.

[0023] Preferably, a scaling unit for improving calculation accuracy is also included.

[0024] Preferably, the scaling unit includes an input adjustment unit for amplifying the second multiplier binary number and an output adjustment unit for reducing the result binary number output by the probability estimation unit:

[0025] The input adjustment unit includes a leading 1 detector and a left shift operation, wherein the leading 1 detector detects the position of the most significant 1 of the second multiplier and amplifies it through the left shift operation;

[0026] The output adjustment unit implements the right shift operation, shifting the output result binary right by the same number of bits to achieve output reduction.

[0027] The present invention provides a unary multiply-accumulator with low hardware overhead, high energy efficiency, and high precision. The solution employed in the present invention generates random numbers based on a Hammerley low-discrepancy sequence and implements multiplication-accumulation operations through counting. The disclosed unary multiply-accumulator can use a unary sequence to calculate the multiplication and accumulation of decimals between 0(-1) and 1. To handle negative numbers, an additional sign bit can be used to indicate their positive or negative nature.

[0028] Compared with the existing technical solutions, the present invention has the following beneficial effects:

[0029] 1. A unary sequence generation unit with lower hardware overhead is proposed to address the energy efficiency degradation problem of unary computing in high-precision scenarios.

[0030] 2. A new type of unary computing multiplication and accumulation unit with high energy efficiency, early termination and low latency is proposed to solve the problem of reduced energy efficiency of unary computing under large-scale computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of traditional unary computing, where (a) is the structure diagram of the unary computing system, (b) is the traditional structure diagram of the unary sequence generation unit, (c) is the structure diagram of the unary computing multiplication unit, and (d) is the structure diagram of the probability estimation unit.

[0032] Figure 2 This is a schematic diagram of the structure of a double-sequence random number generation unit based on Hammersley random numbers with 4-bit accuracy;

[0033] Figure 3 This is a diagram showing the regularity of two columns of Hammersley random numbers with 3-bit precision;

[0034] Figure 4 This is the architecture diagram of the new unary multiplication and accumulation unit with signed bit under 4-bit precision;

[0035] Figure 5 This is an example of a vector multiplication-accumulation (vector inner product) operation based on Hammersley random numbers with 3-bit precision. DETAILED DESCRIPTION

[0036] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0037] The embodiment of the present invention discloses a unary computing multiplication-accumulation unit based on Hammersley random numbers, which can be used for matrix multiplication operations and floating-point number mantissa multiplication processing, and can cooperate with other modules to achieve high-energy-efficiency and high-performance unary computing.

[0038] like Figure 2 As shown, the dual-sequence random number generating unit proposed in this embodiment has the following characteristics.

[0039] The random number generating unit is composed of an n-bit counter and a bit sequence inversion circuit. When the counter is incremented in base 2 form, its count value is used as the first-dimensional Hammersley sequence ( Figure 2 For example, a 3-bit counter (n=3) generates (0.000)² to (0.111)² when counting from 0 to 7.

[0040] Figure 3 This is a diagram showing the regularity of two columns of Hammersley random numbers with 3-bit precision. Figure 3 As shown in Figure 2, the second-dimensional Hammersley sequence forms a quasi-random distribution by reversing the bit order. A counter is used to generate two-dimensional Hammersley random numbers.

[0041] The Hammersley sequence can also be generated in parallel. The specific method is to directly pad the lowest bit of the counter with 1 to obtain odd-numbered Hammersley sequence index values, and to pad the lowest bit with 0 to obtain even-numbered Hammersley sequence index values. In this case, an n-bit counter can generate a Hammersley sequence of length 2(n+1). By padding more 0 / 1 bits, a higher degree of parallelism can be achieved.

[0042] Figure 4 This is the principle diagram of the new unary multiplication and accumulation unit with a signed bit under 4-bit precision. Figure 4 As shown, this implementation has the following optimization details.

[0043] The core of the scaling unit (optional) used to improve accuracy in this embodiment is the leading 1 detector ( Figure 4 The leading 1 detector locates the first significant 1 bit of the second multiplier (x in the figure) and then performs a left shift operation to amplify the second multiplier until the most significant digit aligns with the decimal point. For example, the input (0.0011)² is detected by the leading 1 detector and left-shifted by 3 bits to obtain (0.1100)².

[0044] By generating a unary calculation sequence encoded by the second multiplier, this embodiment can directly obtain the unary calculation multiplication result. Specifically, in unary calculation, the essence of the multiplication operation is to perform a one-to-one bitwise logical AND on two unary calculation sequences. The pre-truncated unary calculation sequence generated by the first-dimensional Hammersley sequence only contains one valid bit, so the calculation result sequence after the AND operation is the corresponding truncated unary sequence itself.

[0045] The resulting unary sequence is accumulated through a counter to obtain a fixed-point binary representation of the result. Since the second multiplier is amplified by the number of bits shifted left in the above details, to ensure that the final result is not affected by this input adjustment, the final binary result needs to be right-shifted by the same number of bits. The principle of improving accuracy of the scaling unit is based on actual measurements: when the Hammersley sequence is used to generate near-zero data, there is a significant loss of accuracy. Therefore, by scaling the multiplier away from the near-zero region, the accuracy can be significantly improved.

[0046] The multiplication-accumulation calculation can be completed by using the data in the accumulation counter (ie, the probability estimator). This embodiment can complete the multiplication-accumulation calculation without increasing the hardware overhead.

[0047] For the sign bit, the XOR method is used for calculation. And the counter used to accumulate the result unary sequence is adjusted according to the output, effectively completing the positive and negative accumulation.

[0048] Implementation Example 1: Double-sequence random number generation unit based on Hammersley random numbers

[0049] The counter increments each cycle until it reaches the first multiplier. For example, with 3-bit precision and a first multiplier of 0.625, the counter's count value sequentially generates the first five samples of the first-dimensional Hammersley sequence (i = 0 to 4). This count value satisfies the requirement of being less than the first multiplier, corresponding to a valid bit. The remaining three bits can be terminated early and not participate in the generation. This counter-based dynamic truncation mechanism optimizes the unary computation sequence generation cycle from a fixed 8 clock cycles to a dynamic 5 clock cycles.

[0050] At the same time, the second-dimensional Hammersley sequence is directly obtained by reversing the order of the count values ​​of the counter, and only the first five samples are obtained.

[0051] In this way, this embodiment can use only one counter to generate the required unary calculation sequence, greatly reducing hardware overhead.

[0052] Implementation Example 2: New Unary Multiply-Accumulate Unit Based on Hammersley

[0053] This embodiment can directly complete the calculation of vector inner products (multiplication and accumulation operations of multiple pairs of data).

[0054] Figure 5 This is an example of a vector inner product operation based on Hammersley random numbers with 3-bit precision. Figure 5 The vector dot product calculation scenario shown in the figure specifically implements a multiply-accumulate operation based on the Hammersley sequence. As shown in the figure, the inner product of the input vectors [0.5, 0.625] and [0.625, 0.25] is a1b1+a2b2. Each product term is completed through the scaling unit, Hammersley sequence generator, and probability estimator, ultimately achieving high-precision and low-overhead calculations at the hardware level.

[0055] Specifically, the first-dimensional Hammersley sequence A[i] corresponding to a1 and a2 is generated using a counter to control when each pair of operand multiplication ends. The second-dimensional Hammersley sequence B is generated by bit-inverting A. Since the decimal value corresponding to a1 is (0.100)2, the count starts from (0.000)2 and ends at (0.011)2. Figure 5 The decimal point and the 0 digits before the decimal point are omitted. At the same time, the binary decimal digit corresponding to b1=0.625 is (0.101)2. No shift processing is required. The unary calculation sequence is directly generated based on the second-dimensional Hammersley sequence comparison and truncated to 4 digits, that is, 1110. The number of 1s in it is counted and normalized to obtain the binary result (0.011)2, which is the product estimate of a1b1 and is placed in the probability estimator ( Figure 4 The counter on the right side is then loaded. The second set of operands, a2 and b2, are then loaded. Similarly, a2 is counted from (0.000)2 to (0.100)2 and then stopped, corresponding to the first five bits of the unary sequence of b2 being intercepted. Since increasing the precision of b2 requires shifting it left by 1 bit and generating the corresponding sequence, the resulting sequence is 10101, which corresponds to counting the number of 1s and shifting it right by 1 bit, resulting in an estimate of the multiplication result of the second set of operands (0.0011)2. The probability estimator accumulates the previous result (0.011)2 to obtain the final result (0.1001)2. The result is consistent with the correct calculation result. If there are scenarios where precision is not a high requirement, the left and right shift operations corresponding to the second set of operands can be omitted. If there are more sets of operands to perform multiplication and accumulation operations, the previous steps are repeated.

[0056] Through the above method, a large number of unary sequence generation units and AND gate calculation units in large-scale unary calculations will be greatly reduced. When using a highly parallel architecture, the unary multiplication and accumulation units can even be further reused, so that the unary matrix multiplication operation can still maintain high energy efficiency and high precision while further reducing latency.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and additions without departing from the principles of the present invention, and these improvements and additions should also be considered as the scope of protection of the present invention.

Claims

1. A multiplication and accumulation device based on unary calculation, characterized in that: include: A sequence generation unit that converts a fixed-point decimal between 0 / -1 and 1 into a unary sequence; Unary multiplication and accumulation unit implemented by fusion with sequence generation unit; A probability estimation unit that converts the unary calculation result obtained by the unary calculation multiplication and accumulation unit back into a fixed-point fraction.

2. A multiplication and accumulation device based on unary calculation as claimed in claim 1, characterized in that: The unary sequence generation unit includes a random number generator capable of generating two-dimensional Hammersley sequences simultaneously, wherein the random number generator only includes a counter, wherein (1) When generating the first-dimensional sequence, the counter generates the first-dimensional random number. The valid bits of the corresponding generated unary sequence are at the front. Therefore, this feature can be used to skip the subsequent invalid bit 0 operation to terminate early. (2) When generating the second-dimensional sequence, a bit order reversal operation is performed through additional wiring, so that the second-dimensional sequence is generated by reversing the bits of the first-dimensional sequence and comparing it with the second multiplier.

3. A multiplication and accumulation device based on unary calculation as claimed in claim 1, characterized in that: For a Hammersley sequence with a number of N, the first-dimensional sequence is generated by Hammersley[i]=i / N, and the second-dimensional sequence is generated by the formula Produced, where i is a non-negative integer, It is the binary inverted form of i.

4. A multiplication and accumulation device based on unary calculation as claimed in claim 3, characterized in that: The steps of executing the unary multiplication and accumulation unit are as follows: Step S1: Generate a first-dimensional Hammersley sequence, and obtain a second-dimensional Hammersley sequence by reversing the binary form of the first-dimensional Hammersley sequence; Step S2: generating a unary calculation sequence corresponding to the second multiplier based on the second-dimensional Hammersley sequence comparison, and determining whether generation of valid bit 1 has ended based on the first-dimensional Hammersley sequence, and terminating the bitwise AND operation; Step S3: When the generation is completed, the corresponding unary sequence is passed to the probability estimator as the unary multiplication result to count the number of 1s and accumulate it with the result of the previous operand pair; If there are more operand pairs that need to be multiplied and accumulated, steps S1 to S3 are repeated.

5. A multiplication and accumulation device based on unary calculation as claimed in claim 4, characterized in that: The effective bit position of the counter when generating the first-dimensional Hammersley sequence is determined by the size of the first multiplier. The counter is terminated when the count value reaches the size of the first multiplier, and the multiplication calculation of the random field is completed.

6. A multiplication and accumulation device based on unary calculation as claimed in claim 1, characterized in that: A scaling unit is also included to improve computational accuracy.

7. A multiplication and accumulation device based on unary calculation as claimed in claim 6, characterized in that: The scaling unit includes an input adjustment unit for amplifying the second multiplier binary number and an output adjustment unit for reducing the result binary number output by the probability estimation unit. The input adjustment unit includes a leading 1 detector and a left shift operation, wherein the leading 1 detector detects the position of the most significant 1 of the second multiplier and amplifies it through the left shift operation; The output adjustment unit implements the right shift operation, shifting the output result binary right by the same number of bits to achieve output reduction.

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