A method for loading, refreshing and on-orbit reconfiguration of FPGA in a real-time information processing system on board a satellite

Abstract

This invention, belonging to the field of onboard intelligent information processing, discloses a method for loading, refreshing, and on-orbit reconfiguration of an FPGA in an onboard real-time information processing system. The system comprises five components: a power supply unit, a measurement and control and configuration management unit, an interface unit, an image processing unit, and a busbar backplane. For an onboard real-time information processing system based on a dynamic redundant architecture, this method proposes a parallel architecture that combines a configuration management FPGA with Nor Flash, NAND Flash, SDRAM memory, and multiple SRAM-based FPGAs. This allows for simultaneous loading and refreshing of multiple SRAM-based FPGAs, improving loading efficiency, shortening on-orbit reconfiguration time, addressing potential hidden path risks in the system, streamlining system size, and improving system cost-effectiveness.

Description

Technical Field

[0001] The present invention relates to the field of on-board intelligent information processing, and in particular to a method for FPGA loading, refreshing and on-orbit reconstruction in an on-board real-time information processing system. Background Art

[0002] With the rapid advancement of aerospace technology, satellites are increasingly being designed for low cost, low weight, and low power consumption. This poses new challenges for onboard real-time information processing technology. Onboard real-time information processing systems based on a dynamic redundant architecture can meet the demands of high throughput, large data processing capabilities, and high reliability while also maintaining low system costs. SRAM-based FPGAs, with their abundant resources, excellent performance, and reprogrammability, have been widely used in onboard real-time information processing systems. To cope with the complex environment of space, an SRAM-based FPGA typically requires a refresh chip, which is coupled with two external Nor Flash memory chips to enable loading, refreshing, and on-orbit reconfiguration of FPGA configuration items. The entire processing system requires 4n Nor Flash chips. As is well known, the unit price of aerospace-grade Nor Flash is around 100,000 yuan. If the entire system requires 40 Nor Flash chips, the cost of these chips alone exceeds 4 million yuan. Furthermore, complex detection processing for high-throughput, large-field-of-view images inevitably requires block-based processing. Consequently, multiple image processing units on the FPGA share pre-detection configuration items. Therefore, the conventional FPGA-plus-refresh chip and Nor Flash approach wastes resources. Furthermore, the radiation-hardened readback and refresh chip typically has a communication rate of only 115,200 bits per second, which slows down the writing of the upload software to its external Nor Flash memory, occupies the fast upload channel for a long time, and affects other satellite operations. Therefore, developing a low-cost SRAM-based FPGA with fast loading, refreshing, and on-orbit reconfiguration time is extremely important. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides a method for FPGA loading, refreshing and on-orbit reconstruction in an on-board real-time information processing system. For the on-board real-time information processing system based on a dynamic redundant architecture, it is proposed to configure and manage FPGA in combination with Nor Flash, NAND Flash, SDRAM memory and a parallel architecture of multiple SRAM-type FPGAs, so as to realize simultaneous loading and refreshing of multiple SRAM-type FPGAs, improve loading efficiency, shorten on-orbit reconstruction time, solve potential hidden dangers of potential paths in the system, streamline the system scale, and improve system cost-effectiveness.

[0004] The present invention provides a satellite real-time information processing system, which comprises five parts: a power supply unit, a measurement, control and configuration management unit, an interface unit, an image processing unit and a busbar backplane.

[0005] Preferably, the measurement, control and configuration management unit includes: an RS422 receiver, a measurement, control and data transmission FPGA, a readback refresh chip, Nor Flash, NAND Flash, SDRAM, and a configuration management FPGA;

[0006] The image processing unit includes: multiple image processing unit FPGAs;

[0007] The RS422 receiver is used to receive the fast uplink data sent by the satellite, and transmit the received uplink data to the measurement and control and data transmission FPGA for on-orbit reconstruction and upgrading;

[0008] The measurement, control and data transmission FPGA is used to receive the fast injection data from the RS422 receiver and send the fast injection data to the configuration management FPGA; it is also used to receive the fast injection data from the RS422 receiver and control the readback refresh chip to store the fast injection data in the Nor Flash plug-in of the readback refresh chip to realize the on-orbit reconstruction of the configuration management FPGA; it is also used to directly control the readback refresh chip to realize the loading and refreshing of the configuration management FPGA;

[0009] The readback refresh chip is used to load and regularly refresh the configuration item software stored in the Nor Flash to the configuration management FPGA through the SelectMAP interface under the control of the measurement and control and data transmission FPGA. At the same time, it can also receive fast injection data, perform read and write operations on the external Nor Flash, and store new configuration item software;

[0010] The Nor Flash is used to store the underlying software configuration items required for normal operation on the satellite;

[0011] The NAND Flash serves as a backup for the Nor Flash and is responsible for storing some configuration items.

[0012] The SDRAM is used for caching fast data for on-track reconstruction;

[0013] The configuration management FPGA is used to simultaneously load and refresh different configuration item software in multiple external Nor Flash chips to multiple image processing unit FPGAs through the SelectMAP interface, and the loaded configuration items and the number of loaded image processing unit FPGAs are arbitrarily combined; it is also used to receive fast injection data and update the configuration items stored in the external Nor Flash and NAND Flash; it is also used to store the injection data in SDRAM;

[0014] The image processing unit FPGA is used to receive configuration item software data of the configuration management FPGA through the SelectMAP interface and run the corresponding configuration item function.

[0015] The present invention also provides an FPGA loading method in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The loading method includes:

[0016] Step 1: After the 42V bus is connected, the measurement and control and data transmission FPGA work normally;

[0017] Step 2: The measurement and control and data transmission FPGA controls the readback refresh chip through the UART interface, and loads the configuration item software in the main Nor Flash plug-in of the readback refresh chip into the configuration management FPGA through the SelectMAP interface;

[0018] Step 3: The successfully loaded configuration management FPGA starts to work normally, and loads the configuration item software stored in the external Nor Flash to each image processing unit FPGA through the SelectMAP interface;

[0019] Step 4: After the FPGA of each image processing unit is loaded normally, the entire system starts to execute the corresponding task.

[0020] Preferably, in step 3, the successfully loaded configuration management FPGA starts to work normally, and the configuration item software stored in the external NorFlash is loaded into each image processing unit FPGA through the SelectMAP interface, including:

[0021] Step 3.1: Simultaneously load multiple image processing unit FPGAs by configuring the management FPGA with multiple external Nor Flash memories.

[0022] In step 3.2, the number of Nor Flashes required by the system has no correlation with the number of image processing unit FPGAs, but only with the number of configuration items of the system image processing unit FPGA;

[0023] In step 3.3, any image processing unit FPGA can load any one of the m configuration item software stored in Nor Flash 1 to Nor Flash m, that is, there is no one-to-one correspondence between the image processing unit FPGA and the configuration item.

[0024] The present invention also provides a method for refreshing an FPGA in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The refreshing method includes:

[0025] Step 1: After the loading process is completed, the system starts to work normally. The readback refresh chip reads the software configuration items in the Nor Flash master and the software loaded in the configuration register of the configuration management FPGA back to the refresh chip for comparison;

[0026] Step 2: The configuration item software loaded by the configuration management FPGA instantiates multiple modules with readback and refresh functions, which can read back m configuration items into the configuration management FPGA, and at the same time read back the successfully loaded image processing unit configuration items and verify them one by one.

[0027] Preferably, in step 1, after the loading process is completed, the system starts to work normally, and the readback refresh chip reads back the software configuration items in the NorFlash master and the software loaded in the configuration register of the configuration management FPGA into the refresh chip for comparison, including:

[0028] Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds;

[0029] In step 1.2, if an exception is found, repeat step 2 of the loading process to reload the software configuration items in the Nor Flash into the configuration management FPGA. After the reload is successful, repeat step 1.

[0030] Preferably, in step 2, the configuration item software loaded by the configuration management FPGA instantiates multiple modules with readback refresh function, which can read back m configuration items into the configuration management FPGA, and simultaneously read back the successfully loaded image processing unit configuration items and verify them one by one, including:

[0031] In step 2.1, if no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds;

[0032] In step 2.2, if an abnormality is found, repeat step 2 of the loading process to reload the software configuration items in the Nor Flash corresponding to the image processing unit FPGA with the abnormality into the corresponding image processing unit FPGA. After the reload is successful, repeat step 1.

[0033] The present invention also provides an on-orbit FPGA reconfiguration method in an on-board real-time information processing system, which is implemented by applying the on-board real-time information processing system. The on-orbit reconfiguration method includes:

[0034] Step 1: The measurement, control and data transmission FPGA receives the fast uplink data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps;

[0035] Step 2: After receiving the fast upload data and the corresponding upload instruction, the measurement and control and data transmission FPGA makes a judgment: if the corresponding configuration item of the configuration management FPGA needs to be reconfigured on-orbit, proceed to step 3; if the configuration item of the image processing unit FPGA needs to be reconfigured on-orbit, proceed to step 6;

[0036] Step 3: The measurement and control and data transmission FPGA sends the received injection software data to the data read-back refresh chip through the UART interface, with a baud rate of 115200;

[0037] Step 4: The readback refresh chip writes the software data into the external Nor Flash, and writes it into the main Nor Flash or the backup Nor Flash according to the instruction requirements;

[0038] Step 5: The readback refresh chip reads the software data from the written Nor Flash and reloads it into the configuration management FPGA through the SelectMAP interface. After the reload is successful, the refresh step 1 is performed again.

[0039] Step 6: The measurement, control and data transmission FPGA forwards the received fast injection data to the configuration management FPGA at a communication rate of 20Mbps.

[0040] Step 7: After receiving the fast injection data, the configuration management FPGA can write the injection data into three different memories: Nor Flash, NAND Flash or SDRAM through instructions;

[0041] Step 8: The configuration management FPGA reads the software data from the written SDRAM and reloads the specific image processing unit FPGA through the SelectMAP interface. After reloading, the system function test is performed. If the test meets the requirements, the software data in the SDRAM is written to the Nor Flash or NAND Flash.

[0042] Step 9: The configuration management FPGA reads the software data from the written Nor Flash and reloads the specific image processing unit FPGA through the SelectMAP interface. After the reload is successful, the refresh step 2 is performed.

[0043] Step 10: The configuration management FPGA reads the software data from the written NAND Flash and reloads the specific image processing unit FPGA through the SelectMAP interface. After the reload is successful, the refresh step 2 is performed.

[0044] Preferably, in step 7, after receiving the fast injection data, the configuration management FPGA can write the injection data into three different memories, namely, Nor Flash, NAND Flash or SDRAM, through instructions.

[0045] Step 7.1: According to the instruction, the data is quickly written into the Nor Flash at a rate of about 12.5kbps.

[0046] In step 7.2, the configuration management FPGA writes the fast injection data into the NAND Flash, which serves as a backup for the NorFlash, and then proceeds to step 9.

[0047] In step 7.3, the configuration management FPGA writes the fast upload data into the SDRAM, and the SDRAM write rate is up to 80Mbps.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] (1) Compared with the traditional solution of one SRAM-type FPGA with one refresh chip and two NOR Flashes, the present invention adopts a configuration management FPGA with a multi-processor parallel architecture, which reduces the number of system refresh chips and NOR Flashes used, and significantly improves the cost-effectiveness.

[0050] (2) There is no binding relationship between the SRAM-type FPGA and the Nor Flash that stores configuration items. The number of loaded FPGAs and software configuration items can be switched arbitrarily according to instructions, making the system more flexible and convenient. It has good expansion capabilities. If the processing power needs to be further improved after being in orbit, more processing units can be activated for expansion.

[0051] (3) Using SDRAM to cache data quickly and further shorten the on-orbit reconstruction time;

[0052] (4) Through the design of multiple bidirectional transceivers and peripheral hardware circuits, the risks of crosstalk and sneak paths that may exist in the SelectMAP interface between the active and standby configuration management FPGAs and the SRAM-type FPGAs in the processing unit in the dynamic redundant architecture are resolved. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1This is a block diagram of the principles of SRAM-type FPGA loading, refreshing, and on-orbit reconstruction in the onboard real-time information processing system of an embodiment of the present invention;

[0055] Figure 2 This is a hardware schematic diagram of the SelectMAP interface implemented in the onboard real-time information processing system based on the cold standby solution according to an embodiment of the present invention;

[0056] Figure 3 This is a hardware schematic diagram of the SelectMAP interface implemented in the onboard real-time information processing system based on the dynamic redundant backup solution according to an embodiment of the present invention.

[0057] Description of the accompanying drawings: 100—measurement, control and configuration management unit, 200—image processing unit, 300—bus backplane, 110—RS422 receiver, 120—measurement, control and data transmission FPGA, 130—readback refresh chip, 140—Nor Flash, 150—NAND Flash, 160—SDRAM, 170—configuration management FPGA, 210—image processing unit FPGA. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] Example 1

[0062] An embodiment of the present invention provides an on-board real-time information processing system for target detection, which includes five parts: a power supply unit, a measurement, control and configuration management unit, an interface unit, an image processing unit and a busbar backplane.

[0063] The power supply unit, measurement, control, and configuration management unit, interface unit, and image processing unit are four different PCBs, each plugged into the busbar backplane via backplane connectors, enabling signal transmission between the four components. This section describes in detail only the measurement, control, and configuration management unit 100, image processing unit 200, and busbar backplane 300, which are relevant for loading, refreshing, and in-orbit reconfiguration.

[0064] Below Figure 1 The functions of each module in the principle block diagram of SRAM-type FPGA loading, refreshing and on-orbit reconstruction in the real-time information processing system on the satellite and the specific loading, refreshing and on-orbit reconstruction process are described in more detail.

[0065] Specifically, the RS422 receiver 110 uses the JSR26C32 from the China Electronics 58th Research Institute. Its primary function is to receive rapid upload data sent by the satellite, typically at a bit rate of 5Mbps, and transmit the received upload data to the measurement, control, and data transmission FPGA 120. This module is used for on-orbit reconfiguration and upgrades, and is not required for normal loading and refreshing. The measurement, control, and data transmission FPGA 120 uses the antifuse FPGA JRTAX2000-LG624 from the China Electronics 58th Research Institute. It has three main functions: first, receiving rapid upload data from the RS422 receiver 110 and transmitting it to the configuration management FPGA 170; second, receiving rapid upload data from the RS422 receiver 110 and controlling the readback refresh chip 130 to store the rapid upload data in the Nor Flash 140 attached to the readback refresh chip 130, enabling on-orbit reconfiguration of the configuration management FPGA 170; and third, directly controlling the readback refresh chip 130 to enable loading and refreshing of the configuration management FPGA. The readback and refresh chip 130 uses Fudan Microelectronics' JFMRS01RH. Controlled by the measurement, control, and data transmission FPGA 120, it loads and periodically refreshes the configuration software stored in the Nor Flash 140 via the SelectMAP interface. It also receives fast upload data and performs read and write operations on the external Nor Flash 140 to store new configuration software. Nor Flash 140 uses Fudan Microelectronics' JFM29GL256RH, primarily responsible for storing software configuration items. Given its fast read speed and ability to directly execute instructions, Nor Flash 140 is primarily used to store low-level software configuration items required for normal onboard operation. NAND Flash 150 offers faster write and erase speeds and a larger capacity than Nor Flash 140. Therefore, due to the limited number of Nor Flash 140s available for on-orbit application upgrades, Orbit's VDNF128G08RS50MS8V25-G is used as NAND Flash 150, serving as a backup for Nor Flash 140 and assuming responsibility for storing some configuration items. Taking advantage of the fast reading speed of SDRAM160, SDRAM160 is mainly used for caching fast data for on-orbit reconstruction, and Orbit's VDSD2G40RS70SS5V75-G is selected.The configuration management FPGA 170 uses Fudan Microelectronics' JFM7K325T-C. Its specific functions include: simultaneously loading and refreshing different configuration item software from multiple external Nor Flash 140 chips to multiple image processing unit FPGAs 210 via the SelectMAP interface, with any combination of loaded configuration items and the number of loaded image processing unit FPGAs 210. It can also receive fast upload data to update and upgrade configuration items stored in the external Nor Flash 140 and NAND Flash 150 chips; and it can quickly save uploaded data in SDRAM, reducing upload time. The image processing unit FPGA 210 uses Fudan Microelectronics' JFM7VX690T36A-RT, receiving configuration item software data from the configuration management FPGA via the SelectMAP interface and executing the corresponding configuration item functions.

[0066] Example 2

[0067] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses an FPGA loading method in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The loading method includes:

[0068] Step 1: After the 42V bus is connected, the measurement, control and data transmission FPGA 120 works normally;

[0069] Step 2: The measurement, control and data transmission FPGA 120 controls the readback refresh chip 130 through the UART interface, and can load the configuration item software in the main Nor Flash 140 plugged into the readback refresh chip 130 into the configuration management FPGA 170 through the SelectMAP interface;

[0070] Step 3: The successfully loaded configuration management FPGA 170 starts to work normally, and loads the configuration item software stored in the external Nor Flash 140 to each image processing unit FPGA 210 through the SelectMAP interface;

[0071] Step 4: After each image processing unit FPGA 210 has been loaded normally, the entire system starts to execute the corresponding task.

[0072] In this embodiment, in step 3, the successfully loaded configuration management FPGA 170 starts to work normally, and the configuration item software stored in the external Nor Flash 140 is loaded into each image processing unit FPGA 210 through the SelectMAP interface, including:

[0073] Step 3.1: Unlike the traditional method of pairing the image processing unit FPGA 210 with the readback refresh chip 130 and NorFlash 140, the configuration management FPGA 170 with multiple external NorFlash 140 memories enables simultaneous loading of multiple image processing unit FPGAs 210, significantly shortening the system program loading time.

[0074] In step 3.2, the number of Nor Flashes 140 required by the system is not related to the number of image processing unit FPGAs 210, but only to the number of configuration options in the system's image processing unit FPGAs 210. This is because complex detection processing for high-throughput, large-field-of-view images inevitably involves segmented and block-based processing, and multiple image processing unit FPGAs 210 share pre-detection configuration software. If the number of configuration options in the image processing unit 200 is m, the number of Nor Flashes 140 required is 2m (including backups).

[0075] In step 3.3, any image processing unit FPGA 210 can load any one of the m configuration items stored in Nor Flash 1 through Nor Flash m. This means there's no one-to-one correspondence between image processing units FPGA 210 and configuration items. The number of image processing units FPGA 210 loaded, as well as the number of image processing units FPGA 210 loaded with different configuration items, can be adjusted in real time based on task requirements, enhancing system flexibility.

[0076] Since SRAM-based FPGAs are sensitive devices, they are easily affected by high-energy particles while in orbit, including total ionizing dose effects (TID) and single event effects (SEE). The impact of single event upsets (SEUs) on SRAM-based FPGAs is particularly significant, so the loaded configuration item software needs to be refreshed periodically.

[0077] Example 3

[0078] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses a method for refreshing an FPGA in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The refreshing method includes:

[0079] Step 1: After the loading process described above is completed, the system starts to work normally. At this time, the readback refresh chip 130 reads back the software configuration items in the Nor Flash main 140 and the software loaded in the configuration register of the configuration management FPGA 170 into the refresh chip, and the refresh chip compares the two.

[0080] Step 2: The configuration item software loaded by the configuration management FPGA 170 instantiates multiple modules with readback and refresh functions, which can read back m configuration items into the configuration management FPGA, and read back the successfully loaded image processing unit configuration items at the same time, and verify them one by one.

[0081] In this embodiment, in step 1, after the loading process is completed, the system starts normal operation, and the readback refresh chip 130 reads back the software configuration items in the Nor Flash master 140 and the software loaded in the configuration register of the configuration management FPGA 170 into the refresh chip for comparison, including:

[0082] Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds;

[0083] In step 1.2, if an abnormality is found, it means that the FPGA has been affected by high-energy particles. Then, repeat step 2 of the above loading process to reload the software configuration items in Nor Flash 140 into the configuration management FPGA 170. After the reload is successful, repeat step 1.

[0084] In this embodiment, in step 2, the configuration item software loaded into the configuration management FPGA 170 instantiates multiple modules with readback and refresh functions, which can read back m configuration items into the configuration management FPGA, and simultaneously read back the successfully loaded image processing unit configuration items and verify them one by one, including:

[0085] In step 2.1, if no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds;

[0086] Step 2.2: If an abnormality is found, repeat step 2 of the above loading process to reload the software configuration items in Nor Flash 140 corresponding to the image processing unit FPGA 210 with the abnormality into the corresponding image processing unit FPGA 210. After the reload is successful, repeat step 1.

[0087] Example 4

[0088] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses an on-orbit FPGA reconfiguration method in an on-board real-time information processing system. By configuring and managing the FPGA 210 in combination with Nor Flash, SDRAM, and NAND Flash, the problem of long time required to load multiple configuration items of the image processing unit is solved. The on-orbit reconfiguration method is implemented using the above-mentioned on-board real-time information processing system, and includes:

[0089] Step 1: The measurement, control and data transmission FPGA 120 receives the fast uplink data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps;

[0090] Step 2: After receiving the fast upload data and the corresponding upload instruction, the measurement, control, and data transmission FPGA 120 makes a judgment: if the corresponding configuration item of the configuration management FPGA 170 needs to be reconfigured on-orbit, proceed to step 3; if the configuration item of the image processing unit FPGA 210 needs to be reconfigured on-orbit, proceed to step 6;

[0091] Step 3: The measurement, control and data transmission FPGA 120 sends the received injection software data to the digital read-back refresh chip 130 through the UART interface, with a baud rate of 115200;

[0092] Step 4: The read-back refresh chip 130 writes the software data into its external Nor Flash 140, which can be written into the main Nor Flash 140 or the backup Nor Flash 140 according to the instruction requirement;

[0093] Step 5: The readback refresh chip 130 reads the software data from the newly written Nor Flash 140 and reloads it into the configuration management FPGA 170 through the SelectMAP interface. After the reload is successful, the refresh process step 1 is performed again.

[0094] Step 6: The measurement, control and data transmission FPGA 120 forwards the received fast injection data to the configuration management FPGA 170 at a communication rate of 20 Mbps.

[0095] Step 7: After receiving the fast injection data, the configuration management FPGA 170 can write the injection data into three different memories, namely, the Nor Flash 140, the NAND Flash 150, or the SDRAM 160, through instructions, and then proceed to step 7.1, step 7.2, and step 7.3 respectively.

[0096] Step 7.1: According to the instruction, the data is quickly written into the Nor Flash 140 at a rate of about 12.5kbps.

[0097] Step 7.2, the configuration management FPGA 170 writes the fast injection data into the NAND Flash 150. The NAND Flash 150 can serve as a backup for the Nor Flash 140 to shorten the injection time, and then proceeds to step 9;

[0098] Step 7.3: Configuration management FPGA 170 writes the fast injection data into SDRAM 160. The SDRAM 160 has a write rate of up to 80 Mbps, which greatly shortens the on-orbit injection time. The on-orbit reconstruction time is limited by the fast injection data rate.

[0099] In step 8, the configuration management FPGA 170 reads the software data from the newly written SDRAM 160 and reloads the specific image processing unit FPGA 210 through the SelectMAP interface. After reloading, the system function test is performed. If the test meets the requirements, the software data in the SDRAM 160 is written to the Nor Flash 140 or NAND Flash 150. This is because the SDRAM 160 cannot save data after power failure and can only temporarily store software configuration items. However, its write speed is faster than that of the Nor Flash 140, making on-orbit testing more convenient.

[0100] Step 9: The configuration management FPGA 170 reads the software data from the newly written Nor Flash 140 and reloads the specific image processing unit FPGA 210 through the SelectMAP interface. After the reload is successful, the refresh process step 2 is performed.

[0101] Step 10: The configuration management FPGA 170 reads the software data from the newly written NAND Flash 150 and reloads the specific image processing unit FPGA 210 through the SelectMAP interface. After the reload is successful, the refresh process step 2 is performed.

[0102] Example 5

[0103] like Figure 2 As shown, the present invention provides a hardware schematic diagram of a SelectMAP interface for a satellite real-time information processing system with a complete cold standby architecture. Figure 2 Only the hardware schematic diagram of the SelectMAP interface between the configuration management FPGA in the measurement and control and configuration management unit 100 and the image processing unit 1 200 is listed. Taking the configuration management FPGA and the FPGA in the image processing unit 1 as an example, the configuration management FPGA loads and refreshes configuration items to an image processing unit FPGA via 15 signal lines. Specifically:

[0104] The signal line controls the input and output direction of the CL1_FR_A_CK_FPGA_DATA_DIR level-shifting isolation chip, enabling bidirectional transmission of the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0]. The eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] and the six control signals CL1_FR_A_CK_FPGA_CCLK, CL1_FR_A_CK_FPGA_PROGRAM_B, CL1_FR_A_CK_FPGA_RDWR_R, CL1_FR_A_CK_FPGA_CSI_B, CL1_FR_A_CK_FPGA_INIT_B, and CL1_FR_A_CK_FPGA_DONE form the SelectMAP loading signal line. The 14 SelectMAP signal lines between the configuration management FPGA and the image processing unit FPGA are electrically connected through the level-shifting isolation chips U1 and U2 in the measurement, control, and configuration management unit 100, the busbar backplane 300, and the level-shifting isolation chips U1 and U2 in the image processing unit 200. The A_CK_VCCA and A_CK_VCCB of the level-shifting isolation chips U1 and U2 in the measurement, control, and configuration management unit 100, and the CL_VCCA and CL_VCCB of the level-shifting isolation chips U1 and U2 in the image processing unit 200, can be consistent or different, with a voltage range of 1.8V to 5.0V. A_CK_VCCA is the same as the bank voltage of the corresponding IO pin of the configuration management FPGA; A_CK_VCCB is consistent with the CL_VCCA level of the level conversion isolation chips U1 and U2 in the image processing unit; CL_VCCB is consistent with the level of a specific IO pin of the image processing unit FPGA, which is determined by the selected FPGA model. In the present invention, the image processing unit FPGA is JFM7VX690T36A-RT, and then CL_VCCB is 1.8V.

[0105] When the configuration item is loaded, CL1_FR_A_CK_FPGA_DATA_DIR is high, and the directions of U2 in the measurement, control, and configuration management unit and U2 in the image processing unit are both A to B. At this time, the configuration item software data is injected into the image processing unit FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the configuration management FPGA IO port, the measurement, control, and configuration management unit U2, and the image processing unit U2, thus completing the loading.

[0106] When refreshing, CL1_FR_A_CK_FPGA_DATA_DIR is at a low level, and the directions of U2 in the measurement, control and configuration management unit and U2 in the image processing unit are both from B to A. At this time, the configuration item software data loaded in the image processing unit is read back to the configuration management FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the image processing unit SelectMAP interface, the image processing unit U2, and the measurement, control and configuration management unit U2.

[0107] Because the image processing unit FPGA has a SelectMAP loading function that requires the use of a specific IO pin, and only a single copy is available, a level conversion isolation chip plays a crucial role in ensuring that both the active and standby measurement, control, and configuration management units 100 in the dynamic redundant architecture can load the image processing unit FPGA. Figure 3 The hardware schematic diagram of the SelectMAP interface implemented in the on-board real-time information processing system based on the dynamic redundant backup solution is given. The level conversion isolation chip port A in the image processing unit 200 receives the SelectMAP signal of the primary and standby configuration management FPGAs respectively, and connects the shaped and isolated SelectMAP signal to the processing unit FPGA at port B. The power-on status of the level conversion isolation chip port A and port B, and the control of OE achieve a double insurance effect, which not only avoids the interference between the primary and standby SelectMAP interface signal lines causing loading failure, but also realizes electrical isolation between the primary and standby configuration management FPGAs, avoiding the occurrence of sneak paths. Taking the configuration management FPGA and the FPGA in the image processing unit 1 as an example, the configuration management FPGA loads and refreshes the configuration items of an image processing unit FPGA through 15 signal lines. Specifically:

[0108] When the main measurement, control, and configuration management unit is operating normally, A_CK_VCC (controlled by the main measurement, control, and configuration management unit) and CL_VCC (controlled by the image processing unit) are powered normally, typically at 1.8V. When the standby measurement, control, and configuration management unit is inoperative, B_CK_VCC (controlled by the standby measurement, control, and configuration management unit) is at zero. At this point, the VCCA and VCCB power supplies of level-shifting isolation chip U1 are normal, and the OE connected to B_CK_VCC is low, allowing U1 to operate normally. When VCCA of level-shifting isolation chip U2 is low, and the OE connected to A_CK_VCC is high, U2 is inoperative, effectively in a high-impedance state, preventing interference with the output signals of the standby configuration management FPGA. When configuration items are loaded, CL1_FR_A_CK_FPGA_DATA_DIR is high, and the direction of U1 in the image processing unit is always A to B. At this point, the configuration item software data is loaded into the image processing unit FPGA via the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] on the configuration management FPGA's IO port and the image processing unit U1. During a refresh, CL1_FR_A_CK_FPGA_DATA_DIR is low, and the image processing unit U1 direction is always from B to A. The loaded configuration item software data in the image processing unit is read back to the configuration management FPGA via the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] on the image processing unit's SelectMAP interface and the image processing unit U1.

[0109] Similarly, when the standby measurement, control, and configuration management unit is operating normally, B_CK_VCC (controlled by the standby measurement, control, and configuration management unit) and CL_VCC (controlled by the image processing unit) are powered normally, typically at 1.8V. When the master measurement, control, and configuration management unit is inoperative, A_CK_VCC (controlled by the master measurement, control, and configuration management unit) is at zero. At this point, the VCCA and VCCB power supplies of level-shifting isolation chip U2 are normal, and the OE connected to A_CK_VCC is low, allowing U2 to operate normally. However, VCCA of level-shifting isolation chip U1 is low, and OE connected to B_CK_VCC is high, allowing U1 to operate in an inoperative, high-impedance state, preventing interference with the output signals of the standby configuration management FPGA. When configuration items are loaded, CL1_FR_B_CK_FPGA_DATA_DIR is high, and the direction of U2 in the image processing unit is always A to B. At this point, the configuration item software data is loaded into the image processing unit FPGA via the eight data signals CL1_FR_B_CK_FPGA_DATA[7:0] on the configuration management FPGA's IO port and image processing unit U2. During a refresh, CL1_FR_B_CK_FPGA_DATA_DIR is low, and the image processing unit's U2 direction is always from B to A. The loaded configuration item software data in the image processing unit is read back to the configuration management FPGA via the eight data signals CL1_FR_B_CK_FPGA_DATA[7:0] on the image processing unit's SelectMAP interface and image processing unit U1.

[0110] According to this solution, the number y of common IOs of the configuration management FPGA should satisfy:

[0111] y≥15*2n

[0112] Wherein: 2n is the number of image processing units 200.

[0113] Similarly, the model and quantity of the backplane connectors selected by the measurement, control and configuration management unit 100 must also meet this requirement.

[0114] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A real-time information processing system on board a satellite, characterized in that: The system comprises five parts: a power supply unit, a measurement, control and configuration management unit (100), an interface unit, an image processing unit (200) and a busbar backplane (300); For a real-time information processing system on board a satellite based on a dynamic redundant architecture, a parallel architecture of a configuration management FPGA (170) with Nor Flash (140), NAND Flash (150), SDRAM (160) memory and multiple SRAM-type FPGAs is proposed; The configuration management FPGA (170) is used to simultaneously load and refresh different configuration item software in multiple external Nor Flash (140) chips to multiple image processing unit FPGAs (210) through a SelectMAP interface, and the loaded configuration items and the number of loaded image processing unit FPGAs (210) can be combined arbitrarily; it is also used to receive fast injection data and update the configuration items stored in the external Nor Flash (140) and NAND Flash (150); it is also used to store the injection data in SDRAM; The successfully loaded configuration management FPGA (170) starts working, and loads the configuration item software stored in the external Nor Flash (140) to each image processing unit FPGA (210) through the SelectMAP interface, including: A plurality of image processing unit FPGAs (210) share pre-detection configuration software; if the number of configuration items of the image processing unit (200) is m, the number of Nor Flashes (140) is 2m; The number of image processing unit FPGA (210) loaded and the number of image processing unit FPGA (210) loaded with different configuration item software can be adjusted in real time according to task requirements.

2. The system according to claim 1, wherein: The measurement, control and configuration management unit (100) further includes: an RS422 receiver (110), a measurement, control and data transmission FPGA (120), a readback refresh chip (130), a Nor Flash (140), a NAND Flash (150), and an SDRAM (160); The image processing unit (200) comprises: multiple image processing unit FPGAs (210); The RS422 receiver (110) is used to receive the rapid uplink data sent by the satellite, and transmit the received uplink data to the measurement, control and data transmission FPGA (120) for on-orbit reconfiguration and upgrading on the satellite; The measurement, control and data transmission FPGA (120) is used to receive the fast injection data from the RS422 receiver (110) and send the fast injection data to the configuration management FPGA (170); it is also used to receive the fast injection data from the RS422 receiver (110) and control the readback refresh chip (130) to store the fast injection data in the Nor Flash (140) external to the readback refresh chip (130), thereby realizing on-track reconstruction of the configuration management FPGA (170); it is also used to directly control the readback refresh chip (130) to realize loading and refreshing of the configuration management FPGA (170); The readback refresh chip (130) is used to load and periodically refresh the configuration item software stored in the Nor Flash (140) to the configuration management FPGA (170) through the SelectMAP interface under the control of the measurement and control and data transmission FPGA (120); at the same time, it can also receive fast injection data, perform read and write operations on the external Nor Flash (140), and store new configuration item software; The Nor Flash (140) is used to store the underlying software configuration items required for normal operation on the satellite; The NAND Flash (150) serves as a backup of the Nor Flash (140) and is responsible for storing some configuration items; The SDRAM (160) is used for caching fast-injection data for on-track reconstruction; The image processing unit FPGA (210) is used to receive configuration item software data of the configuration management FPGA through a SelectMAP interface and run corresponding configuration item functions.

3. A method for loading an FPGA in a satellite real-time information processing system, implemented by applying the satellite real-time information processing system according to any one of claims 1 to 2, characterized in that: The loading method includes: Step 1: After the 42V bus is connected, the measurement, control and data transmission FPGA (120) operates normally; Step 2, the measurement and control and data transmission FPGA (120) controls the readback refresh chip (130) through the UART interface, and loads the configuration item software in the main Nor Flash (140) plugged into the readback refresh chip (130) into the configuration management FPGA (170) through the SelectMAP interface; Step 3, the successfully loaded configuration management FPGA (170) starts to work normally, and loads the configuration item software stored in the external Nor Flash (140) to each image processing unit FPGA (210) through the SelectMAP interface; Step 4: After each image processing unit FPGA (210) has been loaded normally, the entire system starts to execute the corresponding task.

4. The method according to claim 3, characterized in that In step 3, the successfully loaded configuration management FPGA (170) starts to work normally, and loads the configuration item software stored in the external Nor Flash (140) to each image processing unit FPGA (210) through the SelectMAP interface, including: Step 3.1, realizing simultaneous loading of multiple image processing unit FPGAs (210) by configuring the management FPGA (170) and multiple external Nor Flash (140) memories; In step 3.2, the number of Nor Flashes (140) required by the system has no correlation with the number of image processing unit FPGAs (210), but is only related to the number of configuration items of the system image processing unit FPGAs (210); In step 3.3, any image processing unit FPGA (210) can load any one of the m configuration item software stored in Nor Flash 1 to Nor Flash m, that is, there is no one-to-one correspondence between the image processing unit FPGA (210) and the configuration item.

5. A method for refreshing FPGA in a satellite real-time information processing system, implemented by applying the satellite real-time information processing system according to any one of claims 1 to 2, characterized in that: The refreshing method includes: Step 1: After the loading process is completed, the system starts to work normally, and the read-back refresh chip (130) reads back the software configuration items in the Nor Flash main (140) and the software loaded in the configuration register of the configuration management FPGA (170) into the refresh chip for comparison; Step 2: The configuration item software loaded by the configuration management FPGA (170) instantiates a plurality of modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and read back the image processing unit configuration items that have been successfully loaded, and verify them one by one.

6. The method according to claim 5, characterized in that In step 1, after the loading process is completed, the system starts to work normally, and the read-back refresh chip (130) reads back the software configuration items in the Nor Flash main (140) and the software loaded in the configuration register of the configuration management FPGA (170) into the refresh chip for comparison, including: Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds; In step 1.2, if an abnormality is found, repeat step 2 of the loading process to reload the software configuration items in the Nor Flash (140) into the configuration management FPGA (170). After the reload is successful, repeat step 1.

7. The method according to claim 5, characterized in that In step 2, the configuration item software loaded by the configuration management FPGA (170) instantiates a plurality of modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and simultaneously read back the image processing unit configuration items that have been successfully loaded, and perform verification one by one, including: In step 2.1, if no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds; In step 2.2, if an abnormality is found, step 2 of the loading process is repeated to reload the software configuration items in the Nor Flash (140) corresponding to the image processing unit FPGA (210) with the abnormality into the corresponding image processing unit FPGA (210). After the reloading is successful, step 1 is repeated.

8. A method for on-orbit reconfiguration of FPGA in a satellite real-time information processing system, implemented by applying the satellite real-time information processing system according to any one of claims 1-2, characterized in that: The on-orbit reconstruction method comprises: Step 1, the measurement, control and data transmission FPGA (120) receives the fast uplink data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps; Step 2, after the measurement and control and data transmission FPGA (120) receives the fast injection data and the corresponding injection instruction, it makes a judgment: if the corresponding configuration item of the configuration management FPGA (170) needs to be reconfigured on-orbit, then proceed to step 3; if the configuration item of the image processing unit FPGA (210) needs to be reconfigured on-orbit, then proceed to step 6; Step 3, the measurement and control and data transmission FPGA (120) sends the received injection software data to the digital read-back refresh chip (130) through the UART interface, with a baud rate of 115200; Step 4, the read-back refresh chip (130) writes the software data into the external Nor Flash (140), and writes the data into the main Nor Flash (140) or the backup Nor Flash (140) according to the instruction requirement; Step 5, the read-back refresh chip (130) reads the software data from the written Nor Flash (140) and reloads it into the configuration management FPGA (170) through the SelectMAP interface. After the reload is successful, the refresh step 1 is performed again; Step 6: The measurement, control and data transmission FPGA (120) forwards the received fast injection data to the configuration management FPGA (170) at a communication rate of 20 Mbps. Step 7, after receiving the fast injection data, the configuration management FPGA (170) can write the injection data into three different memories, namely, a specific Nor Flash (140), a NAND Flash (150), or an SDRAM (160), through instructions; Step 8, the configuration management FPGA (170) reads the software data from the written SDRAM (160), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface, performs a system function test after reloading, and writes the software data in the SDRAM (160) into the Nor Flash (140) or the NAND Flash (150) after the test meets the requirements; Step 9, the configuration management FPGA (170) reads the software data from the written Nor Flash (140), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface, and then performs the refresh step 2 after the reload is successful; Step 10, the configuration management FPGA (170) reads the software data from the written NAND Flash (150), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface. After the reload is successful, the refresh step 2 is performed.

9. The method according to claim 8, characterized in that In step 7, after receiving the fast injection data, the configuration management FPGA (170) can write the injection data into three different memories, namely, a specific Nor Flash (140), a NAND Flash (150), or an SDRAM (160), through instructions. Step 7.1, according to the instruction, quickly write the data into the Nor Flash (140) at a rate of about 12.5kbps; Step 7.2, the configuration management FPGA (170) writes the fast injection data into the NAND Flash (150), and the NAND Flash (150) serves as a backup for the Nor Flash (140), and then proceeds to step 9; In step 7.3, the configuration management FPGA (170) writes the fast injection data into the SDRAM (160). The write rate of the SDRAM (160) is as high as 80Mbps.

Images