Digital signal encryption method based on different working modes and related equipment

Abstract

The invention provides a digital signal encryption method based on different working modes and electronic equipment. The method is applied to a digital signal encryption system based on different working modes. The digital signal encryption system based on different working modes comprises a switching chip, a digital signal processor and a program storage module, the method comprises the following steps: the switching chip receives a data packet sent by an upper computer and transmits the data packet to the digital signal processor; the digital signal processor analyzes the data packet to obtain plaintext information and a secret key; and the digital signal processor determines a working mode, calls a target encryption algorithm corresponding to the working mode from the program storage module, and encrypts the plaintext information according to the key through the target encryption algorithm to obtain encrypted data. Therefore, diversified encryption of the plaintext information can be realized through the target encryption algorithm corresponding to the working mode.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular to a digital signal encryption method based on different working modes and related devices. Background Art

[0002] With the development of digital signal processing technology, more and more digital signal processing chips are applied to various fields. However, currently only a fixed method can be used to encrypt digital signals, and diversified encryption of digital signals cannot be achieved.

[0003] In view of this, how to achieve diversified encryption of digital signals has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the purpose of the present disclosure is to propose a digital signal encryption method based on different working modes and related devices to solve or partially solve the above technical problems.

[0005] Based on the above purpose, the first aspect of the present disclosure proposes a digital signal encryption method based on different working modes, which is applied to a digital signal encryption system based on different working modes. The digital signal encryption system based on different working modes includes: a switching chip, a digital signal processor and a program storage module; the method includes:

[0006] The adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor;

[0007] The digital signal processor parses the data packet to obtain plaintext information and a key;

[0008] The digital signal processor determines an operating mode, retrieves a target encryption algorithm corresponding to the operating mode from the program storage module, and encrypts the plaintext information according to the key using the target encryption algorithm to obtain encrypted data.

[0009] Based on the same inventive concept, the second aspect of the present disclosure proposes a digital signal encryption system based on different working modes, including: a switching chip, a digital signal processor and a program storage module;

[0010] The adapter chip is configured to receive a data packet sent from the host computer and transmit the data packet to the digital signal processor;

[0011] The digital signal processor is configured to parse the data packet to obtain plaintext information and a key;

[0012] The digital signal processor is configured to determine an operating mode, retrieve a target encryption algorithm corresponding to the operating mode from the program storage module, and encrypt the plaintext information according to the key using the target encryption algorithm to obtain encrypted data.

[0013] Based on the same inventive concept, the third aspect of the present disclosure proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0014] Based on the same inventive concept, a fourth aspect of the present disclosure proposes a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method as described above.

[0015] From the above, it can be seen that the digital signal encryption method and related equipment based on different working modes provided by the present disclosure. The adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor. The digital signal processor parses and processes the data packet to obtain plaintext information and keys. The digital signal processor determines the working mode, calls the target encryption algorithm corresponding to the working mode from the program storage module, and encrypts the plaintext information according to the key through the target encryption algorithm to obtain encrypted data. In this way, different working modes correspond to different encryption algorithms, and through the target encryption algorithm corresponding to the working mode, diversified encryption of plaintext information can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a flow chart of a digital signal encryption method based on different working modes according to an embodiment of the present disclosure;

[0018] Figure 2 It is a structural diagram of a DSP-based encryption system according to an embodiment of the present disclosure;

[0019] Figure 3 It is a structural schematic diagram of a digital signal encryption system based on different working modes according to an embodiment of the present disclosure;

[0020] Figure 4 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] Based on the description of the background technology, with the rapid development of integrated circuits, the functional safety and information security of chips are increasingly concerned by chip manufacturers, and encryption methods are used in communication security. Currently, common encryption hardware is designed and implemented using Field Programmable Gate Array (FPGA). However, FPGA development requires the mastery of hardware description languages ​​such as Verilog or VHDL, which is difficult to develop, has high development costs, is complex and time-consuming, and has high power consumption requirements.

[0024] As mentioned above, how to achieve diversified encryption of digital signals has become an important research issue.

[0025] Based on the above description, if Figure 1 As shown, the digital signal encryption method based on different working modes proposed in this embodiment is applied to a digital signal encryption system based on different working modes, and the digital signal encryption system based on different working modes includes: a switching chip, a digital signal processor and a program storage module; the method includes:

[0026] Step 101: the adapter chip receives a data packet sent from a host computer and transmits the data packet to the digital signal processor.

[0027] In specific implementation, the adapter chip is used for data transmission between the host computer and the digital signal processor. The adapter chip transmits the data packet sent by the host computer to the digital signal processor. Among them, the adapter chip is the CH340 chip, which is a USB bus adapter chip that can realize multiple functions such as USB to serial port, USB to IrDA infrared or USB to printer port.

[0028] Specifically, the host computer sends a data packet through the USB bus, which is converted into a TTL232 serial port through a converter chip, and then sent to the serial port of the digital signal processor.

[0029] Step 102: the digital signal processor parses the data packet to obtain plaintext information and a key.

[0030] In specific implementation, a digital signal processor (DSP) has the characteristics of high speed and real time, and is a programmable chip dedicated to digital signal processing.

[0031] The digital signal processor parses the data packet to obtain plaintext information and a key, so as to facilitate subsequent encryption of the plaintext information according to the key to obtain encrypted data.

[0032] Step 103: The digital signal processor determines an operating mode.

[0033] In specific implementation, a plurality of encryption algorithms are stored in the program storage module. In different working modes, different encryption algorithms are used to encrypt the plain text information.

[0034] Step 104, in response to determining that the working mode is the default mode, the digital signal processor retrieves a first encryption algorithm corresponding to the default mode from the program storage module, and encrypts the plaintext information according to the key through the first encryption algorithm to obtain hexadecimal encrypted data.

[0035] In specific implementation, the default mode is the default mode after the system is powered on, which is convenient for embedding the digital signal encryption system based on different working modes into the external system for use. In the default mode, the encrypted data can be returned by sending the corresponding data packet according to the application layer protocol. The digital signal encryption system based on different working modes is equivalent to a black box for the external system. The digital signal encryption system based on different working modes in the default mode can be used as a subsystem of the external system, can be embedded in the external system for use, and adopts standard UART communication to facilitate external system integration.

[0036] When the working mode of the digital signal encryption system based on different working modes is the default mode, a first encryption algorithm corresponding to the default mode is obtained. The plaintext information is encrypted by the first encryption algorithm according to the key to obtain hexadecimal encrypted data. The first encryption algorithm is the default encryption algorithm.

[0037] Step 105, in response to determining that the working mode is the debugging mode, the digital signal processor retrieves the second encryption algorithm corresponding to the debugging mode from the program storage module, and encrypts the plaintext information according to the key through the second encryption algorithm to obtain encrypted data in ASCII code.

[0038] In specific implementation, the debugging mode is the mode for debugging the system. The control instructions are sent through the serial port debugging assistant to control the digital signal encryption system based on different working modes to enter the debugging mode. In the debugging mode, the user needs to enter the target encryption algorithm, plain text information and key according to the prompt information returned by the serial port debugging assistant. The digital signal encryption system based on different working modes in the debugging mode can be used as the main device, independent of the application layer communication protocol, that is, any serial port debugging assistant can be used.

[0039] When the working mode of the digital signal encryption system based on different working modes is the debugging mode, the second encryption algorithm corresponding to the debugging mode is obtained. The plain text information is encrypted by the second encryption algorithm according to the key to obtain the encrypted data in ASCII code. The second encryption algorithm is the encryption algorithm input by the user.

[0040] Through the above embodiment, the adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor. The digital signal processor parses and processes the data packet to obtain plaintext information and a key. The digital signal processor determines the working mode, retrieves the target encryption algorithm corresponding to the working mode from the program storage module, and passes the target encryption algorithm. When the working mode of the digital signal encryption system based on different working modes is the default mode, the plaintext information can be encrypted by the default first encryption algorithm to obtain the first encrypted data, and the digital signal encryption system based on different working modes can be conveniently integrated into the external system. When the working mode of the digital signal encryption system based on different working modes is the debugging mode, the plaintext information can be encrypted by the input second encryption algorithm to obtain the second encrypted data, and the digital signal encryption system based on different working modes can be debugged. In this way, different working modes correspond to different encryption algorithms, and the diversified encryption of plaintext information can be achieved through the target encryption algorithm corresponding to the working mode.

[0041] In some embodiments, the method further comprises:

[0042] Step 106: In response to determining that the digital signal processor retrieves the symmetric encryption algorithm from the program storage module, a data table of the symmetric encryption algorithm is obtained.

[0043] Step 107, replace the pre-stored bytes in the pre-grouping by searching the data table to obtain replacement bytes.

[0044] Step 108: The digital signal processor performs row shift processing on the replacement byte to obtain a shifted byte.

[0045] Step 109: the digital signal processor reads preset matrix data from the program storage module, and performs column obfuscation processing on the shift bytes according to the preset matrix data to obtain encrypted data.

[0046] In specific implementation, the target encryption algorithm may be a symmetric encryption algorithm. For example, the target encryption algorithm includes at least one of the following: AES encryption algorithm, DES encryption algorithm and SM4 encryption algorithm. Among them, AES (Advanced Encryption Standard) is a symmetric encryption algorithm that uses the same key for encryption and decryption. DES (Data Encryption Standard) is a symmetric encryption algorithm that uses a 64-bit key (56 bits of which are valid and 8 bits are used for verification) for encryption and decryption. SM4 is a symmetric encryption algorithm used to protect data in static storage and transmission channels.

[0047] Combined with the characteristics of digital signal processors, the high-speed arithmetic logic unit (ALU), multiplier and other hardware components inside the digital signal processor are specially optimized for complex operations in encryption algorithms such as AES and SM4 (such as byte replacement and column confusion operations in the AES encryption algorithm, nonlinear transformation and linear transformation in the SM4 encryption algorithm, etc.). With the support of the hardware instruction set, these operations can be completed in a very short time, greatly improving the execution speed of the encryption algorithm. For example, in the column confusion operation of the AES encryption algorithm, the hardware multiplier of the digital signal processor can efficiently complete the matrix multiplication operation.

[0048] Taking the AES encryption algorithm as an example, the steps of AES encryption algorithm and hardware coordination include: (1) Byte replacement: For each byte in each group, the digital signal processor loads the S-box data of the AES encryption algorithm from the program storage module, and replaces the byte in the group with the corresponding byte by searching the S-box table. This search and replacement operation is controlled by the instruction execution unit of the digital signal processor according to the predetermined program flow to control the reading, searching and writing of data to ensure that each byte can be correctly replaced. (2) Row shift: The digital signal processor uses data processing instructions to perform a circular left shift operation on each row in the group. By controlling the storage address and reading order in the data DDR, the first row remains unchanged, the second row is circularly shifted left by 1 byte, the third row is circularly shifted left by 2 bytes, and the fourth row is circularly shifted left by 3 bytes. (3) Column confusion: The digital signal processor reads the fixed matrix data (4x4 matrix) required for column confusion from the program storage module and loads it into another internal data register. Then, the digital signal processor uses the multiplier unit to perform multiplication on each column in the group.

[0049] Select an encryption algorithm and encrypt the plaintext information in the data packet. The following is a code example:

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058] Through the above embodiment, the adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor. The digital signal processor parses the data packet to obtain the plaintext information and the key. The digital signal processor determines the working mode, calls the target encryption algorithm corresponding to the working mode from the program storage module, and encrypts the plaintext information according to the key through the target encryption algorithm to obtain the encrypted data. In this way, different working modes correspond to different encryption algorithms, and through the target encryption algorithm corresponding to the working mode, diversified encryption of plaintext information can be achieved.

[0059] In some embodiments, the digital signal encryption system based on different working modes further includes: a data temporary storage module; after step 102, further includes:

[0060] Step 102A: The digital signal processor sends the data packet, the plaintext information and the key to the data temporary storage module.

[0061] Step 102B: the data temporary storage module stores the data packet, the plaintext information and the key.

[0062] In a specific implementation, the data temporary storage module can be a second-generation double data rate synchronous dynamic random access memory (Double Data Rate 2SDRAM, referred to as DDR2). After the host computer transmits the data packet to the digital signal processor, the digital signal processor sends the data packet to the data temporary storage module, and the data temporary storage module stores the data packet.

[0063] After the digital signal processor parses the data packet to obtain the plaintext information and the key, the digital signal processor sends the plaintext information and the key to the data temporary storage module, and the data temporary storage module stores the plaintext information and the key.

[0064] Among them, a plurality of storage areas are provided in the data temporary storage module. The data temporary storage module judges and processes the received data and stores the data in the corresponding storage area. For example, when the data temporary storage module receives a data packet, the data packet is stored in the first storage area. When the data temporary storage module receives plain text information, the plain text information is stored in the second storage area. When the data temporary storage module receives a key, the key is stored in the third storage area.

[0065] Through the above scheme, the digital signal processor sends the data packet, plaintext information and key to the data temporary storage module, and the data temporary storage module stores the data packet, plaintext information and key. In this way, when the digital processor encrypts the plaintext information, it is convenient to call the plaintext information and key for encryption processing to obtain encrypted data.

[0066] In some embodiments, step 101 includes:

[0067] Step 1011: the digital signal encryption system based on different working modes receives an encryption request instruction and requests a data packet from the host computer.

[0068] Step 1012: After receiving the preset duration of the encryption request instruction, the adapter chip receives data packets within a preset period.

[0069] In specific implementation, after receiving the encryption request instruction, the digital signal encryption system based on different working modes requests a data packet from the upper computer and starts timing. The upper computer sends the data packet to the adapter chip of the digital signal encryption system based on different working modes, and the adapter chip receives the data packet within the preset period after the preset time length of the timing starts.

[0070] For example, the preset duration is 5s and the preset period is 30s. When the digital signal encryption system based on different working modes receives the encryption request instruction, it requests a data packet from the host computer and starts timing. The adapter chip of the digital signal encryption system based on different working modes receives the data packet sent by the host computer at the 5th second after the timing starts, and the received data packet is the data packet within the 5th to 35th second after the timing starts.

[0071] Through the above scheme, after the digital signal encryption system based on different working modes receives the encryption request instruction, it requests a data packet from the upper computer and starts timing. After receiving the preset duration of the encryption request instruction, the adapter chip receives the data packet within the preset period. In this way, the data packet is received while ensuring that the upper computer sends the data packet. By receiving the data packet within the preset period, the received data packets can be reduced while meeting the encryption requirements, thereby reducing the amount of calculation and avoiding wasting computing resources.

[0072] In some embodiments, the digital signal encryption system based on different working modes further includes: an output trigger pin; the method further includes:

[0073] Step 104, obtaining the current state of the digital signal processor, and determining whether the current state is a working state.

[0074] Step 105, in response to determining that the current state is the working state, controlling the output trigger pin to be in a high state.

[0075] Step 106, in response to determining that the current state is the waiting state, controlling the output trigger pin to be in a low state.

[0076] In specific implementation, when the digital signal processor is in working state, the output trigger pin is controlled to be in high state (ie, pulled high). When the digital signal processor is in waiting state, the output trigger pin is controlled to be in low state (ie, pulled low).

[0077] The output trigger pin may be a General Purpose Input / Output (GPIO), which is a common interface type in digital electronic systems and is used to communicate and control external devices. The GPIO interface can be used as an input or output pin and has extremely high flexibility and versatility.

[0078] Through the above scheme, when the digital signal processor is in working state, the output trigger pin is controlled to be in a high state. When the digital signal processor is in a waiting state, the output trigger pin is controlled to be in a low state. In this way, it is possible to accurately judge whether the digital signal processor is in working state according to the state of the output trigger pin, thereby judging whether the digital signal processor is performing encryption processing.

[0079] In some embodiments, step 101 includes:

[0080] Step 101A: the adapter chip receives a data packet sent from the host computer via the USB bus.

[0081] Step 101B: the adapter chip converts digital communication into serial communication, and transmits the data packet to the digital signal processor via the TTL232 serial port.

[0082] In a specific implementation, the communication mode between the adapter chip and the host computer is digital communication, and the communication mode between the adapter chip and the digital signal processor is serial communication.

[0083] The host computer sends data packets to the adapter chip through the USB bus, and the adapter chip receives the data packets through the USB bus. The adapter chip transmits the data packets to the digital signal processor through the TTL232 serial port.

[0084] When the host computer sends a data packet through the USB bus, the adapter chip receives the data packet. The conversion circuit inside the adapter chip converts the digital communication format of the USB bus into the TTL232 serial port communication format for data transmission with the digital signal processor. During the data transmission process, the adapter chip is used to manage the flow and rate matching of the data, including the transmission rate of the USB bus and the communication parameters of the TTL232 serial port (such as baud rate, data bits, stop bits, etc.), and appropriately caches and sends and receives data packets.

[0085] Through the above scheme, the digital communication is converted into serial communication using the adapter chip, and the data packet sent by the host computer can be transmitted to the digital signal processor.

[0086] In some embodiments, after step 103, the method further includes:

[0087] Step 103A: the digital signal processor sends the encrypted data to the adapter chip via the TTL232 serial port.

[0088] Step 103B: the adapter chip converts the serial communication into digital communication, and transmits the encrypted data to the host computer via the USB bus.

[0089] In a specific implementation, the communication mode between the adapter chip and the digital signal processor is serial communication, and the communication mode between the adapter chip and the host computer is digital communication.

[0090] After the digital signal processor decrypts the plaintext information to obtain the encrypted data, it sends the encrypted data to the adapter chip through the TTL232 serial port. The adapter chip transmits the encrypted data to the host computer through the USB bus.

[0091] Through the above scheme, the serial communication is converted into digital communication using the adapter chip, and the encrypted data encrypted by the digital signal processor can be transmitted to the host computer.

[0092] Through the above embodiment, the adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor. The digital signal processor parses the data packet to obtain the plaintext information and the key. The digital signal processor determines the working mode, calls the target encryption algorithm corresponding to the working mode from the program storage module, and encrypts the plaintext information according to the key through the target encryption algorithm to obtain the encrypted data. In this way, different working modes correspond to different encryption algorithms, and through the target encryption algorithm corresponding to the working mode, diversified encryption of plaintext information can be achieved.

[0093] It should be noted that the embodiments of the present disclosure may be further described in the following manner:

[0094] Figure 2 FIG. 1 is a schematic diagram of the structure of the DSP-based encryption system of the embodiment of the present disclosure. Figure 2 As shown in the figure, the encryption system based on DSP includes: encryption device and personal computer (PC). The encryption device includes: adapter chip (CH340 chip), digital signal processor (DSP), program storage module (NANDflash and SDcard) and data temporary storage module (DDR2). The PC includes: host computer serial port assistant and integrated development environment (CCS5.5 IDE).

[0095] The disclosed embodiment implements different encryption algorithms through DSP, and converts serial communication into USB communication through CH340 chip to exchange data with the host computer. The program will be solidified in NAND Flash or SD card to realize automatic operation when the system is powered on, and the external DDR2 is used as a data temporary storage module. At the same time, a serial port debugging assistant is used to interact in the form of ASCII code or hexadecimal data, and the application layer communication protocol is used to communicate with the host computer. The protocol here specifies the contents such as frame header, key and plaintext information, target encryption algorithm, checksum and frame tail, and the system can be debugged through a debugger.

[0096] Among them, GPIO is used as an output trigger pin. When the encryption algorithm starts, the output trigger pin will be pulled high; when the encryption algorithm ends, the output trigger pin will be pulled low. The use of external triggers can synchronize the operation of the encryption system with that of external devices, and this trigger mechanism can better integrate the encryption system into the overall architecture. When data needs to be encrypted and transmitted, the trigger signal will start the acceleration function of the encryption system, thereby quickly completing the encryption operation.

[0097] Encryption process: The host computer sends a data packet through the USB bus, which is converted to a TTL232 serial port by the CH340 chip and then sent to the serial port of the DSP. At this time, after receiving the data packet, the DSP first temporarily stores it in the DDR. Then, after the DSP parses the content of the data packet, it temporarily stores the plaintext information and the key in different areas of the DDR. At this time, the encryption system starts to encrypt the plaintext information according to the target encryption algorithm in the data packet. The encrypted encrypted data is sent to the CH340 chip through the serial port interface of the DSP, and then converted to USB and sent to the host computer. The DSP uses a two-level deep cache area to receive serial port data, that is, the receiving data and the encryption execution do not interfere with each other, meeting the requirements of the host computer sending data packet interval changes.

[0098] Encryption result: The upper computer software controls two built-in parallel interaction methods to realize the transmission of encrypted data.

[0099] The hardware design of the symmetric encryption algorithm based on DSP has a unique system architecture that combines DSP with storage and communication components. It also provides two parallel modes of communication interaction to provide convenient support for different needs.

[0100] The present invention has two built-in interaction modes, and the onboard LED light is used to indicate the current mode:

[0101] Default mode: The system is in default mode after power-on. In default mode, the encryption system can be easily embedded in other devices for use. By sending the corresponding data packet according to the application layer protocol, the encrypted data can be returned. In default mode, the encryption system can be considered a black box to the external system.

[0102] Debug mode: You can enter the debug mode by sending control commands through the serial port debugging assistant. In the debug mode, the user needs to enter the algorithm selection, plain text, key and other information according to the prompt information returned by the serial port debugging assistant.

[0103] The encryption device in the default mode is used as a subsystem of the external system and can be embedded in the external system for use. It uses standard UART communication to facilitate external system integration.

[0104] The encryption device in debug mode can be used as a master device and is independent of the application layer communication protocol, that is, any serial port debugging assistant can be used.

[0105] The two modes return encrypted data in different encoding methods. The default mode returns encrypted data in hexadecimal format, and the debug mode returns encrypted data in ASCII format.

[0106] Through the above embodiments, the DSP-based encryption system provides a variety of built-in encryption programs for selection. And the standard serial port communication can be easily integrated into the external system for use, and can be plug-and-play. It is suitable for application scenarios with strict requirements on power consumption and has the advantage of rapid transplantation.

[0107] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the present embodiment can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0108] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0109] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present disclosure also provides a digital signal encryption system based on different working modes.

[0110] refer to Figure 3 , the digital signal encryption system based on different working modes includes: a switching chip 301, a digital signal processor 302 and a program storage module 303;

[0111] The adapter chip 301 is configured to receive a data packet sent from a host computer and transmit the data packet to the digital signal processor;

[0112] The digital signal processor 302 is configured to parse the data packet to obtain plaintext information and a key;

[0113] The digital signal processor 302 is configured to determine an operating mode;

[0114] In response to determining that the working mode is the default mode, the digital signal processor 302 retrieves a first encryption algorithm corresponding to the default mode from the program storage module 303, and encrypts the plaintext information according to the key using the first encryption algorithm to obtain hexadecimal encrypted data;

[0115] In response to determining that the working mode is the debugging mode, the digital signal processor 302 retrieves the second encryption algorithm corresponding to the debugging mode from the program storage module 303, and uses the second encryption algorithm to encrypt the plaintext information according to the key to obtain encrypted data in ASCII code.

[0116] In some embodiments, it also includes:

[0117] In response to determining that the digital signal processor 302 retrieves a symmetric encryption algorithm from the program storage module 303, obtaining a data table of the symmetric encryption algorithm;

[0118] Replace the pre-stored bytes in the pre-group by searching the data table to obtain replacement bytes;

[0119] The digital signal processor 302 performs row shift processing on the replacement byte to obtain a shift byte;

[0120] The digital signal processor 302 reads preset matrix data from the program storage module, and performs column obfuscation processing on the shift bytes according to the preset matrix data to obtain encrypted data.

[0121] In some embodiments, the digital signal encryption system based on different working modes further includes: a data temporary storage module;

[0122] The digital signal processor 302 sends the data packet, the plaintext information and the key to the data temporary storage module;

[0123] The data temporary storage module stores the data packet, the plaintext information and the key.

[0124] In some embodiments,

[0125] The digital signal encryption system based on different working modes receives an encryption request instruction and requests a data packet from the host computer;

[0126] After receiving the preset duration of the encryption request instruction, the adapter chip 301 receives data packets within a preset period.

[0127] In some embodiments, the digital signal encryption system based on different working modes further includes: an output trigger pin;

[0128] Acquire the current state of the digital signal processor 302, and determine whether the current state is a working state;

[0129] In response to determining that the current state is a working state, controlling the output trigger pin to be in a high state;

[0130] In response to determining that the current state is the waiting state, the output trigger pin is controlled to be in a low state.

[0131] In some embodiments,

[0132] The adapter chip 301 is configured to receive data packets sent from the host computer via the USB bus;

[0133] The adapter chip 301 is configured to convert digital communication into serial communication and transmit the data packet to the digital signal processor 302 via the TTL232 serial port.

[0134] In some embodiments,

[0135] The digital signal processor 302 is configured to send the encrypted data to the adapter chip 301 via a TTL232 serial port;

[0136] The adapter chip 301 is configured to convert serial communication into digital communication and transmit the encrypted data to the host computer via a USB bus.

[0137] For the convenience of description, the above system is described by dividing the functions into various modules. Of course, when implementing the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0138] The system of the above embodiment is used to implement the corresponding digital signal encryption method based on different working modes in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0139] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the digital signal encryption method based on different working modes described in any of the above embodiments is implemented.

[0140] Figure 4A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0141] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0142] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0143] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0144] The communication interface 1040 is used to connect a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB (Universal Serial Bus), network cable, etc.), or through a wireless mode (such as mobile network, WIFI (Wireless Fidelity), Bluetooth, etc.).

[0145] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0146] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0147] The electronic device of the above embodiment is used to implement the corresponding digital signal encryption method based on different working modes in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0148] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present disclosure also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the digital signal encryption method based on different working modes as described in any of the above embodiments.

[0149] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0150] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the digital signal encryption method based on different working modes as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0151] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0152] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the system can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram systems are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0153] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0154] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present disclosure. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A digital signal encryption method based on different working modes, characterized in that: The invention is applied to a digital signal encryption system based on different working modes, wherein the digital signal encryption system based on different working modes comprises: a switching chip, a digital signal processor and a program storage module; the method comprises: The adapter chip receives the data packet sent by the host computer and transmits the data packet to the digital signal processor; The digital signal processor parses the data packet to obtain plaintext information and a key; The digital signal processor determines an operating mode; In response to determining that the working mode is the default mode, the digital signal processor retrieves a first encryption algorithm corresponding to the default mode from the program storage module, and encrypts the plaintext information according to the key using the first encryption algorithm to obtain hexadecimal encrypted data; In response to determining that the working mode is the debugging mode, the digital signal processor retrieves a second encryption algorithm corresponding to the debugging mode from the program storage module, and encrypts the plaintext information according to the key using the second encryption algorithm to obtain encrypted data in ASCII code.

2. The method according to claim 1, characterized in that Also includes: In response to determining that the digital signal processor calls the symmetric encryption algorithm from the program storage module, obtaining a data table of the symmetric encryption algorithm; Replace the pre-stored bytes in the pre-group by searching the data table to obtain replacement bytes; The digital signal processor performs row shift processing on the replacement byte to obtain a shift byte; The digital signal processor reads preset matrix data from the program storage module, and performs column obfuscation processing on the shift bytes according to the preset matrix data to obtain encrypted data.

3. The method according to claim 1, characterized in that The digital signal encryption system based on different working modes also includes: a data temporary storage module; After the digital signal processor parses the data packet to obtain plaintext information and a key, the method further includes: The digital signal processor sends the data packet, the plaintext information and the key to the data temporary storage module; The data temporary storage module stores the data packet, the plaintext information and the key.

4. The method according to claim 1, characterized in that: The adapter chip receives a data packet sent by the host computer, including: The digital signal encryption system based on different working modes receives an encryption request instruction and requests a data packet from the host computer; After receiving the preset time length of the encryption request instruction, the switching chip receives data packets within a preset period.

5. The method according to claim 1, characterized in that The digital signal encryption system based on different working modes further includes: an output trigger pin; the method further includes: Acquire the current state of the digital signal processor, and determine whether the current state is a working state; In response to determining that the current state is a working state, controlling the output trigger pin to be in a high state; In response to determining that the current state is the waiting state, the output trigger pin is controlled to be in a low state.

6. The method according to claim 1, characterized in that The adapter chip receives a data packet sent by the host computer and transmits the data packet to the digital signal processor, including: The adapter chip receives data packets sent from the host computer via the USB bus; The adapter chip converts digital communication into serial communication, and transmits the data packet to the digital signal processor via the TTL232 serial port.

7. The method according to claim 1, characterized in that After the digital signal processor determines the working mode, retrieves the target encryption algorithm corresponding to the working mode from the program storage module, and encrypts the plaintext information according to the key using the target encryption algorithm to obtain encrypted data, the method further includes: The digital signal processor sends the encrypted data to the adapter chip via the TTL232 serial port; The adapter chip converts serial communication into digital communication and transmits the encrypted data to the host computer via the USB bus.

8. A digital signal encryption system based on different working modes, characterized in that: include: Adapter chip, digital signal processor and program storage module; The adapter chip is configured to receive a data packet sent from the host computer and transmit the data packet to the digital signal processor; The digital signal processor is configured to parse the data packet to obtain plaintext information and a key; The digital signal processor is configured to determine an operating mode, retrieve a target encryption algorithm corresponding to the operating mode from the program storage module, and encrypt the plaintext information according to the key using the target encryption algorithm to obtain encrypted data.

9. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 7.

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