Chisel limit model detection acceleration method and system based on control flow and data flow information

Abstract

The invention discloses a Chisel limit model detection acceleration method and system based on control flow and data flow information, and belongs to the field of formal verification of hardware design. The method comprises the following steps: compiling a to-be-verified program to obtain an FIRRTL intermediate representation in a compiling process and an FIRRTL abstract syntax tree of the to-be-verified program; according to the FIRRTL abstract syntax tree, obtaining branch structure information of a to-be-verified program; in combination with the FIRRTL abstract syntax tree, performing assertion-based slicing on a to-be-verified program, and retaining an FIRRTL intermediate representation related to assertion; generating a migration system S based on the FIRRTL intermediate representation related to the assertion; and detecting the to-be-verified program based on the migration system S and the branch structure information. According to the method, the BMC verification process of hardware design generated by Chisel can be accelerated by using the control flow and data flow information in the program.

Description

Technical Field

[0001] The present invention belongs to the field of formal verification of hardware design, and in particular relates to a Chisel bounded model detection acceleration method and system based on control flow and data flow information. Background Art

[0002] Chisel is an open source hardware construction language for hardware design proposed by the University of California, Berkeley. It is embedded in the Scala language, which allows hardware developers to use Scala's language features and programming paradigms to construct complex hardware modules. Since Scala is an object-oriented and functional language, Chisel allows users to describe circuits more concisely, perform modular and parameterized designs, and has been widely used in the design of RISC-V processors, such as Rocket Chip and NutShell. In order to ensure the correctness of the hardware design, formal verification techniques such as Bounded Model Checking (BMC) are used to verify the correctness of the design.

[0003] Bounded model checking is a technique commonly used in formal verification. In hardware verification, it aims to verify whether the hardware design satisfies the property within a given clock cycle. BMC symbolically explores all feasible circuit executions within a finite number of clock cycles to check whether the circuit behavior violates the property. The behavior of the circuit can be defined as the transition relationship between circuit states. BMC expands the transition relationship k times (k is a predefined bound) to obtain a set of SMT formulas, which are input into the SMT solver for solution. If the solver gives a set of satisfiable assignments, it proves that the property can be violated, otherwise it proves that the circuit satisfies the given property within the first k clock cycles. BMC has been introduced into the hardware design generated by Chisel.

[0004] Currently, most SMT solvers (including Z3) work based on the DPLL(T) framework. Figure 1 As shown in the figure, DPLL(T) first performs Boolean abstraction on the input formula, replaces the atomic formula in the formula with Boolean variables, and solves it by combining the SAT solver and the theoretical solver. DPLL(T) iteratively assigns values ​​to the variable by selecting a Boolean variable and performing unit clause propagation. If there is no conflict after all Boolean variables are assigned, and the theoretical solver checks that there is no violation of the theory, the solution is valid; otherwise, when a conflict occurs, backtrack and make a new decision until a conflict-free solution is found or it is determined that there is no solution. In this process, the order in which the Boolean variables are selected has a great impact on the efficiency of the solution.

[0005] The formal verification process of the existing Chisel hardware design verification framework ChiselTest is to compile the Chisel program into a FIRRTL intermediate representation, and then convert it into a migration system. The migration system is further encoded into the SMT2 format through BMC. The SMT solver is usually used as a back-end solver, but the SMT solver is aimed at general constraint solving and cannot obtain high-level information in the program. The control flow and data flow information in the program can be used in the solver's variable selection strategy to improve the solving efficiency.

[0006] Therefore, the existing verification technology has the following main disadvantages:

[0007] 1) Low verification efficiency: The SMT solver used as the backend by the ChiselTest verification framework adopts a general algorithm for constraint solving, which fails to utilize the high-level structural information in the program, has a large search space, and has low solving efficiency.

[0008] 2) Lack of targeted optimization strategies: The control flow information in the program can be used to guide the search process of the SMT solver; data flow analysis of the program can use application slicing to directly reduce the space of the program to be verified. Summary of the invention

[0009] In view of the main problems of the prior art being low verification efficiency and lack of optimization methods for Chisel BMC verification, the present invention provides a Chisel bounded model detection acceleration method and system based on control flow and data flow information, aiming to accelerate the BMC verification process of hardware design generated by Chisel by utilizing the control flow and data flow information in the program.

[0010] To achieve the above objectives, the technical solution of the present invention includes the following contents.

[0011] A Chisel bounded model detection acceleration method based on control flow and data flow information, the method comprising:

[0012] Compile the program to be verified to obtain the FIRRTL intermediate representation in the compilation process and the FIRRTL abstract syntax tree of the program to be verified;

[0013] According to the FIRRTL abstract syntax tree, the branch structure information of the program to be verified is obtained; wherein the branch structure information includes: the order between branch conditions or the edge information of the branch condition graph;

[0014] In combination with the FIRRTL abstract syntax tree, the program to be verified is sliced ​​based on assertions, and the FIRRTL intermediate representation related to the assertions is retained; wherein the assertions are obtained based on the Chisel program;

[0015] Generate a migration system S based on the FIRRTL intermediate representation associated with the assertion;

[0016] The program to be verified is detected based on the migration system S and the branch structure information.

[0017] Furthermore, in combination with the FIRRTL abstract syntax tree, assertion-based slicing is performed on the program to be verified, and the FIRRTL intermediate representation related to the assertion is retained, including:

[0018] Traverse the FIRRTL abstract syntax tree and build a data flow graph;

[0019] Performing graph reachability analysis on the data flow graph, and obtaining signals in the assertion and a set of nodes on which the signals depend based on the analysis results; wherein the signals include: ports and registers;

[0020] For any FIRRTL intermediate representation, if the signals referenced by the FIRRTL intermediate representation are not in the set of signals in the assertion and the signal dependency nodes, the FIRRTL intermediate representation is not retained.

[0021] Further, according to the FIRRTL abstract syntax tree, the branch structure information of the program to be verified is obtained, including:

[0022] Identify the branch structure in the FIRRTL abstract syntax tree, and build a branch structure graph with branch conditions as nodes and branch nesting relationships as edges;

[0023] Perform topological sorting on the branch structure graph to obtain the order between branch conditions;

[0024] The branch conditions are numbered according to the order between the branch conditions and stored through the FIRRTL built-in data structure annotation;

[0025] or,

[0026] Identify the branch structure in the FIRRTL abstract syntax tree, and use the branch conditions as nodes and the branch nesting relationships as edges to build a branch structure graph.

[0027] The edge information in the branch structure graph is stored in the FIRRTL built-in data structure annotation; wherein each edge of the branch structure graph corresponds to an annotation in the FIRRTL built-in data structure annotation.

[0028] Furthermore, the detection of the program to be verified is performed based on the migration system S and the branch structure information, including:

[0029] The branch structure information is encoded into the migration system S to obtain the migration system S′ ;

[0030] Migrate system S ′ After k steps of expansion, it is encoded into an SMT file;

[0031] The SMT file is solved using a solver to obtain a detection result of the program to be verified.

[0032] Furthermore, in the case where the branch structure information is the order between branch conditions, the branch structure information is encoded into the migration system S to obtain the migration system S ′ ,include:

[0033] Obtain the node corresponding to the branch condition in the migration system S from the FIRRTL built-in data structure annotation;

[0034] Modify the node identifier to obtain the migration system S ′ .

[0035] Furthermore, in the case where the branch structure information is the side information of the branch condition graph, the branch structure information is encoded into the migration system S to obtain the migration system S ′ ,include:

[0036] Traversing the annotation list of the FIRRTL built-in data structure annotation to locate each edge of the branch structure graph to a corresponding node in the migration system S;

[0037] Encode the edge information into the node identifier of the migration system S, and obtain the migration system S ′ .

[0038] Furthermore, the migration system S ′ Expand k steps, including:

[0039] Get Migration System S ′ The number of branch nodes in m;

[0040] Based on the number m of branch nodes, the migration system S ′ The identifier of the node and the expansion step number i in the middle, modify the migration system S ′ The identifier of the node in the migration system S ′ The expansion result.

[0041] Furthermore, the solver includes: an SMT solver, a boolector solver or an improved SMT solver; wherein the improved SMT solver is to obtain corresponding branch variables based on the order between branch conditions when the DPLL (T) framework makes a decision to select a Boolean variable and when all branch variables have not been decided, the process of obtaining the order between branch conditions includes:

[0042] In the case where the branch structure information is the order between branch conditions, based on the migration system S ′ Get the identifier of the node in the expansion result;

[0043] In the case where the branch structure information is the side information of the branch condition graph, based on the migration system S ′ The edge information is obtained by using the identifier of the node in the expansion result, and after reconstructing the branch condition graph according to the edge information, the order between the branch conditions is obtained based on the reconstructed branch condition graph.

[0044] A Chisel bounded model detection acceleration system based on control flow and data flow information, the system comprising:

[0045] A program compilation module is used to compile the program to be verified, and obtain the FIRRTL intermediate representation in the compilation process and the FIRRTL abstract syntax tree of the program to be verified;

[0046] A control flow analysis module, used for obtaining branch structure information of the program to be verified according to the FIRRTL abstract syntax tree; wherein the branch structure information includes: the order between branch conditions or the edge information of the branch condition graph;

[0047] A data flow analysis module, used for slicing the program to be verified based on assertions in combination with the FIRRTL abstract syntax tree, and retaining the FIRRTL intermediate representation related to the assertions; wherein the assertions are obtained based on the Chisel program;

[0048] A system generation module is used to generate a migration system S based on the FIRRTL intermediate representation related to the assertion;

[0049] A program detection module is used to detect the program to be verified based on the migration system S and the branch structure information.

[0050] An electronic device comprises: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the Chisel bounded model detection acceleration method based on control flow and data flow information described in any one of the above items is implemented.

[0051] Compared with the prior art, the present invention has at least the following beneficial effects.

[0052] 1) The present invention reduces the search space by giving priority to branch variables when making decisions. Experiments show that the total solution time of the present invention on two open source processors, riscv-mini and Nutshell, is reduced from 27670.00s to 8899.62s.

[0053] 2) The present invention combines data flow information for slicing. By deleting statements that are not related to the assertions to be verified, the size of the program to be verified is reduced. Experiments show that through data flow optimization, the total solution time of the present invention on two open source processors, riscv-mini and Nutshell, is reduced from 27670.00s to 17812.36s; combined with control flow optimization, it is reduced from 27670.00s to 7425.20s. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is the framework diagram of DPLL(T).

[0055] Figure 2 This is a flowchart of the Chisel bounded model detection acceleration method based on control flow and data flow information. DETAILED DESCRIPTION

[0056] The present invention is described in detail below with reference to the accompanying drawings and embodiments. It should be pointed out that the described embodiments are only intended to facilitate the understanding of the present invention and do not have any limiting effect on the present invention.

[0057] The present invention is based on Chisel compiler FIRRTL, ChiselTest framework and Z3 SMT solver, and its process is as follows: Figure 2 As shown, the specific steps include the following steps.

[0058] Step 1: Analyze program control flow information in the High FIRRTL stage.

[0059] Add a compilation process to the FIRRTL compiler, traverse the FIRRTL abstract syntax tree to identify the branch structure (such as when...otherwise...), and build a branch structure graph with branch conditions as nodes and branch nesting relationships as edges. Perform topological sorting on the branch structure graph to obtain the order between branch conditions. Number the branch conditions according to the order and store them through the FIRRTL built-in data structure annotation so that the information can be passed on throughout the compilation process.

[0060] Step 2: Slice the program based on assertions in the low FIRRTL stage and only keep signals related to assertions.

[0061] Traverse the FIRRTL abstract syntax tree, build a data flow graph, and obtain the set of signals and their dependent nodes in the assertion through graph reachability analysis. For all FIRRTL intermediate representations, if the signals (ports, registers, etc.) they reference are not in the set of assertion signals and their dependent nodes, they will not be retained.

[0062] Step 3: Encode the branch structure information into the migration system.

[0063] After generating the migration system, traverse the annotation list, find the corresponding node in the migration system for each annotation, extract the node sequence information, and encode it by modifying the node identifier in the migration system. For example, if the sequence number of node T is 5, change its identifier to T_#5.

[0064] Step 4: Expand the branch structure information to k cycles.

[0065] During the BMC verification process, ChiselTest expands the migration system k steps and encodes it into SMT. For the i-th step of the expansion, the variable encoding T_#j is modified to T_#j', where j'=i*m+j, and m is the number of branch nodes.

[0066] Step 5: Use the solver to solve the problem.

[0067] The back-end solver can choose different solvers and implement corresponding decision heuristic methods under the DPLL(T) framework, such as SMT, boolector and other solvers.

[0068] In one embodiment, the smt file obtained by ChiselTest encoding is passed to the Z3 SMT solver for solving. In the SMT solver, the DPLL framework will select a Boolean variable when making a decision, and decide the value of this Boolean variable. The present invention modifies the method of selecting variables when making a decision: when the branch variables are not all decided, the branch variables are selected first, and the order of selecting the branch variables is based on the order encoded in the variable identifier.

[0069] In addition, since the purpose of encoding in step 3 is to pass the control flow information to the solver, the encoding method can be changed. Therefore, the present invention also provides another implementation method. The difference between this implementation method and the above implementation method is that the branch structure diagram is stored in the annotation during control flow analysis, and each edge of the branch structure diagram corresponds to an annotation. As the compilation process proceeds, these annotations will be passed in each stage. After the migration system is generated, the annotation list is traversed, and according to each annotation, the corresponding node in the migration system is located, and the edges stored in the annotation are encoded into the migration system node identifier. When solving, the encoding information is used to restore the branch structure diagram in the solver, and the order between variables is calculated in the solver.

[0070] In summary, the present invention inserts a compilation process into the FIRRTL compiler to obtain control flow information, establishes a branch structure diagram, and topologically sorts the branch variables as a basis for the subsequent input solver to determine the decision order, and the decision process is modified in the solver to determine the decision order based on the order between variables derived in advance. The branch structure actually contains the following information: when the Boolean variable represented by the when branch condition is decided to be true or false, the Boolean variable represented by the statement in the block should also be assigned the same Boolean value. Therefore, the priority selection of branch variables can make the statements in the block be assigned at the same time, otherwise it may be necessary to explore more assignment combinations. In addition, the hardware last connection semantics indicates that the last connection in multiple connection operations for the same signal is effective. This results in that if the same signal is connected in multiple when statement blocks of the same level, the when branch variable at the last position should be given priority.

[0071] The present invention combines control flow optimization with data flow optimization. In addition to proposing to use program control flow information to accelerate BMC solving, the present invention introduces data flow-based slicing technology on this basis. By deleting statements irrelevant to the assertions to be verified, the code fragments to be verified are reduced, and the program space to be verified is directly reduced.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art should understand that any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention, and the protection scope shall be based on that defined in the claims.

Claims

1. A Chisel bounded model detection acceleration method based on control flow and data flow information, characterized in that: The method comprises: Compile the program to be verified to obtain the FIRRTL intermediate representation in the compilation process and the FIRRTL abstract syntax tree of the program to be verified; According to the FIRRTL abstract syntax tree, the branch structure information of the program to be verified is obtained; wherein the branch structure information includes: the order between branch conditions or the edge information of the branch condition graph; In combination with the FIRRTL abstract syntax tree, the program to be verified is sliced ​​based on assertions, and the FIRRTL intermediate representation related to the assertions is retained; wherein the assertions are obtained based on the Chisel program; Generate a migration system S based on the FIRRTL intermediate representation associated with the assertion; The program to be verified is detected based on the migration system S and the branch structure information.

2. The method according to claim 1, characterized in that Combined with the FIRRTL abstract syntax tree, the program to be verified is sliced ​​based on assertions, and the FIRRTL intermediate representation related to the assertions is retained, including: Traverse the FIRRTL abstract syntax tree and build a data flow graph; Performing graph reachability analysis on the data flow graph, and obtaining signals in the assertion and a set of nodes on which the signals depend based on the analysis results; wherein the signals include: ports and registers; For any FIRRTL intermediate representation, if the signals referenced by the FIRRTL intermediate representation are not in the set of signals in the assertion and the signal dependency nodes, the FIRRTL intermediate representation is not retained.

3. The method according to claim 1, characterized in that According to the FIRRTL abstract syntax tree, the branch structure information of the program to be verified is obtained, including: Identify the branch structure in the FIRRTL abstract syntax tree, and build a branch structure graph with branch conditions as nodes and branch nesting relationships as edges; Perform topological sorting on the branch structure graph to obtain the order between branch conditions; The branch conditions are numbered according to the order between the branch conditions and stored through the FIRRTL built-in data structure annotation; or, Identify the branch structure in the FIRRTL abstract syntax tree, and use branch conditions as nodes and branch nesting relationships as edges to build a branch structure graph. The edge information in the branch structure graph is stored in the FIRRTL built-in data structure annotation; wherein each edge of the branch structure graph corresponds to an annotation in the FIRRTL built-in data structure annotation.

4. The method according to claim 3, characterized in that Detecting the program to be verified based on the migration system S and the branch structure information includes: The branch structure information is encoded into the migration system S to obtain the migration system S ′ ; Migrate system S ′ After k steps of expansion, it is encoded into an SMT file; The SMT file is solved using a solver to obtain a detection result of the program to be verified.

5. The method according to claim 4, characterized in that In the case where the branch structure information is the order between branch conditions, the branch structure information is encoded into the migration system S to obtain the migration system S ′ ,include: Obtain the node corresponding to the branch condition in the migration system S from the FIRRTL built-in data structure annotation; Modify the node identifier to obtain the migration system S ′ .

6. The method according to claim 4, characterized in that In the case where the branch structure information is the side information of the branch condition graph, the branch structure information is encoded into the migration system S to obtain the migration system S ′ ,include: Traversing the annotation list of the FIRRTL built-in data structure annotation to locate each edge of the branch structure graph to a corresponding node in the migration system S; Encode the edge information into the node identifier of the migration system S, and obtain the migration system S ′ .

7. The method according to claim 4, characterized in that The migration system S ′ Expand k steps, including: Get Migration System S ′ The number of branch nodes in m; Based on the number m of branch nodes, the migration system S ′ The identifier of the node and the expansion step number i in the middle, modify the migration system S ′ The identifier of the node in the migration system S ′ The expansion result.

8. The method according to claim 4, characterized in that The solver includes: an SMT solver, a boolector solver or an improved SMT solver; wherein the improved SMT solver is to obtain corresponding branch variables based on the order between branch conditions when the DPLL (T) framework makes a decision to select a Boolean variable and when all branch variables have not been decided, the process of obtaining the order between branch conditions includes: In the case where the branch structure information is the order between branch conditions, based on the migration system S ′ Get the identifier of the node in the expansion result; In the case where the branch structure information is the side information of the branch condition graph, based on the migration system S ′ The edge information is obtained by using the identifier of the node in the expansion result, and after reconstructing the branch condition graph according to the edge information, the order between the branch conditions is obtained based on the reconstructed branch condition graph.

9. A Chisel bounded model detection acceleration system based on control flow and data flow information, characterized in that: The system comprises: A program compilation module is used to compile the program to be verified, and obtain the FIRRTL intermediate representation in the compilation process and the FIRRTL abstract syntax tree of the program to be verified; A control flow analysis module, used for obtaining branch structure information of the program to be verified according to the FIRRTL abstract syntax tree; wherein the branch structure information includes: the order between branch conditions or the edge information of the branch condition graph; A data flow analysis module, used for slicing the program to be verified based on assertions in combination with the FIRRTL abstract syntax tree, and retaining the FIRRTL intermediate representation related to the assertions; wherein the assertions are obtained based on the Chisel program; A system generation module is used to generate a migration system S based on the FIRRTL intermediate representation related to the assertion; A program detection module is used to detect the program to be verified based on the migration system S and the branch structure information.

10. An electronic device, characterized in that: The electronic device comprises: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the Chisel bounded model detection acceleration method based on control flow and data flow information as described in any one of claims 1 to 8 is implemented.

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