Rule-based automatic layout method for PCB function modules

Abstract

The invention discloses a rule-based automatic layout method for PCB (printed circuit board) functional modules, which belongs to the technical field of PCB layout design and comprises the following steps of: reading and writing related data; identifying the types of the function modules of the automatic layout, and performing multi-terminal network splitting based on schematic diagram data according to the types of the modules; defining layout priorities for the split networks and layout devices according to the types of the function modules; constructing a surface layer wiring performance quantitative index of the layout result; establishing a mixed variable multi-objective optimization model for performing automatic layout on the module device, solving a Pareto optimal solution set of the model by utilizing a multi-objective optimization algorithm, and selecting a global layout result of the PCB function module according to layout preference; and legalizing and post-processing the global layout result. According to the automatic layout method, a high-quality module automatic layout result is obtained through automatic optimization of wiring performance, and the accuracy and attractiveness of the device layout position are further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB layout design, and in particular to an automatic layout method of a PCB functional module based on rules. Background Art

[0002] In the PCB physical design process, PCB layout design is of utmost importance. The PCB layout results will have a significant impact on the downstream processes of physical design such as wiring and simulation. A good PCB layout design is the basis for the PCB circuit to be in good working condition.

[0003] Due to the large number of PCB design scenarios, the complex geometry and electrical constraints in different scenarios bring great difficulties to the modeling of automatic layout. In the traditional design process, experienced layout engineers use EDA software to perform manual layout design. The repeated design of modules with the same or similar components in the PCB and the repeated iteration of the physical design process consume a lot of manpower and material resources. The automatic layout algorithm of functional modules can liberate layout engineers from repetitive work with low technical content, and improve the efficiency of PCB layout and even the entire design process.

[0004] Although large EDA software all include functions for automatic layout of PCBs, these software only place components in sequence according to network connection relationships, or establish simple optimization layout models for solving based on netlist data and device specification data. The automatic layout results cannot meet the complex geometric and electrical constraints in the corresponding scenarios, and the accuracy of device layout positions is poor. Currently, the design of PCB automatic layout algorithms mostly adopts the technical route of VLSI layout planning: using B*-tree or sequence-equivalent compact layout coding to build a combinatorial optimization model for automatic layout, and then using an efficient intelligent optimization algorithm for solving. However, the performance of the solution algorithm of the combinatorial optimization model will drop sharply as the scale increases. The layout based on compact coding is difficult to handle the complex geometric constraints in the layout scenario, resulting in the quality of the automatic layout results being difficult to meet the requirements. Summary of the invention

[0005] The purpose of the present invention is to provide a rule-based automatic layout method for PCB functional modules to solve the problems mentioned in the background technology.

[0006] To achieve the above object, the present invention provides a rule-based automatic layout method for PCB functional modules, which is implemented through five modules: a schematic-based network splitting module, a network and device priority definition module, a surface routability modeling module, a hybrid decision variable optimization modeling and solution module, and an automatic layout DFM rule optimization module;

[0007] The specific steps of the automatic layout method are as follows:

[0008] Step S1: Read the type, size and pin data of the automatically laid out components and write them into the "Module_BasicInfo.txt" file; read the netlist information and write the network connection relationship and network attributes into the "Net_Info.txt" file; read the schematic structured data and write the device and pin data into the "Schematic_Info.txt" file; read the DFM rule data and store it into the "DFM_Rule.txt" file; the network connection data includes the network connection relationship, network attributes, etc.;

[0009] Step S2: Read the type data of components from the "Module_BasicInfo.txt" file, and identify the type of functional modules according to the type of IC devices; read the netlist information and schematic diagram data, call the schematic-based network splitting module to split the netlist according to the type of functional modules, and write the type of functional modules and the netlist splitting results into the "Net_Info.txt" file;

[0010] Step S3: Read the module and netlist information, call the network and device priority definition module according to the functional module type to define the network and device priority, and write them into files respectively;

[0011] Step S4: reading layout device information and netlist information, and constructing surface routability quantitative indicators using a surface routability modeling module;

[0012] Step S5: read the network and device priority data, call the hybrid decision variable optimization modeling and solution module to build a hybrid variable multi-objective optimization model and solve it to obtain the automatic optimization layout result, and then save the automatic optimization layout result into a file;

[0013] Step S6: read the module global layout and DFM rule data, call the automatic layout DFM rule optimization module to legalize and optimize the layout results, and write the layout results into a file;

[0014] Step S7: Read the layout result from the file, and convert the layout result into the layout file data format used by the user according to the user's needs.

[0015] Preferably, step S2 specifically comprises:

[0016] Step S21: Read the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and pass in the function module type;

[0017] Step S22: parsing the device name and connection point coordinate data from the schematic structured data, and matching the relevant network from the netlist information;

[0018] Step S23: starting from the pins of the main IC device, locating related devices according to the association relationship between the main IC device and the auxiliary devices in the netlist information, and grouping the layout auxiliary devices according to the coordinates of the auxiliary device connection points and the IC device pin coordinates in the schematic diagram using a clustering algorithm;

[0019] Step S24: traverse the pins of each main IC device and the corresponding grouped auxiliary devices, sort the grouped devices according to the pin coordinates of the main IC device in the schematic diagram and the connection point coordinates of the auxiliary devices in the schematic diagram, and obtain multiple two-terminal networks after splitting according to the sorting results;

[0020] Step S25: Store the split netlist information into the "Net_Info.txt" file.

[0021] Preferably, step S3 specifically comprises:

[0022] Step S31: Read module and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the functional module type;

[0023] Step S32: defining the network connection priority according to the module type and the network type;

[0024] Step S33: defining device priority according to device type and associated network type;

[0025] Step S34: defining the priority of the device placement orientation according to the module type, network type and device type;

[0026] Step S35: Write the network priority and the device priority into the "Net_Priority.txt" and "Module_Priority.txt" files respectively.

[0027] Preferably, step S4 is specifically:

[0028] Step S41: Read the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the functional module type;

[0029] Step S42: matching the netlist information according to the device information, identifying the network connection between the main chip device and the auxiliary device, and the network connection between the auxiliary devices;

[0030] Step S43: performing disorderly escape according to the position of the IC device pins on the IC device, and fanning out the IC device pins to the periphery of the device; grouping the auxiliary devices according to the placement positions in the network, and using an ordered escape algorithm to escape the pins connecting the auxiliary devices to the IC device and fan out to one side of the IC device;

[0031] Step S44: group and match the fan-out sequence of the IC device with the fan-out sorting position of the attached device, and define the quantitative index of the surface routability in the matching result;

[0032] Step S45: Calculate the quantitative index according to the device placement information and pass it to the hybrid decision variable optimization modeling and solution module.

[0033] Preferably, step S5 is specifically:

[0034] Step S51: Read layout device and netlist information from "Module_BasicInfo.txt" and "Net_Info.txt" files, read network and device priority data from "Net_Priority.txt" and "Module_Priority.txt" files, and input layout preference information;

[0035] Step S52: construct layout quality quantitative indicators with the rotation angle vector Θ, the horizontal coordinate vector X and the vertical coordinate vector Y of all modules as independent variables: call the surface routability modeling module to construct routability quantitative indicators N(Θ,X,Y); construct the automatic layout line length indicator L(Θ,X,Y), layout area indicator S(Θ,X,Y) and overlap constraint indicator O(Θ,X,Y) according to the network and device priority data;

[0036] Step S53: Establish a mixed variable constraint multi-objective optimization model with the device rotation direction and coordinates as decision variables, routability, line length and layout area as objective functions, and overlap area as a constraint:

[0037]

[0038] Step S54: Utilize the efficient mixed variable multi-objective optimization problem to solve the optimization model and obtain the Pareto optimal solution set NS of the multi-objective optimization model:

[0039] NS={(Θ1,X1,Y1),(Θ2,X2,Y2),…,(Θ n ,X n ,Y n )};

[0040] Step S55: determine whether there is a layout preference; if there is a layout preference, go to step S56; if there is no layout preference, go to step S57;

[0041] Step S56: Determine the weight vector K of the optimization target according to the layout preference, and construct a metric for evaluating the non-dominated solutions in NS. Obtain the automatic optimization layout result from the Pareto optimal solution set, and go to step S58. Specifically, the metric for evaluating the non-dominated solutions in NS is:

[0042] f(N(Θ,X,Y),L(Θ,X,Y),S(Θ,X,Y),K);

[0043] Step S57: Select the layout solution corresponding to the Knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58;

[0044] Step S58: Save the automatic optimization layout result into the "Global_Placement.txt" file.

[0045] Preferably, step S6 specifically comprises:

[0046] Step S61: Read module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in module type information;

[0047] Step S62: Determine the post-processing principle of module layout according to the module data, and judge whether the main IC device and the auxiliary device are arranged on different surfaces; if they are arranged on different surfaces, go to step S63; if they are not arranged on different surfaces, go to step S64;

[0048] Step S63: Legalize the layout result according to the different-plane layout rules and DFM setting data, and go to step S67;

[0049] Step S64: determine whether it is a single-master IC device module layout or a multi-master IC device module layout scenario; if it is a single-master IC device module layout, go to step S65; if it is not a single-master IC device module layout, go to step S66;

[0050] Step S65: According to the principle of single main IC device functional module layout, the module layout result is post-processed with the main IC device as the center, and then the process goes to step S67;

[0051] Step S66: According to the principle of multi-main IC device functional module layout, the module layout result is post-processed with the main IC device as the center and each main IC and auxiliary device cooperating with each other, and then the process goes to step S67;

[0052] Step S67: Write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

[0053] Therefore, the present invention adopts the above-mentioned rule-based automatic layout method of PCB functional modules, which has the following beneficial effects:

[0054] (1) Rapidly generate automatic layout results of functional module devices based on existing layout data files, and can be imported into common PCB design EDA software, greatly reducing the workload of engineers in repeated design of functional modules in PCB layout design and improving PCB layout design efficiency;

[0055] (2) The present invention relates to modeling, solving and simulation technology for complex optimization problems of PCB automatic layout, and more specifically, to a method for realizing automatic layout of circuit components based on designed circuit data, which can be used for automatic layout of components when PCB modules with the same or similar functions are repeatedly designed;

[0056] (3) The present invention can automatically place the main components and auxiliary components constituting the functional module according to the device attributes of the module and the netlist data to realize the automatic layout of the functional module, greatly improve the repeated design efficiency of the functional module in the PCB board, and shorten the PCB physical design process;

[0057] (4) The present invention utilizes efficient optimization technology of complex optimization models and proposes an automated layout technology for repeated design scenarios of functional modules in PCBs. The technology can realize automatic layout of functional modules based on network connection data, module device parameters, schematic diagrams, and design intentions of senior layout engineers, thereby greatly improving the design efficiency of PCBs.

[0058] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a module structure block diagram of an embodiment of the present invention;

[0060] Figure 2 A flowchart of a rule-based automatic layout method for PCB functional modules according to an embodiment of the present invention;

[0061] Figure 3 is a flow chart of step S2 of an embodiment of the present invention;

[0062] Figure 4 is a flowchart of step S3 of an embodiment of the present invention;

[0063] Figure 5 is a flowchart of step S4 of an embodiment of the present invention;

[0064] Figure 6 is a flow chart of step S5 of an embodiment of the present invention;

[0065] Figure 7 is a flow chart of step S6 of an embodiment of the present invention;

[0066] Reference numerals

[0067] 101. Automatic layout data preprocessing stage; 102. Module automatic optimization layout stage; 103. Automatic layout post-processing stage; 104. Schematic-based network splitting module; 105. Network and device priority definition module; 106. Surface routability modeling module; 107. Hybrid decision variable optimization modeling and solution module; 108. Automatic layout DFM rule optimization module. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0069] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0070] Example

[0071] like Figure 1 As shown, the present invention provides a rule-based automatic layout method for PCB functional modules, which includes three stages: an automatic layout data preprocessing stage 101, a module automatic optimization layout stage 102, and an automatic layout post-processing stage 103. The method is implemented by five modules: a schematic-based network splitting module 104, a network and device priority definition module 105, a surface routability modeling module 106, a hybrid decision variable optimization modeling and solution module 107, and an automatic layout DFM rule optimization module 108. Among them, the main key technologies of the automatic layout data preprocessing stage are implemented by the schematic-based network splitting module 104 and the network and device priority definition module 105; the module automatic optimization layout stage 102 is implemented by the surface routability modeling module 106 and the hybrid decision variable optimization modeling and solution module 107; and the automatic layout post-processing stage is implemented by the automatic layout DFM rule optimization module 108.

[0072] like Figure 2 As shown, the specific steps of this method are as follows:

[0073] Step S1: Read the type, size and pin data of the automatically laid out components and write them into the "Module_BasicInfo.txt" file; read the netlist information and write the network connection relationship and network properties into the "Net_Info.txt" file; read the schematic structured data and write the device and pin data into the "Schematic_Info.txt" file; read the DFM rule data and store it in the "DFM_Rule.txt" file.

[0074] Step S2: Read the component type data from the "Module_BasicInfo.txt" file, and identify the functional module type according to the IC device type; read the netlist information and schematic diagram data, call the schematic-based network splitting module 104 to split the netlist according to the functional module type, and write the functional module type and netlist splitting results into the "Net_Info.txt" file.

[0075] Step S3: Read the module and netlist information, call the network and device priority definition module 105 according to the functional module type to define the network and device priorities, and write them into files respectively.

[0076] Step S4: Read layout device information and netlist information, and use the surface routability modeling module 106 to construct a surface routability quantitative index.

[0077] Step S5: read the network and device priority data, call the hybrid decision variable optimization modeling and solving module 107 to build a hybrid variable multi-objective optimization model and solve it to obtain the automated optimization layout result, and then save the automated optimization layout result into a file.

[0078] Step S6: Read the module global layout and DFM rule data, call the automatic layout DFM rule optimization module 108 to legalize and optimize the layout results, and write the layout results into a file.

[0079] Step S7: Read the layout result from the file, and convert the layout result into the layout file data format used by the user according to the user's needs, so as to facilitate its import into the adopted PCB design EDA software.

[0080] In this embodiment, if Figure 3 As shown, step S2 is specifically as follows:

[0081] Step S21: Read the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and pass in the functional module type.

[0082] Step S22: parse the device name and connection point coordinate data from the schematic structured data, and match the relevant network from the netlist information.

[0083] Step S23: Starting from the pins of the main IC device, locate the related devices according to the association relationship between the main IC device and the auxiliary devices in the netlist information, and use a clustering algorithm to group the layout auxiliary devices according to the coordinates of the auxiliary device connection points in the schematic diagram and the coordinates of the IC device pins.

[0084] Step S24: traverse the pins of each main IC device and the corresponding grouped auxiliary devices, sort the grouped devices according to the pin coordinates of the main IC device in the schematic diagram and the connection point coordinates of the auxiliary devices in the schematic diagram, and obtain multiple two-terminal networks after splitting according to the sorting results.

[0085] Step S25: Store the split netlist information into the "Net_Info.txt" file.

[0086] The schematic-based multi-terminal network splitting module 104 realizes the multi-terminal network splitting based on the parseable schematic data, and reduces the freedom of network connection representation and device location by reducing the number of devices / pins in the network, thereby greatly improving the accuracy of device location in automatic layout design.

[0087] In this embodiment, if Figure 4 As shown, step S3 is specifically as follows:

[0088] Step S31: Read module and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the functional module type.

[0089] Step S32: Define the network connection priority according to the module type and the network type.

[0090] Step S33: Define device priority according to device type and associated network type.

[0091] Step S34: defining the priority of the device placement orientation according to the module type, network type and device type.

[0092] Step S35: Write the network priority and the device priority into the "Net_Priority.txt" and "Module_Priority.txt" files respectively.

[0093] The network and device priority definition module 105 standardizes and defines the priorities according to the network connection attributes in the functional modules, realizes the optimal placement of layout devices based on the priorities, and obtains the automated layout results that comply with the physical design rules.

[0094] In this embodiment, if Figure 5 As shown, step S4 is specifically as follows:

[0095] Step S41: Read the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the functional module type. The layout device information is the IC device pin information.

[0096] Step S42: matching the netlist information according to the device information, identifying the network connection between the main chip device and the auxiliary device, and the network connection between the auxiliary devices.

[0097] Step S43: Perform disorderly escape according to the position of the IC device pins on the IC device, and fan out the IC device pins to the periphery of the device; group the auxiliary devices according to their placement in the network, and use an ordered escape algorithm to escape the pins connecting the auxiliary devices to the IC device and fan out to one side of the IC device.

[0098] Step S44: group and match the fan-out sequence of the IC device with the fan-out sorting position of the attached device, and define the quantitative index of the surface routability in the matching result.

[0099] Step S45: Calculate the quantitative index according to the device placement information and pass it to the hybrid decision variable optimization modeling and solving module 107.

[0100] In response to the surface routing requirements of the functional modules, the surface routability modeling module 106 constructs a low-complexity routability quantitative modeling strategy, and obtains high-quality module automatic layout results through automatic optimization of routability.

[0101] In this embodiment, if Figure 6 As shown, step S5 is implemented by the hybrid decision variable optimization modeling and solution module 107, specifically:

[0102] Step S51: Read layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files, read network and device priority data from the "Net_Priority.txt" and "Module_Priority.txt" files, and input layout preference information.

[0103] Step S52: Construct layout quality quantitative indicators using the rotation angle vector Θ, the horizontal coordinate vector X and the vertical coordinate vector Y of all modules as independent variables: call the surface routability modeling module 106 to construct routability quantitative indicators N(Θ,X,Y); construct the automatic layout line length indicator L(Θ,X,Y), layout area indicator S(Θ,X,Y) and overlap constraint indicator O(Θ,X,Y) according to the network and device priority data.

[0104] Step S53: Establish a mixed variable constraint multi-objective optimization model with the device rotation direction and coordinates as decision variables, routability, line length and layout area as objective functions, and overlap area as a constraint:

[0105]

[0106] Step S54: Utilize the efficient mixed variable multi-objective optimization problem to solve the optimization model and obtain the Pareto optimal solution set NS of the multi-objective optimization model:

[0107] NS={(Θ1,X1,Y1),(Θ2,X2,Y2),…,(Θ n ,X n ,Y n )}.

[0108] Step S55: Determine whether there is a layout preference; if there is a layout preference, go to step S56; if there is no layout preference, go to step S57.

[0109] Step S56: Determine the weight vector K of the optimization target according to the layout preference, and construct a metric for evaluating the non-dominated solutions in NS. Obtain the automatic optimization layout result from the Pareto optimal solution set, and go to step S58. Specifically, the metric for evaluating the non-dominated solutions in NS is:

[0110] f(N(Θ,X,Y),L(Θ,X,Y),S(Θ,X,Y),K).

[0111] Step S57: Select the layout solution corresponding to the Knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58.

[0112] Step S58: Save the automatic optimization layout result into the "Global_Placement.txt" file.

[0113] In this embodiment, if Figure 7 As shown, step S6 is implemented by the automatic layout DFM rule optimization module 108, specifically:

[0114] Step S61: Read module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in module type information.

[0115] Step S62: Determine the module layout post-processing principle according to the module data, and judge whether the main IC device and the auxiliary device are arranged on different surfaces; if so, go to step S63; if not, go to step S64.

[0116] Step S63: Legalize the layout result according to the different-plane layout rules and DFM setting data, and go to step S67.

[0117] Step S64: Determine whether it is a single-master IC device module layout or a multi-master IC device module layout scenario; if it is a single-master IC device module layout, go to step S65; if it is not a single-master IC device module layout, go to step S66.

[0118] Step S65: According to the principle of single main IC device functional module layout, the module layout result is post-processed with the main IC device as the center, and then go to step S67.

[0119] Step S66: According to the principle of multi-main IC device functional module layout, the module layout result is post-processed with the main IC device as the center and each main IC and auxiliary device cooperating with each other, and then go to step S67.

[0120] Step S67: Write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

[0121] The automatic layout DFM rule optimization module 108 adopts a device coordinate continuous movement strategy for complex irregular layout area constraints, and further optimizes the layout results in combination with the disturbance of the module orientation; for different scenarios such as off-plane layout of main IC devices and auxiliary devices, single-sided layout of single main IC devices, and module layout of multiple main IC devices, layout legalization and optimization strategies for layout module types are designed.

[0122] Therefore, the present invention adopts the above-mentioned rule-based automatic layout method of PCB functional modules, establishes a hybrid decision variable optimization model for the layout optimization problem, and designs an efficient solution algorithm to realize the automatic layout of module devices. This modeling optimization method can adapt to the complex geometric constraints in different layout scenarios, and can perform customized automatic layout of functional modules for different PCB manufacturing processes and technical requirements.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A rule-based automatic layout method for PCB functional modules, characterized in that: The automatic layout method is implemented by a schematic-based network splitting module, a network and device priority definition module, a surface routability modeling module, a hybrid decision variable optimization modeling and solving module, and an automatic layout DFM rule optimization module; The specific steps of the automatic layout method are as follows: Step S1: Read the type, size and pin data of the automatically laid out components and write them into the "Module_BasicInfo.txt" file; read the netlist information and write the network connection relationship and network attributes into the "Net_Info.txt" file; read the schematic structured data and write the device and pin data into the "Schematic_Info.txt" file; read the DFM rule data and store it into the "DFM_Rule.txt" file; Step S2: Read the type data of components from the "Module_BasicInfo.txt" file, and identify the type of functional modules according to the type of IC devices; read the netlist information and schematic diagram data, call the schematic diagram-based network splitting module to split the netlist according to the type of functional modules, and write the type of functional modules and the netlist splitting results into the "Net_Info.txt" file; Step S3: Read the module and netlist information, call the network and device priority definition module according to the functional module type to define the network and device priority, and write them into files respectively; Step S4: reading layout device information and netlist information, and constructing surface routability quantitative indicators using a surface routability modeling module; Step S5: read the network and device priority data, call the hybrid decision variable optimization modeling and solution module to build a hybrid variable multi-objective optimization model and solve it to obtain the automatic optimization layout result, and then save the automatic optimization layout result into a file; Step S6: read the module global layout and DFM rule data, call the automatic layout DFM rule optimization module to legalize and optimize the layout results, and write the layout results into a file; Step S7: Read the layout result from the file, and convert the layout result into the layout file data format used by the user according to the user's needs.

2. The rule-based automatic layout method of PCB functional modules according to claim 1, characterized in that: Step S2 is specifically as follows: Step S21: Read the netlist information and schematic structured data from the "Net_BasicInfo.txt" and "Schematic_Info.txt" files respectively, and pass in the function module type; Step S22: parsing the device name and connection point coordinate data from the schematic structured data, and matching the relevant network from the netlist information; Step S23: starting from the pins of the main IC device, locating related devices according to the association relationship between the main IC device and the auxiliary devices in the netlist information, and grouping the layout auxiliary devices according to the coordinates of the auxiliary device connection points and the IC device pin coordinates in the schematic diagram using a clustering algorithm; Step S24: traverse the pins of each main IC device and the corresponding grouped auxiliary devices, sort the grouped devices according to the pin coordinates of the main IC device in the schematic diagram and the connection point coordinates of the auxiliary devices in the schematic diagram, and obtain multiple two-terminal networks after splitting according to the sorting results; Step S25: Store the split netlist information into the "Net_Info.txt" file.

3. The rule-based automatic layout method of PCB functional modules according to claim 1, characterized in that: Step S3 is specifically as follows: Step S31: Read the module and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the function module type; Step S32: defining the network connection priority according to the module type and the network type; Step S33: defining device priority according to device type and associated network type; Step S34: defining the priority of the device placement orientation according to the module type, network type and device type; Step S35: Write the network priority and the device priority into the "Net_Priority.txt" and "Module_Priority.txt" files respectively.

4. The rule-based automatic layout method of PCB functional modules according to claim 1, characterized in that: Step S4 is specifically as follows: Step S41: Read the layout device and netlist information from the "Module_BasicInfo.txt" and "Net_Info.txt" files respectively, and pass in the functional module type; Step S42: matching the netlist information according to the device information, identifying the network connection between the main chip device and the auxiliary device, and the network connection between the auxiliary devices; Step S43: performing disorderly escape according to the position of the IC device pins on the IC device, and fanning out the IC device pins to the periphery of the device; grouping the auxiliary devices according to the placement positions in the network, and using the escape algorithm to orderly escape the pins connecting the auxiliary devices to the IC device and fan out to one side of the IC device; Step S44: group and match the fan-out sequence of the IC device with the fan-out sorting position of the attached device, and define the quantitative index of the surface routability in the matching result; Step S45: Calculate the quantitative index according to the device placement information and pass it to the hybrid decision variable optimization modeling and solution module.

5. The rule-based automatic layout method of PCB functional modules according to claim 1, characterized in that: Step S5 is specifically as follows: Step S51: Read layout device and netlist information from "Module_BasicInfo.txt" and "Net_Info.txt" files, read network and device priority data from "Net_Priority.txt" and "Module_Priority.txt" files, and input layout preference information; Step S52: construct layout quality quantitative indicators with the rotation angle vector Θ, the horizontal coordinate vector X and the vertical coordinate vector Y of all modules as independent variables: call the surface routability modeling module to construct routability quantitative indicators N(Θ,X,Y); construct the automatic layout line length indicator L(Θ,X,Y), layout area indicator S(Θ,X,Y) and overlap constraint indicator O(Θ,X,Y) according to the network and device priority data; Step S53: Establish a mixed variable constraint multi-objective optimization model with the device rotation direction and coordinates as decision variables, routability, line length and layout area as objective functions, and overlap area as a constraint: Step S54: Utilize the efficient mixed variable multi-objective optimization problem to solve the optimization model and obtain the Pareto optimal solution set NS of the multi-objective optimization model: NS={(Θ1,X1,Y1),(Θ2,X2,Y2),…,(Θ n ,X n ,Y n )}; Step S55: determining whether there is a layout preference; If there is a layout preference, go to step S56; If there is no layout preference, go to step S57; Step S56: Determine the weight vector K of the optimization target according to the layout preference, and construct a metric for evaluating the non-dominated solutions in NS. The automatic optimization layout result is obtained from the Pareto optimal solution set, and then go to step S58. The metric for evaluating the non-dominated solutions in NS is: f(N(Θ,X,Y),L(Θ,X,Y),S(Θ,X,Y),K); Step S57: Select the layout solution corresponding to the Knee point from the Pareto frontier as the automatic optimization layout result, and go to step S58; Step S58: Save the automatic optimization layout result into the "Global_Placement.txt" file.

6. The rule-based automatic layout method of PCB functional modules according to claim 1, characterized in that: Step S6 is specifically as follows: Step S61: Read module layout and DFM rule data from "Global_Placement.txt" and "DFM_Rule.txt" respectively, and pass in module type information; Step S62: Determine the post-processing principle of module layout according to the module data, and judge whether the main IC device and the auxiliary device are arranged on different surfaces; if they are arranged on different surfaces, go to step S63; if they are not arranged on different surfaces, go to step S64; Step S63: Legalize the layout result according to the different-plane layout rules and DFM setting data, and go to step S67; Step S64: determine whether it is a single-master IC device module layout or a multi-master IC device module layout scenario; if it is a single-master IC device module layout, go to step S65; if it is not a single-master IC device module layout, go to step S66; Step S65: According to the principle of single main IC device functional module layout, the module layout result is post-processed with the main IC device as the center, and then the process goes to step S67; Step S66: According to the principle of multi-main IC device functional module layout, the module layout result is post-processed with the main IC device as the center and each main IC and auxiliary device cooperating with each other, and then the process goes to step S67; Step S67: Write the layout result into the "Placement.txt" file, and convert the layout result into the layout file data format used by the user according to the user's needs.

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