An automatic routing method for EDA circuit schematic display

Abstract

This invention discloses an automatic routing method for EDA circuit schematic display, including step S1: obtaining the connection relationships and coordinate sets of components, and dividing the components into hierarchical channels; step S2: sorting the connection relationships and coordinate sets, finding the two furthest points to determine the horizontal path of the bus, classifying the coordinate points to determine the vertical range of the bus, identifying non-conflicting tracks as vertical paths, and combining the horizontal and vertical paths to determine the bus path; step S3: determining the branch path from the bus to each pin based on the horizontal coordinate of the vertical path in the hierarchical channel and the coordinates of each pin; step S4: obtaining the vertical range of the hierarchical channel, comparing it with the vertical range of the bus, determining the vertical path of the branch line, integrating the horizontal path and the branch path to each pin, and determining the overall path of the branch line. Compared with the prior art, this invention optimizes the utilization space of the channels, reduces intersections, standardizes the routing sequence, and makes the routing more compact and aesthetically pleasing.

Description

Technical Field

[0001] This invention relates to the field of electronic automation design, and in particular to an automatic wiring method for displaying EDA circuit schematics. Background Technology

[0002] Circuit diagram display plays a crucial role in EDA (Electronic Design Automation) software design. EDA software is typically used to design, simulate, and verify electronic circuits, and the circuit diagram display function is one of the main interfaces for users to interact with the circuit design. It not only makes the circuit design process more intuitive and efficient but also allows engineers to visually inspect the circuit design, enabling them to promptly identify and correct errors in the design process, helping them achieve accuracy, reliability, and maintainability in their circuit designs. Automatic wiring is a key step in circuit diagram display. Circuit wiring reflects the connection relationships of circuit component ports and signal flow. In complex designs, a large number of wirings are often required; therefore, efficient automatic wiring methods can shorten wiring time and reduce the engineer's observation costs. Furthermore, when designing automatic wiring methods for circuit diagrams, certain rules and constraints must be met based on the actual application context to ensure the rationality and practicality of the wiring.

[0003] Currently, the common automatic routing technologies used for circuit diagram display include channel algorithms and heuristic search algorithms. There are also automatic routing methods that consider integrating different algorithms. [1] proposes to divide the routing process into horizontal channels and vertical channels, use heuristic search algorithms to allocate horizontal channels, and use dynamic perception search technology to allocate vertical channels, making full use of the circuit layout information to reduce the search process. [2] proposes a connection arrangement algorithm between channels, which focuses on the area between levels and avoids the situation of horizontal line segment overlap by splitting vertical line segments. However, in actual large-scale complex circuits, there are also cross-level connections and feedback connections, so additional constraints are needed to optimize the direction of the connections. [3] proposes the entire circuit schematic layout and routing process. For the routing part, the idea of ​​using common vertical lines is used to allocate multiple lines, and a column gap compression algorithm based on greedy algorithm is proposed to reduce the distance between columns and improve the aesthetics of the circuit diagram. Similarly, this routing algorithm only focuses on the connection direction between channels and does not provide a detailed description of the global routing.

[0004] However, the above algorithm only considers the connection path and does not consider the relationship between the bus and the branch line. It simply connects from one port to another and then represents the entire path using the bus. However, in actual circuits, some pins are connected to branch lines. For example, there is a bus called addr[3:0] and pins called p1 and p2. p1 is connected to branch line addr[0] and p2 is connected to branch line addr[1]. That is, p1 is connected to bit 0 of the bus addr and p2 is connected to bit 1 of the bus addr. The above algorithm does not consider how to distinguish between the bus path and the branch line path. Instead, it represents the entire path using the bus addr[3:0]. This is not a clear representation of the circuit and is not conducive to circuit designers analyzing the circuit.

[0005] Therefore, there is an urgent need for an automatic routing method for EDA circuit schematic display that is aesthetically pleasing, has a fast layout speed, and does not have the characteristics of line overlap. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention discloses an automatic routing method for EDA circuit schematic display, comprising:

[0007] Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and perform hierarchical layout of the components and divide the hierarchical channels.

[0008] Step S2: Sort the connection relationships of all components and their corresponding coordinate sets, find the two coordinate points that are farthest apart to determine the horizontal path of the bus, then classify the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and sort the vertical ranges to determine the non-conflicting tracks as the vertical path of the bus. Combine the horizontal and vertical paths of the bus to determine the bus path.

[0009] Step S3: Determine the branch path from the bus to each pin based on the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component.

[0010] Step S4: Based on the coordinate set corresponding to the connection relationship of the branch lines, obtain the vertical range of each level channel, compare it with the vertical range of the bus in the level channel to determine the vertical path of the branch line, integrate the horizontal path of the bus and the branch line path from the bus to each component pin, and determine the overall path of the branch line.

[0011] Furthermore, step S1 also includes:

[0012] When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located on the left boundary of the component where the upper and lower pins are located, and the ordinate value of the virtual pin is the ordinate value after shifting the ordinate of the actual upper and lower pins of the component upward or downward by one cell.

[0013] Furthermore, step S2 includes:

[0014] Step S21: Sort the connection relationships of all components and their corresponding coordinate sets to find the two coordinate points that are farthest apart, and determine the preset vertical coordinates according to the linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinates. The horizontal coordinates of the two endpoints of the horizontal line segment are the horizontal coordinates of the two coordinate points that are farthest apart.

[0015] Step S22: Obtain the maximum and minimum values ​​of the vertical coordinates of the pins of the components in each hierarchical channel, and compare them with the preset vertical coordinates to determine the vertical range of the hierarchical channel;

[0016] Step S23: Sort the set of longitudinal ranges in each of the hierarchical channels, and allocate non-conflicting tracks as longitudinal paths of the bus in the hierarchical channels in a preset order, and obtain the horizontal coordinates of the longitudinal paths.

[0017] Step S24: Connect the horizontal line segment to the vertical path, and use the resulting path as the bus path.

[0018] Furthermore, step S23 also includes:

[0019] The set of preset vertical ranges in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical ranges in the current track are compared with other tracks in order from front to back to determine whether there is a conflict between the vertical ranges in the current track and the vertical ranges of the previous track.

[0020] If the determination is negative, the vertical range of the current track is assigned to the previous track, the current track is deleted, the current track is set as the next track, and the process is repeated for each track.

[0021] If the judgment is yes, then the current track is compared with the next preceding track.

[0022] Furthermore, step S3 includes:

[0023] Step S31: Obtain the set of vertical paths connecting the pins of each component in the hierarchical channel;

[0024] Step S32: Compare the horizontal coordinate values ​​in the set of vertical paths, obtain the vertical path that is farthest from the current pin, and obtain a horizontal path that connects to the current pin without crossing any components from the vertical path. Connect the horizontal path with the vertical path in step S23.

[0025] Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

[0026] Furthermore, step S32 includes:

[0027] After obtaining the vertical path that is furthest from the current pin in the set of vertical paths, determine whether the horizontal connection between the current pin and the vertical path that is furthest from the current pin can be made to not coincide with other horizontal connections.

[0028] If the determination is negative, a linear search is performed from the current pin position to the farthest vertical path to find a vertical line that does not overlap with any vertical path.

[0029] Connect the current pin horizontally to the vertical line to determine one end of the vertical line;

[0030] Connect the other end of the vertical line to the longitudinal path to obtain a horizontal line segment. When the vertical line coincides with other horizontal line segments, shift the horizontal line segment upward by one unit length.

[0031] The vertical line, the horizontal line connecting the vertical line to the current pin, and the horizontal line segment connecting the vertical path are connected to form the horizontal path from the vertical path of the bus to the current pin.

[0032] Furthermore, step S4 includes:

[0033] Step S41: Based on the coordinate set corresponding to the connection relationship of the branch line, sort the coordinate set of the connection relationship of the branch line to determine the two points that are farthest apart, integrate the horizontal path of the bus, and determine the horizontal path of the branch line.

[0034] Step S42: Based on the vertical coordinate of the pin of the hierarchical channel and the vertical coordinate of the horizontal path of the branch line, obtain the vertical range of the branch line in the hierarchical channel; based on the horizontal coordinate of the bus in the vertical path of the hierarchical channel, obtain the vertical path of the branch line in the hierarchical channel.

[0035] Step S43: Determine the overall path of the branch line based on its horizontal path and its vertical path in the hierarchical channel.

[0036] Compared with the prior art, the present invention has at least the following beneficial effects:

[0037] This invention introduces a vertical sorting algorithm for hierarchical channels, which optimizes the use of channel space, reduces intersections, and standardizes the wiring sequence, making the overall wiring more compact and aesthetically pleasing.

[0038] Meanwhile, when designing branching paths, the present invention only performs wiring when a line segment that does not overlap with the longitudinal path is found, thus the present invention also avoids line overlap to a greater extent.

[0039] This invention can efficiently display circuit schematics. Compared with heuristic routing algorithms, this invention reduces a large number of search operations and inflection point setting operations, thus significantly improving the speed of determining connection paths.

[0040] Furthermore, this invention can effectively handle complex circuits and components, not only displaying the complete bus connection path but also distinguishing between bus paths and branch paths. This invention is also applicable to non-bus connection relationships; therefore, compared to existing technologies, this invention can more completely display the connection information of the circuit design. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of the automatic routing method for EDA circuit schematic display provided by the present invention;

[0043] Figure 2 This is a flowchart of determining the bus path provided by the present invention;

[0044] Figure 3 This is a flowchart of the process for determining the branch path from the bus path to the pin, provided by the present invention.

[0045] Figure 4 This is a flowchart of determining the overall circuit path provided by the present invention;

[0046] Figure 5 This is a schematic diagram of the connection relationship provided by the present invention.

[0047] Figure 6 This is a schematic diagram of the hierarchical channel provided by the present invention;

[0048] Figure 7 This is a schematic diagram of the bus path determination of the horizontal line segment provided by the present invention;

[0049] Figure 8This is a schematic diagram of the vertical line segment sorting algorithm provided by the present invention;

[0050] Figure 9 This is a schematic diagram of the bus path provided by the present invention;

[0051] Figure 10 This is a schematic diagram of the branching path from the bus path to the pin provided by the present invention;

[0052] Figure 11 This is a schematic diagram of the overall circuit path provided in an embodiment of the present invention. Detailed Implementation

[0053] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0054] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0055] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0056] Existing algorithms only consider the connection path and do not consider the relationship between the bus and the branch lines. They simply connect from one port to another and represent the entire path using the bus. However, in actual circuits, some pins are connected to branch lines. For example, there may be a bus line called addr[3:0] and pins called p1 and p2. p1 is connected to branch line addr[0] and p2 is connected to branch line addr[1]. That is, p1 is connected to bit 0 of the bus addr and p2 is connected to bit 1 of the bus addr. The above algorithms do not consider how to distinguish between the bus path and the branch line path. Instead, they represent the entire path using the bus addr[3:0]. This is not a clear representation of the circuit and is not conducive to circuit designers analyzing the circuit.

[0057] To address the above problems, this invention relates to an automatic routing method for EDA circuit schematic display, comprising:

[0058] Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and perform hierarchical layout of the components and divide the hierarchical channels.

[0059] Step S2: Sort the connection relationships of all components and their corresponding coordinate sets, find the two coordinate points that are farthest apart to determine the horizontal path of the bus, then classify the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and sort the vertical ranges to determine the non-conflicting tracks as the vertical path of the bus. Combine the horizontal and vertical paths of the bus to determine the bus path.

[0060] Step S3: Determine the branch path from the bus to each pin based on the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component.

[0061] Step S4: Based on the coordinate set corresponding to the connection relationship of the branch lines, obtain the vertical range of each level channel, compare it with the vertical range of the bus in the level channel to determine the vertical path of the branch line, integrate the horizontal path of the bus and the branch line path from the bus to each component pin, and determine the overall path of the branch line.

[0062] Please see Figure 1 This is a flowchart of the entire invention. Figure 1 As can be seen from this, the present invention is mainly divided into four processes, among which "obtaining the coordinate set of connection relationship" is also step S1 in the above process;

[0063] "Determine the bus path" is step S2 in the above process;

[0064] "Divergent determination of the bus path to the pin branch path" is also step S3 in the above process.

[0065] "Determine the overall path of the branch line" is step S4 in the above process.

[0066] In step S1 above, the following is also included:

[0067] When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located on the left boundary of the component where the upper and lower pins are located, and the ordinate value of the virtual pin is the ordinate value after shifting the ordinate of the actual upper and lower pins of the component upward or downward by one cell.

[0068] That is, for special pins, such as the top and bottom pins of a component, a virtual pin is introduced. This virtual pin is located on the left boundary of the component, and its y-value in the Cartesian coordinate system is shifted upward or downward by one cell from the y-value of the top and bottom pins of the component.

[0069] The virtual pin is added to the coordinate set of the connection relationship for calculation. When calculating the branch path, the horizontal and vertical paths from the virtual pin to the actual upper and lower pins need to be added at the end.

[0070] Furthermore, step S2 above includes:

[0071] Step S21: Sort the connection relationships of all components and their corresponding coordinate sets to find the two coordinate points that are farthest apart, and determine the preset vertical coordinates according to the linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinates. The horizontal coordinates of the two endpoints of the horizontal line segment are the horizontal coordinates of the two coordinate points that are farthest apart.

[0072] Step S22: Obtain the maximum and minimum values ​​of the vertical coordinates of the pins of the components in each hierarchical channel, and compare them with the preset vertical coordinates to determine the vertical range of the hierarchical channel;

[0073] Step S23: Sort the set of longitudinal ranges in each of the hierarchical channels, and allocate non-conflicting tracks as longitudinal paths of the bus in the hierarchical channels in a preset order, and obtain the horizontal coordinates of the longitudinal paths.

[0074] Step S24: Connect the horizontal line segment to the vertical path, and use the resulting path as the bus path.

[0075] Please see Figure 2 This is a flowchart of the process for determining the bus path in this invention. Figure 2 As can be seen from this, the bus path determination process of the present invention is mainly divided into four steps, among which "the two points P1(x1, y1) and p2(x2, y2) that are farthest apart are determined by a linear search algorithm within the range of [x1, x2]" is the process of determining the horizontal line segment in step S21 above.

[0076] "Determining the vertical range of the hierarchical channel" is the same as step S22 above;

[0077] "Sorting the set of vertical ranges of the hierarchical channels to determine the vertical path" is the same as step S23 above;

[0078] "Obtaining the bus path" is the same as step S24 above.

[0079] Please see Figure 5 This is a schematic diagram of the connection relationship of the circuit to be analyzed in this invention. The circuit contains five components: A, B, C, D, and E. Figure 5 The connection relationship between the addr[4:0] bus and the new_addr[10:0] bus is shown, where ellipses represent pins, rounded rectangles and thick arrows represent buses, and thin arrows represent sub-lines;

[0080] Figure 6This is a schematic diagram of the hierarchical channel in the present invention, wherein the hierarchical channel is the range from the right edge of the widest component to the left edge of the component in the next level after the components are laid out in layers.

[0081] Please see Figure 7 This is a flowchart of obtaining the horizontal line segment in step S21 above, which firstly based on... Figure 5 In step S21, taking the addr[4:0] bus as an example, the coordinate set corresponding to the given connection relationship can find the two points a2(x1, y1) and d5(x2, y2) that are farthest apart. Then, through the linear search algorithm, a y value is found, and a line segment AB that does not cross the components and does not overlap with other line segments is obtained.

[0082] The line segment AB mentioned above is the same as the horizontal line segment obtained in step S21 above.

[0083] Furthermore, step S23 in this invention further includes:

[0084] The set of preset vertical ranges in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical ranges in the current track are compared with other tracks in order from front to back to determine whether there is a conflict between the vertical ranges in the current track and the vertical ranges of the previous track.

[0085] If the determination is negative, the vertical range of the current track is assigned to the previous track, the current track is deleted, the current track is set as the next track, and the process is repeated for each track.

[0086] If the judgment is yes, then the current track is compared with the next preceding track.

[0087] Please see Figure 8 This is a flowchart of obtaining the horizontal coordinate of the vertical path in step S23 above. In step S22, the vertical range of each connection relationship in the hierarchical channel can be obtained, and the set of vertical ranges in the hierarchical channel S{R1,R2,R3,…} can be obtained.

[0088] Then, the vertex values ​​of the vertical range are sorted from smallest to largest. Starting from the sorting order, it is tested whether the line segment with the larger vertex value can fill the same track occupied by the line segment with the smaller vertex value without any range conflict. If so, it is assigned to the track; otherwise, it will try to traverse the next track in the same way. After determining the order of the vertical path of the line segment, the physical position of the line segment is determined.

[0089] Here, "testing whether the line segment with the larger vertex value can fill the same track occupied by the line segment with the smaller vertex value, and whether there is a range conflict" is the same as "determining whether there is a conflict between the longitudinal range of the current track and the longitudinal range of the track ahead" mentioned earlier.

[0090] "If yes, it is assigned to a track," which is the same as the previous statement: "When it is determined to be yes, the vertical range of the current track is assigned to the previous track, the current track is deleted, the current track is set as the next track, and the tracks are traversed one by one."

[0091] The above-described sorting method of the present invention can make the overall circuit diagram more aesthetically pleasing and improve space utilization.

[0092] Please see Figure 9 This is a schematic diagram of obtaining the bus path in this invention. After steps S22 and S23, the paths of buses such as addr[4:0] and new_addr[10:0] can be obtained. Figure 9 The middle part is represented by a thick solid line.

[0093] Furthermore, step S3 above includes:

[0094] Step S31: Obtain the set of vertical paths connecting the pins of each component in the hierarchical channel;

[0095] Step S32: Compare the horizontal coordinate values ​​in the set of vertical paths, obtain the vertical path that is farthest from the current pin, and obtain a horizontal path that connects to the current pin without crossing any components from the vertical path. Connect the horizontal path with the vertical path in step S23.

[0096] Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

[0097] Please see Figure 3 This is a flowchart for determining the branching path in this invention. Figure 2 As can be seen from this, the process of determining the branch path of the present invention is mainly divided into three steps, among which "obtaining the set of horizontal coordinates of the vertical path of the pin in the hierarchical channel" is the above-mentioned step S31.

[0098] "Determine the longest path from the bus path to the pin among multiple connection relationships" is also the "compare the horizontal coordinate values ​​in the set of vertical paths, obtain the vertical path that is farthest from the current pin, and obtain the horizontal path that connects to the current pin without crossing any components from the vertical path" in step S32 above. Step S32 is expressed as obtaining the horizontal path that connects to the pin from the vertical path that is farthest from the pin, which also corresponds to the longest path.

[0099] "Based on the x value of the bus path in the hierarchical channel for each connection relationship, the path of the bus path to the pin for each connection relationship can be obtained, and the branch line information is attached." This is the above step S33. In this process, the branch line information is attached, which is the branch line path in the above step S33.

[0100] Specifically, step S32 in this invention further includes the following steps:

[0101] After obtaining the vertical path that is furthest from the current pin in the set of vertical paths, determine whether the horizontal connection between the current pin and the vertical path that is furthest from the current pin can be made to not coincide with other horizontal connections.

[0102] If the determination is negative, a linear search is performed from the current pin position to the farthest vertical path to find a vertical line that does not overlap with any vertical path.

[0103] Connect the current pin horizontally to the vertical line to determine one end of the vertical line;

[0104] Connect the other end of the vertical line to the longitudinal path to obtain a horizontal line segment. When the vertical line coincides with other horizontal line segments, shift the horizontal line segment upward by one unit length.

[0105] The vertical line, the horizontal line connecting the vertical line to the current pin, and the horizontal line segment connecting the vertical path are connected to form the horizontal path from the vertical path of the bus to the current pin.

[0106] Please see Figure 10 This is a schematic diagram illustrating the branch path from the bus path to the pin in this invention. Figure 10 In the diagram, pins b1[2:0] are connected to the e[1:0] bus and the d[1:0] bus;

[0107] According to steps S31 and S32, the pin furthest from the pin is e[1:0], and its x-coordinate is known to be x. max .Depend on Figure 10 It can be seen that if a straight line is drawn directly from e[1:0] to b1[2:0], there is line overlap. Therefore, starting from d1[2:0], in (x, x max Within the range of x, find the line segment B'(x) that does not coincide with other vertical line segments. mid ,y-UNIT_GAP)C'(x mid ,y+UNIT_GAP).

[0108] Determine x mid After the value, in the range [x mid x max The search yielded line segment A(x).mid ,y mid )B(x max ,y mid Line segment AB does not coincide with other line segments and does not cross any components. Determine y. mid Then, the common branch path A->B->C->D can be obtained. According to step S33, the branch paths from bus e[1:0] and bus d[1:0] to pin b1[2:0] can be determined respectively. For the case where a single pin has multiple connection relationships, we use diagonal lines to distinguish the paths in the view.

[0109] according to Figure 3 The process shown in the figure involves calculating the bus path to the pin branch path for each connection relationship in the embodiment.

[0110] After obtaining the branch path through the above process, the overall path of the circuit to be analyzed can be obtained by combining the bus path and the branch path. Specifically, step S4 above includes:

[0111] Step S41: Based on the coordinate set corresponding to the connection relationship of the branch line, sort the coordinate set of the connection relationship of the branch line to determine the two points that are farthest apart, integrate the horizontal path of the bus, and determine the horizontal path of the branch line.

[0112] Step S42: Based on the vertical coordinate of the pin of the hierarchical channel and the vertical coordinate of the horizontal path of the branch line, obtain the vertical range of the branch line in the hierarchical channel; based on the horizontal coordinate of the bus in the vertical path of the hierarchical channel, obtain the vertical path of the branch line in the hierarchical channel.

[0113] Step S43: Determine the overall path of the branch line based on its horizontal path and its vertical path in the hierarchical channel.

[0114] Please see Figure 4 This is a flowchart illustrating the overall path determination of the branch lines in this invention. Figure 4 As can be seen from this, the process of determining the overall path of the branch line in this invention is mainly divided into four steps. Among them, "based on the coordinate set of the connection relationship of the branch line, the vertical range of the hierarchical channel can be obtained. The vertical range of the hierarchical channel is compared with the y value obtained by the bus in step S21 to determine the y value of the overall path of the branch line. The x value of the hierarchical channel is assigned to the path of the branch line", which is equivalent to the process of obtaining the vertical range of the branch line in the hierarchical channel in step S41 above. The y value here is also the preset vertical coordinate in step S21.

[0115] "Using the hierarchical channel x value obtained from the bus path in step S22 as the hierarchical channel x value of the overall path of the branch line" is equivalent to the process of obtaining the horizontal coordinate value of the branch line in step S42 above.

[0116] "Add the bus path to the pin branch path obtained in step S3 to the branch path to obtain the final overall branch path," which is equivalent to the process of obtaining the overall branch path in step S43 above. Please refer to [link to relevant documentation]. Figure 11 This is a schematic diagram of the overall circuit to be analyzed in this invention. Figure 11 As can be seen, it distinguishes between the bus path and the branch path, indicating the information about the branch's connection to the pin. In practical applications, the overall path of the branch can be obtained according to step S4, and then mouse click operations can be added to the view to make the branch path appear above the bus path. Figure 11 The gray path represents the overall path of the sub-line addr[1].

[0117] The process of the present invention will be described in its entirety below, including the following steps:

[0118] Step S1, obtain the coordinate set of connection relationships: read the circuit design file, obtain the information of components and their connection relationships, perform layered layout of components, divide the hierarchical channels, and find the coordinate set of the corresponding pins according to the connection relationships;

[0119] For special pins, such as the top and bottom pins of a component, a virtual pin position is introduced. This virtual pin position is located at the left boundary of the component, and its y-value in the Cartesian coordinate system is shifted upward or downward by one cell from the y-value of the top and bottom pins of the component.

[0120] The virtual pin is added to the coordinate set of the connection relationship for calculation. When calculating the branch path, the horizontal and vertical paths from the virtual pin to the actual upper and lower pins are added at the end.

[0121] Step S2, determining the bus path, consists of the following steps:

[0122] Step S21: Sort the coordinate set of the connection relationship to obtain the two points p1(x1,y1) and p2(x2,y2) that are farthest apart. Then, through a linear search algorithm, find a y value to obtain a line segment that does not cross the component and does not overlap with other line segments. Let the endpoints be A(x1,y) and B(x2,y). This line segment passes through all the level channels corresponding to the coordinate set.

[0123] Step S22: Classify the coordinates in the coordinate set according to the hierarchical channel, and obtain the pin with the minimum and maximum ordinate in the hierarchical channel. Compare the obtained pin ordinate with the y value obtained in step S21 to obtain the vertical range R[y', y”] of the coordinate set in the hierarchical channel.

[0124] Step S23: Sort the set of vertical ranges S{R1,R2,R3,…} of the hierarchical channels in ascending order of vertex value. Starting from the sorting order, test whether the line segment with the larger vertex value can fill the same track occupied by the line segment with the smaller vertex value, and whether there is a range conflict. If so, it is assigned to the track.

[0125] Otherwise, it will try to traverse the next track in the same way;

[0126] The x-coordinate of the coordinate set in the vertical path of the hierarchical channel is determined using this method.

[0127] In step S24, based on the y-value obtained in step S21, the longitudinal range of each level channel obtained in step S22, and the x-value of the level channel obtained in step S23, the bus path can be obtained.

[0128] Step S3, determining the branch path from the bus path to the pin, consists of the following steps:

[0129] Step S31: Because there are multiple pins, that is, there may be multiple sets of coordinates with connection relationships that contain the coordinates of this one multi-pin;

[0130] Based on step S2, the bus path for each connection relationship is obtained, indicating that in the hierarchical channel, the pin may correspond to the x-coordinate value of multiple vertical paths. Let the obtained set be X{x1, x2, x3, ...}.

[0131] Step S32: Sort the set X to obtain the x that is farthest from the pin. max Let the pin coordinates be P(x, y), determine the line segment A(x, y). max If B(x,y) does not coincide with other line segments, then starting from pin P(x,y), perform a linear search to find the line segment in (x,y). max Within the range of x, find the line segment that does not coincide with other vertical line segments, and denote it as C(x). mid ,y-UNIT_GAP)D(x mid ,y+UNIT_GAP), where UNIT_GAP is the minimum spacing between lines.

[0132] Determine x mid After the value, in the range [x mid x max The search yields the horizontal line segment E(x). mid y mid )F(x max y mid Line segment EF does not overlap with other line segments and does not cross components.

[0133] Step S33: Based on steps S31 and S32, obtain the longest bus path to the pin among multiple connection relationships. Then, based on the x value of the bus path in the hierarchical channel for each connection relationship, the path from the bus path to the pin for each connection relationship can be obtained, along with the branch line information.

[0134] Step S4, determine the overall path of the branch line, which consists of the following steps:

[0135] Step S41: Based on the coordinate set of the connection relationship of the branch lines, the vertical range of the hierarchical channel can be obtained. The vertical range of the hierarchical channel is compared with the y value obtained by the bus in step S21 to determine the y value of the horizontal path of the branch line.

[0136] Step S42: Take the x value of the vertical path obtained by the bus path in the hierarchical channel in step S22 as the x value of the vertical path of the branch line in the hierarchical channel.

[0137] Step S43: Add the bus path to the pin obtained in step S3 to the branch line path. Finally, the overall path of the branch line is obtained.

[0138] Based on the automatic routing method for EDA circuit schematic display proposed in this invention, this invention has the following beneficial effects:

[0139] This invention introduces a vertical sorting algorithm for hierarchical channels, which optimizes the use of channel space, reduces intersections, and standardizes the wiring sequence, making the overall wiring more compact and aesthetically pleasing.

[0140] Meanwhile, when designing branching paths, the present invention only performs wiring when a line segment that does not overlap with the longitudinal path is found, thus the present invention also avoids line overlap to a greater extent.

[0141] This invention can efficiently display circuit schematics. Compared with heuristic routing algorithms, this invention reduces a large number of search operations and inflection point setting operations, thus significantly improving the speed of determining connection paths.

[0142] Furthermore, this invention can effectively handle complex circuits and components, not only displaying the complete bus connection path but also distinguishing between bus paths and branch paths. This invention is also applicable to non-bus connection relationships; therefore, compared to existing technologies, this invention can more completely display the connection information of the circuit design.

[0143] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An automatic routing method for displaying EDA circuit schematics, characterized in that, include: Step S1: Read the design file of the circuit to be analyzed, obtain the connection relationship of all components and the corresponding coordinate set, and perform hierarchical layout of the components and divide the hierarchical channels. Step S2: Sort the connection relationships of all components and their corresponding coordinate sets, find the two coordinate points that are farthest apart to determine the horizontal path of the bus, then classify the coordinate points according to the hierarchical channels to determine the vertical range of the bus, and sort the vertical ranges to determine the non-conflicting tracks as the vertical path of the bus. Combine the horizontal and vertical paths of the bus to determine the bus path. Step S3: Determine the branch path from the bus to each pin based on the horizontal coordinate of the vertical path of the bus path in the hierarchical channel and the coordinates of the pins of each component. Step S4: Based on the coordinate set corresponding to the connection relationship of the branch lines, obtain the vertical range of each level channel, compare it with the vertical range of the bus in the level channel to determine the vertical path of the branch line, integrate the horizontal path of the bus and the branch line path from the bus to each component pin, and determine the overall path of the branch line.

2. The automatic routing method for EDA circuit schematic display according to claim 1, characterized in that, Step S1 further includes: When there are upper and lower pins in the circuit to be analyzed, a virtual pin is introduced for the circuit to be analyzed. The virtual pin is located on the left boundary of the component where the upper and lower pins are located, and the ordinate value of the virtual pin is the ordinate value after shifting the ordinate of the actual upper and lower pins of the component upward or downward by one cell.

3. The automatic routing method for EDA circuit schematic display according to claim 1, characterized in that, Step S2 includes: Step S21: Sort the connection relationships of all components and their corresponding coordinate sets to find the two coordinate points that are farthest apart, and determine the preset vertical coordinates according to the linear search algorithm, so that a horizontal line segment that does not cross any component can be obtained through the preset vertical coordinates. The horizontal coordinates of the two endpoints of the horizontal line segment are the horizontal coordinates of the two coordinate points that are farthest apart. Step S22: Obtain the maximum and minimum values ​​of the vertical coordinates of the pins of the components in each hierarchical channel, and compare them with the preset vertical coordinates to determine the vertical range of the hierarchical channel; Step S23: Sort the set of longitudinal ranges in each of the hierarchical channels, and allocate non-conflicting tracks as longitudinal paths of the bus in the hierarchical channels in a preset order, and obtain the horizontal coordinates of the longitudinal paths. Step S24: Connect the horizontal line segment to the vertical path, and use the resulting path as the bus path.

4. The automatic routing method for EDA circuit schematic display according to claim 3, characterized in that, Step S23 further includes: The set of preset vertical ranges in the hierarchical channel is sorted in order according to the vertex value of each vertical range, and each vertical range is preset as a track. Starting from the sorting order, the vertical ranges in the current track are compared with other tracks in order from front to back to determine whether there is a conflict between the vertical ranges in the current track and the vertical ranges of the previous track. If the determination is negative, the vertical range of the current track is assigned to the previous track, the current track is deleted, the current track is set as the next track, and the process is repeated for each track. If the judgment is yes, then the current track is compared with the next preceding track.

5. The automatic routing method for EDA circuit schematic display according to claim 4, characterized in that, Step S3 includes: Step S31: Obtain the set of vertical paths connecting the pins of each component in the hierarchical channel; Step S32: Compare the horizontal coordinate values ​​in the set of vertical paths, obtain the vertical path that is farthest from the current pin, and obtain a horizontal path that connects to the current pin without crossing any components from the vertical path. Connect the horizontal path with the vertical path in step S23. Step S33: Obtain the lateral path of each pin and use it as the branch path from the bus to each pin.

6. The automatic routing method for EDA circuit schematic display according to claim 5, characterized in that, Step S32 includes: After obtaining the vertical path that is furthest from the current pin in the set of vertical paths, determine whether the horizontal connection between the current pin and the vertical path that is furthest from the current pin can be made to not coincide with other horizontal connections. If the determination is negative, a linear search is performed from the current pin position to the farthest vertical path to find a vertical line that does not overlap with any vertical path. Connect the current pin horizontally to the vertical line to determine one end of the vertical line; Connect the other end of the vertical line to the longitudinal path to obtain a horizontal line segment. When the vertical line coincides with other horizontal line segments, shift the horizontal line segment upward by one unit length. The vertical line, the horizontal line connecting the vertical line to the current pin, and the horizontal line segment connecting the vertical path are connected to form the horizontal path from the vertical path of the bus to the current pin.

7. The automatic routing method for EDA circuit schematic display according to claim 6, characterized in that, Step S4 includes: Step S41: Based on the coordinate set corresponding to the connection relationship of the branch line, sort the coordinate set of the connection relationship of the branch line to determine the two points that are farthest apart, integrate the horizontal path of the bus, and determine the horizontal path of the branch line. Step S42: Based on the vertical coordinate of the pin of the hierarchical channel and the vertical coordinate of the horizontal path of the branch line, obtain the vertical range of the branch line in the hierarchical channel; based on the horizontal coordinate of the bus in the vertical path of the hierarchical channel, obtain the vertical path of the branch line in the hierarchical channel. Step S43: Determine the overall path of the branch line based on its horizontal path and its vertical path in the hierarchical channel.

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