A time delay determination method and apparatus, electronic device, and storage medium

Abstract

Embodiments of the present application provide a time delay determination method and device, electronic equipment and storage medium. The scheme is as follows: determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system; in the case that the first line channel and the second line channel establish a link through a first quantum bit, obtaining the relative time delay between the signal transmission time lengths corresponding to the first line channel and the second line channel; finding a first time delay of the first line channel and a second time delay of the second line channel at the current time; updating the first time delay and / or the second time delay based on the first time delay, the second time delay and the relative time delay. Through the technical scheme provided by the embodiments of the present application, the time delay of signal transmission between each pulse modulation line channel and each magnetic flux modulation line channel in the quantum computing measurement and control system is determined, so that the quantum state regulation signal and the quantum bit frequency regulation signal can be transmitted to the quantum bit at the same time, and the accuracy of quantum computing is improved.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and in particular to a method, device, electronic device and storage medium for determining time delay. Background Art

[0002] Quantum computing is a computational model that uses the basic properties of quantum mechanics to solve problems. By building a quantum physics hardware system that can be precisely operated and running quantum computing software to implement quantum algorithms, computational problems can be solved and applied to specific problems or fields.

[0003] During quantum computing, a quantum computing measurement and control system (such as an integrated measurement and control machine) transmits quantum state modulation signals via pulse modulation lines to the interface of the corresponding pulse modulation line (i.e., the XY line) for the qubit. It also transmits qubit frequency control signals via flux modulation lines to the interface of the corresponding flux modulation line (i.e., the Z line) for the same qubit. The qubit performs quantum computing based on the received quantum state control signals and qubit frequency control signals. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a method, apparatus, electronic device, and storage medium for determining the delay in signal transmission between each pulse modulation channel and each flux modulation channel in a quantum computing measurement and control system, thereby ensuring that the quantum state control signal and the qubit frequency control signal can be transmitted to the qubit simultaneously, thereby improving the accuracy of quantum computing. The specific technical solution is as follows:

[0005] An embodiment of the present application provides a method for determining a time delay, the method comprising:

[0006] Determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0007] When the first line channel and the second line channel are linked via the first quantum bit, obtaining a relative delay between corresponding signal transmission times of the first line channel and the second line channel;

[0008] Finding a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays or delays updated before the current moment;

[0009] The first delay and / or the second delay are updated based on the first delay, the second delay, and the relative delay.

[0010] The embodiment of the present application further provides a delay determination device, the device comprising:

[0011] A first determination module is used to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0012] an acquisition module, configured to acquire, when the first line channel and the second line channel are linked via the first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel;

[0013] A first search module is configured to search for a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays or delays updated before the current moment;

[0014] A first updating module is configured to update the first delay and / or the second delay based on the first delay, the second delay, and the relative delay.

[0015] An embodiment of the present application further provides an electronic device, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0016] Memory for storing computer programs;

[0017] The processor is configured to implement any of the above-mentioned delay determination method steps when executing a program stored in the memory.

[0018] An embodiment of the present application further provides a computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned delay determination method steps is implemented.

[0019] An embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-mentioned delay determination methods.

[0020] An embodiment of the present application also provides a quantum computing measurement and control system to implement any of the above-mentioned delay determination methods.

[0021] Beneficial effects of the embodiments of the present invention:

[0022] The technical solution provided by the embodiment of the present invention determines the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system. Then, based on the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the corresponding signal transmission times of the first line channel and the second line channel, the first delay and / or the second delay can be updated, thereby realizing the determination of the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0023] Since the first delay and / or the second delay are updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay match the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0024] In addition, when the first delay or the second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment based on the relative delay between the first line channel or the second line channel and other line channels, then updating the first delay and / or the second delay based on the relative delay between the first line channel and the second line channel can effectively establish the correlation in delay between the various line channels, so that the delays between each of the ultimately determined line channels are correlated with each other, effectively improving the accuracy and correlation of the determined delays. Moreover, if a line channel is replaced, signal transmission can be directly performed based on the determined delay without the need to re-determine the delay, thereby improving the applicability of the determined delay.

[0025] Of course, it is not necessary to achieve all of the advantages described above simultaneously in order to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 A schematic diagram of a first flow chart of a method for determining a time delay provided in an embodiment of the present application;

[0028] Figure 2A second flow chart of the delay determination method provided in an embodiment of the present application;

[0029] Figure 3 A third flow chart of the delay determination method provided in an embodiment of the present application;

[0030] Figure 4 A fourth flow chart of the delay determination method provided in an embodiment of the present application;

[0031] Figure 5 A fifth flow chart of the delay determination method provided in an embodiment of the present application;

[0032] Figure 6 A sixth flow chart of the delay determination method provided in an embodiment of the present application;

[0033] Figure 7 A seventh flow chart of the delay determination method provided in an embodiment of the present application;

[0034] Figure 8 This is a schematic diagram of an eighth flow chart of the delay determination method provided in an embodiment of the present application;

[0035] Figure 9 A ninth flow chart of the method for determining the time delay provided in an embodiment of the present application;

[0036] Figure 10 A tenth flowchart of the delay determination method provided in an embodiment of the present application;

[0037] Figure 11 This is a schematic diagram of an eleventh flow chart of the delay determination method provided in an embodiment of the present application;

[0038] Figure 12 This is a twelfth flow chart of the delay determination method provided in an embodiment of the present application;

[0039] Figure 13 A schematic diagram of the structure of a delay determination device provided in an embodiment of the present application;

[0040] Figure 14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] In related technologies, since the quantum state modulation signal and the quantum bit frequency control signal are transmitted to the quantum bits on the quantum chip through the pulse modulation line channel and the flux modulation line channel respectively, different processing is required for the quantum state modulation signal and the quantum bit frequency control signal, such as noise reduction, coupling and other processing. This makes it impossible for the quantum bit to receive the quantum state modulation signal and the quantum bit frequency control signal at the same time if the quantum computing measurement and control system sends the quantum state modulation signal and the quantum bit frequency control signal at the same time, thereby affecting the quantum computing process of the quantum bit.

[0043] In related technologies, for the XY-line interface and Z-line interface corresponding to each quantum bit, the relative delay between the corresponding signals of the two interfaces is determined, thereby ensuring that the XY-line interface and the Z-line interface can receive signals at the same time, providing a guarantee for the quantum computing process.

[0044] However, since the determined delay is the signal transmission delay corresponding to the XY line interface and Z line interface corresponding to each quantum bit, the delay is only related to the XY line interface and Z line interface corresponding to each quantum bit, and has no correlation with other quantum bits. Moreover, since the delay is only bound to the XY line interface and Z line interface on the quantum bit, once the line channel connected by the XY line interface and the Z line interface changes, that is, when a line switching operation is performed, it is necessary to re-determine the delay between the XY line interface and the Z line interface on the quantum bit.

[0045] In order to solve the problems in the related art, the embodiment of the present application provides a method for determining a time delay. Figure 1 As shown, Figure 1 This is a first flow chart of a method for determining a time delay provided in an embodiment of the present application. The method can be applied to any electronic device and includes the following steps.

[0046] Step S101: determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0047] Step S102 : When a link is established between a first line channel and a second line channel through a first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel is obtained.

[0048] Step S103 , searching for a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0049] Step S104: Update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0050] In an embodiment of the present application, the above-mentioned quantum computing measurement and control system may include devices such as an arbitrary waveform generator and a DC source. Devices such as the arbitrary waveform generator and the DC source may include multiple signal transmission line channels. For the pulse modulation line channel for transmitting the quantum state control signal (i.e., the third line channel hereinafter) and the flux modulation line channel for transmitting the quantum bit frequency control signal (i.e., the fourth line channel hereinafter), the third line channel and the fourth line channel can establish a link through the quantum bit on the quantum chip, that is, the third line channel is connected to the interface of the XY line corresponding to the quantum bit, and the fourth line channel is connected to the interface of the Z line corresponding to the quantum bit.

[0051] In the embodiment of the present application, the quantum computing measurement and control system may include multiple third circuit channels and multiple fourth circuit channels. Here, the number of the third circuit channels and the fourth circuit channels in the quantum computing measurement and control system is not specifically limited.

[0052] pass Figure 1 The method shown in the figure determines the first and second circuit channels to be processed in the quantum computing measurement and control system. Then, based on the first delay of the first circuit channel at the current moment, the second delay of the second circuit channel at the current moment, and the relative delay between the corresponding signal transmission times of the first and second circuit channels, the first delay and / or the second delay can be updated, thereby determining the signal transmission delay between any pulse modulation circuit channel and each flux modulation circuit channel in the quantum computing measurement and control system.

[0053] Since the first delay and / or the second delay are updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay match the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing. In addition, when the first delay or the second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment based on the relative delay between the first line channel or the second line channel and other line channels, then updating the first delay and / or the second delay based on the relative delay between the first line channel and the second line channel can effectively establish the correlation in delay between the various line channels, so that the delays between each of the ultimately determined line channels are correlated with each other, effectively improving the accuracy and correlation of the determined delays. Moreover, if a line channel is replaced, signal transmission can be directly performed based on the determined delay without the need to re-determine the delay, thereby improving the applicability of the determined delay.

[0054] The embodiments of the present application are described below through specific examples.

[0055] With respect to the above step S101, that is, determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system, the first line channel is used to transmit the quantum state control signal, and the second line channel is used to transmit the quantum bit frequency control signal.

[0056] In an embodiment of the present application, for multiple third line channels and multiple fourth line channels included in the quantum computing measurement and control system, the electronic device can obtain any one of the third line channels as the first line channel to be processed, and obtain any one of the fourth line channels as the second line channel to be processed.

[0057] In an optional embodiment, in order to avoid the situation where the determined first line channel and second line channel remain unchanged, the electronic device pre-stores a table or character string indicating whether each third line channel and each fourth line channel have ever established a link through a quantum bit (i.e., the second quantum bit below).

[0058] For ease of understanding, the following description uses a table format, namely the first table, as an example. The value of each cell in the first table indicates whether the third and fourth circuit channels corresponding to the cell have ever established a link via the second qubit. The first table can be shown in Table 1.

[0059] Table 1

[0060] XY / Z Z1 Z2 Z3 … XY1 0 / 1 0 / 1 0 / 1 … XY2 0 / 1 0 / 1 0 / 1 … XY3 0 / 1 0 / 1 0 / 1 … … … … … …

[0061] In Table 1, each row corresponds to a third channel in the quantum computing measurement and control system, and each column corresponds to a fourth channel in the quantum computing measurement and control system. Each cell in Table 1 contains a corresponding third channel, fourth channel, and value.

[0062] In an optional embodiment, the value corresponding to each cell in Table 1 can be a first value, such as 0 in Table 1, or a second value, such as 1 in Table 1. When the value corresponding to a cell is 0, it indicates that before the current moment, the third and fourth circuit channels corresponding to the cell have not established a link via the second qubit. When the value corresponding to a cell is 1, it indicates that before the current moment, the third and fourth circuit channels corresponding to the cell have established a link via the second qubit.

[0063] In an optional embodiment, the initialization value of each cell in Table 1 can be the first value. The first value and the second value can be any value. In the embodiment of the present application, the first value is 0 and the second value is 1 as an example for illustration only, and does not serve any limiting purpose.

[0064] In an optional embodiment, the electronic device can also express the above Table 1 in the form of a string. For ease of understanding, the following example is used to illustrate that the values ​​corresponding to the cells in Table 1 are all the above first values. The above Table 1 can be expressed as

[0065] In the embodiment of the present application, the representation of the first list and the character string is not specifically limited. For ease of understanding, the following description is based on the first list as an example, which does not serve any limiting purpose.

[0066] In an optional embodiment, when determining the first line channel and the second line channel, as shown in FIG. Figure 2 As shown, Figure 2 This is a second flow chart of the delay determination method provided in the embodiment of the present application. Figure 2 In the method shown, the above step S101 is refined into the following steps, namely step S1011.

[0067] Step S1011 , according to the third line channel, fourth line channel and value corresponding to each cell in the first list, determining the third line channel and fourth line channel corresponding to the target cell as the first line channel and the second line channel to be processed.

[0068] The numerical value corresponding to the above-mentioned target cell is a first numerical value, and the first numerical value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

[0069] In this step, the electronic device may traverse each cell in the first list according to a pre-set traversal order, such as row-by-row or column-by-column traversal. During the traversal process, if a cell with the aforementioned first value is found, the cell is determined as the target cell. At this point, the electronic device may determine the third and fourth line channels corresponding to the target cell as the first and second line channels to be processed. In other words, the third line channel corresponding to the target cell is determined as the first line channel to be processed, and the fourth line channel corresponding to the target cell is determined as the second line channel to be processed.

[0070] For ease of understanding, the first list shown in Table 2 is used as an example for explanation.

[0071] Table 2

[0072] XY / Z Z1 Z2 Z3 Z4 XY1 1 0 0 0 XY2 0 0 0 0 XY3 1 1 1 0 XY4 0 0 0 1

[0073] According to Table 2, the above quantum computing measurement and control system includes 4 third line channels, namely XY1-XY4, and 4 fourth line channels, namely Z1-Z4.

[0074] The electronic device can traverse the cells in Table 2 row by row. When traversing the cell corresponding to XY1 and Z1, the electronic device can traverse the next cell, namely the cell corresponding to XY1 and Z2, because the corresponding value is 1, that is, the second value, not the first value. At this time, the electronic device can traverse the next cell, namely, the cell corresponding to XY1 and Z2. Because the corresponding value is 0, that is, the first value, the electronic device can determine that cell as the target cell.

[0075] After determining the cells corresponding to XY1 and Z2 as target cells, the electronic device can determine the third line channel corresponding to the target cell as the first line channel to be processed, that is, the first line channel is the line channel corresponding to XY1, and determine the fourth line channel corresponding to the target cell as the second line channel to be processed, that is, the second line channel is the line channel corresponding to the above-mentioned Z2.

[0076] In the above embodiment, only the first list is used as an example to illustrate the determination of the first line channel and the second line channel. In addition, the electronic device can also determine the first line channel and the second line channel based on the line channel and value corresponding to the above character string. For details, please refer to the method shown in step S1011 above, and will not be described in detail here.

[0077] Through the step S1011, the electronic device can determine the third channel and the fourth channel corresponding to the target cell with the first value as the first channel to be processed and the second channel to be processed according to the value corresponding to each cell in the first list. This effectively avoids the electronic device determining the third channel and the fourth channel once linked through the third quantum bit as the first channel and the second channel, reduces the repetition of the determined first channel and the second channel, and improves the efficiency of the corresponding time delay between the channels.

[0078] For the step S102, the relative time delay between the signal transmission time lengths corresponding to the first channel and the second channel is obtained when the first channel and the second channel are linked through the first quantum bit.

[0079] In this step, when the first channel and the second channel are linked through a quantum bit (denoted as the first quantum bit) on the quantum chip, the electronic device can obtain the time delay (denoted as the relative time delay) between the signal transmission time length of the first channel transmitting the quantum state control signal and the signal transmission time length of the second channel transmitting the quantum bit frequency control signal.

[0080] In an optional embodiment, the relative time delay can be the time length required to be compensated by the first channel relative to the second channel, or the time length required to be compensated by the second channel relative to the first channel. At this time, the relative time delay is a positive number.

[0081] In another optional embodiment, the relative time delay can be the time length required to be compensated or delayed by the first channel relative to the second channel, or the time length required to be compensated or delayed by the second channel relative to the first channel. At this time, the relative time delay can be a positive number or a negative number.

[0082] In the embodiments of the present application, the relative time delay is not specifically limited.

[0083] In an optional embodiment, for the relative time delay, after the first channel and the second channel are linked through the first quantum bit, the electronic device can obtain the signal transmission time length (denoted as the first transmission time length) of the quantum state control signal transmitted to the first quantum bit through the first channel, and obtain the signal transmission time length (denoted as the second transmission time length) of the quantum bit frequency control signal transmitted to the first quantum bit through the second channel. The electronic device can calculate the time difference between the first transmission time length and the second transmission time length as the relative time delay.

[0084] In an optional embodiment, the relative delay can reflect the relationship between the first transmission duration and the second transmission duration. For example, if the relative delay is the first transmission duration minus the second transmission duration, then when the relative delay is a positive number, the electronic device can determine that the first transmission duration is greater than the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is slower than the speed at which the second line channel transmits the quantum bit frequency control signal; when the relative delay is a negative number, the electronic device can determine that the first transmission duration is less than the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is faster than the speed at which the second line channel transmits the quantum bit frequency control signal; when the relative delay is 0, the electronic device can determine that the first transmission duration is equal to the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is the same as the speed at which the second line channel transmits the quantum bit frequency control signal.

[0085] In an optional embodiment, after a first channel and a second channel establish a link via a first qubit, an XYZ timing experiment can be performed on the first qubit to determine the relative delay between the transmission times of the corresponding signals on the first and second channels. In this case, the electronic device can obtain the relative delay.

[0086] By transmitting a π pulse on the first channel, if the frequency of the first qubit is the qubit's operating frequency, this π pulse can excite the qubit to the |1> state. Therefore, by transmitting a square wave of a certain amplitude on the second channel, the qubit's frequency can be changed, thereby affecting the effect of the π pulse on the qubit's excitation to the |1> state. When the square wave and the π pulse overlap, the probability of the qubit being excited to the |1> state changes abruptly. Therefore, in the aforementioned XYZtiming experiment, by continuously varying the timing of the square wave relative to the π pulse, the time at which the square wave and the π pulse center are perfectly aligned can be accurately determined—that is, the time at which the |1> state is minimized. At this point, the electronic device can determine the relative delay between the corresponding signal transmission times on the first and second channels.

[0087] In the embodiment of the present application, there is no specific limitation on the method for obtaining the relative duration between the signal transmission durations corresponding to the first line channel and the second line channel.

[0088] Regarding the above step S103, the first delay of the first line channel and the second delay of the second line channel at the current moment are found; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0089] In an optional embodiment, the electronic device pre-stores the correspondence between the third line channel and the time delay (recorded as the first correspondence), and the correspondence between the fourth line channel and the time delay (recorded as the second correspondence).

[0090] In an optional embodiment, the first correspondence relationship and the second correspondence relationship may be expressed in the form of a table or a character string, etc. Here, the expression method of the first correspondence relationship and the second correspondence relationship is not specifically limited.

[0091] For ease of understanding, the first correspondence relationship and the second correspondence relationship are described below in the form of a table. The first correspondence relationship may be shown in Table 3, and the second correspondence relationship may be shown in Table 4.

[0092] Table 3

[0093] Line path XY1 XY2 XY3 … Time delay 0 0 0 …

[0094] Table 4

[0095] Line path Z1 Z2 Z3 … Time delay 0 0 0 …

[0096] In Tables 3 and 4 above, each third channel and each fourth channel has a corresponding delay. The delay corresponding to each channel in Tables 3 and 4 is a preset delay, i.e., 0 in Tables 3 and 4. When the delay corresponding to any channel is updated, the delay corresponding to that channel in Table 3 or 4 is recorded as the updated delay. This example uses a preset delay of 0 for illustration purposes only and does not constitute a limitation.

[0097] In this embodiment of the present application, the latency corresponding to each channel in the second and third lists can be expressed as the corresponding waiting time when the channel transmits the corresponding quantum state control signal or qubit frequency control signal. The difference between the latency corresponding to any two channels is the time difference between the signals sent by the two channels when transmitting the corresponding quantum state control signal or qubit frequency control signal.

[0098] The delay updates in Tables 3 and 4 above can be based on the relative delay between any set of third and fourth line channels, or can be based on the corresponding delay update amounts of other associated line channels. The delay update process is described below and is not detailed here.

[0099] In an optional embodiment, when searching for the first delay and the second delay, as shown in FIG. Figure 3 As shown, Figure 3 This is a third flow chart of the delay determination method provided in the embodiment of the present application. Figure 3In the method shown, the above step S103 is refined into the following steps, namely step S1031 - step S1032.

[0100] Step S1031 : According to the first correspondence between line channels and delays in the second list, a delay corresponding to the first line channel is searched and used as the first delay.

[0101] In this step, the second list may reflect a first correspondence between each third line channel and a delay. After determining the first line channel, the electronic device may, based on the first correspondence between the third line channels and the delays in the first list, determine the delay corresponding to the first line channel in the first list as the first delay. This first delay may be the preset delay, or a delay updated before the current moment, i.e., a delay updated based on the relative delay between the first line channel and another fourth line channel, or a delay updated based on the corresponding delay update amount of other line channels associated with the first line channel.

[0102] Step S1032: According to the second correspondence between the line channels and the delays in the third list, the delay corresponding to the second line channel is searched and used as the second delay.

[0103] In this step, the third list may reflect a second correspondence between each fourth line channel and a delay. After determining the second line channel, the electronic device may, based on the second correspondence between the fourth line channel and the delay in the second list, determine the delay corresponding to the second line channel in the second list as the second delay. This second delay may be the preset delay, or a delay updated before the current moment, i.e., a delay updated based on the relative delay between the second line channel and other third line channels, or a delay updated based on the corresponding delay update amount of other line channels associated with the second line channel.

[0104] exist Figure 3 In the illustrated embodiment, the search for the first and second delays is described using the first and second correspondences in a table format as an example. When the first and second correspondences are in other formats, such as the aforementioned string format, the search for the first and second delays can be performed using the method described in steps S1031 and S1032, which will not be described in detail here.

[0105] In the above Figure 3 In the embodiment shown, step S1031 may be performed before step S1032, after step S1032, or simultaneously with step S1032. The execution order of step S1031 and step S1032 is not specifically limited.

[0106] Through the above steps S1031 and S1032, the electronic device can record the above first correspondence relationship through the first list and the above second correspondence relationship through the second list, which effectively improves the convenience and accuracy of obtaining the above first delay and second delay.

[0107] In the above embodiment, the first correspondence relationship and the second correspondence relationship are recorded using the second list and the third list respectively. In addition, the first correspondence relationship and the second correspondence relationship may also be recorded in the same list.

[0108] In the above Figure 1 In the method shown, step S102 is performed before step S103. Alternatively, step S102 may be performed after step S103 or simultaneously with step S103. The order of performing steps S102 and S103 is not specifically limited.

[0109] Regarding the above step S104, that is, based on the first delay, the second delay and the relative delay, the first delay and / or the second delay is updated.

[0110] In this step, after obtaining the relative delay, the first delay, and the second delay, the electronic device may choose to update the first delay, the second delay, or both the first delay and the second delay based on the relative delay, the first delay, and the second delay. The method for updating the first delay and / or the second delay is described below and is not further elaborated here.

[0111] In an optional embodiment, in the above Figure 3 In the illustrated embodiment, the above step S104 can be further divided into the following steps, namely step S1041 .

[0112] Step S1041: Based on the first delay, the second delay, and the relative delay, update the first delay in the second list, and / or update the second delay in the third list.

[0113] In this step, when the electronic device updates the delay according to the first delay, the second delay and the relative delay, it may update the first delay in the second list and / or update the second delay in the third list respectively.

[0114] In an optional embodiment, when updating the first time delay, the electronic device may update the first time delay in the second list.

[0115] In another optional embodiment, when updating the second time delay, the electronic device may update the second time delay in the third list.

[0116] In another optional embodiment, when the first delay and the second delay are updated simultaneously, the electronic device may update the first delay in the second list and update the second delay in the third list respectively.

[0117] Through the above-mentioned step S1041, when the electronic device updates the above-mentioned first delay and / or second delay, it directly updates the first delay in the above-mentioned second list and / or the second delay in the third list, so as to facilitate the subsequent transmission of quantum state control signals and quantum bit frequency control signals to quantum bits directly according to the delays in the second list and the third list, thereby providing protection for the quantum computing process.

[0118] In an optional embodiment, according to the above Figure 1 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 4 As shown, Figure 4 This is a fourth flow chart of the delay determination method provided in the embodiment of the present application. Figure 4 In the method shown, the above step S104 is refined into the following steps, namely step S1042.

[0119] Step S1042: According to the first delay, the second delay and the relative delay, the first delay is updated to the eighth delay, and the second delay is updated to the ninth delay. The difference between the eighth delay and the ninth delay matches the relative delay.

[0120] In this step, the electronic device can update the first delay and the second delay at the same time based on the first delay, the second delay and the relative delay, so that the difference between the updated first delay (recorded as the eighth delay) and the updated second delay (recorded as the ninth delay) matches the above relative delay.

[0121] The matching of the difference between the eighth and ninth delays with the relative delay can be expressed as the same magnitude and the same or opposite signs. For ease of understanding, taking the relative delay as the difference between the second transmission duration and the first transmission duration as an example, in this case, the numerical magnitude of the difference between the eighth and ninth delays is the same as the numerical magnitude of the relative delay, and the sign of the difference is opposite to that of the relative delay. That is, when the relative delay is positive, the difference is negative, and when the relative delay is negative, the difference is positive. The matching of the difference between the eighth and ninth delays with the relative delay is not specifically limited herein.

[0122] In the embodiments of the present application, the updating of the first time delay and the second time delay in step S1042 can represent an increase of the first time delay and the second time delay, or a decrease of the first time delay and the second time delay, or an increase of one time delay (e.g., the first time delay) and a decrease of the other time delay (e.g., the second time delay). Here, the adjustment manner of the first time delay and the second time delay is not limited.

[0123] Through step S1042, the electronic device can update the first time delay and the second time delay based on the relative time delay, so that the difference between the updated first time delay and the updated second time delay matches the relative time delay, thereby ensuring that the first line channel and the second line channel can simultaneously transmit the quantum state control signal and the quantum bit frequency control signal to the quantum bit, and ensuring the accuracy of quantum computing.

[0124] In an optional embodiment, according to the method shown in Figure 1 The embodiments of the present application also provide a time delay determination method. As shown in Figure 5 Figure 5 The fifth flowchart of the time delay determination method provided by the embodiments of the present application is shown in Figure 5 In the method shown in step S104, step S104 is refined into the following steps, i.e., step S1043 and step S1044.

[0125] In step S1043, when the relative time delay indicates that the signal transmission time length of the first line channel is greater than the signal transmission time length of the second line channel, the second time delay is updated to a sixth time delay according to the first time delay and the relative time delay, and the difference between the first time delay and the sixth time delay is the relative time delay.

[0126] In this step, when the relative time delay indicates that the first transmission time length is greater than the second transmission time length, for example, when the relative time delay is positive, the electronic device can determine that the speed of the first line channel in transmitting the quantum state control signal is slower than the speed of the second line channel in transmitting the quantum bit frequency control signal. At this time, for the line channel with faster transmission, i.e., the second line channel, the electronic device can update the time delay of the second line channel. That is, the electronic device can update the second time delay according to the first time delay and the relative time delay to obtain a sixth time delay.

[0127] The difference between the first time delay and the sixth time delay is the relative time delay, that is, the sixth time delay is the difference between the first time delay and the relative time delay.

[0128] In step S1044, when the relative time delay indicates that the signal transmission time length of the first line channel is less than the signal transmission time length of the second line channel, the first time delay is updated to a seventh time delay according to the second time delay and the relative time delay, and the difference between the second time delay and the seventh time delay is the relative time delay. ​

[0129] In this step, when the relative time delay indicates that the first transmission time length is less than the second transmission time length, i.e., when the relative time delay is negative, the electronic device can determine that the first line channel transmits the quantum state control signal at a speed faster than the second line channel transmits the quantum bit frequency control signal. At this time, for the signal line channel that transmits faster, i.e., the first line channel, the electronic device can update the time delay of the first line channel. That is, the electronic device can update the first time delay according to the second time delay and the relative time delay to obtain a seventh time delay.

[0130] The difference between the second time delay and the seventh time delay is the relative time delay, i.e., the seventh time delay is the difference between the second time delay and the relative time delay.

[0131] In the embodiments of the present application, the steps S1043 and S1044 are respectively performed when the first transmission time length is different from the second transmission time length. Here, the performance of the steps S1043 and S1044 is not specifically limited.

[0132] Through the steps S1043-S1044, when the first time delay or the second time delay is updated based on the relative time delay, the electronic device updates the time delay of the line channel that transmits signals at a faster speed according to the time delay of the line channel that transmits signals at a slower speed in the first line channel and the second line channel and the relative time delay, which can realize the update of the first time delay or the second time delay and ensure that the updated first time delay and the second time delay match the relative time delay.

[0133] In addition, when the time delay is updated based on the relative time delay, the electronic device only updates one of the first time delay and the second time delay, which reduces the operation difficulty of time delay updating and reduces the number of operations corresponding to the relative global update.

[0134] In the above Figure 5 The method shown in the above

[0135] In one optional embodiment, when the first time delay is greater than the second time delay, according to the method shown in the above Figure 1 The embodiments of the present application also provide a time delay determination method. As shown in the above Figure 6 Figure 6 The sixth flowchart of the time delay determination method provided by the embodiments of the present application. In Figure 6 ​In the method shown, the above step S104 is refined into the following steps, namely step S1045-step S1046.

[0136] Step S1045: When the first difference is smaller than the relative delay, the first delay is updated to the first sum value.

[0137] The first difference is the difference between the first delay and the second delay, and the first sum is the sum of the second delay and the relative delay.

[0138] Step S1046: When the first difference is greater than the relative delay, the second delay is updated to the second difference.

[0139] The second difference is the difference between the first delay and the relative delay.

[0140] For ease of understanding, the first delay is t XY , the second delay is t Z , the relative delay is t as an example for explanation.

[0141] Due to t XY Greater than t Z Therefore, the first difference t1 must be greater than 0, that is, t1 = t XY -t Z > 0. The electronic device may compare the first difference t1 with the relative delay t.

[0142] When the first difference t1 is less than the relative delay t, the electronic device can XY Update, that is, the updated t′ XY =t Z +t. t Z +t is the first sum value mentioned above. At this time, due to t XY -t Z <t,因此,t XY <t+t Z , that is, the updated t′ XY Relative to t before update XY Correspondingly, the delay update amount corresponding to the first delay is Δ=t′ XY -t XY =t Z +tt XY .

[0143] When the first difference t1 is greater than the relative delay t, the electronic device can Z Update, that is, the updated t′ Z =t XY -t.t XY -t is the second difference mentioned above. At this time, due to t XY -t Z>t, therefore, t XY -t>t Z , that is, the updated t′ Z Relative to t before update Z Correspondingly, the delay update amount corresponding to the second delay is Δ=t′ Z -t Z =t XY -tt Z .

[0144] In an optional embodiment, when the first difference is the same as the relative delay, the electronic device may match the first delay and the second delay corresponding to the current moment with the relative delay. In this case, the electronic device may not perform any processing, that is, not update the first delay and the second delay.

[0145] The above steps S1045 and S1046 are respectively executed by the electronic device when the comparison result between the first difference and the relative delay is different. Here, the execution of the above steps S1045 and S1046 is not specifically limited.

[0146] In an embodiment of the present application, when the first delay is greater than the second delay, through the above-mentioned steps S1045-S1046, the electronic device can perform an increase operation on the basis of the first delay or the second delay when updating the first delay or the second delay, so that the updated first delay or the second delay will not have a negative delay, thereby reducing the risk of abnormal data.

[0147] In addition, when delay updating is performed based on relative delay, the electronic device only updates one of the first delay or the second delay, which reduces the operational difficulty of delay updating and the number of operations corresponding to relative global updates.

[0148] In an optional embodiment, when the second delay is greater than the first delay, according to the above Figure 1 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 7 As shown, Figure 7 This is a seventh flow chart of the delay determination method provided in the embodiment of the present application. Figure 7 In the method shown, the above step S104 is refined into the following steps, namely step S1047 to step S1048.

[0149] Step S1047: When the third difference is smaller than the relative delay, the second delay is updated to the second sum value.

[0150] The third difference is the difference between the second delay and the first delay, and the second sum is the sum of the first delay and the relative delay.

[0151] Step S1048: When the third difference is greater than the relative delay, the first delay is updated to a fourth difference.

[0152] The fourth difference is the difference between the second delay and the relative delay.

[0153] For ease of understanding, the first delay is still taken as t XY , the second delay is t Z , the relative delay is t as an example for explanation.

[0154] Due to t XY Less than t Z Therefore, the third difference t3 must be greater than 0, that is, t3 = t Z -t XY > 0. The electronic device may compare the third difference t3 with the relative delay t.

[0155] When the third difference t3 is less than the relative delay t, the electronic device can Z Update, that is, the updated t′ Z =t XY +t. t XY +t is the second sum value mentioned above. At this time, due to t Z -t XY <t,因此,t Z <t+t XY , that is, the updated t′ Z Relative to t before update Z Correspondingly, the delay update amount corresponding to the second delay is Δ=t′ Z -t Z =t+t XY -t Z .

[0156] When the third difference t3 is greater than the relative delay t, the electronic device can XY Update, that is, the updated t′ XY =t Z -t.t Z -t is the fourth difference mentioned above. At this time, due to t Z -t XY >t, therefore, t Z -t>t xY , that is, the updated t′ xY Relative to t before update XY Correspondingly, the delay update amount corresponding to the first delay is Δ=t′ XY -t XY =t Z -tt XY .

[0157] In an optional embodiment, when the third difference is the same as the relative delay, the electronic device may match the first delay and the second delay corresponding to the current moment with the relative delay. In this case, the electronic device may not perform any processing, that is, not update the first delay and the second delay.

[0158] The above steps S1047 and S1048 are respectively executed by the electronic device when the comparison result between the third difference value and the relative delay is different. Here, the execution of the above steps S1047 and S1048 is not specifically limited.

[0159] In an embodiment of the present application, when the first delay is less than the second delay, through the above-mentioned steps S1047-S1048, the electronic device can add operations on the basis of the first delay or the second delay when updating the first delay or the second delay, so that the updated first delay or the second delay will not have a negative delay, thereby reducing the risk of abnormal data.

[0160] In addition, when delay updating is performed based on relative delay, the electronic device only updates one of the first delay or the second delay, which reduces the operational difficulty of delay updating and the number of operations corresponding to relative global updates.

[0161] In an optional embodiment, when the first delay and the second delay are the same, that is, the t XY and t Z If the first and second delays are the same, the electronic device may update the first delay or the second delay by referring to the method shown in step S1045 or step S1047 above, or the electronic device may update the first delay and the second delay at the same time. The method for updating the delay when the first and second delays are the same is not specifically limited.

[0162] In an optional embodiment, according to the above Figure 2 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 8 As shown, Figure 8 This is a flow chart of the eighth method for determining the time delay provided in the embodiment of the present application. Figure 8 The following step is added to the method shown, namely step S105.

[0163] Step S105 : updating the value corresponding to the target cell to a second value, where the second value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

[0164] In this step, after updating the first delay and / or the second delay, the electronic device may update the value corresponding to the first cell in the first list to a second value, such as 1 in Table 2. The second value may indicate that the third and fourth line channels corresponding to the cell were linked via the third qubit before the current moment.

[0165] For ease of understanding, the above Table 2 is still used as an example for explanation. After the cells corresponding to XY1 and Z2 are determined as target cells and the delays corresponding to XY1 and / or Z2 are updated, the electronic device can update the values ​​of the cells corresponding to XY1 and Z2 in the above Table 2 to 1, and obtain Table 5.

[0166] Table 5

[0167] XY / Z Z1 Z2 Z3 Z4 XY1 1 1 0 0 XY2 0 0 0 0 XY3 1 1 1 0 XY4 0 0 0 1

[0168] In an embodiment of the present application, after the delay of the third line channel and / or the fourth line channel corresponding to the target cell is updated, by updating the value corresponding to the target cell to the second value, it is convenient for subsequent electronic devices to re-determine the new first line channel and second line channel based on the first list, thereby realizing the determination and update of the delay of all line channels.

[0169] In an optional embodiment, according to the above Figure 8 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 9 As shown, Figure 9 This is a ninth flow chart of the delay determination method provided in the embodiment of the present application. Figure 9 The following steps are added to the method shown, namely step S106 - step S107.

[0170] Step S106: searching all fifth line channels associated with the updated line channels based on the first list, where the updated line channels are the first line channels for delay update and / or the second line channels for delay update.

[0171] In an optional embodiment, when searching for all fifth line channels associated with the update line channel, the electronic device may first search for the line channels directly associated with the update line channel (recorded as the ninth line channel) based on the first list, and then, for each ninth line channel, search for a line channel directly associated with the ninth line channel and not repeated, as the line channel indirectly associated with the update line channel (recorded as the tenth line channel). Similarly, search for a line channel directly associated with each tenth line channel and not repeated, until there is no line channel directly associated with and not repeated for each line channel, thereby obtaining all third line channels associated with the update line channel.

[0172] The direct association between the two line paths can be represented as: in the first list, the values of the cells corresponding to the two line paths are the second values.

[0173] For ease of understanding, the search process of the fifth line path is described by taking the time delay updated by the electronic device based on the relative time delay as the second time delay and Table 5 as an example.

[0174] After the electronic device updates the value of the target cell corresponding to XY1 and Z2 to 1, since the second time delay is updated, the electronic device can determine the second line path corresponding to the second time delay as the update line path. For Z2, according to Table 5, since the values of the cells corresponding to XY1 and Z1, the cells corresponding to XY3 and Z1, and the cells corresponding to XY3 and Z3 are all the second values, the electronic device can determine that Z1, Z3, XY1 and XY3 are all directly associated with Z2. That is, Z1, Z3, XY1 and XY3 are all the fifth line paths directly associated with Z2.

[0175] For each of Z1, Z3, XY1 and XY3, the electronic device can further search for the line path associated with the line path. For example, for Z1, the value of the cell corresponding to XY1 and Z1 is 1, and the value of the cell corresponding to XY3 and Z1 is 1, but XY3 is already the fifth line path, so Z1 does not have a directly associated and non-repeated line path. Similarly, Z3, XY1 and XY3 do not have a directly associated and non-repeated line path. At this time, the electronic device can determine that the line paths associated with Z2 include Z1, Z3, XY1 and XY3.

[0176] In the embodiments of the present application, the number of the fifth line paths associated with the update line path is not specifically limited.

[0177] In step S107, the third time delay of each fifth line path at the current time is updated according to the time delay update amount corresponding to the update line path.

[0178] In this step, for each fifth line path, the electronic device can search for the time delay of the fifth line path at the current time in the second list or the third list. The electronic device can synchronously update the time delay of the fifth line path at the current time according to the time delay update amount corresponding to the update line path.

[0179] The update manner of the third time delay is the same as the time delay update manner of the update line path.

[0180] For ease of understanding, the search process of the fifth line path is described by taking the time delay update amount corresponding to the update line path as the above-mentioned Δ and the time delay of the fifth line path at the current time as t7.

[0181] If the update method of the delay corresponding to the above-mentioned updated line channel is to increase Δ, the electronic device can determine that the updated delay of the fifth line channel is t7+Δ; if the update method of the delay corresponding to the above-mentioned updated line channel is to decrease Δ, the electronic device can determine that the updated delay of the fifth line channel is t7-Δ.

[0182] In an embodiment of the present application, after the electronic device updates the delay of the above-mentioned update line channel, it synchronously updates the delay corresponding to its associated fifth line channel according to the delay of the update line channel, so that the delay difference between the fifth line channel and the update line channel remains unchanged, thereby ensuring that the delay between the update line channel and the fifth line channel matches the relative delay between the two, thereby ensuring that the signal can be transmitted to different quantum bits on the quantum chip at the same time, thereby improving the accuracy of quantum computing.

[0183] In an optional embodiment, according to the above Figure 8 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 10 As shown, Figure 10 This is a tenth flow chart of the delay determination method provided in the embodiment of the present application. Figure 10 The following step is added to the method shown, namely step S108.

[0184] Step S108 , if it is determined that the target cell exists in the first list, then return to the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, until the target cell does not exist in the first list.

[0185] In this step, after the electronic device updates the value of the target cell to the second value, it can continue to traverse the first list. When traversing to a cell whose value is the first value, the electronic device can determine that the cell is the target cell, and return to execute the step S1011 to determine the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, until there is no target cell in the first list.

[0186] Through step S108, after updating the delay of the third and / or fourth line channels corresponding to each target cell, the electronic device continues to update the delay of the third and / or fourth line channels corresponding to other target cells in the first list until the value of each cell in the first list is the second value. At this point, the electronic device can determine the delay corresponding to each third and fourth line channels. The delay corresponding to any third and fourth line channels matches the relative delay between the two channels, thereby improving the accuracy of the determined delay.

[0187] In an optional embodiment, according to the above Figure 1 The present invention also provides a method for determining a time delay, such as Figure 11 As shown, Figure 11 This is a schematic diagram of an eleventh flow chart of a method for determining a time delay provided in an embodiment of the present application. The method includes the following steps.

[0188] Step S1101: determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0189] Step S1102: When a link is established between a first line channel and a second line channel through a first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel is obtained.

[0190] Step S1103 , searching for a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0191] Step S1104: Update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0192] The above steps S1101 to S1104 are the same as the above steps S101 to S104.

[0193] Step S1105: Determine the minimum delay based on the fifth delay corresponding to each sixth line channel at the current moment, where the sixth line channel is the third line channel with a delay updated before the current moment, or the sixth line channel is the fourth line channel with a delay updated before the current moment.

[0194] In an optional embodiment, for the second list, the electronic device may determine all third line channels that have undergone delay updates before the current moment, and record them as sixth line channels. The electronic device may obtain the fifth delay corresponding to each sixth line channel at the current moment from the second list and select the minimum delay (recorded as the first minimum delay).

[0195] In another optional embodiment, for the third list, the electronic device may determine all fourth line channels that have undergone delay updates before the current moment, recording them as sixth line channels. The electronic device may obtain the fifth delay corresponding to each sixth line channel at the current moment from the third list and select the minimum delay (recorded as the second minimum delay).

[0196] Step S1106 : If the minimum delay is not equal to the third value, then for each sixth line channel, the fifth delay of the sixth line channel is updated to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay.

[0197] In an optional embodiment, for the first minimum delay, the electronic device may compare the first minimum delay with a third value. If the first minimum delay is not equal to the third value, then for each sixth line channel, the electronic device may update the fifth delay corresponding to the sixth line channel in the first list to the difference between the fifth delay and the first minimum delay.

[0198] In another optional embodiment, for the second minimum delay, the electronic device may compare the second minimum delay with a third value. If the second minimum delay is not equal to the third value, then for each sixth line channel, the electronic device may update the fifth delay corresponding to the sixth line channel in the second list to the difference between the fifth delay and the second minimum delay.

[0199] In an optional embodiment, the third value may be 0. When the first minimum delay is equal to the third value, the electronic device may not perform any processing. Alternatively, when the second minimum delay is equal to the third value, the electronic device may not perform any processing.

[0200] Through the above steps S1105-S1106, the electronic device can reset the minimum delay value in the above first list and the second list to zero, effectively reducing the data size of each delay in the first list and the second list, making it convenient for subsequent electronic devices to transmit the above quantum state control signals and quantum bit frequency control signals according to the delays in the first list and the second list.

[0201] In the above Figure 11The illustrated method uses the aforementioned minimum delays, i.e., the first minimum delay and the second minimum delay, as an example, where both are positive numbers. Alternatively, when the first minimum delay and the second minimum delay are negative numbers, the electronic device can add the absolute value of the first minimum delay or the second minimum delay to the fourth delay of each sixth line channel at the current moment to achieve the aforementioned zeroing.

[0202] In an optional embodiment, according to the above Figure 1 The method shown in the embodiment of the present application also provides a method for determining the time delay. Figure 12 As shown, Figure 12 This is a twelfth flow chart of the delay determination method provided in an embodiment of the present application. The method includes the following steps.

[0203] Step S1201: determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0204] Step S1202: When a link is established between a first line channel and a second line channel through a first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel is obtained.

[0205] Step S1203 , searching for a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0206] Step S1204: Update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0207] The above steps S1201 to S1204 are the same as the above steps S101 to S104.

[0208] Step S1205: When the first line channel and the second line channel establish a link through the second quantum bit, if an enable signal for the second quantum bit is received, the third delay of the first line channel at the current moment and the fourth delay of the second line channel at the current moment are found.

[0209] In this step, when the first channel and the second channel establish a link via the second qubit, the user can trigger an enable signal for the second qubit. The electronic device then receives the enable signal. Upon receiving the enable signal, the electronic device searches the second list for the current delay corresponding to the first channel (referred to as the third delay) and searches the third list for the current delay corresponding to the second channel (referred to as the fourth delay).

[0210] In the embodiment of the present application, the first qubit, the second qubit, and the third qubit can be any qubit on the quantum chip. The first qubit, the second qubit, and the third qubit can be the same or different.

[0211] Step S1206: According to the time difference between the third delay and the fourth delay, the quantum state control signal and the quantum bit frequency control signal are transmitted to the second quantum bit using the first line channel and the second line channel respectively.

[0212] In this step, after finding and obtaining the above-mentioned third delay and fourth delay, the electronic device can transmit a quantum state control signal to the second quantum bit through the first line channel and transmit a quantum bit frequency control signal to the second quantum bit through the second line channel according to the time difference between the third delay and the fourth delay.

[0213] For ease of understanding, assume the third delay is 10 nanoseconds (ns) and the fourth delay is 20 ns. The time difference between the fourth delay and the third delay is 10 ns. After the electronic device transmits the quantum state control signal to the second qubit via the first circuit channel, 10 ns later, the electronic device can transmit the qubit frequency control signal to the second qubit via the second circuit channel. Under this condition, the second qubit will receive both the quantum state control signal and the qubit frequency control signal simultaneously.

[0214] Through the above steps S1205-S1206, after the line channels for transmitting the quantum state control signal and the quantum bit frequency control signal are connected to the quantum bit, signal transmission is performed according to the time delay corresponding to each line channel in the above second list and third list, so that the quantum state control signal and the quantum bit frequency control signal can reach the quantum bit at the same time, avoiding the influence of the time delay of different line channels on the quantum computing process, and improving the efficiency of quantum computing.

[0215] In the above Figure 12In the illustrated embodiment, the transmission of signals required for the quantum computation process for a second qubit is described using only the connection between the first and second circuit channels as an example. After determining the delay for each circuit channel in the second and third lists, the electronic device can transmit signals based on the delays in the second and third lists to implement the quantum computation process for each qubit.

[0216] Based on the same inventive concept, according to the delay determination method provided in the above embodiment of the present application, the embodiment of the present application also provides a delay determination device. Figure 13 As shown, Figure 13 A schematic diagram of the structure of a delay determination device provided in an embodiment of the present application. The device includes the following modules.

[0217] A first determining module 1301 is configured to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal and the second line channel is used to transmit a quantum bit frequency control signal;

[0218] An acquisition module 1302 is configured to acquire a relative delay between corresponding signal transmission times of the first line channel and the second line channel when the first line channel and the second line channel establish a link via the first qubit;

[0219] A first search module 1303 is configured to search for a first delay of a first line channel and a second delay of a second line channel at a current moment; wherein the first delay and the second delay are preset delays or delays updated before the current moment;

[0220] The first updating module 1304 is configured to update the first delay and / or the second delay based on the first delay, the second delay, and the relative delay.

[0221] Optionally, the delay determination device may further include:

[0222] a second search module, configured to search for a third delay of the first line channel at a current moment and a fourth delay of the second line channel at a current moment if an enable signal for the second qubit is received when the first line channel and the second line channel establish a link through the second qubit;

[0223] The transmission module is used to transmit the quantum state control signal and the quantum bit frequency control signal to the second quantum bit using the first line channel and the second line channel respectively according to the time difference between the third delay and the fourth delay.

[0224] Optionally, the first determining module 1301 may be configured to determine the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, based on the third line channel, the fourth line channel, and the value corresponding to each cell in the first list;

[0225] Among them, the numerical value corresponding to the target cell is the first numerical value, and the first numerical value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

[0226] Optionally, the delay determination device may further include:

[0227] The second updating module is used to update the value corresponding to the target cell to a second value after updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay, wherein the second value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

[0228] Optionally, the delay determination device may further include:

[0229] a third search module, configured to search, based on the first list, for all fifth line channels associated with the updated line channel after updating the value corresponding to the target cell to the second value, where the updated line channel is the first line channel for time delay update and / or the second line channel for time delay update;

[0230] The third updating module is configured to update the delay of each fifth line channel at a current moment according to the delay update amount corresponding to the updated line channel.

[0231] Optionally, the delay determination device may further include:

[0232] The calling module is used to, after updating the numerical value corresponding to the target cell to the second numerical value, return to calling the first determination module to execute the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, if it is determined that the target cell exists in the first list, until the target cell no longer exists in the first list.

[0233] Optionally, the delay determination device may further include:

[0234] a second determining module, configured to determine a minimum delay based on a fifth delay corresponding to each sixth line channel at a current moment, where the sixth line channel is a third line channel with a delay updated before the current moment, or the sixth line channel is a fourth line channel with a delay updated before the current moment;

[0235] The fourth updating module is configured to update, for each sixth line channel, the fifth delay of the sixth line channel to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay if the minimum delay is not equal to the third value.

[0236] Optionally, the first updating module 1304 may be configured to update the first delay to a first sum value if the first delay is greater than the second delay and the first difference is less than the relative delay;

[0237] When the first difference is greater than the relative delay, updating the second delay to the second difference;

[0238] The first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the relative delay, and the second difference is the difference between the first delay and the relative delay.

[0239] Optionally, the first updating module 1304 may be configured to update the second delay to a second sum value if the second delay is greater than the first delay and the third difference is less than the relative delay;

[0240] When the third difference is greater than the relative delay, updating the first delay to the fourth difference;

[0241] The third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the relative delay, and the fourth difference is the difference between the second delay and the relative delay.

[0242] Optionally, the first updating module 1304 may be configured to update the second delay to a sixth delay based on the first delay and the relative delay when the relative delay indicates that the signal transmission duration of the first line channel is longer than the signal transmission duration of the second line channel, where the difference between the first delay and the sixth delay is the relative delay.

[0243] When the relative delay indicates that the signal transmission duration of the first line channel is less than the signal transmission duration of the second line channel, the first delay is updated to the seventh delay according to the second delay and the relative delay, and the difference between the second delay and the seventh delay is the relative delay.

[0244] Optionally, the first updating module 1304 may be configured to update the first delay to an eighth delay and the second delay to a ninth delay based on the first delay, the second delay, and the relative delay, and the difference between the eighth delay and the ninth delay matches the relative delay.

[0245] Optionally, the first search module 1303 may be configured to search for a delay corresponding to the first line channel according to a first correspondence between line channels and delays in the second list, as the first delay;

[0246] According to the second correspondence between the line channels and the delays in the third list, searching for the delay corresponding to the second line channel as the second delay;

[0247] The first updating module 1304 may be specifically configured to update the first delay in the second list and / or update the second delay in the third list based on the first delay, the second delay and the relative delay.

[0248] Through the device provided in the embodiments of the present application, after determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system, the first delay and / or the second delay can be updated based on the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the corresponding signal transmission times of the first line channel and the second line channel, thereby realizing the determination of the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0249] Since the first delay and / or the second delay are updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay match the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0250] In addition, when the first delay or the second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment based on the relative delay between the first line channel or the second line channel and other line channels, then updating the first delay and / or the second delay based on the relative delay between the first line channel and the second line channel can effectively establish the correlation in delay between the various line channels, so that the delays between each of the ultimately determined line channels are correlated with each other, effectively improving the accuracy and correlation of the determined delays. Moreover, if a line channel is replaced, signal transmission can be directly performed based on the determined delay without the need to re-determine the delay, thereby improving the applicability of the determined delay.

[0251] Based on the same inventive concept, according to the delay determination method provided in the above embodiment of the present application, the embodiment of the present application also provides an electronic device, such as Figure 14 As shown, it includes a processor 1401, a communication interface 1402, a memory 1403 and a communication bus 1404, wherein the processor 1401, the communication interface 1402, and the memory 1403 communicate with each other through the communication bus 1404.

[0252] a memory 1403 for storing a computer program;

[0253] a processor 1401 for executing the program stored in the memory 1403 to implement the following steps:

[0254] determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, the first line channel being used for transmitting a quantum state control signal, and the second line channel being used for transmitting a quantum bit frequency control signal;

[0255] in a case where the first line channel and the second line channel are linked through a first quantum bit, obtaining a relative time delay between signal transmission time lengths corresponding to the first line channel and the second line channel;

[0256] finding a first time delay of the first line channel and a second time delay of the second line channel at a current time; wherein the first time delay and the second time delay are preset time delays, or time delays obtained by updating before the current time;

[0257] updating the first time delay and / or the second time delay based on the first time delay, the second time delay, and the relative time delay.

[0258] Through the electronic device provided in the embodiments of the present application, after determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system, the first time delay of the first line channel at the current time, the second time delay of the second line channel at the current time, and the relative time delay between the signal transmission time lengths corresponding to the first line channel and the second line channel can be used to update the first time delay and / or the second time delay, so as to determine the signal transmission time delay between any pulse modulation line channel and each magnetic flux modulation line channel in the quantum computing measurement and control system.

[0259] Since the first time delay and / or the second time delay are updated based on the relative time delay between the first line channel and the second line channel, the updated first time delay and / or the updated second time delay match the relative time delay, effectively ensuring the accuracy of the updated first time delay and / or the updated second time delay, so that the quantum state control signal and the quantum bit frequency control signal transmitted through the first line channel and the second line channel, respectively, can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0260] In addition, when the first time delay or the second time delay is a time delay obtained before the current time, that is, the first time delay and the second time delay have been updated according to the relative time delays between the first line channel or the second line channel and other line channels before the current time, the first time delay and / or the second time delay are updated according to the relative time delays between the first line channel and the second line channel, which can effectively establish the correlation of the time delays of the line channels, so that the time delays between each line channel are associated with each other, the accuracy and correlation of the determined time delays are effectively improved, and once the line channel replacement occurs, the signal transmission can be directly performed according to the determined time delays, without the need to re-determine the time delays, thereby improving the applicability of the determined time delays.

[0261] In addition, compared with the signal receiving interface binding mode of the quantum bit in the related art, the time delay in the embodiment of the application is bound with the line channel of the signal transmission, so that when the line replacement occurs, the time delays between the line channels are globally associated, that is, the time delays between the line channels for transmitting the quantum state control signal and the line channels for transmitting the quantum bit frequency control signal after the line replacement are also accurate, which avoids the need to re-determine the time delay in the line replacement in the related art, and improves the effectiveness and applicability of the determined time delay.

[0262] The communication bus mentioned in the electronic device can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0263] The communication interface is used for communication between the electronic device and other devices.

[0264] The memory can include a random access memory (RAM) and can also include a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0265] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0266] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned delay determination methods.

[0267] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer program product containing instructions, which, when executed on a computer, enables the computer to execute any of the delay determination methods in the above-mentioned embodiments.

[0268] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a quantum computing measurement and control system to implement any of the above-mentioned delay determination methods.

[0269] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0270] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0271] Each embodiment in this specification is described in a related manner. Similar portions between embodiments can be referenced to each other. Each embodiment focuses on the differences between other embodiments. In particular, for embodiments such as apparatus, electronic equipment, computer-readable storage medium, computer program product, and quantum computing and measurement and control system, since they are generally similar to method embodiments, their descriptions are relatively simplified. For relevant portions, reference can be made to the descriptions of the method embodiments.

[0272] The above merely provides the preferred embodiments of the application, and not intended to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the protection scope of the application.

Claims

1. A method for determining a time delay, characterized in that: The method comprises: Determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal; When the first line channel and the second line channel are linked via the first quantum bit, obtaining a relative delay between corresponding signal transmission times of the first line channel and the second line channel; Finding a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays or delays updated before the current moment; The first delay and / or the second delay are updated based on the first delay, the second delay, and the relative delay.

2. The method according to claim 1, characterized in that The method further comprises: When the first channel and the second channel establish a link through the second qubit, if an enable signal for the second qubit is received, finding a third delay of the first channel and a fourth delay of the second channel at the current moment; According to the time difference between the third delay and the fourth delay, the quantum state control signal and the quantum bit frequency control signal are transmitted to the second quantum bit using the first line channel and the second line channel respectively.

3. The method according to claim 1, characterized in that The step of determining a first circuit channel to be processed and a second circuit channel to be processed in the quantum computing measurement and control system includes: According to the third line channel, the fourth line channel, and the value corresponding to each cell in the first list, the third line channel and the fourth line channel corresponding to the target cell are determined as the first line channel to be processed and the second line channel to be processed; The value corresponding to the target cell is a first value, and the first value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

4. The method according to claim 3, characterized in that After updating the first delay and / or the second delay based on the first delay, the second delay, and the relative delay, the method further includes: The value corresponding to the target cell is updated to a second value, where the second value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

5. The method according to claim 4, characterized in that: After updating the value corresponding to the target cell to the second value, the method further includes: Based on the first list, searching for all fifth line channels associated with the updated line channels, where the updated line channels are the first line channels for delay update and / or the second line channels for delay update; The delay of each fifth line channel at the current moment is updated according to the delay update amount corresponding to the updated line channel.

6. The method according to claim 4, characterized in that After updating the value corresponding to the target cell to the second value, the method further includes: If it is determined that the target cell exists in the first list, the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed is returned to execution until the target cell does not exist in the first list.

7. The method according to claim 6, characterized in that The method further comprises: Determining a minimum delay based on a fifth delay corresponding to each sixth line channel at a current moment, where the sixth line channel is a third line channel with a delay updated before the current moment, or the sixth line channel is a fourth line channel with a delay updated before the current moment; If the minimum delay is not equal to the third value, then for each sixth line channel, the fifth delay of the sixth line channel is updated to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay.

8. The method according to claim 1, characterized in that If the first delay is greater than the second delay, the step of updating the first delay and / or the second delay based on the first delay, the second delay, and the relative delay includes: When the first difference is less than the relative delay, updating the first delay to a first sum value; When the first difference is greater than the relative delay, updating the second delay to a second difference; The first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the relative delay, and the second difference is the difference between the first delay and the relative delay.

9. The method according to claim 1, characterized in that If the second delay is greater than the first delay, the step of updating the first delay and / or the second delay based on the first delay, the second delay, and the relative delay includes: When the third difference is less than the relative delay, updating the second delay to a second sum value; When the third difference is greater than the relative delay, updating the first delay to a fourth difference; The third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the relative delay, and the fourth difference is the difference between the second delay and the relative delay.

10. The method according to claim 1, characterized in that The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay includes: When the relative delay indicates that the signal transmission duration of the first line channel is longer than the signal transmission duration of the second line channel, updating the second delay to a sixth delay based on the first delay and the relative delay, where a difference between the first delay and the sixth delay is the relative delay; When the relative delay indicates that the signal transmission duration of the first line channel is less than the signal transmission duration of the second line channel, the first delay is updated to a seventh delay based on the second delay and the relative delay, and a difference between the second delay and the seventh delay is the relative delay.

11. The method according to claim 1, wherein The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay includes: According to the first delay, the second delay and the relative delay, the first delay is updated to an eighth delay, and the second delay is updated to a ninth delay, and a difference between the eighth delay and the ninth delay matches the relative delay.

12. The method according to claim 1, characterized in that The step of finding the first delay of the first line channel and the second delay of the second line channel at the current moment includes: According to the first correspondence between the line channels and the delays in the second list, searching for the delay corresponding to the first line channel as the first delay; According to the second correspondence between the line channels and the delays in the third list, searching for the delay corresponding to the second line channel as the second delay; The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay includes: Based on the first delay, the second delay and the relative delay, the first delay in the second list is updated, and / or the second delay in the third list is updated.

13. A delay determination device, characterized in that: The device comprises: A first determination module is used to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal; an acquisition module, configured to acquire, when the first line channel and the second line channel are linked via the first qubit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel; A first search module is configured to search for a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays or delays updated before the current moment; A first updating module is configured to update the first delay and / or the second delay based on the first delay, the second delay, and the relative delay.

14. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor, configured to implement the method steps described in any one of claims 1 to 12 when executing a program stored in a memory.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 12 are implemented.

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