Method and device for detecting abnormity of time service link

Abstract

The invention provides a method and device for detecting abnormity of a time service link, and the method comprises the following steps: S1, selecting a section from a main time service link as a to-be-replaced section, and replacing the to-be-replaced section with a standard reference link as a detection time service link; s2, calculating the time difference of the time service signals received by the receiving equipment from the two time service links; s3, judging whether the replaced section is normal or not according to the time difference; and S4, taking the section except the section to be replaced in the main time service link as a residual section, replacing the residual section by using the standard reference link to serve as a detection time service link, and repeating the steps S2-S3. The method has the beneficial effects that the troubleshooting range can be quickly narrowed by adopting a link replacement mode, a large-scale link problem is positioned as a small-section problem, so that abnormal equipment is found within a small number of iterations, the absolute delay inequality can be accurately calculated by a receiving end due to introduction of a standard reference link, and the fault detection accuracy is improved. The signal sending time can be obtained for quantization time delay, and the detection precision is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of timing, and in particular relates to a method and device for detecting abnormality in a timing link. Background Art

[0002] Network timing systems are widely used in scenarios such as communication networks, financial transactions, and power dispatching. They transmit synchronization signals through the link between the master timing device and the receiving device to ensure the consistency of the clocks of each node. However, due to the large number of devices in the link, the complex physical length, and the complex topology, delay errors are often difficult to locate in a timely manner, and the receiving end cannot know the actual time when the signal is sent. As a result, traditional single-link measurement methods are unable to quantify the absolute delay or quickly identify the fault segment, posing challenges to system reliability and maintenance efficiency. Summary of the Invention

[0003] In view of this, the present invention aims to provide a method and device for detecting timing link anomalies, in order to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows: A first aspect of the present invention provides a method for detecting an abnormality in a timing link, comprising the following steps: S1. Select a section in the main timing link as the section to be replaced, and use the standard reference link to replace the section to be replaced as the detection timing link; S2. The timing device sends a timing signal, which is sent to the receiving device through the main timing link and the detection timing link respectively. The time difference between the receiving device receiving the timing signal from the two timing links is calculated; S3. Determine whether the replaced segment is normal based on the time difference; S4. Remove the segments to be replaced in S1 from the main timing link as the segments to be replaced, use the standard reference link to replace the remaining segments as the new detection timing link, and repeat S2-S3.

[0005] Furthermore, the specific steps of S2 are as follows: The formula for calculating the time difference ΔT when the receiving device receives the timing signals from two timing links is as follows: ΔT=|Tm-Tn|; Wherein, Tm is the time when the receiving device receives the timing signal from the main timing link, and Tn is the time when the receiving device receives the timing signal from the detection timing link; The specific steps of S3 are as follows: Compare the time difference ΔT and H; If ΔT>H, the replaced segment is determined to be an abnormal segment; If ΔT≤H, the replaced segment is determined to be a normal segment, where H is a preset threshold.

[0006] Furthermore, the calculation formula of the preset threshold H is as follows: ; in is the standard reference link delay, is the number of devices in the standard reference link, is the physical length of the standard reference link, is the number of devices in the replaced segment, is the physical length of the replaced segment, and k is the tolerance factor.

[0007] Furthermore, the method further includes the following steps: S5. Select a section in the abnormal section as the section to be replaced, use the standard reference link to replace the section to be replaced as the detection timing link, and repeat steps S3, S4, and S5 until the abnormal device in the main timing link is detected.

[0008] Furthermore, the method further includes the following steps: Construct a graph based on multiple main timing links between a timing device and multiple receiving devices; Each main timing link is divided into multiple regions. Each region is a node in the graph, and the connections between regions are edges in the graph. The standard reference link is replaced independently for each area, and the arrival time difference ΔT of the timing signal before and after the replacement is collected. ΔT is written into the graph as the characteristic value of the node corresponding to this area; Collect historical graph structure and node features as input, and use failure data as labels to build a data set; Use the data set to train the graph neural network to generate a predictive model; The real-time graph structure and node features are input into the prediction model, and the prediction model outputs the predicted delay fault data.

[0009] Furthermore, the steps for constructing a standard reference link are as follows: a set of devices with known delay characteristics are selected; Connect devices with known delay characteristics according to a predetermined topology as a standard reference link; The delay of the standard reference link is measured and calibrated so that the delay value of the standard reference link is within a preset accuracy range.

[0010] Furthermore, in S1, the timing link between the timing device and the receiving device is collected as the main timing link.

[0011] Furthermore, after determining in S3 that the replaced section is an abnormal section, an alarm message is sent to the management system, and the alarm message includes the location of the abnormal section.

[0012] A second aspect of the present invention provides a device for detecting an abnormality in a timing link, comprising: A detection timing link generation module is configured to select a segment in the main timing link as a segment to be replaced, and use a standard reference link to replace the segment to be replaced as a detection timing link; A time difference detection module is configured to send a timing signal through a timing device, and the timing signal is sent to a receiving device through a main timing link and a detection timing link respectively, and calculate the time difference between the timing signals received by the receiving device from the two timing links; an abnormality determination module configured to receive the time difference calculated by the time difference detection module and determine whether the replaced segment is normal based on the time difference; The iterative execution module removes the segments to be replaced in the main timing link as the remaining segments, uses the standard reference link to replace the remaining segments as the detection timing link, and sends it to the time difference detection module.

[0013] A third aspect of the present invention provides a computer-readable storage medium storing a computer program, which implements the method described in the first aspect when executed by a processor.

[0014] Compared with the prior art, the method and device for detecting timing link anomalies described in the present invention have the following beneficial effects: (1) The present invention discloses a method for detecting timing link anomalies. The present invention adopts a link replacement method to quickly narrow the scope of troubleshooting and locate large-scale link problems as small-segment problems, thereby finding abnormal devices within a relatively small number of iterations. The introduction of a standard reference link enables the receiving end to accurately calculate the absolute delay difference, overcoming the deficiency of the traditional method that the time when the signal is sent cannot be known and the delay is difficult to quantify. After the abnormal segment is found, the sub-segment is further replaced by a cyclic measurement, which can further refine the troubleshooting and improve the accuracy of the alarm.

[0015] (2) The method for detecting timing link anomalies described in the present invention constructs multiple main timing links into a graph and writes regional features into the graph nodes. It then uses a graph neural network to perform supervised learning on the historical graph. It can utilize the topological associations and historical failure modes between links, comprehensively consider the delay characteristics between each region, and achieve rapid fault prediction and positioning of the real-time graph, significantly improving the intelligence level and response speed of the system, while reducing manual maintenance costs and misjudgment rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute part of the present invention, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings: Figure 1 A schematic diagram of the method flow in an embodiment of the present invention; Figure 2 The figure is a flowchart of the delay prediction method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0020] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0021] Example 1: like Figure 1 As shown, a method for detecting timing link abnormality includes the following steps: S1. Select a section in the main timing link as the section to be replaced, and use the standard reference link to replace the section to be replaced as the detection timing link; S2. The timing device sends a timing signal, which is sent to the receiving device through the main timing link and the detection timing link respectively. The time difference between the receiving device receiving the timing signal from the two timing links is calculated; S3. Determine whether the replaced segment is normal based on the time difference; S4. Remove the segments to be replaced in S1 from the main timing link as the segments to be replaced, use the standard reference link to replace the remaining segments as the new detection timing link, and repeat S2-S3.

[0022] The specific steps of S2 are as follows: The formula for calculating the time difference ΔT when the receiving device receives the timing signals from two timing links is as follows: ΔT=|Tm-Tn|; Wherein, Tm is the time when the receiving device receives the timing signal from the main timing link, and Tn is the time when the receiving device receives the timing signal from the detection timing link; The specific steps of S3 are as follows: Compare the time difference ΔT and H; If ΔT>H, the replaced segment is determined to be an abnormal segment; If ΔT≤H, the replaced segment is determined to be a normal segment, where H is a preset threshold.

[0023] Furthermore, the calculation formula of the preset threshold H is as follows: ; in is the standard reference link delay, is the number of devices in the standard reference link, is the physical length of the standard reference link, is the number of devices in the replaced segment, is the physical length of the replaced segment, and k is the tolerance factor.

[0024] The calculation formula of the preset threshold H represents the delay contribution per unit device number and per unit length in the standard reference link, reflecting the delay characteristics of the standard link.

[0025] Multiply this value by the product of the number of devices and the length of the segment to be replaced to estimate the expected latency of the segment under normal conditions. The tolerance factor adjusts the leniency of the threshold to allow for a certain degree of latency fluctuation. The parameter value range is between 1.0 and 2.0, depending on the system's fault tolerance requirements. A smaller value (k) (such as 1.0) is suitable for high-precision scenarios, while a larger value (such as 2.0) is suitable for scenarios with a higher tolerance for latency fluctuation.

[0026] The following steps are also included: S5. Select a section in the abnormal section as the section to be replaced, use the standard reference link to replace the section to be replaced as the detection timing link, and repeat steps S3, S4, and S5 until the abnormal device in the main timing link is detected.

[0027] The following steps are also included to predict the delay: The method for predicting latency is as follows: Construct a graph based on multiple main timing links between a timing device and multiple receiving devices; Each main timing link is divided into multiple regions. Each region is a node in the graph, and the connections between regions are edges in the graph. The standard reference link is replaced independently for each area, and the arrival time difference ΔT of the timing signal before and after the replacement is collected. ΔT is written into the graph as the characteristic value of the node corresponding to this area; Collect historical graph structure and node features as input, and use failure data as labels to build a data set; Use the data set to train the graph neural network to generate a predictive model; The real-time graph structure and node features are input into the prediction model, and the prediction model outputs the predicted delay fault data.

[0028] For example, if there are two links, each divided into three segments, the graph contains six nodes, with edges representing the physical or logical connections between segments. For each node, ΔT is calculated using the aforementioned substitution method and recorded as the node's characteristic value in the graph. For example, if a segment has a ΔT of 30 nanoseconds, this value is written to the corresponding node.

[0029] The training process uses historical graph data as input, including node features (ΔT) and edge relationships, with labels indicating whether delay failures occurred in the historical data. Through supervised learning, the GNN learns the relationship between node features and topological structure in the graph and failures. The GNN architecture utilizes a graph convolutional network (GCN), which aggregates information from neighboring nodes through multiple layers of convolution, ultimately outputting the failure probability of each node. During training, the model is optimized using a cross-entropy loss function, with a batch size of 32, a learning rate of 0.01, and 100 training epochs. During real-time operation, the GNN is fed with real-time graph data, and it predicts which nodes are likely to fail. For example, if a node's ΔT increases abnormally, the GNN might output a failure probability of 0.9, alerting maintenance personnel.

[0030] When an abnormal section is detected, the system sends an alarm to the management system. This information includes the location of the abnormal section (e.g., "Device C to D"), the ΔT value (e.g., "30 nanoseconds"), and the possible cause (e.g., "Loose fiber connection"). This information is sent via the SNMP protocol or a custom message format.

[0031] The alarm device can be composed of multiple functional units. The link acquisition unit is responsible for collecting the topology and equipment information of the main timing link, which can be implemented through software modules. The reference link construction unit builds a standard reference link, which may include hardware devices (such as time synchronization servers) and measurement tools. The replacement link generation unit selects the segment to be replaced and generates a detection timing link, which is implemented through a network switching device. The synchronous transmission and time difference detection unit controls signal transmission and calculates ΔT, and can be composed of a high-precision clock and receiving module. The iterative execution unit realizes the subdivision and cyclic detection of abnormal segments and can be controlled by automated scripts.

[0032] The steps for building a standard reference link are as follows: select a set of devices with known delay characteristics; Connect devices with known delay characteristics according to a predetermined topology as a standard reference link; The delay of the standard reference link is measured and calibrated so that the delay value of the standard reference link is within a preset accuracy range.

[0033] The standard reference link is a link with known latency. The topology of the link with known latency is the same as that of the segment to be replaced. It is used for comparison with the primary timing link. The specific construction method is as follows: First, select a set of devices with known and stable delay characteristics. Use high-precision time synchronization equipment (such as cesium atomic clocks) as signal sources, along with low-latency fiber optic links and calibrated switches. The delay characteristics of these devices can be provided by the manufacturer or obtained through laboratory testing. Next, connect these devices in a predetermined topology (the same as the topology of the segment to be replaced). This topology can be a simple serial connection or another known delay configuration with parallel backup links. Avoid using uncalibrated patch cables or low-quality connectors during connection. Measure the end-to-end delay of a standard reference link using high-precision measuring instruments. Use a time interval counter to record the signal propagation time from the starting point to the end point, averaging multiple measurements to minimize error. Finally, perform delay calibration to ensure that the delay of the standard reference link is within a pre-defined accuracy range (e.g., ±1 nanosecond). During calibration, adjust device parameters or add delay compensators to stabilize the delay at the target value. If the measured delay is 50 nanoseconds, but the target accuracy requires an error of less than 1 nanosecond, fine-tune the equipment.

[0034] Consider a standard reference link consisting of three devices connected in series, with a total length of 10 kilometers. If the measurement results show a latency of 50 microseconds and a standard deviation of less than 0.5 microseconds across multiple measurements, the link is considered to meet accuracy requirements and can serve as a benchmark for subsequent comparisons.

[0035] In S1, the timing link between the timing device and the receiving device is collected as the main timing link.

[0036] A timing system transmits time signals from a timing device (such as a GPS receiver or atomic clock) to a receiving device via a series of intermediate devices (such as switches, routers, and fiber optic links). To ensure the accuracy of the timing signal, comprehensive information about the primary timing link between the timing device and the receiving device must be collected. This link may include multiple devices and connections, forming a complex network structure.

[0037] The collection process specifically includes the following aspects: First, obtain the complete topology of the primary timing link through a network management system or manual configuration. This requires recording the identification and location of each device on the link, as well as the connections between them. For example, a network topology discovery protocol (such as LLDP) can be used to generate a link diagram that shows the signal transmission path from the timing device to the receiving device.

[0038] In some embodiments, key information of each device is recorded, including device type (such as fiber optic transceiver or time synchronization server), model, inherent delay characteristics, etc. This information helps in subsequent analysis of the source of delay anomalies.

[0039] In S1, the main timing link is divided into multiple segments. The division is based on the number of devices or physical length. For example, a link with 10 devices can be divided into two or more segments; or a 100-kilometer link can be divided into two or more 50-kilometer segments based on the fiber length.

[0040] After determining that the replaced section is an abnormal section in S3, an alarm message is sent to the management system, and the alarm message includes the location of the abnormal section.

[0041] In order to detect abnormal sections in the main timing link, it is necessary to replace part of the main timing link with a standard reference link to generate a detection timing link. In a more specific embodiment, half of the sections on the main timing link are selected as the sections to be replaced. The "half" here is defined according to the number of devices or the physical length. For example, if the main timing link consists of 10 devices (of course it can be more, and the present invention is more effective when there are more devices), the first 5 devices are selected as the sections to be replaced; if the total length of the link is 100 kilometers, the first 50 kilometers are selected. It is preferred to use the definition of the number of devices.

[0042] The selected segment to be replaced is disconnected from the main timing link and replaced with a standard reference link. This can be done physically (e.g., reconnecting optical fibers) or through virtual network configuration (e.g., adjusting routing tables).

[0043] The time signal will be transmitted to the receiving device through the partial main time signal link and the standard reference link, forming a detection time signal link.

[0044] For example, assuming the main time signal link contains devices A-B-C-D-E, and the section to be replaced is A-B-C, then A-B-C is replaced by the standard reference link X-Y-Z, and the final detection time signal link is X-Y-Z-D-E.

[0045] The time signal is sent to both links through a splitter or a multi-output module. The error in the sending time is controlled within nanoseconds using a high-precision clock (such as a PTP protocol supported clock).

[0046] The receiving device records the time Tm when the signal is received from the main time signal link and the time Tn when the signal is received from the detection time signal link, and then calculates the time difference ΔT = |Tm-Tn|. For example, if Tm is 10:00:00.000050 seconds and Tn is 10:00:00.000030 seconds, then ΔT = 20 nanoseconds.

[0047] Then, ΔT is compared with a preset threshold H. If ΔT > H, it means that the time delay of the section to be replaced is too different from the standard reference link, and the section is determined to be an abnormal section; if ΔT ≤ H, it is considered that the time delay of the section to be replaced is normal. For example, if H is set to 15 nanoseconds and ΔT is 20 nanoseconds, then the section to be replaced is determined to be abnormal.

[0048] The calculation of ΔT reflects the difference in time delay between the two links. Since the time delay of the standard reference link is known and stable, ΔT is mainly caused by the abnormal time delay of the section to be replaced in the main time signal link, and is therefore used as the basis for anomaly detection.

[0049] In order to further locate the abnormal device, iterative detection of the main time signal link is required.

[0050] First, another half of the section on the main time signal link that has not been replaced is selected as a new section to be replaced. For example, if the first 5 devices are replaced, the last 5 devices are selected for the second time.

[0051] The replacement and time difference detection steps are repeated for the new section to be replaced to determine whether it is an abnormal section. Through this bisection method, the abnormal range is quickly narrowed down. For example, if there are 10 devices in the main time signal link, the first 5 devices are found to be abnormal in the first detection, and then one half (such as the first 2 devices) of the first 5 devices is selected for the next detection, and so on, until the specific device is located.

[0052] When a section is determined to be abnormal, it is further divided into two sub-sections within the area, and the replacement and detection steps are repeated for each sub-section. This process is recursive until the abnormal section is refined to a single device or connection.

[0053] For example, assuming that the first detection finds that the first 5 devices (A-B-C-D-E) are abnormal, the 5 devices are divided into two parts, A-B and C-D-E, and are replaced by standard reference links and detected respectively. If A-B is normal and C-D-E is abnormal, continue to subdivide in C-D-E, and finally locate the abnormal device D.

[0054] The replacement link method can quickly narrow down the troubleshooting range, locate large-scale link problems as small section problems, and find abnormal devices in fewer iterations. The introduction of the standard reference link enables the receiving end to accurately calculate the absolute time delay difference, obtain the quantized time delay when the signal is sent, and further select a section in the abnormal section as a replacement section for replacement measurement, thereby improving the detection accuracy.

[0055] After constructing a plurality of main timing links into a graph and writing regional features into graph nodes, the graph neural network is used for supervised learning of historical graphs, which can utilize the topological association and historical fault mode between links, comprehensively consider the time delay features between regions, realize rapid fault prediction and positioning of real-time graphs, significantly improve the intelligent level and response speed of the system, and reduce the manual maintenance cost and misjudgment rate.

[0056] An apparatus for detecting timing link abnormalities, comprising: A detection timing link generation module configured to select a section in the main timing link as a replacement section, and replace the replacement section with a standard reference link as a detection timing link; A time difference detection module configured to send a timing signal by a timing device, the timing signal being sent to a receiving device through the main timing link and the detection timing link, and calculate the time difference between the receiving device receiving the timing signal from the two timing links; An abnormality determination module configured to receive the time difference calculated by the time difference detection module, and determine whether the replaced section is normal according to the time difference; An iteration execution module configured to remove the section of the replacement section from the main timing link as a remaining section, replace the remaining section with a standard reference link as a detection timing link, and send it to the time difference detection module.

[0057] Embodiment two: A computer-readable storage medium storing a computer program, the computer program being executed by a processor to implement the method of embodiment one.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for detecting anomalies in a timing link, characterized in that: The following steps are involved: S1. Select a section in the main timing link as the section to be replaced, and use the standard reference link to replace the section to be replaced as the detection timing link; S2. The timing device sends a timing signal, which is sent to the receiving device through the main timing link and the detection timing link respectively. The time difference between the receiving device receiving the timing signal from the two timing links is calculated; S3. Determine whether the replaced segment is normal based on the time difference; S4. Remove the segments to be replaced in S1 from the main timing link as the segments to be replaced, use the standard reference link to replace the remaining segments as the new detection timing link, and repeat S2-S3.

2. The method for detecting a timing link anomaly according to claim 1, wherein: The specific steps of S2 are as follows: The formula for calculating the time difference ΔT when the receiving device receives the timing signals from two timing links is as follows: ΔT=|Tm-Tn|; Wherein, Tm is the time when the receiving device receives the timing signal from the main timing link, and Tn is the time when the receiving device receives the timing signal from the detection timing link; The specific steps of S3 are as follows: Compare the time difference ΔT and H; If ΔT>H, the replaced segment is determined to be an abnormal segment; If ΔT≤H, the replaced segment is determined to be a normal segment, where H is a preset threshold.

3. The method for detecting a timing link anomaly according to claim 2, wherein: The calculation formula of the preset threshold H is as follows: ； in is the standard reference link delay, is the number of devices in the standard reference link, is the physical length of the standard reference link, is the number of devices in the replaced segment, is the physical length of the replaced segment, and k is the tolerance factor.

4. The method for detecting timing link anomaly according to claim 1, wherein: The following steps are also included: S5. Select a section in the abnormal section as the section to be replaced, use the standard reference link to replace the section to be replaced as the detection timing link, and repeat steps S3, S4, and S5 until the abnormal device in the main timing link is detected.

5. The method for detecting timing link anomaly according to claim 1, wherein: The following steps are also included: Construct a graph based on multiple main timing links between a timing device and multiple receiving devices; Each main timing link is divided into multiple regions. Each region is a node in the graph, and the connections between regions are edges in the graph. The standard reference link is replaced independently for each area, and the arrival time difference ΔT of the timing signal before and after the replacement is collected. ΔT is written into the graph as the characteristic value of the node corresponding to this area; Collect historical graph structure and node features as input, and use failure data as labels to build a data set; Use the data set to train the graph neural network to generate a predictive model; The real-time graph structure and node features are input into the prediction model, and the prediction model outputs the predicted delay fault data.

6. The method for detecting a timing link anomaly according to claim 1, wherein: The steps for building a standard reference link are as follows: select a set of devices with known delay characteristics; Connect devices with known delay characteristics according to a predetermined topology as a standard reference link; The delay of the standard reference link is measured and calibrated so that the delay value of the standard reference link is within a preset accuracy range.

7. The method for detecting timing link anomalies according to claim 1, wherein: In the S1, the timing link between the timing device and the receiving device is collected as the main timing link.

8. The method for detecting timing link anomalies according to claim 1, wherein: After determining that the replaced section is an abnormal section in S3, an alarm message is sent to the management system, and the alarm message includes the location of the abnormal section.

9. A device for detecting timing link anomalies, characterized in that: include: A detection timing link generation module is configured to select a segment in the main timing link as a segment to be replaced, and use a standard reference link to replace the segment to be replaced as a detection timing link; A time difference detection module is configured to send a timing signal through a timing device, and the timing signal is sent to a receiving device through a main timing link and a detection timing link respectively, and calculate the time difference between the timing signals received by the receiving device from the two timing links; an abnormality determination module configured to receive the time difference calculated by the time difference detection module and determine whether the replaced segment is normal based on the time difference; The iterative execution module removes the segments to be replaced in the main timing link as the remaining segments, uses the standard reference link to replace the remaining segments as the detection timing link, and sends it to the time difference detection module.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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