Fingerprint sensor and display device including same

Abstract

The invention relates to a fingerprint sensor and a display device including the same. The fingerprint sensor includes: a gate line on a substrate and configured to provide a gate signal; a reset voltage line configured to provide a reset voltage; an initialization voltage line configured to provide an initialization voltage; a readout line on the gate line and configured to provide a sensing signal; a light receiving element on the readout line; a first sensor transistor configured to provide a sensing current based on a voltage of a sensor node, the sensor node being a first electrode of the light receiving element; a second sensor transistor including a second-first sensor transistor and a second-second sensor transistor connected in series between a reset voltage line and a gate electrode of the first sensor transistor; and a third sensor transistor including a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and the first electrode of the first sensor transistor.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0002] As the information-oriented society develops, more and more demands are emerging on display devices for displaying images in various ways. For example, display devices can be used with or incorporated into various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. In the display device, because each pixel of the display panel can include a light-emitting element capable of emitting light by itself, an image can be displayed without a backlight unit that provides light to the display panel.

[0003] The display device may include a display panel that displays an image, an optical sensor that detects light, a fingerprint sensor that detects a person's fingerprint, etc. As electronic devices that employ display devices are diversified, it is desired to provide display devices in various designs. For example, the display device may expand a display area for displaying an image by removing a sensor device such as a separate optical sensor or fingerprint sensor.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure include a fingerprint sensor capable of reducing process time, saving process cost, and minimizing or reducing a non-display area, and a display device including the fingerprint sensor.

[0006] However, aspects of the embodiments according to the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the embodiments according to the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to some embodiments, a fingerprint sensor includes: a gate line on a substrate to provide a gate signal; a reset voltage line to provide a reset voltage; an initialization voltage line to provide an initialization voltage; a readout line on the gate line to provide a sensing signal; a light receiving element on the readout line; a first sensor transistor to control a sensing current based on a voltage of a sensor node, which is a first electrode of the light receiving element; a second sensor transistor including a second-first sensor transistor and a second-second sensor transistor connected in series between the reset voltage line and a gate electrode of the first sensor transistor; and a third sensor transistor including a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and a first electrode of the first sensor transistor.

[0008] According to some embodiments, the respective semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor may be in the same layer and include low temperature polysilicon.

[0009] According to some embodiments, the second sensor transistor may provide a reset voltage to the sensor node based on the reset signal.

[0010] According to some embodiments, the third sensor transistor may electrically connect the readout line to the first electrode of the first sensor transistor based on the gate signal.

[0011] According to some embodiments, the fingerprint sensor may further include: an active layer on the substrate and including semiconductor regions of the first sensor transistor, the second sensor transistor and the third sensor transistor; a first gate layer on the active layer; a second gate layer on the first gate layer; a first source metal layer on the second gate layer; a second source metal layer on the first source metal layer; and a third source metal layer on the second source metal layer and including a readout line.

[0012] According to some embodiments, the fingerprint sensor may further include a first sensor connection electrode that is in the first source metal layer and electrically connects the gate electrode of the first sensor transistor to the second electrode of the second-second sensor transistor.

[0013] According to some embodiments, the fingerprint sensor may also include a first sensor anode connecting electrode and a second sensor anode connecting electrode, the first sensor anode connecting electrode being in the second source metal layer and connected to the first sensor connecting electrode, the second sensor anode connecting electrode being in the third source metal layer and electrically connecting the first sensor anode connecting electrode to the sensor electrode of the light receiving element.

[0014] According to some embodiments, the fingerprint sensor may further include: a reset signal line in the second gate layer to provide a reset signal; and a second sensor connection electrode in the first source metal layer and electrically connecting the reset signal line to the gate electrode of each of the second-first sensor transistor and the second-second sensor transistor.

[0015] According to some embodiments, the fingerprint sensor may further include: a third sensor connection electrode in the first source metal layer and connected to the first electrode of the third-first sensor transistor; and a readout electrode in the second source metal layer and electrically connecting the third sensor connection electrode to the readout line.

[0016] According to some embodiments, the reset voltage line may include a horizontal reset voltage line in the second source metal layer and extending in the first direction, and a vertical reset voltage line in the third source metal layer and extending parallel to the readout line.

[0017] According to some embodiments, the fingerprint sensor may further include a fourth sensor connection electrode in the first source metal layer and electrically connecting the first electrode of the second-first sensor transistor to the horizontal reset voltage line.

[0018] According to some embodiments, a display device includes: a pixel including a pixel circuit on a substrate and a light emitting element connected to the pixel circuit; a fingerprint sensor including a sensor circuit in the same layer as the pixel circuit and a light receiving element connected to the sensor circuit and in the same layer as the light emitting element; a gate line providing a gate signal to the pixel circuit and the sensor circuit; a reset voltage line providing a reset voltage to the sensor circuit; a first initialization voltage line providing a first initialization voltage to the pixel circuit; a second initialization voltage line providing a second initialization voltage to the pixel circuit and the sensor circuit; and a readout line receiving a sensing signal from the sensor circuit. According to some embodiments, the sensor circuit includes: a first sensor transistor controlling a sensing current based on a voltage of a sensor node as a first electrode of the light receiving element; a second sensor transistor including a second-first sensor transistor and a second-second sensor transistor connected in series between the reset voltage line and a gate electrode of the first sensor transistor; and a third sensor transistor including a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and a first electrode of the first sensor transistor.

[0019] According to some embodiments, the respective semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor may be in the same layer and include low temperature polysilicon.

[0020] According to some embodiments, the display device may further include: an active layer on the substrate and including semiconductor regions of a first sensor transistor, a second sensor transistor, and a third sensor transistor; a first gate layer on the active layer; a second gate layer on the first gate layer; a first source metal layer on the second gate layer; a second source metal layer on the first source metal layer; and a third source metal layer on the second source metal layer and including a readout line.

[0021] According to some embodiments, the display device may further include: a display driver that drives the pixels and the fingerprint sensor; a data line that is connected to the display driver, extends in a first direction, and provides a data voltage to the pixel; a first bridge line that is connected to the display driver and extends in the first direction; and a second bridge line that electrically connects the first bridge line to the data line or the readout line.

[0022] According to some embodiments, the first bridge line may be in the third source metal layer and extend in parallel with the readout line.The second bridge line may be in the second source metal layer and extend in a second direction crossing the first direction.

[0023] According to some embodiments, a display device includes: a pixel including a pixel circuit on a substrate and a light emitting element connected to the pixel circuit; a fingerprint sensor including a sensor circuit and a light receiving element, the sensor circuit being in the same layer as the pixel circuit, the light receiving element being connected to the sensor circuit and being in the same layer as the light emitting element; and a readout line configured to provide a sensing signal received from the sensor circuit. According to some embodiments, the pixel circuit includes: a first transistor controlling a driving current flowing through the light emitting element; a second transistor providing a data voltage to a first electrode of the first transistor; a third transistor electrically connecting a second electrode of the first transistor to a gate electrode of the first transistor; a fourth transistor discharging the gate electrode of the first transistor to a first initialization voltage; a fifth transistor providing a driving voltage to a first electrode of the first transistor; a sixth transistor electrically connecting the second electrode of the first transistor to a first electrode of the light emitting element; a seventh transistor discharging the first electrode of the light emitting element to a second initialization voltage; and an eighth transistor providing a bias voltage to a first electrode of the first transistor. According to some embodiments, the sensor circuit includes: a first sensor transistor that controls a sensing current based on a voltage of a sensor node that is a first electrode of a light receiving element; a second sensor transistor that provides a reset voltage to a sensor node that is a gate electrode of the first sensor transistor; and a third sensor transistor that electrically connects a readout line to the first electrode of the first sensor transistor. Semiconductor regions of the first, second, third, fourth, fifth, sixth, seventh, and eighth transistors of the pixel circuit are in the same layer as semiconductor regions of the first, second, and third sensor transistors of the sensor circuit and include low-temperature polysilicon.

[0024] According to some embodiments, the third transistor may include a third-first transistor and a third-second transistor connected in series between a gate electrode of the first transistor and a second electrode of the first transistor. According to some embodiments, the fourth transistor may include a fourth-first transistor and a fourth-second transistor connected in series between a gate electrode of the first transistor and a first initialization voltage line providing a first initialization voltage.

[0025] According to some embodiments, the second sensor transistor may include a second-first sensor transistor and a second-second sensor transistor connected in series between a reset voltage line providing a reset voltage and the sensor node. According to some embodiments, the third sensor transistor may include a third-first sensor transistor and a third-second sensor transistor connected in series between a readout line and a first electrode of the first sensor transistor.

[0026] According to some embodiments, the display device may further include: a display driver that drives the pixels and the fingerprint sensor; a data line that is connected to the display driver, extends in a first direction, and provides a data voltage to the pixel; a first bridge line that is connected to the display driver and extends in the first direction; and a second bridge line that electrically connects the first bridge line to the data line or the readout line.

[0027] According to some embodiments, a fingerprint sensor according to an embodiment and a display device including the fingerprint sensor may include a sensor circuit including only a sensor transistor having a silicon-based semiconductor region, thereby reducing process time, saving process costs, and minimizing or reducing a non-display area.

[0028] However, aspects and features of the embodiments of the present disclosure are not limited to those described above, and various other aspects and features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a perspective view showing a display device according to some embodiments;

[0031] Figure 2 is a cross-sectional view showing a display device according to some embodiments;

[0032] Figure 3 is a plan view showing a display unit of a display device according to some embodiments;

[0033] Figure 4 is a block diagram showing a display panel and a display driver according to some embodiments;

[0034] Figure 5 is a plan view showing an emission area and a sensor area in a display device according to some embodiments;

[0035] Figure 6 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0036] Figure 7 is a circuit diagram of a fingerprint sensor of a display device according to some embodiments;

[0037] Figure 8 is a layout diagram showing pixels and a fingerprint sensor of a display device according to some embodiments;

[0038] Fig. 9is a layout diagram showing an active layer, a first gate layer, and a second gate layer of a pixel in a display device according to some embodiments;

[0039] Fig.10 is a layout diagram showing a first source metal layer, a second source metal layer, and a third source metal layer of a pixel in a display device according to some embodiments;

[0040] Fig.11 is along Fig. 9 and Fig.10 A cross-sectional view taken along line II';

[0041] Fig.12 is a layout diagram showing an active layer, a first gate layer, and a second gate layer of a fingerprint sensor in a display device according to some embodiments;

[0042] Fig.13 is a layout diagram showing a first source metal layer, a second source metal layer, and a third source metal layer of a fingerprint sensor in a display device according to some embodiments;

[0043] Fig.14 is along Fig.12 and Fig.13 A cross-sectional view taken along line II-II';

[0044] Fig.15 is a diagram showing one example of an arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments;

[0045] Fig.16 is a diagram showing another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments;

[0046] Fig.17 is a diagram showing still another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments; and

[0047] Fig.18 is a diagram showing still another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments. DETAILED DESCRIPTION

[0048] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various embodiments or embodiments of the present invention. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of devices or methods using one or more disclosed contents of the disclosed contents disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or by one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessary ambiguity of various embodiments. In addition, various embodiments can be different, but do not have to be exclusive, nor do they limit the present disclosure. For example, without departing from the present disclosure, the specific shape, configuration and characteristics of the embodiments can be used or implemented in other embodiments.

[0049] Unless otherwise specified, the described embodiments should be understood as providing features of different details of some ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0050] The use of cross-hatching and / or shading in the drawings is generally used to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0051] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described order. Likewise, the same reference numerals represent the same elements.

[0052] When an element or layer is referred to as being on, connected to, or coupled to another element or layer, it may be directly on, directly connected to, or directly coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers. For this reason, the term "connection" may refer to a physical connection, electrical connection, and / or fluid connection with or without intervening elements.

[0053] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and thus the X-axis, Y-axis and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0054] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, XZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] Although the terms "first", "second", etc. may be used to describe various types of elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0056] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, elements or features described as being below or below other elements or features will then be oriented to be above the other elements or features. Thus, the term "below" can encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0057] The terms used herein are used to describe the purpose of specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "a kind of" and "the" are intended to also include plural forms. In addition, the terms "comprises", "comprising", "includes" and / or "including" when used in this specification specify the existence of stated features, integral bodies, steps, operations, elements, components and / or groups thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, rather than as terms of degree, and therefore, are used to allow for the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0058] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic illustrations of embodiments and / or intermediate structures. As such, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific illustrated regional shapes, but should include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, the shapes of these regions are not necessarily intended to be limiting.

[0059] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, components and / or modules. It will be understood by those skilled in the art that these blocks, units, components and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits), discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, components and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control blocks, units, components and / or modules to perform various functions discussed herein, and blocks, units, components and / or modules can be optionally driven by firmware and / or software. It is also conceivable that each block, unit, component and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, without departing from the scope of the present disclosure, each block, unit, component and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units, components and / or modules. In addition, without departing from the scope of the present disclosure, the blocks, units, components and / or modules of some embodiments can be physically combined into more complex blocks, units, components and / or modules.

[0060] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and disclosure, and should not be interpreted as an ideal or overly formal meaning, unless clearly defined in this article.

[0061] Hereinafter, specific embodiments of the present disclosure are described with reference to the accompanying drawings.

[0062] Figure 1 is a perspective view showing a display device according to some embodiments.

[0063] Reference Figure 1The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile PCs (UMPCs), etc. For example, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMDs).

[0064] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, in a plan view, the display device 10 may have a shape similar to a quadrilateral shape, having a short side in the X-axis direction and a long side in the Y-axis direction. The corner where the short side in the X-axis direction and the long side in the Y-axis direction meet may be rounded to have a curvature (e.g., a set curvature or a predetermined curvature), or may be at right angles. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0065] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0066] The display panel 100 may include a main area MA and a sub area SBA.

[0067] The main area MA may include a display area DA and a non-display area NDA arranged around the display area DA (e.g., around or outside the display area DA), wherein the display area DA includes pixels that display an image. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0068] For example, the self-luminous element may include one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the embodiments of the present disclosure are not limited thereto.

[0069] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate electrode driver that provides a gate signal to a gate line and a fan-out line that connects the display driver 200 to the display area DA.

[0070] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. Alternatively, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0071] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may provide a data voltage to a data line. The display driver 200 may provide a power voltage to a power line, and may provide a gate electrode control signal to a gate electrode driver. The display driver 200 may receive a sensing signal through a readout line. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be located in a sub-region SBA, and may overlap with the main region MA in a thickness direction (Z-axis direction) by bending the sub-region SBA. For another example, the display driver 200 may be mounted on a circuit board 300.

[0072] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0073] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may provide a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a set or predetermined frequency). The touch driver 400 may calculate whether an input has been made and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0074] The power supply unit 500 may be located on the circuit board 300 to provide a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to provide it to a driving voltage line, and may generate a common voltage to provide it to a common electrode shared by light-emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element. The power supply unit 500 may generate an initialization voltage to provide it to an initialization voltage line, generate a reference voltage to provide it to a reference voltage line, generate a bias voltage to provide it to a bias voltage line, and generate a reset voltage to provide it to a reset voltage line.

[0075] Figure 2 is a cross-sectional view illustrating a display device according to some embodiments.

[0076] Reference Figure 2 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EDL, and an encapsulation layer TFEL.

[0077] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0078] The transistor layer TFTL may be located on the substrate SUB. The transistor layer TFTL may include a plurality of transistors constituting pixels and fingerprint sensors. The transistor layer TFTL may also include gate lines, data lines, power lines, readout lines, bridge lines, and leads connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate electrode driver is formed on one side of the non-display area NDA of the display panel 100, the gate electrode driver may include a transistor.

[0079] The transistor layer TFTL may be located in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, power lines, readout lines, and bridge lines of the transistor layer TFTL may extend from the display area DA to the display driver 200. The leads of the transistor layer TFTL may be located in the sub-area SBA.

[0080] The light emitting element layer EDL may be located on the transistor layer TFTL. The light emitting element layer EDL may include a light emitting element of a pixel, a light receiving element of a fingerprint sensor, and a pixel defining layer defining the pixel and the fingerprint sensor. The light emitting element may emit light by being formed by a pixel electrode, a light emitting layer, and a common electrode stacked in sequence, and the light receiving element may receive light by being formed by a sensor electrode, a light receiving layer, and a common electrode stacked in sequence. The light emitting element and the light receiving element of the light emitting element layer EDL may be located in the display area DA.

[0081] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage (e.g., a set or predetermined voltage) through the transistor of the transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, electrons may move to the organic light-emitting layer through the electron transport layer, and holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but embodiments of the present disclosure are not limited thereto.

[0082] For another example, the plurality of light emitting elements may include a quantum dot light emitting diode (including a quantum dot light emitting layer), an inorganic light emitting diode (including an inorganic semiconductor), or a micro light emitting diode.

[0083] The light receiving element can receive light and convert light energy into an electrical signal. When the user's finger touches the display panel 100, the light emitted from the light emitting element can be reflected by the finger, and the light receiving element can receive the reflected light. The sensing signal of the fingerprint sensor that receives the light reflected by the ridge of the finger can be different from the sensing signal of the fingerprint sensor that receives the light reflected by the valley of the finger. The main processor can distinguish the difference between these sensing signals to generate sensing data, and can determine whether the ridge of the finger has touched or the valley of the finger has touched based on the sensing data. Therefore, the display device 10 can recognize the pattern of the user's fingerprint based on the sensing data. For example, the light receiving element can be an organic photodiode, but it is not limited to this according to the embodiments of the present disclosure.

[0084] The encapsulation layer TFEL may cover the top surface and the side surface of the light emitting element layer EDL and may protect the light emitting element layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EDL.

[0085] The touch sensing unit TSU may be located on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing the touch of a user in a capacitive manner and a touch line connecting the plurality of touch electrodes to the touch driver 400. The plurality of touch electrodes of the touch sensing unit TSU may be located in a touch sensor area overlapping the display area DA. The touch line of the touch sensing unit TSU may be located in a touch peripheral area overlapping the non-display area NDA. For example, the touch sensing unit TSU may sense the touch of a user by using a mutual capacitance method or a self-capacitance method.

[0086] For another example, the touch sensing unit TSU may be located on a separate substrate, and the separate substrate is located on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0087] The color filter layer CFL may be located on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each color filter may selectively transmit light of a specific wavelength and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of the light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent or reduce color distortion caused by reflection of external light.

[0088] Since the color filter layer CFL is directly located on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0089] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0090] Figure 3 is a plan view showing a display unit of a display device according to some embodiments. Figure 4 is a block diagram illustrating a display panel and a display driver according to some embodiments.

[0091] Reference Figure 3 and Figure 4 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include pixels SP, a fingerprint sensor OPD, power lines VL, data lines DL, readout lines ROL, bridge lines BRS, gate lines GL, and emission control lines EML.

[0092] Each of the plurality of pixels SP may be connected to a gate line GL, an emission control line EML, a data line DL, and a power line VL. Each pixel SP may include at least one transistor, a light emitting element, and a capacitor.

[0093] Each of the plurality of fingerprint sensors OPD may be connected to a gate line GL, a power line VL, and a readout line ROL. Each of the plurality of fingerprint sensors OPD may include at least one transistor and a light receiving element.

[0094] The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction. The gate lines GL may sequentially provide gate signals to the pixels SP and the fingerprint sensor OPD.

[0095] The emission control lines EML may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The emission control lines EML may sequentially provide emission signals to the pixels SP.

[0096] The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. Some of the data lines DL may be electrically connected to the display driver 200 through the bridge line BRS, while other of the data lines DL may be directly connected to the display driver 200. The data lines DL may provide a data voltage to the pixel SP. The data voltage may determine the brightness of each pixel SP.

[0097] The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The power lines VL may provide power voltages to the pixels SP and the fingerprint sensor OPD. Some of the power lines VL may be electrically connected to the display driver 200 via the bridge wires BRS, while others of the power lines VL may be directly connected to the display driver 200. In this article, the power voltage may be a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage may be a high potential voltage for driving a light emitting element, and the common voltage may be a low potential voltage for driving a light emitting element and a light receiving element.

[0098] The readout lines ROL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The readout lines ROL may provide a sensing signal of the fingerprint sensor OPD to the display driver 200. Some of the readout lines ROL may be electrically connected to the display driver 200 through a bridge line BRS, while others of the readout lines ROL may be directly connected to the display driver 200.

[0099] The bridge wire BRS may electrically connect the display driver 200 to each of the data lines DL, the power lines VL, and the readout lines ROL. The bridge wire BRS may provide a data voltage received from the display driver 200 to some of the data lines DL. The bridge wire BRS may provide a power voltage received from the display driver 200 to some of the power lines VL. The bridge wire BRS may provide a sensing signal received from some of the readout lines ROL to the display driver 200.

[0100] The bridge wire BRS may include a first bridge wire BRS1 and a second bridge wire BRS2. The first bridge wire BRS1 may extend from the display driver 200 to the display area DA in the Y-axis direction. The second bridge wire BRS2 may extend from the first bridge wire BRS1 in the X-axis direction or in a direction opposite to the X-axis direction, and may be connected to each of the data line DL, the power line VL, and the readout line ROL. The second bridge wire BRS2 may electrically connect the first bridge wire BRS1 to the data line DL or the readout line ROL. Since the display device 10 includes the bridge wire BRS, the fan-out line extending from the display driver 200 to the display area DA may be omitted, and the size of the non-display area NDA may be minimized or reduced.

[0101] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate electrode driver 610, an emission control driver 620, a first gate electrode control line GSL1, and a second gate electrode control line GSL2.

[0102] The first gate electrode control line GSL1 may extend from the display driver 200 to the gate electrode driver 610. The first gate electrode control line GSL1 may provide the gate electrode driver 610 with a gate electrode control signal GCS received from the display driver 200.

[0103] The second gate electrode control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate electrode control line GSL2 may provide the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0104] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be located closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 through an anisotropic conductive film (ACF).

[0105] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0106] The timing controller 210 may receive the digital video data DATA and the timing signal from the circuit board 300. The timing controller 210 may generate the data control signal DCS for controlling the operation timing of the data driver 220, the gate electrode control signal GCS for controlling the operation timing of the gate electrode driver 610, and the emission control signal ECS for controlling the operation timing of the emission control driver 620 based on the timing signal. The timing controller 210 may provide the gate electrode control signal GCS to the gate electrode driver 610 through the first gate electrode control line GSL1. The timing controller 210 may provide the emission control signal ECS to the emission control driver 620 through the second gate electrode control line GSL2. The timing controller 210 may provide the digital video data DATA and the data control signal DCS to the data driver 220.

[0107] The data driver 220 may convert the digital video data DATA into an analog data voltage and output the analog data voltage to the data line DL. The gate signal of the gate electrode driver 610 may select a pixel SP to which the data voltage is provided, and the selected pixel SP may receive the data voltage through the data line DL. The data driver 220 may provide a sensing signal received through the readout line ROL to a host processor.

[0108] The power supply unit 500 may be located on the circuit board 300 to provide a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a power voltage to provide it to the power line VL, and generate a common voltage to provide it to a common electrode shared by the pixel SP and the fingerprint sensor OPD. The power supply unit 500 may generate an initialization voltage to provide it to an initialization voltage line, generate a reference voltage to provide it to a reference voltage line, generate a bias voltage to provide it to a bias voltage line, and generate a reset voltage to provide it to a reset voltage line.

[0109] The gate electrode driver 610 may be located at one outer side of the display area DA or at one side of the non-display area NDA. The emission control driver 620 may be located at the other outer side of the display area DA or at the other side of the non-display area NDA. However, the embodiments of the present disclosure are not limited thereto. For another example, the gate electrode driver 610 and the emission control driver 620 may be located at either one side or the other side of the non-display area NDA.

[0110] The gate electrode driver 610 may include a plurality of transistors for generating gate signals based on the gate electrode control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission signals based on the emission control signal ECS. For example, the transistors of the gate electrode driver 610 and the transistors of the emission control driver 620 may be formed in the same layer as the transistors of each pixel SP. The gate electrode driver 610 may provide a gate signal to the gate line GL, and the emission control driver 620 may provide an emission signal to the emission control line EML.

[0111] Figure 5 is a plan view showing an emission area and a sensor area in a display device according to some embodiments.

[0112] Reference Figure 5 , the display area DA may include an emission area EA and a non-emission area NEA. The emission area EA may emit light of a light emitting element, and the light emitting element may not be located in the non-emission area NEA. The non-emission area NEA may include sensor areas PDA spaced apart from each other, and having at least one emission area EA between the sensor areas PDA. The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3. For example, the first emission area EA1 may emit light of a first color or red light, the second emission area EA2 may emit light of a second color or green light, and the third emission area EA3 may emit light of a third color or blue light, but is not limited thereto.

[0113] One unit pixel UP may represent a white grayscale by including one first emission area EA1, two second emission areas EA2, and one third emission area EA3, but the configuration of the unit pixel UP is not limited thereto. The white grayscale may be represented by a combination of light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3.

[0114] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different in size from each other. For example, the size of the third emission area EA3 may be larger than the size of the first emission area EA1, and the size of the first emission area EA1 may be larger than the size of the second emission area EA2. However, the embodiments according to the present disclosure are not limited thereto. For another example, the sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be the same.

[0115] The sensor area PDA may be surrounded by the first emission area EA1, the second emission area EA2, and the third emission area EA3. The sensor area PDA may be adjacent to the first emission area EA1 or the third emission area EA3 in the X-axis direction, and may be adjacent to the second emission area EA2 in the Y-axis direction. The sensor areas PDA may be spaced apart from each other, and there may be at least one emission area EA between the sensor areas PDA. The sensor area PDA may receive light reflected by a finger.

[0116] Figure 6 is a circuit diagram showing a pixel of a display device according to some embodiments.

[0117] Reference Figure 6 The pixel SP may be connected to a first gate line GWL, a second gate line GIL, a third gate line GBL, an emission control line EML, a data line DL, a driving voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a bias voltage line VBL and a low potential line VSSL.

[0118] The pixel SP may include a light emitting element ED and a pixel circuit for driving the light emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, and an eighth transistor ST8, and a first capacitor C1 and a second capacitor C2.

[0119] The first transistor ST1 may control a driving current provided to the light emitting element ED. The first transistor ST1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor ST1 may be connected to a third node N3, the first electrode of the first transistor ST1 may be connected to a first node N1, and the second electrode of the first transistor ST1 may be connected to a second node N2. For example, the first electrode of the first transistor ST1 may be a source electrode, and the second electrode of the first transistor ST1 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0120] The first transistor ST1 may control a source-drain current (Isd) (hereinafter referred to as a "driving current") according to a data voltage applied to a gate electrode. The driving current (Isd) flowing through the channel of the first transistor ST1 may be proportional to the square of the difference between the threshold voltage (Vth) and the voltage (Vsg) between the source electrode and the gate electrode of the first transistor ST1 (Isd = k × (Vsg - Vth) 2 ). Herein, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg is a source-gate voltage of the first transistor ST1, and Vth is a threshold voltage of the first transistor ST1.

[0121] The light emitting element ED may emit light by receiving a driving current (Isd). The emission amount or brightness of the light emitting element ED may be proportional to the size of the driving current (Isd). The light emitting element ED may include a first electrode, a second electrode, and a light emitting layer located between the first electrode and the second electrode. The first electrode of the light emitting element ED may be connected to a fourth node N4. The first electrode of the light emitting element ED may be connected to a second electrode of the sixth transistor ST6 and a first electrode of the seventh transistor ST7 through the fourth node N4. For example, the first electrode of the light emitting element ED may be an anode electrode or a pixel electrode, and the second electrode of the light emitting element ED may be a cathode electrode or a common electrode, but is not limited thereto according to an embodiment of the present disclosure. The second electrode of the light emitting element ED may be connected to a low potential line VSSL and may receive a low potential voltage from the low potential line VSSL.

[0122] The second transistor ST2 may be turned on by the first gate signal of the first gate line GWL to electrically connect the data line DL to the first node N1 as the first electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal to provide a data voltage to the first node N1. The gate electrode of the second transistor ST2 may be connected to the first gate line GWL, the first electrode of the second transistor ST2 may be connected to the data line DL, and the second electrode of the second transistor ST2 may be connected to the first node N1. The second electrode of the second transistor ST2 may be connected to the first electrode of the first transistor ST1, the second electrode of the fifth transistor ST5, and the second electrode of the eighth transistor ST8 through the first node N1. For example, the first electrode of the second transistor ST2 may be a source electrode, and the second electrode of the second transistor ST2 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0123] The third transistor ST3 may be turned on by the first gate signal of the first gate line GWL to electrically connect the second node N2, which is the second electrode of the first transistor ST1, to the third node N3, which is the gate electrode of the first transistor ST1. The third transistor ST3 may include a third-first transistor ST3-1 and a third-second transistor ST3-2 connected in series. The third-first transistor ST3-1 and the third-second transistor ST3-2 may be connected in series between the third node N3 and the second node N2. The gate electrode of the third-first transistor ST3-1 and the gate electrode of the third-second transistor ST3-2 may be integrally formed and electrically connected to the first gate line GWL. The second electrode of the third-first transistor ST3-1 may be connected to the third node N3, and the first electrode of the third-second transistor ST3-2 may be connected to the second node N2. The first electrode of the third-first transistor ST3-1 and the second electrode of the third-second transistor ST3-2 may be integrally formed and connected to the first capacitor electrode of the second capacitor C2. For example, a first electrode of each of the third-first transistor ST3-1 and the third-second transistor ST3-2 may be a source electrode, and a second electrode of each of the third-first transistor ST3-1 and the third-second transistor ST3-2 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0124] The fourth transistor ST4 may be turned on by the second gate signal of the second gate line GIL to electrically connect the third node N3 as the gate electrode of the first transistor ST1 to the first initialization voltage line VIL1. The fourth transistor ST4 may be turned on based on the second gate signal to discharge the gate electrode of the first transistor ST1 to the first initialization voltage. The fourth transistor ST4 may include a fourth-first transistor ST4-1 and a fourth-second transistor ST4-2 connected in series. The fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may be connected in series between the third node N3 and the first initialization voltage line VIL1. The gate electrode of the fourth-first transistor ST4-1 and the gate electrode of the fourth-second transistor ST4-2 may be integrally formed and connected to the second gate line GIL. The first electrode of the fourth-first transistor ST4-1 may be connected to the third node N3, and the second electrode of the fourth-second transistor ST4-2 may be connected to the first initialization voltage line VIL1. The second electrode of the fourth-first transistor ST4-1 and the first electrode of the fourth-second transistor ST4-2 may be integrally formed. For example, a first electrode of each of the fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may be a source electrode, and a second electrode of each of the fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0125] The fifth transistor ST5 may be turned on by the emission signal of the emission control line EML to electrically connect the driving voltage line VDDL to the first node N1 which is the first electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 may be connected to the emission control line EML, the first electrode of the fifth transistor ST5 may be connected to the driving voltage line VDDL, and the second electrode of the fifth transistor ST5 may be connected to the first node N1. The second electrode of the fifth transistor ST5 may be electrically connected to the first electrode of the first transistor ST1, the second electrode of the second transistor ST2, and the second electrode of the eighth transistor ST8 through the first node N1. For example, the first electrode of the fifth transistor ST5 may be a source electrode, and the second electrode of the fifth transistor ST5 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0126] The sixth transistor ST6 may be turned on by the emission signal of the emission control line EML to electrically connect the second node N2, which is the second electrode of the first transistor ST1, to the fourth node N4, which is the first electrode of the light emitting element ED. The gate electrode of the sixth transistor ST6 may be connected to the emission control line EML, the first electrode of the sixth transistor ST6 may be connected to the second node N2, and the second electrode of the sixth transistor ST6 may be connected to the fourth node N4. The first electrode of the sixth transistor ST6 may be connected to the second electrode of the first transistor ST1 and the first electrode of the third-second transistor ST3-2 through the second node N2. The second electrode of the sixth transistor ST6 may be connected to the first electrode of the light emitting element ED and the first electrode of the seventh transistor ST7 through the fourth node N4. For example, the first electrode of the sixth transistor ST6 may be a source electrode, and the second electrode of the sixth transistor ST6 may be a drain electrode, but it is not limited thereto according to the embodiments of the present disclosure.

[0127] When all of the fifth transistor ST5 , the first transistor ST1 , and the sixth transistor ST6 are turned on, a driving current (Isd) may be provided to the plurality of light emitting elements ED.

[0128] The seventh transistor ST7 may be turned on by the third gate signal of the third gate line GBL to electrically connect the second initialization voltage line VIL2 to the fourth node N4 as the first electrode of the light emitting element ED. By turning on the seventh transistor ST7 based on the third gate signal, the first electrode of the light emitting element ED may be discharged to the second initialization voltage. The gate electrode of the seventh transistor ST7 may be connected to the third gate line GBL, the first electrode of the seventh transistor ST7 may be connected to the fourth node N4, and the second electrode of the seventh transistor ST7 may be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor ST7 may be connected to the first electrode of the light emitting element ED and the second electrode of the sixth transistor ST6 through the fourth node N4. For example, the first electrode of the seventh transistor ST7 may be a source electrode, and the second electrode of the seventh transistor ST7 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0129] The eighth transistor ST8 may be turned on by the third gate signal of the third gate line GBL to electrically connect the bias voltage line VBL to the first node N1 as the source electrode of the first transistor ST1. The eighth transistor ST8 may be turned on based on the third gate signal to provide a bias voltage to the first node N1. The eighth transistor ST8 may improve the hysteresis of the first transistor ST1 by providing a bias voltage to the source electrode of the first transistor ST1. The gate electrode of the eighth transistor ST8 may be connected to the third gate line GBL, the first electrode of the eighth transistor ST8 may be connected to the bias voltage line VBL, and the second electrode of the eighth transistor ST8 may be connected to the first node N1. The second electrode of the eighth transistor ST8 may be electrically connected to the first electrode of the first transistor ST1, the second electrode of the second transistor ST2, and the second electrode of the fifth transistor ST5 through the first node N1. For example, the first electrode of the eighth transistor ST8 may be a source electrode, and the second electrode of the eighth transistor ST8 may be a drain electrode, but it is not limited thereto according to the embodiments of the present disclosure.

[0130] Each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7 and the eighth transistor ST8 may include a silicon-based semiconductor region. For example, each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7 and the eighth transistor ST8 may include a semiconductor region made of low-temperature polysilicon (LTPS). The semiconductor region made of low-temperature polysilicon may have high electron mobility and excellent conduction characteristics. That is, because the display device 10 includes the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7 and the eighth transistor ST8 having excellent conduction characteristics, a plurality of pixels SP may be driven in a stable and effective manner.

[0131] Each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may correspond to a p-type transistor. For example, each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may output a current flowing into its first electrode to its second electrode based on a gate electrode low voltage applied to its gate electrode.

[0132] The display device 10 may include a pixel circuit consisting only of transistors having a silicon-based semiconductor region, thereby reducing process time, saving process costs, and minimizing or reducing the non-display area NDA, compared with a case where the pixel circuit includes both a transistor having a silicon-based semiconductor region and a transistor having an oxide-based semiconductor region.

[0133] The first capacitor C1 may be connected between the third node N3 as the gate electrode of the first transistor ST1 and the driving voltage line VDDL. For example, the first capacitor electrode of the first capacitor C1 may be connected to the third node N3, and the second capacitor electrode of the first capacitor C1 may be connected to the driving voltage line VDDL, thereby maintaining a potential difference between the driving voltage line VDDL and the gate electrode of the first transistor ST1.

[0134] The second capacitor C2 may be connected between the first electrode of the third-first transistor ST3-1 and the driving voltage line VDDL to reduce a kickback voltage. The second capacitor C2 may stably maintain the voltage of the first electrode of the third-first transistor ST3-1 and the second electrode of the third-second transistor ST3-2 formed integrally, thereby reducing a leakage current flowing through the third-first transistor ST3-1 and the third-second transistor ST3-2.

[0135] Figure 7 is a circuit diagram of a fingerprint sensor of a display device according to some embodiments.

[0136] Reference Figure 7 , the fingerprint sensor OPD may be connected to the first gate line GWL, the reset signal line GRL, the reset voltage line VRL, the second initialization voltage line VIL2, the readout line ROL, and the low potential line VSSL.

[0137] The fingerprint sensor OPD may include a light receiving element PD and a sensor circuit for driving the light receiving element PD. The sensor circuit may include a first sensor transistor PT1, a second sensor transistor PT2, and a third sensor transistor PT3.

[0138] The first sensor transistor PT1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first sensor transistor PT1 may be connected to a sensor node NS, the first electrode of the first sensor transistor PT1 may be connected to a third sensor transistor PT3, and the second electrode of the first sensor transistor PT1 may be connected to a second initialization voltage line VIL2. The first sensor transistor PT1 may control a source-drain current (Isd') (hereinafter referred to as "sensing current") based on a voltage of the sensor node NS which is a first electrode of the light receiving element PD. The sensing current (Isd') flowing through the channel of the first sensor transistor PT1 may be proportional to the square of the difference between the threshold voltage (Vth') and the voltage (Vsg') between the source electrode and the gate electrode of the first sensor transistor PT1 (Isd'=k'×(Vsg'-Vth') 2 ). Herein, k' is a proportionality coefficient determined by the structure and physical characteristics of the first sensor transistor PT1, Vsg' is a source-gate voltage of the first sensor transistor PT1, and Vth' is a threshold voltage of the first sensor transistor PT1. The first electrode of the first sensor transistor PT1 may be a source electrode, and the second electrode of the first sensor transistor PT1 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0139] The second sensor transistor PT2 may be turned on by the reset signal of the reset signal line GRL to provide a reset voltage to the sensor node NS. The second sensor transistor PT2 may include a second-first sensor transistor PT2-1 and a second-second sensor transistor PT2-2 connected in series. The second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may be connected in series between the reset voltage line VRL and the light receiving element PD. The gate electrode of the second-first sensor transistor PT2-1 and the gate electrode of the second-second sensor transistor PT2-2 may be integrally formed and electrically connected to the reset signal line GRL. The first electrode of the second-first sensor transistor PT2-1 may be connected to the reset voltage line VRL, and the second electrode of the second-second sensor transistor PT2-2 may be connected to the first electrode of the light receiving element PD. The second electrode of the second-first sensor transistor PT2-1 and the first electrode of the second-second sensor transistor PT2-2 may be integrally formed. A first electrode of each of the second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may be a source electrode, and a second electrode of each of the second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0140] The third sensor transistor PT3 may be turned on by the first gate signal of the first gate line GWL to electrically connect the first electrode of the first sensor transistor PT1 to the readout line ROL. The third sensor transistor PT3 may include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be connected in series between the first electrode of the first sensor transistor PT1 and the readout line ROL. The gate electrode of the third-first sensor transistor PT3-1 and the gate electrode of the third-second sensor transistor PT3-2 may be integrally formed and electrically connected to the first gate line GWL. The first electrode of the third-first sensor transistor PT3-1 may be connected to the readout line ROL, and the second electrode of the third-second sensor transistor PT3-2 may be connected to the first electrode of the first sensor transistor PT1. The second electrode of the third-first sensor transistor PT3-1 and the first electrode of the third-second sensor transistor PT3-2 may be integrally formed. A first electrode of each of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be a source electrode, and a second electrode of each of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be a drain electrode, but embodiments according to the present disclosure are not limited thereto.

[0141] The light receiving element PD can recognize the pattern of the user's fingerprint based on the light reflected from the user's finger. The first electrode of the light receiving element PD can be connected to the sensor node NS which is the gate electrode of the first sensor transistor PT1, and the second electrode of the light receiving element PD can be connected to the low potential line VSSL. The second electrode of the light receiving element PD can receive a low potential voltage from the low potential line VSSL.

[0142] When the user's finger touches the display panel 100, the light receiving element PD may receive light reflected by the ridge or valley of the finger. The light output from the light emitting element ED may be reflected by the ridge or valley of the finger, and the reflected light may reach the light receiving element PD. The light receiving element PD may convert the energy of light into an electrical signal (current or voltage) formed between the first electrode and the second electrode of the light receiving element PD, and the converted electrical signal may flow from the low potential line VSSL to the sensor node NS as a reverse bias current. For example, when the light receiving element PD receives light and an electric field is formed between the first electrode and the second electrode of the light receiving element PD, the reverse bias current may flow through the light receiving element PD in proportion to the amount of light, and the voltage at the sensor node NS may change. Therefore, when the light receiving element PD receives light, the voltage at the sensor node NS may decrease, and the sensing current (or source-drain current) may flow in the first sensor transistor PT1. The sensing current of the first sensor transistor PT1 may be applied to the display driver 200 as a sensing signal through the third sensor transistor PT3 and the readout line ROL.

[0143] Each of the first sensor transistor PT1, the second sensor transistor PT2, and the third sensor transistor PT3 may include a silicon-based semiconductor region. For example, each of the first sensor transistor PT1, the second sensor transistor PT2, and the third sensor transistor PT3 may include a semiconductor region made of low-temperature polycrystalline silicon (LTPS). The semiconductor region made of low-temperature polycrystalline silicon may have high electron mobility and excellent conduction characteristics. Therefore, the display device 10 includes the first sensor transistor PT1, the second sensor transistor PT2, and the third sensor transistor PT3 having excellent conduction characteristics, thereby stably and effectively driving multiple fingerprint sensors OPD.

[0144] Each of the first sensor transistor PT1, the second sensor transistor PT2, and the third sensor transistor PT3 may correspond to a p-type transistor. For example, each of the first sensor transistor PT1, the second sensor transistor PT2, and the third sensor transistor PT3 may output a current flowing from the first electrode to the second electrode based on a gate low voltage applied to the gate electrode.

[0145] The display device 10 may include a sensor circuit consisting only of sensor transistors having a silicon-based semiconductor region, thereby reducing process time, saving process costs, and minimizing or reducing a non-display area NDA, compared to a case where the sensor circuit includes both a sensor transistor having a silicon-based semiconductor region and a sensor transistor having an oxide-based semiconductor region.

[0146] Figure 8 is a layout diagram showing pixels and a fingerprint sensor of a display device according to some embodiments. Fig. 9 is a layout diagram showing an active layer, a first gate layer, and a second gate layer of a pixel in a display device according to some embodiments. Fig.10 is a layout diagram showing a first source metal layer, a second source metal layer, and a third source metal layer of a pixel in a display device according to some embodiments. Fig.11 is along Fig. 9 and Fig.10 A cross-sectional view taken along line II'.

[0147] Reference Figures 8 to 11 , the display area DA may include a plurality of pixels SP and a fingerprint sensor OPD. The pixel circuit of the pixel SP and the sensor circuit of the fingerprint sensor OPD may be located in the same layer and share a gate line GL and a power line VL. The light emitting element ED of the pixel SP and the light receiving element PD of the fingerprint sensor OPD may be located in the same layer and may share a common electrode CAT corresponding to a second electrode of the light emitting element ED and a second electrode of the light receiving element PD.

[0148] The pixel SP may include a light emitting element ED and a pixel circuit for driving the light emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, and an eighth transistor ST8, and a first capacitor C1 and a second capacitor C2.

[0149] The first transistor ST1 may include a semiconductor region ACT1, a gate electrode GE1, a first electrode SE1, and a second electrode DE1. The semiconductor region ACT1, the first electrode SE1, and the second electrode DE1 of the first transistor ST1 may be located in the active layer ACTL, and the gate electrode GE1 of the first transistor ST1 may be located in the first gate layer GTL1. The gate electrode GE1 of the first transistor ST1 may be a portion of the first capacitor electrode CPE1 of the first gate layer GTL1 and may overlap with the semiconductor region ACT1 of the first transistor ST1.

[0150] The first capacitor electrode CPE1 may be electrically connected to the second electrode of the third-first transistor ST3-1 and the first electrode of the fourth-first transistor ST4-1 through the first connection electrode CE1 of the first source metal layer SDL1. The first electrode SE1 of the first transistor ST1 may be integrally formed with the second electrode DE2 of the second transistor ST2 and the second electrode of the fifth transistor ST5. The first electrode SE1 of the first transistor ST1 may be electrically connected to the second electrode of the eighth transistor ST8 through the second connection electrode CE2 of the first source metal layer SDL1. The second electrode DE1 of the first transistor ST1 may be integrally formed with the first electrode of the third-second transistor ST3-2 and the first electrode of the sixth transistor ST6.

[0151] The second transistor ST2 may include a semiconductor region ACT2, a gate electrode GE2, a first electrode SE2, and a second electrode DE2. The semiconductor region ACT2, the first electrode SE2, and the second electrode DE2 of the second transistor ST2 may be located in the active layer ACTL, and the gate electrode GE2 of the second transistor ST2 may be located in the first gate layer GTL1. The gate electrode GE2 of the second transistor ST2 may overlap with the semiconductor region ACT2 of the second transistor ST2 and may be a part of the first gate line GWL. The first gate line GWL may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode SE2 of the second transistor ST2 may be electrically connected to the data line DL of the third source metal layer SDL3 through the first data connection electrode DNE1 of the first source metal layer SDL1 and the second data connection electrode DNE2 of the second source metal layer SDL2. The data line DL may be located in the third source metal layer SDL3 and extend in the Y-axis direction. The second electrode DE2 of the second transistor ST2 may be formed integrally with the first electrode SE1 of the first transistor ST1 and the second electrode of the fifth transistor ST5. The second electrode DE2 of the second transistor ST2 may be electrically connected to the second electrode of the eighth transistor ST8 through the second connection electrode CE2 of the first source metal layer SDL1 .

[0152] The third transistor ST3 may include a third-first transistor ST3-1 and a third-second transistor ST3-2 connected in series. Each of the third-first transistor ST3-1 and the third-second transistor ST3-2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of each of the third-first transistor ST3-1 and the third-second transistor ST3-2 may be located in the active layer ACTL, and the gate electrode of each of the third-first transistor ST3-1 and the third-second transistor ST3-2 may be located in the first gate layer GTL1. The gate electrode of the third-first transistor ST3-1 may overlap with the semiconductor region of the third-first transistor ST3-1, and the gate electrode of the third-second transistor ST3-2 may overlap with the semiconductor region of the third-second transistor ST3-2.

[0153] The gate electrode of the third-first transistor ST3-1 and the gate electrode of the third-second transistor ST3-2 may be integrally formed. The gate electrode of the third-second transistor ST3-2 may be a portion of the first gate line GWL extending in the X-axis direction, and the gate electrode of the third-first transistor ST3-1 may be a portion of a protrusion protruding from the first gate line GWL in the Y-axis direction. The second electrode of the third-first transistor ST3-1 may be integrally formed with the first electrode of the fourth-first transistor ST4-1, and may be electrically connected to the first capacitor electrode CPE1 of the first gate layer GTL1 through the first connection electrode CE1 of the first source metal layer SDL1. The first electrode of the third-first transistor ST3-1, the second electrode of the third-second transistor ST3-2, and the first capacitor electrode CPE3 of the second capacitor C2 may be integrally formed. The second capacitor C2 may stably maintain the voltage of the first electrode of the third-first transistor ST3-1 and the voltage of the second electrode of the third-second transistor ST3-2, thereby reducing the leakage current flowing through the third-first transistor ST3-1 and the third-second transistor ST3-2. A first electrode of the third-second transistor ST3 - 2 may be integrally formed with the second electrode DE1 of the first transistor ST1 and the first electrode of the sixth transistor ST6 .

[0154] The fourth transistor ST4 may include a fourth-first transistor ST4-1 and a fourth-second transistor ST4-2 connected in series. Each of the fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of each of the fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may be located in the active layer ACTL, and the gate electrode of each of the fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 may be located in the first gate layer GTL1. The gate electrode of the fourth-first transistor ST4-1 may overlap with the semiconductor region of the fourth-first transistor ST4-1, and the gate electrode of the fourth-second transistor ST4-2 may overlap with the semiconductor region of the fourth-second transistor ST4-2.

[0155] The gate electrode of the fourth-first transistor ST4-1 and the gate electrode of the fourth-second transistor ST4-2 may be integrally formed and may be part of the second gate line GIL. The second gate line GIL may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode of the fourth-first transistor ST4-1 may be integrally formed with the second electrode of the third-first transistor ST3-1 and may be electrically connected to the first capacitor electrode CPE1 of the first gate layer GTL1 through the first connection electrode CE1 of the first source metal layer SDL1. The second electrode of the fourth-first transistor ST4-1 and the first electrode of the fourth-second transistor ST4-2 may be integrally formed. The second electrode of the fourth-second transistor ST4-2 may be electrically connected to the first initialization voltage line VIL1.

[0156] The first initialization voltage line VIL1 may include a first vertical initialization voltage line VIL1a and a first horizontal initialization voltage line VIL1b. The first vertical initialization voltage line VIL1a may be located in the first source metal layer SDL1 and extend in the Y-axis direction. The first vertical initialization voltage line VIL1a may contact the second electrode of the fourth-second transistor ST4-2. The first vertical initialization voltage line VIL1a may be located in some of the plurality of pixel columns. The first horizontal initialization voltage line VIL1b may be located in the second gate layer GTL2 and extend in the X-axis direction. The first horizontal initialization voltage line VIL1b may be located in some of the plurality of pixel rows. A plurality of first vertical initialization voltage lines VIL1a and a plurality of first horizontal initialization voltage lines VIL1b may be connected in a grid shape. Therefore, the first initialization voltage line VIL1 may provide a first initialization voltage to the second electrode of the fourth-second transistor ST4-2.

[0157] The fifth transistor ST5 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fifth transistor ST5 may be located in the active layer ACTL, and the gate electrode of the fifth transistor ST5 may be located in the first gate layer GTL1. The gate electrode of the fifth transistor ST5 may overlap with the semiconductor region of the fifth transistor ST5.

[0158] The gate electrode of the fifth transistor ST5 may be part of the emission control line EML. The emission control line EML may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode of the fifth transistor ST5 may be connected to the drive voltage line VDDL of the first source metal layer SDL1. The drive voltage line VDDL may be located in the first source metal layer SDL1 and extend in the Y-axis direction. The drive voltage line VDDL may provide a drive voltage to the first electrode of the fifth transistor ST5. The horizontal voltage line HVDL may be located in the second source metal layer SDL2 and extend in the X-axis direction. A plurality of drive voltage lines VDDL and a plurality of horizontal voltage lines HVDL may be connected in a grid shape. The second electrode of the fifth transistor ST5 may be integrally formed with the first electrode SE1 of the first transistor ST1 and the second electrode DE2 of the second transistor ST2. The second electrode of the fifth transistor ST5 may be electrically connected to the second electrode of the eighth transistor ST8 through the second connection electrode CE2 of the first source metal layer SDL1.

[0159] The sixth transistor ST6 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the sixth transistor ST6 may be located in the active layer ACTL, and the gate electrode of the sixth transistor ST6 may be located in the first gate layer GTL1. The gate electrode of the sixth transistor ST6 may overlap with the semiconductor region of the sixth transistor ST6.

[0160] The gate electrode of the sixth transistor ST6 may be part of the emission control line EML. The emission control line EML may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode of the sixth transistor ST6 may be integrally formed with the second electrode DE1 of the first transistor ST1 and the first electrode of the third-second transistor ST3-2. The second electrode of the sixth transistor ST6 may be integrally formed with the first electrode of the seventh transistor ST7 and may be electrically connected to the first electrode or the pixel electrode AE ​​of the light emitting element ED through the first anode connection electrode ANE1 of the first source metal layer SDL1, the second anode connection electrode ANE2 of the second source metal layer SDL2, and the third anode connection electrode ANE3 of the third source metal layer SDL3.

[0161] The second electrode or the common electrode CAT of the light emitting element ED may be electrically connected to a low potential line VSSL and may receive a low potential voltage from the low potential line VSSL.

[0162] The seventh transistor ST7 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the seventh transistor ST7 may be located in the active layer ACTL, and the gate electrode of the seventh transistor ST7 may be located in the first gate layer GTL1. The gate electrode of the seventh transistor ST7 may overlap with the semiconductor region of the seventh transistor ST7.

[0163] The gate electrode of the seventh transistor ST7 may be part of the third gate line GBL. The third gate line GBL may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode of the seventh transistor ST7 may be integrally formed with the second electrode of the sixth transistor ST6, and may be electrically connected to the first electrode or the pixel electrode AE ​​of the light emitting element ED through the first anode connection electrode ANE1, the second anode connection electrode ANE2, and the third anode connection electrode ANE3. The second electrode of the seventh transistor ST7 may be electrically connected to the second initialization voltage line VIL2.

[0164] The second initialization voltage line VIL2 may include a second vertical initialization voltage line VIL2a and a second horizontal initialization voltage line VIL2b. The second vertical initialization voltage line VIL2a may be located in the first source metal layer SDL1 and extend in the Y-axis direction. The second vertical initialization voltage line VIL2a may be located in some other pixel columns among the plurality of pixel columns. The second horizontal initialization voltage line VIL2b may be located in the second gate layer GTL2 and extend in the X-axis direction. The second horizontal initialization voltage line VIL2b may be located in some other pixel rows among the plurality of pixel rows. A plurality of second vertical initialization voltage lines VIL2a and a plurality of second horizontal initialization voltage lines VIL2b may be connected in a grid shape. Therefore, the second initialization voltage line VIL2 may provide a second initialization voltage to the second electrode of the seventh transistor ST7.

[0165] The eighth transistor ST8 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the eighth transistor ST8 may be located in the active layer ACTL, and the gate electrode of the eighth transistor ST8 may be located in the first gate layer GTL1. The gate electrode of the eighth transistor ST8 may overlap with the semiconductor region of the eighth transistor ST8.

[0166] The gate electrode of the eighth transistor ST8 may be part of the third gate line GBL. The third gate line GBL may be located in the first gate layer GTL1 and extend in the X-axis direction. The first electrode of the eighth transistor ST8 may be electrically connected to the second bridge line BRS2 through the third connection electrode CE3 of the first source metal layer SDL1. In this article, the second bridge line BRS2 electrically connected to the eighth transistor ST8 may correspond to the bias voltage line VBL. The second electrode of the eighth transistor ST8 may be electrically connected to the first electrode SE1 of the first transistor ST1, the second electrode DE2 of the second transistor ST2, and the second electrode of the fifth transistor ST5 through the second connection electrode CE2 of the first source metal layer SDL1.

[0167] The bridge wire BRS may include a first bridge wire BRS1 and a second bridge wire BRS2. The first bridge wire BRS1 may be located in the third source metal layer SDL3 and extend in the Y-axis direction (e.g., extend in parallel with the readout line ROL). The second bridge wire BRS2 may be located in the second source metal layer SDL2, may be connected to the first bridge wire BRS1, and may extend in the X-axis direction or in a direction opposite to the X-axis direction. The bridge wire BRS may be electrically connected to each of the data line DL, the power line VL, and the readout line ROL. Since the display device 10 includes the bridge wire BRS, the fan-out line extending from the display driver 200 to the display area DA may be omitted, and the size of the non-display area NDA may be minimized or reduced.

[0168] The first capacitor C1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The first capacitor electrode CPE1 may be located in the first gate layer GTL1 and integrally formed with the gate electrode GE1 of the first transistor ST1, and may be electrically connected to the second electrode of the third-first transistor ST3-1 and the first electrode of the fourth-first transistor ST4-1.

[0169] The second capacitor electrode CPE2 may be located in the second gate layer GTL2 and connected to the driving voltage line VDDL of the first source metal layer SDL1. Therefore, the second capacitor electrode CPE2 may receive a driving voltage from the driving voltage line VDDL.

[0170] The second capacitor C2 may include a first capacitor electrode CPE3 and a second capacitor electrode CPE4. The first capacitor electrode CPE3 of the second capacitor C2 may be located in the active layer ACTL and integrally formed with a first electrode of the third-first transistor ST3-1 and a second electrode of the third-second transistor ST3-2.

[0171] The second capacitor electrode CPE4 of the second capacitor C2 may be located in the second gate layer GTL2 and connected to the driving voltage line VDDL of the first source metal layer SDL1. Therefore, the second capacitor electrode CPE4 of the second capacitor C2 may receive a driving voltage from the driving voltage line VDDL.

[0172] exist Fig.11 In the embodiment, the display panel 100 may include a substrate SUB, a transistor layer TFTL (refer to Figure 2 )、Light Emitting Element Layer EDL (refer to Figure 2 ) and encapsulation layer TFEL.

[0173] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0174] The transistor layer TFTL may include a buffer layer BF, an active layer ACTL, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, an interlayer insulating layer ILD, a first source metal layer SDL1, a first passivation layer PAS1, a second source metal layer SDL2, a second passivation layer PAS2, a third source metal layer SDL3, a third passivation layer PAS3, and a planarization layer OC.

[0175] The buffer layer BF may be located on the substrate SUB. The buffer layer BF may include an inorganic insulating material capable of preventing or reducing the penetration of air, pollutants or moisture. The buffer layer BF may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer and an amorphous silicon layer, but is not limited thereto according to an embodiment of the present invention.

[0176] The active layer ACTL may be located on the buffer layer BF. The active layer ACTL may include a semiconductor region ACT1, first and second electrodes SE1 and DE1 of the first transistor ST1 and a semiconductor region ACT2, first and second electrodes SE2 and DE2 of the second transistor ST2.

[0177] The first gate insulating layer GI1 may be located on the active layer ACTL and the buffer layer BF. The first gate insulating layer GI1 may insulate the active layer ACTL from the first gate layer GTL1. The first gate insulating layer GI1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto according to an embodiment of the present invention.

[0178] The first gate layer GTL1 may be located on the first gate insulating layer GI1. The first gate layer GTL1 may include a gate electrode GE1 of the first transistor ST1, a gate electrode GE2 of the second transistor ST2, and a first capacitor electrode CPE1.

[0179] The second gate insulating layer GI2 may be on the first gate layer GTL1 and the first gate insulating layer GI1. The second gate insulating layer GI2 may insulate the first gate layer GTL1 from the second gate layer GTL2. The second gate insulating layer GI2 may be made of the material in the first gate insulating layer GI1.

[0180] The second gate layer GTL2 may be located on the second gate insulating layer GI2. The second gate layer GTL2 may include a second capacitor electrode CPE2.

[0181] The interlayer insulating layer ILD may be on the second gate layer GTL2 and the second gate insulating layer GI2. The interlayer insulating layer ILD may insulate the second gate layer GTL2 from the first source metal layer SDL1.

[0182] The first source metal layer SDL1 may be located on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a first data link electrode DNE1, a driving voltage line VDDL, a first link electrode CE1, a first vertical initialization voltage line VIL1a, and a second vertical initialization voltage line VIL2a.

[0183] The first passivation layer PAS1 may be on the first source metal layer SDL1 and the interlayer insulating layer ILD. The first passivation layer PAS1 may insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0184] The second source metal layer SDL2 may be located on the first passivation layer PAS1. The second source metal layer SDL2 may include a second data link electrode DNE2 and a horizontal voltage line HVDL.

[0185] The second passivation layer PAS2 may be on the second source metal layer SDL2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second source metal layer SDL2 from the third source metal layer SDL3.

[0186] The third source metal layer SDL3 may be located on the second passivation layer PAS2. The third source metal layer SDL3 may include a data line DL and a first bridge line BRS1.

[0187] The third passivation layer PAS3 may be located on the third source metal layer SDL3 and the second passivation layer PAS2. The third passivation layer PAS3 may protect the pixel circuit of the pixel SP.

[0188] The planarization layer OC may be located on the third passivation layer PAS3. The planarization layer OC may planarize the top of the transistor layer TFTL. The planarization layer OC may include an organic insulating material such as polyimide (PI).

[0189] The light emitting element layer EDL may include a pixel defining layer PDL and a light emitting element ED.

[0190] The pixel defining layer PDL may be located on the planarization layer OC. The pixel defining layer PDL may define a plurality of emission areas EA or a plurality of opening areas. The pixel defining layer PDL may separate and insulate the pixel electrodes AE of the plurality of pixels SP.

[0191] The light emitting element ED may be located on the planarization layer OC. The light emitting element ED of each of the plurality of pixels SP may include a pixel electrode AE, a light emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be located on the planarization layer OC. The pixel electrode AE ​​may overlap one of the plurality of emission areas EA defined by the pixel defining layer PDL. The pixel electrode AE ​​may receive a driving current from a pixel circuit of the pixel SP.

[0192] The light-emitting layer EL may be located on the pixel electrode AE. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. In the case where the light-emitting layer EL corresponds to the organic light-emitting layer, when a voltage (e.g., a set or predetermined voltage) is applied to the pixel electrode AE ​​in the pixel circuit of the pixel SP and the common electrode CAT receives a common voltage or a cathode voltage, holes may move to the light-emitting layer EL through the hole transport layer, electrons may move to the light-emitting layer EL through the electron transport layer, and holes and electrons may recombine with each other in the light-emitting layer EL to emit light.

[0193] The common electrode CAT may be disposed on the light emitting layer EL. For example, the common electrode CAT may be formed in the form of an electrode common to all pixels SP, rather than being dedicated to each of the pixels SP. The common electrode CAT may be located on the light emitting layer EL in the plurality of emission areas EA, and may be located on the pixel defining layer PDL in an area other than the plurality of emission areas EA.

[0194] The encapsulation layer TFEL may be located on the common electrode CAT to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent or reduce the penetration of pollutants, oxygen or moisture into the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one organic layer to protect the plurality of light emitting elements ED from impurities such as dust.

[0195] Fig.12 is a layout diagram showing an active layer, a first gate layer, and a second gate layer of a fingerprint sensor in a display device according to some embodiments. Fig.13 is a layout diagram showing a first source metal layer, a second source metal layer, and a third source metal layer of a fingerprint sensor in a display device according to some embodiments. Fig.14 is along Fig.12 and Fig.13 Hereinafter, the same configuration as that described above will be briefly described, or some descriptions of the same configuration as that described above may be omitted.

[0196] Reference Figure 12 to Figure 14 , the fingerprint sensor OPD may include a light receiving element PD and a sensor circuit for driving the light receiving element PD. The sensor circuit may include a first sensor transistor PT1, a second sensor transistor PT2, and a third sensor transistor PT3. The fingerprint sensor OPD may be connected to a first gate line GWL, a reset signal line GRL, a reset voltage line VRL, a second initialization voltage line VIL2, and a readout line ROL.

[0197] The first gate line GWL may be located in the first gate layer GTL1 and extend in the X-axis direction. The first gate line GWL may provide a first gate signal to a gate electrode of the third sensor transistor PT3.

[0198] The reset signal line GRL may be located in the second gate layer GTL2 and extend in the X-axis direction. The reset signal line GRL may provide a reset signal to the gate electrode of the second sensor transistor PT2 through the second sensor connection electrode PCE2 of the first source metal layer SDL1.

[0199] The reset voltage line VRL may provide a reset voltage to the first electrode PSE2-1 of the second-first sensor transistor PT2-1. The reset voltage line VRL may include a vertical reset voltage line VRLa and a horizontal reset voltage line VRLb. The vertical reset voltage line VRLa may be located in the third source metal layer SDL3 and extend in the Y-axis direction. The vertical reset voltage line VRLa may be arranged in parallel with the readout line ROL. The vertical reset voltage line VRLa may be connected to the horizontal reset voltage line VRLb of the second source metal layer SDL2.

[0200] The horizontal reset voltage line VRLb may be located in the second source metal layer SDL2 and extend in the X-axis direction. The horizontal reset voltage line VRLb may provide a reset voltage to the first electrode PSE2-1 of the second-first sensor transistor PT2-1 through the fourth sensor connection electrode PCE4 of the first source metal layer SDL1.

[0201] The second initialization voltage line VIL2 may include a second vertical initialization voltage line VIL2a and a second horizontal initialization voltage line VIL2b. The second horizontal initialization voltage line VIL2b may be located in the second gate layer GTL2 and extend in the X-axis direction. The second horizontal initialization voltage line VIL2b may be located in some other pixel rows among the plurality of pixel rows. The plurality of second vertical initialization voltage lines VIL2a and the plurality of second horizontal initialization voltage lines VIL2b may be connected in a grid shape. Therefore, the second initialization voltage line VIL2 may provide a second initialization voltage to the second electrode of the first sensor transistor PT1.

[0202] The first sensor transistor PT1 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the first sensor transistor PT1 may be located in the active layer ACTL, and the gate electrode of the first sensor transistor PT1 may be located in the first gate layer GTL1. The gate electrode of the first sensor transistor PT1 may overlap with the semiconductor region of the first sensor transistor PT1.

[0203] The gate electrode of the first sensor transistor PT1 may be electrically connected to the second electrode PDE2-2 of the second-second sensor transistor PT2-2 through the first sensor connection electrode PCE1 located in the first source metal layer SDL1. The first sensor connection electrode PCE1 may be electrically connected to the first electrode or sensor electrode PE of the light receiving element PD through the first sensor anode connection electrode PNE1 located in the second source metal layer SDL2 and the second sensor anode connection electrode PNE2 located in the third source metal layer SDL3. The first sensor connection electrode PCE1, the first sensor anode connection electrode PNE1 and the second sensor anode connection electrode PNE2 may correspond to Figure 7 The first electrode of the first sensor transistor PT1 may be integrally formed with the second electrode PDE3-2 of the third-second sensor transistor PT3-2. The second electrode of the first sensor transistor PT1 may be electrically connected to the second initialization voltage line VIL2.

[0204] The second sensor transistor PT2 may include a second-first sensor transistor PT2-1 and a second-second sensor transistor PT2-2 connected in series. The second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may include semiconductor regions PACT2-1 and PACT2-2, gate electrodes PGE2-1 and PGE2-2, first electrodes PSE2-1 and PSE2-2, and second electrodes PDE2-1 and PDE2-2, respectively. The semiconductor regions PACT2-1 and PACT2-2, the first electrodes PSE2-1 and PSE2-2, and the second electrodes PDE2-1 and PDE2-2 of the second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may be located in the active layer ACTL, and the gate electrodes PGE2-1 and PGE2-2 of the second-first sensor transistor PT2-1 and the second-second sensor transistor PT2-2 may be located in the first gate layer GTL1. The gate electrode PGE2-1 of the second-first sensor transistor PT2-1 may overlap the semiconductor region PACT2-1 of the second-first sensor transistor PT2-1, and the gate electrode PGE2-2 of the second-second sensor transistor PT2-2 may overlap the semiconductor region PACT2-2 of the second-second sensor transistor PT2-2.

[0205] The gate electrode PGE2-1 of the second-first sensor transistor PT2-1 and the gate electrode PGE2-2 of the second-second sensor transistor PT2-2 may be integrally formed. The gate electrode PGE2-1 of the second-first sensor transistor PT2-1 and the gate electrode PGE2-2 of the second-second sensor transistor PT2-2 may be electrically connected to the reset signal line GRL of the second gate layer GTL2 through the second sensor connection electrode PCE2 of the first source metal layer SDL1. The first electrode PSE2-1 of the second-first sensor transistor PT2-1 may be electrically connected to the horizontal reset voltage line VRLb of the second source metal layer SDL2 through the fourth sensor connection electrode PCE4 of the first source metal layer SDL1. The second electrode PDE2-1 of the second-first sensor transistor PT2-1 and the first electrode PSE2-2 of the second-second sensor transistor PT2-2 may be integrally formed. The second electrode PDE2-2 of the second-second sensor transistor PT2-2 may be electrically connected to the gate electrode of the first sensor transistor PT1 through the first sensor connection electrode PCE1 of the first source metal layer SDL1.

[0206] The third sensor transistor PT3 may include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may include semiconductor regions PACT3-1 and PACT3-2, gate electrodes PGE3-1 and PGE3-2, first electrodes PSE3-1 and PSE3-2, and second electrodes PDE3-1 and PDE3-2, respectively. The semiconductor regions PACT3-1 and PACT3-2, the first electrodes PSE3-1 and PSE3-2, and the second electrodes PDE3-1 and PDE3-2 of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be located in the active layer ACTL, and the gate electrodes PGE3-1 and PGE3-2 of the third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be located in the first gate layer GTL1. The gate electrode PGE3-1 of the third-first sensor transistor PT3-1 may overlap the semiconductor region PACT3-1 of the third-first sensor transistor PT3-1, and the gate electrode PGE3-2 of the third-second sensor transistor PT3-2 may overlap the semiconductor region PACT3-2 of the third-second sensor transistor PT3-2.

[0207] The gate electrode PGE3 - 1 of the third-first sensor transistor PT3 - 1 and the gate electrode PGE3 - 2 of the third-second sensor transistor PT3 - 2 may be integrally formed.

[0208] The gate electrode PGE3-1 of the third-first sensor transistor PT3-1 may be a part of the first gate line GWL extending in the X-axis direction, and the gate electrode PGE3-2 of the third-second sensor transistor PT3-2 may be a part of a protrusion protruding from the first gate line GWL in the Y-axis direction. The first electrode PSE3-1 of the third-first sensor transistor PT3-1 may be electrically connected to the readout line ROL of the third source metal layer SDL3 through the third sensor connection electrode PCE3 of the first source metal layer SDL1 and the readout electrode ROE of the second source metal layer SDL2. The readout line ROL may be located in the third source metal layer SDL3 and extend in the Y-axis direction, and may provide a sensing signal of the fingerprint sensor OPD to the display driver 200. The second electrode PDE3-1 of the third-first sensor transistor PT3-1 and the first electrode PSE3-2 of the third-second sensor transistor PT3-2 may be integrally formed. The second electrode PDE3-2 of the third-second sensor transistor PT3-2 may be integrally formed with the first electrode of the first sensor transistor PT1.

[0209] The light emitting element layer EDL may include a pixel defining layer PDL and a light receiving element PD. The light receiving element PD may be located on a planarization layer OC. The light receiving element PD of each of the plurality of fingerprint sensors OPD may include a sensor electrode PE, a light receiving layer RCL, and a common electrode CAT. The sensor electrode PE may be located on the planarization layer OC and may be located in the same layer as the pixel electrode AE ​​of the pixel SP. The sensor electrode PE may overlap one of the plurality of sensor areas PDA defined by the pixel defining layer PDL.

[0210] The light receiving layer RCL may be located on the sensor electrode PE. When the user's finger touches the display panel 100, the light receiving layer RCL may receive light reflected by the ridge or valley of the finger. The light output from the light emitting element ED may be reflected by the ridge or valley of the finger, and the reflected light may reach the light receiving layer RCL. The light receiving element PD may convert the energy of the light into an electrical signal (current or voltage) formed between the first electrode and the second electrode of the light receiving element PD, and the converted electrical signal may flow from the low potential line VSSL to the sensor node NS as a reverse bias current. For example, when the light receiving element PD receives light and an electric field is formed between the first electrode and the second electrode of the light receiving element PD, the reverse bias current may flow through the light receiving element PD in proportion to the amount of light, and the voltage at the sensor node NS may change. Therefore, when the light receiving element PD receives light, the voltage at the sensor node NS may decrease, and the sensing current (or source-drain current) may flow in the first sensor transistor PT1. The sensing current of the first sensor transistor PT1 may be applied to the display driver 200 as a sensing signal through the third sensor transistor PT3 and the readout line ROL.

[0211] The common electrode CAT may be located on the light receiving layer RCL. For example, the common electrode CAT may be implemented in the form of an electrode common to all fingerprint sensors OPD, rather than being dedicated to each of the fingerprint sensors OPD. The common electrode CAT may be located on the light receiving layer RCL in the plurality of sensor areas PDA, and may be located on the pixel defining layer PDL in an area other than the plurality of sensor areas PDA.

[0212] Fig.15 is a diagram showing one example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments. Fig.16 is a diagram illustrating another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments. Fig.17 is a diagram showing still another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments. Fig.18is a diagram showing still another example of arrangement of a pixel circuit and a sensor circuit in a display device according to some embodiments.

[0213] Reference Figures 15 to 18 , the display area DA may include a plurality of pixels SP and a plurality of fingerprint sensors OPD. The pixel circuits of the pixels SP and the sensor circuits of the fingerprint sensors OPD may be located in the same layer and share the gate lines GL and the power lines VL. The light emitting elements ED of the pixels SP and the light receiving elements PD of the fingerprint sensors OPD may be located in the same layer and may share a common electrode CAT corresponding to the second electrodes of the light emitting elements ED and the second electrodes of the light receiving elements PD.

[0214] exist Fig.15 In the embodiment, the display device 10 may include pixels SP and a fingerprint sensor OPD having a ratio of 2:1. Fig.16 In the embodiment, the display device 10 may include pixels SP and a fingerprint sensor OPD having a ratio of 4:1. Fig.17 In the embodiment, the display device 10 may include pixels SP and a fingerprint sensor OPD having a ratio of 6:1. Fig.18 In the embodiment, the display device 10 may include a pixel SP and a fingerprint sensor OPD having a ratio of 8:1. Figures 15 to 18 When the display device 10 includes a display area DA of the same size, as the proportion of the pixels SP increases, the proportion of the fingerprint sensor OPD can be reduced in the display area DA. Fig.18 The display device 10 may include a relatively large number of pixels SP to maximize the display resolution. Fig.15 The display device 10 may include a relatively large number of fingerprint sensors OPD to improve sensitivity.

[0215] The description of the embodiment described above is illustrative only, and those skilled in the art will understand that, according to the description of the embodiment described above, various modifications and equivalent other embodiments are possible. Therefore, the actual protection scope of the present invention should be determined by the appended claims and their equivalents, and all differences within the equivalent range of the contents stated in the claims should be interpreted as included in the protection scope determined by the claims and their equivalents.

Claims

1. A fingerprint sensor, comprising: a gate line on the substrate and configured to provide a gate signal; a reset voltage line configured to provide a reset voltage; an initialization voltage line, configured to provide an initialization voltage; a readout line on the gate line and configured to provide a sensing signal; a light receiving element on the readout line; a first sensor transistor configured to provide a sensing current based on a voltage of a sensor node, the sensor node being a first electrode of the light receiving element; a second sensor transistor including a second-first sensor transistor and a second-second sensor transistor connected in series between the reset voltage line and a gate electrode of the first sensor transistor; as well as The third sensor transistor includes a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and the first electrode of the first sensor transistor.

2. The fingerprint sensor according to claim 1, wherein: The respective semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor are in the same layer and include low temperature polysilicon.

3. The fingerprint sensor according to claim 1, wherein: The second sensor transistor is configured to provide the reset voltage to the sensor node based on a reset signal.

4. The fingerprint sensor according to claim 1, wherein: The third sensor transistor is configured to electrically connect the readout line to the first electrode of the first sensor transistor based on the gate signal.

5. The fingerprint sensor according to claim 1, further comprising: an active layer on the substrate and including semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor; a first gate layer, on the active layer; a second gate layer, on the first gate layer; a first source metal layer, on the second gate layer; a second source metal layer, on the first source metal layer; as well as A third source metal layer is on the second source metal layer and includes the readout line. 6 . The fingerprint sensor of claim 5 , further comprising a first sensor connection electrode in the first source metal layer and configured to electrically connect the gate electrode of the first sensor transistor to the second electrode of the second-second sensor transistor.

7. The fingerprint sensor according to claim 6, further comprising: a first sensor anode connection electrode in the second source metal layer and connected to the first sensor connection electrode; as well as A second sensor anode connecting electrode is in the third source metal layer and is configured to electrically connect the first sensor anode connecting electrode to the sensor electrode of the light receiving element.

8. The fingerprint sensor according to claim 5, further comprising: a reset signal line in the second gate layer and configured to provide a reset signal; as well as A second sensor connection electrode is in the first source metal layer and is configured to electrically connect the reset signal line to the gate electrode of each of the second-first sensor transistor and the second-second sensor transistor.

9. The fingerprint sensor according to claim 5, further comprising: a third sensor connection electrode in the first source metal layer and connected to the first electrode of the third-first sensor transistor; as well as A readout electrode is in the second source metal layer and is configured to electrically connect the third sensor connection electrode to the readout line.

10. The fingerprint sensor according to claim 5, wherein: The reset voltage line includes a horizontal reset voltage line in the second source metal layer and extending in a first direction, and a vertical reset voltage line in the third source metal layer and extending parallel to the readout line. 11 . The fingerprint sensor of claim 10 , further comprising a fourth sensor connection electrode in the first source metal layer and configured to electrically connect the first electrode of the second-first sensor transistor to the horizontal reset voltage line.

12. A display device, comprising: A pixel including a pixel circuit on a substrate and a light emitting element connected to the pixel circuit; A fingerprint sensor comprising a sensor circuit and a light receiving element, the sensor circuit being in the same layer as the pixel circuit, the light receiving element being connected to the sensor circuit and being in the same layer as the light emitting element; a gate line configured to provide a gate signal to the pixel circuit and the sensor circuit; a reset voltage line configured to provide a reset voltage to the sensor circuit; A first initialization voltage line, configured to provide a first initialization voltage to the pixel circuit; a second initialization voltage line configured to provide a second initialization voltage to the pixel circuit and the sensor circuit; as well as a sense line configured to receive a sensing signal from the sensor circuit, Wherein, the sensor circuit comprises: a first sensor transistor configured to control a sensing current based on a voltage of a sensor node, the sensor node being a first electrode of the light receiving element; a second sensor transistor including a second-first sensor transistor and a second-second sensor transistor connected in series between the reset voltage line and a gate electrode of the first sensor transistor; and The third sensor transistor includes a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and the first electrode of the first sensor transistor.

13. The display device according to claim 12, wherein: The respective semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor are in the same layer and include low temperature polysilicon.

14. The display device according to claim 12, further comprising: an active layer on the substrate and including semiconductor regions of the first sensor transistor, the second sensor transistor, and the third sensor transistor; a first gate layer, on the active layer; a second gate layer, on the first gate layer; a first source metal layer, on the second gate layer; a second source metal layer, on the first source metal layer; as well as A third source metal layer is on the second source metal layer and includes the readout line.

15. The display device according to claim 14, further comprising: a display driver configured to drive the pixels and the fingerprint sensor; a data line connected to the display driver, extending in a first direction, and configured to provide a data voltage to the pixel; a first bridge line connected to the display driver and extending in the first direction; as well as The second bridge line electrically connects the first bridge line to the data line or the readout line.

16. The display device according to claim 15, wherein: The first bridge line extends in the third source metal layer and in parallel with the readout line, and The second bridge line is in the second source metal layer and extends in a second direction intersecting the first direction.

17. A display device, comprising: A pixel including a pixel circuit on a substrate and a light emitting element connected to the pixel circuit; A fingerprint sensor comprising a sensor circuit and a light receiving element, the sensor circuit being in the same layer as the pixel circuit, the light receiving element being connected to the sensor circuit and being in the same layer as the light emitting element; as well as a sense line configured to provide a sense signal received from the sensor circuit, Wherein, the pixel circuit comprises: a first transistor configured to control a driving current flowing through the light emitting element; a second transistor configured to provide a data voltage to a first electrode of the first transistor; a third transistor configured to electrically connect the second electrode of the first transistor to the gate electrode of the first transistor; a fourth transistor configured to discharge the gate electrode of the first transistor to a first initialization voltage; a fifth transistor configured to provide a driving voltage to the first electrode of the first transistor; a sixth transistor configured to electrically connect the second electrode of the first transistor to the first electrode of the light emitting element; a seventh transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage; and an eighth transistor configured to provide a bias voltage to the first electrode of the first transistor, and Wherein, the sensor circuit comprises: a first sensor transistor configured to control a sensing current based on a voltage of a sensor node which is a first electrode of the light receiving element; a second sensor transistor configured to provide a reset voltage to the sensor node which is a gate electrode of the first sensor transistor; and a third sensor transistor configured to electrically connect the readout line to the first electrode of the first sensor transistor, Wherein, the semiconductor regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor of the pixel circuit are in the same layer as the semiconductor regions of the first sensor transistor, the second sensor transistor and the third sensor transistor of the sensor circuit and contain low-temperature polycrystalline silicon.

18. The display device according to claim 17, wherein: The third transistor includes a third-first transistor and a third-second transistor connected in series between the gate electrode of the first transistor and the second electrode of the first transistor, and The fourth transistor includes a fourth-first transistor and a fourth-second transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line providing the first initialization voltage.

19. The display device according to claim 18, wherein: The second sensor transistor includes a second-first sensor transistor and a second-second sensor transistor connected in series between a reset voltage line configured to provide the reset voltage and the sensor node, and The third sensor transistor includes a third-first sensor transistor and a third-second sensor transistor connected in series between the readout line and the first electrode of the first sensor transistor.

20. The display device according to claim 17, further comprising: a display driver configured to drive the pixels and the fingerprint sensor; a data line connected to the display driver, extending in a first direction, and configured to provide the data voltage to the pixel; a first bridge line connected to the display driver and extending in the first direction; as well as The second bridge line electrically connects the first bridge line to the data line or the readout line.

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