Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises shifting registers from the first level to the Nth level which are cascaded, and further comprises auxiliary units from the first level to the (N-2m) th level which are arranged in the first direction. The ith auxiliary unit is electrically connected with the (i-m + 1) th-level shift register cascaded along the first scanning direction through the first scanning control unit; the first scanning control unit is used for being started when the scanning direction of the first scanning drive circuit is the first scanning direction. The jth auxiliary unit is electrically connected with the (j + m + 1) th-level shift register cascaded along the second scanning direction through the second scanning control unit; the second scanning control unit is used for being started when the scanning direction of the first scanning drive circuit is a second scanning direction, and the second scanning direction is opposite to the first scanning direction. According to the embodiment of the invention, the number of prepared driving circuits is reduced, so that a narrow frame of the display panel is realized or the space area of the display panel is saved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes multiple drive units. The operation of the display panel requires multiple drive signals to perform different working processes, so a large number of drive units are needed in the display panel. The preparation of multiple drive units tends to occupy a large space of the display panel, which is not conducive to achieving a narrow frame, improving the space utilization of the display panel, and increasing the screen-to-body ratio. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including:

[0005] A plurality of pixel circuits, wherein the pixel circuits include a driving transistor, a first module and a second module, and at least one of the first module and the second module is electrically connected to the driving transistor; in a working cycle of the pixel circuit, a start time of the first module is later than a start time of the second module;

[0006] A plurality of first scan lines and a plurality of second scan lines, the first scan lines are electrically connected to the control end of the first module, and the second scan lines are electrically connected to the control end of the second module;

[0007] The first scanning driving circuit comprises a first stage to an Nth stage shift register cascaded along a first scanning direction, wherein an output end of the shift register is electrically connected to the first scanning line;

[0008] The 1st to (N-2m)th auxiliary units are arranged along a first direction, and the output ends of the auxiliary units are electrically connected to the second scanning line; the first direction is parallel to the first scanning direction;

[0009] A plurality of first scanning control units, wherein the i-th auxiliary unit arranged along the first direction is electrically connected to the i-m+1-th stage shift register cascaded along the first scanning direction through the first scanning control unit; the first scanning control unit is used to be turned on when the scanning direction of the first scanning driving circuit is the first scanning direction;

[0010] A plurality of second scanning control units, wherein the j-th auxiliary unit arranged along the first direction is electrically connected to the j+m+1-th stage shift register cascaded along the second scanning direction through the second scanning control unit; the second scanning control unit is used to be turned on when the scanning direction of the first scanning driving circuit is the second scanning direction, and the second scanning direction is opposite to the first scanning direction;

[0011] 1≤i≤(N-2m), 1≤j≤(N-2m), m≥1.

[0012] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0013] In the embodiment of the present application, the display panel is provided with not only a shift register for outputting control signals required by circuits such as pixel circuits, but also an auxiliary unit for outputting control signals required by circuits such as pixel circuits, which is conducive to reducing the number of scanning drive circuits required to be prepared in the display panel by using the auxiliary unit. In addition, the number of auxiliary units arranged along the first direction is 2m less than the number of shift registers, and there is an electrical connection between the auxiliary unit and the shift register, which is conducive to providing feasible conditions for the shift register to provide drive signals to the auxiliary unit, providing feasible conditions for reducing the preparation of the drive unit in the display panel, and being conducive to reducing the number of prepared drive circuits when setting the display panel along the first scanning direction and the second scanning direction, thereby achieving a narrow frame of the display panel or saving the space area of ​​the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0015] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0016] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of a shift register circuit provided in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of an auxiliary unit provided in an embodiment of the present application;

[0019] Figure 5 A method provided in the embodiment of the present application Figure 1 A schematic plan view of the middle area E1;

[0020] Figure 6 A working timing diagram of a display panel provided in an embodiment of the present application;

[0021] Figure 7 A working timing diagram of another display panel provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of another shift register provided in an embodiment of the present application;

[0023] Fig. 9 A schematic plan view of another area E1 provided in an embodiment of the present application;

[0024] Fig.10 A schematic plan view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0026] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0027] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0028] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0029] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0030] It should be understood that although the terms first, second, etc. may be used to describe modules, scan lines, control transistors, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish modules, scan lines, control transistors, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first module may also be referred to as the second module, and similarly, the second module may also be referred to as the first module. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0031] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application, Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 3 A schematic diagram of a shift register circuit provided in an embodiment of the present application is provided. Figure 4 A schematic diagram of an auxiliary unit provided in an embodiment of the present application, Figure 5 A method provided in the embodiment of the present application Figure 1 Schematic plan view of the middle area E1.

[0032] The present application embodiment provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a plurality of pixel circuits A10. Figure 2 As shown, the pixel circuit A10 includes a driving transistor Md, a first module 10 and a second module 20. The driving transistor Md can generate a light-emitting driving current to drive the light-emitting element 200 to emit light. At least one of the first module 10 and the second module 20 in the pixel circuit A10 is electrically connected to the driving transistor Md. In a working cycle of the pixel circuit A10, the opening time of the first module 10 is later than the opening time of the second module 20.

[0033] The display panel 100 further includes a plurality of first scan lines SL1 and a plurality of second scan lines SL2, wherein the first scan lines SL1 are electrically connected to the control terminal 101 of the first module 10, and the second scan lines SL2 are electrically connected to the control terminal 201 of the second module 20. In combination with the fact that the first module 10 is turned on later than the second module 20 in one working cycle of the pixel circuit A10, it can be seen that the first scan line SL1 and the second scan line SL2 transmit valid signals at different times, resulting in different turn-on times of the first module 10 and the second module 20. In one working cycle of the pixel circuit A10, the first scan line SL1 transmits a valid signal earlier than the second scan line SL2.

[0034] Combination Figure 3 As shown, the display panel 100 further includes a first scan driving circuit A20, and the first scan driving circuit A20 includes 1st to Nth shift registers VSR cascaded along the first scanning direction J1. Optionally, the first scan driving circuit A20 includes N cascaded shift registers VSR. The output end of the shift register VSR is electrically connected to the first scan line SL1, and the shift register VSR can output a driving signal for controlling the operation of the first module 10.

[0035] In the related art, according to the working requirements of the display panel, a shift register that can be cascaded in the forward direction and a shift register that can be cascaded in the reverse direction are included. However, the preparation of such a function will add a driving unit prepared in the display panel, which is easy to occupy a larger position in the display panel, which is not conducive to realizing a narrow frame of the display panel or squeezing the space of other circuit units. Therefore, in order to reduce the area of ​​the display panel 100 occupied by the driving unit when including the forward and reverse scanning functions in the display panel 100, the technical solution of the present application is proposed.

[0036] Combination Figure 4 As shown, the display panel 100 also includes the 1st to (N-2m)th auxiliary units A30 arranged along the first direction X1, and then includes (N-2m) auxiliary units A30 in the first direction X1. The output end of the auxiliary unit A30 is electrically connected to the second scan line SL2, and the auxiliary unit A30 can be used to output a driving signal for controlling the operation of the second module 20, which is beneficial to save the scanning drive circuit prepared separately for outputting the driving signal for controlling the operation of the second module 20, and reduces the number of drive circuits prepared in the display panel. Among them, the first direction X1 is parallel to the first scanning direction J1. Then, the N cascaded shift registers VSR in the first scanning drive circuit A20 can also be arranged along the first direction X1, which is the same as the arrangement of the (N-2m) auxiliary units A30 arranged in the first direction X1.

[0037] The display panel 100 also includes a plurality of first scanning control units A40, and the i-th auxiliary unit A30(i) arranged along the first direction X2 is electrically connected to the i-m+1-th shift register VSR(i-m+1) cascaded along the first scanning direction J1 through the first scanning control unit A40, 1≤i≤(N-2m), m≥1, which is beneficial for utilizing the first scanning control unit A40 to electrically connect the auxiliary unit A30 with the shift register VSR, thereby facilitating the auxiliary unit A30 to utilize part of the circuit in the shift register VSR to complete the function of outputting the control signal required by the second module 20, thereby facilitating saving the need to prepare part of the circuit structure in the driving unit for outputting the control signal required by the second module 20.

[0038] In combination with the above content, it is proposed that the first scan driving circuit A20 includes N cascaded shift registers VSR, and (N-2m) auxiliary units A30 are arranged in the first direction X1. Among the multiple auxiliary units A30 and the shift register VSR arranged in the first direction X1, the number of auxiliary units A30 is 2m less than the number of shift registers VSR. Therefore, setting the i-th auxiliary unit A30 (i) and the i-m+1-th shift register VSR (i-m+1) is conducive to reducing the number of auxiliary units A30 prepared, and using the signal in the i-m+1-th shift register VSR (i-m+1) to drive the auxiliary unit A30 to work, so as to avoid the auxiliary unit A30 requiring an additional circuit to provide a driving signal. Moreover, it is beneficial to realize that when the i-m+1th level shift register VSR(i-m+1) is working, the i-th auxiliary unit A30(i) also starts working, thereby completing the i-th auxiliary unit A30 starting to work before the i+m-th level shift register VSR(i+m) works, and realizing that in one working cycle of the pixel circuit A10, the second scanning signal line SL2 transmits a valid signal before the first scanning signal line SL1, so that the start time of the first module 10 is later than the start time of the second module 20.

[0039] The first scanning control unit A40 is set to be turned on when the scanning direction of the first scanning driving circuit A20 is the first scanning direction J1, that is, when the cascade direction of the multiple shift registers VSR of the first scanning driving circuit A20 is in the first scanning direction J1, the first scanning control unit A40 is turned on, so that the multiple auxiliary units A30 arranged along the first direction X1 are also turned on along the first scanning direction J1.

[0040] In addition, the display panel 100 further includes a plurality of second scanning control units A50, and the j-th auxiliary unit A30 arranged along the first direction X1 is electrically connected to the j+m-th shift register VSR(j+m+1) of the cascade J1 along the first scanning direction through the second scanning control unit A50. The second scanning control unit A50 is used to be turned on when the scanning direction of the first scanning driving circuit A20 is the second scanning direction J2, and the second scanning direction J2 is opposite to the first scanning direction J1. In the embodiment of the present application, the first scanning direction J1 is described as the forward scanning direction, and the second scanning direction X2 is described as the reverse scanning direction. When the driving unit in the display panel 100 is in the reverse scanning mode, it is beneficial to use the second scanning control unit A50 to electrically connect the auxiliary unit A30 with the shift register VSR, so that the auxiliary unit A30 uses part of the circuit in the shift register VSR to complete the function of outputting the control signal required by the second module 20, thereby saving the part of the circuit in the driving unit that needs to be prepared to output the control signal required by the second module 20.

[0041] In combination with the above content, setting the j-th auxiliary unit A30(j) and the j+m+1-th shift register VSR(j+m+1), 1≤j≤(N-2m), m≥1, is beneficial to reducing the number of auxiliary units A30 prepared, and using the signal in the j+m+1-th shift register VSR(j+m+1) to drive the auxiliary unit A30 to work, thereby avoiding the need for an additional circuit to provide a driving signal for the auxiliary unit A30. The structure is thus conducive to reducing the necessity of preparing additional auxiliary units A30 when scanning along the second scanning direction J2, and is conducive to achieving that when the j+m+1th level shift register VSR(j+m+1) is working, the jth auxiliary unit A30(j) also starts working, thereby completing the jth auxiliary unit A30(j) starting to work before the j+mth level shift register VSR(j+m) works, and achieving in one working cycle of the pixel circuit A10 that the second scanning signal line SL2 transmits a valid signal before the first scanning signal line SL1, so that the start time of the first module 10 is later than the start time of the second module 20.

[0042] In the embodiment of the present application, the display panel 100 is provided with not only a shift register VSR for outputting control signals required by circuits such as the pixel circuit A10, but also an auxiliary unit A30 for outputting control signals required by circuits such as the pixel circuit A10, which is conducive to using the auxiliary unit A30 to reduce the number of scan drive circuits required to be prepared in the display panel 100. In addition, the number of auxiliary units A30 arranged along the first direction X1 is 2m less than the number of shift registers VSR, and there is an electrical connection between the auxiliary unit A30 and the shift register VSR, which is conducive to providing feasible conditions for the shift register VSR to provide a drive signal to the auxiliary unit A30, providing a feasible condition for reducing the preparation of the drive unit in the display panel 100, and being conducive to reducing the number of prepared drive circuits when the display panel 100 is provided along the first scanning direction X1 and the second scanning direction X2, thereby achieving a narrow frame of the display panel 100 or saving the space area of ​​the display panel 100.

[0043] Figure 6 A working timing diagram of a display panel provided in an embodiment of the present application, Figure 7 A working timing diagram of another display panel provided in an embodiment of the present application.

[0044] In one embodiment of the present application, Figure 1 , Figure 5 As shown, m=1 is set.

[0045] Taking N=6, that is, taking the first to sixth shift registers VSR included in the same first scan driving circuit A20 as an example, at this time, the number of auxiliary units A30 arranged along the first direction X1 needs to be set to be 2m less, that is, the number of auxiliary units A30 arranged in the first direction X1 can be set to 4. It can be seen that at this time, the number of shift registers VSR arranged along the first direction X1 is 2 more than the auxiliary unit A30, and optionally, the extra shift registers VSR can be used to provide a trigger signal for cascading multiple shift registers VSR and starting the auxiliary unit A30.

[0046] It should be noted that if Figure 6 , Figure 7 As shown, taking N=6, m=1 as an example, Figure 6 , Figure 7 The S1(n) represented in the figure is the control signal S1 outputted from the output terminal OUT of the n-th stage shift register VSR(n), and the value range of n is an integer between 1 and 6. Figure 6 , Figure 7 The S2(i) represented in the figure is the control signal S2 outputted from the output terminal of the i-th auxiliary unit A30(i), and the value range of i is an integer between 1-4.

[0047] For example, in combination Figure 6As shown, optionally, the signals output by the first scanning line SL1 and the second scanning line SL2 are valid when they are at a low level. The first to sixth shift register circuits VSR are scanned along the first scanning direction J1. When i=1, the first auxiliary unit A30(1) is electrically connected to the first shift register circuit VSR(1) through the first scanning control unit A40. Similarly, when i=2, the second auxiliary unit A30(2) is electrically connected to the second shift register circuit VSR(2). ..., when i=4, the fourth auxiliary unit A30(2) is electrically connected to the fourth shift register circuit VSR(2). It should be noted that, optionally, the trigger terminal IN of the first shift register VSR(1) can receive the first trigger signal, and the signal S1(1) generated by the output terminal OUT of the first shift register VSR(1) can be used to provide a trigger signal for the second shift register VSR(2). The second-stage shift register VSR(2) is electrically connected to the pixel circuit A10 in the same row as the first auxiliary unit A30(1), the third-stage shift register VSR(3) is electrically connected to the pixel circuit A10 in the same row as the second auxiliary unit A30(2), the fourth-stage shift register VSR(4) is electrically connected to the pixel circuit A10 in the same row as the third auxiliary unit A30(3), and the fifth-stage shift register VSR(5) is electrically connected to the pixel circuit A10 in the same row as the fourth auxiliary unit A30(4). Therefore, when the first-stage shift register VSR(1) is working, the first auxiliary unit A30(1) also starts working, and the pixel circuit A10 in the pixel row electrically connected to the first auxiliary unit A30(1) receives the effective control signal transmitted by the second scan line SL2, and the second module 20 in the pixel circuit A10 is turned on. In the cascaded shift register VSR, the output end of the previous stage shift register VSR is electrically connected to the trigger end of the next stage shift register VSR. When the output end of the previous stage shift register VSR outputs a signal, the next stage shift register VSR is triggered to start working. Therefore, the second stage shift register VSR (2) starts working after receiving the trigger signal provided by the first stage shift register VSR (1). The second stage shift register VSR (2) is electrically connected to the second auxiliary unit A30 (2). When the second stage shift register VSR (2) starts working, the pixel circuit A10 in the pixel row electrically connected to the second stage shift register VSR (2) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the second stage shift register VSR (2) and the first auxiliary unit A30 (1) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the second auxiliary unit A30 (2) also starts working.Similarly, when the third-stage shift register VSR(3) starts to work, the pixel circuit A10 in the pixel row electrically connected to the third-stage shift register VSR(3) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the third-stage shift register VSR(3) and the second auxiliary unit A30(2) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the third auxiliary unit A30(3) also starts to work. When the fourth shift register VSR (4) starts to work, the pixel circuit A10 in the pixel row electrically connected to the fourth shift register VSR (4) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fourth shift register VSR (4) and the third auxiliary unit A30 (3) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the fourth auxiliary unit A30 (4) also starts to work. When the fifth shift register VSR (5) starts to work, the pixel circuit A10 in the pixel row electrically connected to the fifth shift register VSR (5) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fifth shift register VSR (5) and the fourth auxiliary unit A30 (4) completes the work of the second module 20 and the first module 10. Optionally, the sixth stage shift register VSR (6) may be used to receive a trigger signal output by the fifth stage shift register VSR (5) to test whether the cascade connection of the plurality of shift registers VSR in the first scan driving circuit A20 is working normally.

[0048] For example, in combination Figure 7As shown, optionally, the signals output by the first scanning line SL1 and the second scanning line SL2 are valid when they are at a low level. The first to sixth shift register circuits VSR are scanned along the second scanning direction J2. When j=4, the fourth auxiliary unit A30(4) is electrically connected to the sixth shift register circuit VSR(6) through the second scanning control unit A50. Similarly, when j=3, the third auxiliary unit A30(3) is electrically connected to the fifth shift register circuit VSR(5). ..., when j=1, the first auxiliary unit A30(1) is electrically connected to the third shift register circuit VSR(2). It should be noted that, optionally, the trigger terminal IN of the sixth-stage shift register VSR (6) can receive the second trigger signal STV2, and the control signal S1 (6) outputted by the output terminal OUT of the sixth-stage shift register VSR (6) can be used to provide a trigger signal to the fifth-stage shift register VSR (5); the fifth-stage shift register VSR (5) and the fourth auxiliary unit A30 (4) are electrically connected to the pixel circuit A10 in the same row; the fourth-stage shift register VSR (4) and the third auxiliary unit A30 (3) are electrically connected to the pixel circuit A10 in the same row; the third-stage shift register VSR (3) and the second auxiliary unit A30 (2) are electrically connected to the pixel circuit A10 in the same row; and the second-stage shift register VSR (2) and the first auxiliary unit A30 (1) are electrically connected to the pixel circuit A10 in the same row. Therefore, when the sixth-stage shift register VSR (6) is working, the fourth auxiliary unit A30 (4) also starts working, and the pixel circuit A10 in the pixel row electrically connected to the fourth auxiliary unit A30 (1) receives the effective control signal transmitted by the second scan line SL2, and the second module 20 in the pixel circuit A10 is turned on. In the cascaded shift register VSR, the output end of the previous stage shift register VSR is electrically connected to the trigger end of the next stage shift register VSR. When the output end of the previous stage shift register VSR outputs a signal, the next stage shift register VSR is triggered to start working. Therefore, the fifth stage shift register VSR (5) starts working after receiving the trigger signal provided by the sixth stage shift register VSR (6). The fifth shift register VSR(5) is electrically connected to the third auxiliary unit A30(3). When the fifth shift register VSR(5) starts to work, the pixel circuit A10 in the pixel row electrically connected to the fifth shift register VSR(5) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fifth shift register VSR(5) and the fourth auxiliary unit A30(4) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the third auxiliary unit A30(3) also starts to work.Similarly, when the fourth-stage shift register VSR(4) starts to work, the pixel circuit A10 in the pixel row electrically connected to the fourth-stage shift register VSR(4) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fourth-stage shift register VSR(4) and the third auxiliary unit A30(3) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the second auxiliary unit A30(2) also starts to work. When the third-stage shift register VSR (3) starts to work, the pixel circuit A10 in the pixel row electrically connected to the third-stage shift register VSR (3) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the third-stage shift register VSR (3) and the second auxiliary unit A30 (2) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the first auxiliary unit A30 (1) also starts to work. When the second-stage shift register VSR (2) starts to work, the pixel circuit A10 in the pixel row electrically connected to the second-stage shift register VSR (2) receives the effective control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the second-stage shift register VSR (2) and the first auxiliary unit A30 (1) completes the work of the second module 20 and the first module 10. Optionally, the first stage shift register VSR(1) may be used to receive a trigger signal output by the second stage shift register VSR(2) to test whether the cascade connection of the multiple shift registers VSR in the first scan driving circuit A20 is working normally.

[0049] It should be noted that in some other embodiments, m can be set equal to other positive integers, for example, m=2. In this case, the time interval between the start-up time of the first module 10 and the second module 20 in the same pixel circuit A10 is the time for scanning 2 pixel rows.

[0050] In one embodiment of the present application, continue to refer to Figure 1 , Figure 5As shown, the output ends of the first to m-th and N-m+1-th to N-th shift registers VSR are not electrically connected to the first scan line SL1; and the m+1-th to Nm-th shift registers VSR are electrically connected to the first scan line SL1. In combination with the above embodiments, it can be seen that the number of N cascaded shift registers VSR in the same first scan drive circuit A20 is 2m more than the number of auxiliary units A30 arranged along the first direction X1, and the first module 10 and the second module 20 in the pixel circuit A10 both need to receive control signals, then the number of auxiliary units A30 can be equal to the number of pixel rows in the display panel 100, so as to ensure the stable operation of the first module 10 and the second module 20 of the pixel circuit A10 in each pixel row.

[0051] The shift registers VSR in the first to m-th level and the N-m+1-th level to the N-th level shift registers VSR are all shift registers VSR that are not electrically connected to the first scan line SL1, so it can be seen that the first to m-th level and the N-m+1-th level to the N-th level shift registers VSR are 2m shift registers VSR more than the auxiliary unit A30. Then, optionally, the first to m-th level and the j+m-th level to the N-th level shift registers VSR may not be electrically connected to the pixel circuit A10, and the first to m-th level and the j+m-th level to the N-th level shift registers VSR may be virtual shift registers, which are used to provide a trigger signal circuit for the shift register VSR electrically connected to the pixel circuit A10. Exemplarily, when the multiple cascaded shift registers VSR in the first scan drive circuit A20 scan along the first scan direction J1, the first to m-th level shift registers VSR are used to provide a drive signal for the auxiliary unit A30, so that the second module 20 starts the scan time of m rows earlier than the first module 10. Exemplarily, when the multiple cascaded shift registers VSR in the first scan driving circuit A20 scan along the second scan direction J2, the N-m+1th to Nth shift registers VSR are used to provide a driving signal for the auxiliary unit A30, so that the second module 20 starts scanning m rows earlier than the first module 10. For example, when N=6, m=1, and the multiple cascaded shift registers VSR in the first scan driving circuit A20 scan along the first scan direction J1, the first-stage shift register VSR(1) and the sixth-stage shift register VSR(6) are not electrically connected to the first scan line SL1, and the second-stage shift register VSR(2) to the fifth-stage shift register VSR(5) are electrically connected to the first scan line SL1.

[0052] In the embodiment of the present application, the output ends of the first to mth levels and the N-m+1th to Nth levels of the shift registers VSR are arranged to be non-electrically connected to the first scan line SL1; and the m+1th to Nmth levels of the shift registers VSR are electrically connected to the first scan line SL1, which is beneficial to multiplexing the circuit signals in the shift registers VSR as the driving signals of the auxiliary unit A30, and is beneficial to realizing that the pixel circuit A10 in the pixel row electrically connected to the auxiliary unit A30 and the shift register VSR can first receive the signal transmitted by the second scan line SL2 and then receive the signal transmitted by the first scan line SL1, which is beneficial to the stable operation of the pixel circuit A10.

[0053] In one embodiment of the present application, continue to refer to Figure 1 , Figure 3-Figure 5 As shown, the shift register VSR includes a control module V10 and an output module V20, the control module V10 is electrically connected to the control terminal of the output module V20 and is used to control the output module V20 to output an enable signal and a disable signal. Optionally, the high level signal VGH is a disable signal.

[0054] The control module V10 includes transistors M1 to M5, which are used to jointly control the output module V20 to output an enable signal and a disable signal.

[0055] The first scanning control unit A40 is connected between the control end of the auxiliary unit A30 and the control module V10 of the shift register VSR. In combination with the above, the auxiliary unit A30 is used to output the enable signal and the disable signal transmitted by the second scanning line SL2, so as to control the opening and closing of the second module 20 in the pixel circuit A10. Optionally, the signal received by the control end of the auxiliary unit A30 can be used to control the auxiliary unit A30 to output the enable signal or the disable signal. The control module V10 of the shift register VSR is electrically connected to the control end of the auxiliary unit A30 by using the first scanning control unit A40, which is conducive to multiplexing the signal generated by the control module V10 in the shift register VSR as a control unit for controlling the auxiliary unit A30 to transmit the enable signal or the disable signal. In addition, in the multiple pixel rows in the display panel 100, in order to save the scanning time of the display panel 100, the work of other stages is usually completed in advance before the current pixel row enters the light-emitting work, such as the reset stage, the data signal writing stage, etc. Therefore, when the multiple shift registers VSR scan along the first scanning direction J1, correspondingly, the multiple pixel circuits A10 electrically connected to the shift registers VSR also start to emit light in sequence along the first scanning direction J1. It can be understood that in the multiple working stages of the pixel circuit A10 before the light-emitting stage, the pixel circuits A10 in the multiple pixel rows also start different working stages in sequence along the first scanning direction J1. Therefore, when the first scanning control unit A40 is electrically connected between the i-m+1th shift register VSR(i-m+1) and the i-th auxiliary unit A30(i), the pixel row electrically connected to the i-m+1th shift register VSR(i-m+1) enters the light-emitting stage before the pixel row electrically connected before the i-th auxiliary unit A30(i). It is beneficial that when the enable signal transmitted by the i-m+1th level shift register VSR(i-m+1) controls the operation of the first module 10, after the pixel circuit A10 electrically connected to the i-th auxiliary unit A30(i) receives a valid signal, the second module 20 is turned on and enters another working stage before the first module 10 is turned on. In this stage, the second module 20 in the pixel circuit A10 electrically connected to the i-th auxiliary unit A30(i) is turned on, ensuring that the turn-on time of the second module 20 in the same pixel circuit A10 is earlier than the turn-on time of the first module 10.

[0056] The second scanning control unit A50 is connected between the control end of the auxiliary unit A30 and the control module V10 of the shift register VSR. Similarly, when the second scanning control unit A50 electrically connects the control module V10 of the shift register VSR to the auxiliary unit A30, it is beneficial to make the signal generated by the control module V10 of the shift register VSR not only control the output module V20 in the shift register VSR to output the enable signal and the disable signal, but also use the signal to multiplex as a control unit for controlling the auxiliary unit A30 to output the enable signal and the disable signal, which is beneficial to reduce the necessity of preparing a control circuit in cooperation with the auxiliary unit A30, thereby saving the circuit structure. When multiple shift registers VSR scan along the second scanning direction J2, correspondingly, multiple pixel circuits A10 electrically connected to the shift register VSR also start to emit light in sequence along the second scanning direction J2. It can be understood that in multiple working stages before the light-emitting stage of the pixel circuit A10, the pixel circuits A10 in multiple pixel rows also start different working stages in sequence along the second scanning direction J2. Therefore, when the first scanning control unit A40 is electrically connected between the j+m+1th shift register VSR(j+m+1) and the jth auxiliary unit A30(j), the pixel row electrically connected to the j+m+1th shift register VSR(j+m+1) enters the light-emitting stage before the pixel row electrically connected before the jth auxiliary unit A30. This is beneficial to make the pixel circuit A10 electrically connected to the jth auxiliary unit A30(j) receive a valid signal when the enable signal transmitted by the j+m+1th shift register VSR(j+m+1) controls the operation of the first module 10, and the second module 20 is turned on to enter another working stage before the first module 10 is turned on. In this stage, the second module 20 in the pixel circuit A10 electrically connected to the jth auxiliary unit A30(j) is turned on to ensure that the turn-on time of the second module 20 in the same pixel circuit A10 is earlier than the turn-on time of the first module 10.

[0057] In the embodiment of the present application, the first scanning control unit A40 is turned on when multiple shift registers VSR are cascaded along the first scanning direction J1, and the control module V10 of the shift register VSR is electrically connected to the control end of the auxiliary unit A30 by using the first scanning control unit A40; the second scanning control unit A50 is turned on when multiple shift registers VSR are cascaded along the second scanning direction J2, and the control module V10 of the shift register VSR is electrically connected to the control end of the auxiliary unit A30 by using the second scanning control unit A50, which is beneficial to reducing the circuit structure prepared in the display panel 100, and is beneficial to reducing the driving circuit prepared when the display panel 100 includes forward and reverse scanning functions, thereby helping to improve the space utilization and circuit utilization of the display panel 100, increase the possibility of preparing other functional modules in the display panel 100, and reduce the preparation cost of the display panel 100.

[0058] In one embodiment of the present application, continue to refer to Figure 3 As shown, the control module V10 includes a first node N1 and a second node N2, the output module V20 includes a first output module OUT1 and a second output module OUT2, the first output module OUT1 and the second output module OUT2 are electrically connected to the first node N1 and the second node N2 respectively, the first scanning control unit A40 is connected to the first node N1 and the second node N2, and the second scanning control unit A50 is electrically connected to the first node N1 and the second node N2.

[0059] Optionally, one of the first output module OUT1 and the second output module OUT2 in the first output module V20 outputs an enable signal, and the other outputs a disable signal; in the embodiment of the present application, the first output module OUT1 outputs a disable signal, and the second output module OUT2 outputs an enable signal as an example for explanation. Optionally, the first node N1 is electrically connected to the control end of the first output module OUT1, and the second node N2 is electrically connected to the control end of the second output module OUT2, which is conducive to using the circuit to receive and realize the synchronous control of the auxiliary unit V30 by the control module V10.

[0060] In one embodiment of the present application, continue to refer to Figure 4 , Figure 5 As shown, the auxiliary unit A30 includes a third output module OUT3 and a fourth output module OUT4, the first scanning control unit A40 includes a first subunit A401 and a second subunit A402, and the second scanning control unit A50 includes a third subunit A501 and a fourth subunit A502. Optionally, one of the third output module OUT3 and the fourth output module OUT4 in the auxiliary unit A30 outputs an enable signal and the other outputs a disable signal; in the embodiment of the present application, the third output module OUT3 outputs a disable signal and the fourth output module OUT4 outputs an enable signal as an example for description.

[0061] The first subunit A401 and the third subunit A501 are both electrically connected between the first node N1 and the control terminal of the third output module OUT3. The second subunit A402 and the fourth subunit A502 are both electrically connected between the second node N2 and the control terminal of the fourth output module OUT4.

[0062] When the multiple shift registers VSR are cascaded along the first scanning direction J1, the first scanning control unit A40 is turned on. Then the first subunit A401 and the second subunit A402 are also turned on. Using the first subunit A401 to electrically connect the first node N1 with the third output module OUT3 is conducive to the control module V10 controlling the first output module OUT1 to turn on the output non-enable signal, and at the same time controlling the third output module OUT3 of the auxiliary unit A30 to turn on the output non-enable signal. Using the second subunit A402 to electrically connect the second node N2 with the fourth output module OUT4 is conducive to the control module V10 controlling the second output module OUT2 to turn on the output enable signal, and at the same time controlling the fourth output module OUT4 of the auxiliary unit A30 to turn on the output enable signal.

[0063] When the plurality of shift registers VSR are cascaded along the second scanning direction J2, the second scanning control unit A40 is turned on. Then the third subunit A501 and the fourth subunit A502 are both turned on. The third subunit A501 is used to electrically connect the first node N1 with the third output module OUT3, which is conducive to the control module V10 controlling the first output module OUT1 to start outputting a non-enable signal, and at the same time controlling the third output module OUT3 of the auxiliary unit A30 to start outputting a non-enable signal. The fourth subunit A502 is used to electrically connect the second node N2 with the fourth output module OUT4, which is conducive to the control module V10 controlling the second output module OUT2 to start outputting an enable signal, and at the same time controlling the fourth output module OUT4 of the auxiliary unit A30 to start outputting an enable signal.

[0064] In one embodiment of the present application, Figure 3-Figure 5 As shown, the circuit structure of the third output module OUT3 is the same as that of the first output module OUT1 , and the circuit structure of the fourth output module OUT4 is the same as that of the second output module OUT2 .

[0065] In the embodiment of the present application, the third output module OUT3 in the auxiliary unit A30 is set to have the same circuit module as the first output module OUT1 in the shift register VSR, which is beneficial to improving the feasibility of the control module V10 to simultaneously drive the first output module OUT3 and the first output module OUT1, and the fourth output module OUT4 in the auxiliary unit A30 is set to have the same circuit structure as the second output module OUT2 in the shift register VSR, which is beneficial to improving the feasibility of the control module V10 to simultaneously drive the second output module OUT2 and the fourth output module OUT4, which is beneficial to reducing the difficulty in preparing multiple driving units in the display panel 100 and reducing the preparation cost of the display panel 100.

[0066] In one embodiment of the present application, continue to refer to Figure 3-Figure 5As shown, the first output module OUT1 and the third output module OUT3 both include a first output transistor T1, the first electrode of the first output transistor T1 in the first output module OUT2 is electrically connected to the output end of the shift register VSR, and the first electrode of the first output transistor T1 in the third output module OUT3 is electrically connected to the output end of the auxiliary unit A30, which is conducive to using the first output transistor T1 to realize the function of outputting the enable signal of the first output module OUT1 and the third output module OUT3. The gate of the first output transistor T1 in the first output module OUT1 can be reused as the control end of the first output module OUT1, and the gate of the first output transistor T1 is electrically connected to the first node N1. The gate of the first output transistor T1 in the second output module OUT2 can be reused as the control end of the third output module OUT3, and the gate of the first output transistor T1 is electrically connected to the first scanning control unit A40 and the second scanning control unit A50. Optionally, the first output transistor T1 is a P-type transistor.

[0067] The second output module OUT2 and the fourth output module OUT4 both include a second output transistor T2 and a first voltage-stabilizing capacitor C1. Among them, the two plates of the first voltage-stabilizing capacitor C1 are electrically connected to the first pole and the gate of the second output transistor T2, respectively. Optionally, the second pole of the second output transistor T2 is used to receive a clock signal, and optionally, the clock signal is a square wave signal. It should be noted that the shift register VSR can receive the first clock signal CK1 and the second clock signal CK2, and the clock signal receiving end in the adjacent two-stage shift register VSR alternately receives the first clock signal CK1 and the second clock signal CK2. Optionally, the second output transistor T2 is a P-type transistor, which is turned on when a low-level signal is received. When the clock signal received by the second pole of the second output transistor T2 jumps low, the first voltage-stabilizing capacitor C1 can pull down the gate of the second output transistor T2 through coupling, thereby driving the second output transistor T2 to turn on. The first pole of the second output transistor M2 in the second output module OUT2 is also electrically connected to the output end of the shift register VSR. At this time, the second output module OUT2 transmits the enable signal to the first module 10 of the pixel circuit A10.

[0068] The first electrode of the second output transistor T2 in the fourth output module OUT4 is also electrically connected to the output end of the auxiliary unit A30. Similarly, in the fourth output module OUT4, the second electrode of the second output transistor T2 is also electrically connected to the clock signal. Optionally, the second output transistor T2 is a P-type transistor, which is turned on when receiving a low-level signal. When the clock signal received by the second electrode of the second output transistor T2 jumps low, the first voltage-stabilizing capacitor C1 can pull down the gate of the second output transistor T2 through coupling, thereby driving the second output transistor T2 to turn on. At this time, the fourth output module OUT4 outputs the enable signal from the first electrode to the output end of the auxiliary unit A30.

[0069] In one embodiment of the present application, continue to refer to Figure 3-Figure 5 As shown, the second output module OUT2 and the fourth output module OUT4 are both provided with a first protection transistor T3, and the first electrode of the first protection transistor T3 is electrically connected to the gate of the second output transistor T2. The second electrode of the first protection transistor T3 in the second output module OUT2 is electrically connected to the second node N2, and the second electrode of the first protection transistor T3 in the fourth output module OUT4 is multiplexed as the control terminal of the fourth output module OUT4.

[0070] Since the second output transistors T2 in the second output module OUT2 and the fourth output module OUT4 are both turned on, and since the first voltage-stabilizing capacitor C1 in the second output module OUT2 is located between the first electrode and the gate of the second output transistor T2, and the first voltage-stabilizing capacitor C1 and the second output transistor T2 in the fourth output module OUT4 are also located between the first electrode and the gate of the second output transistor T2, then, when the second output module OUT2 and the fourth output module OUT4 are electrically connected and turned on, the gate of the second output transistor T2 in the second output module OUT2 will be simultaneously affected by the coupling of the first voltage-stabilizing capacitor C1 in the second output module OUT2 and the fourth output module OUT4, and similarly, the gate of the second output transistor T2 in the fourth output module OUT2 will be simultaneously affected by the coupling of the first voltage-stabilizing capacitor C1 in the second output module OUT2 and the fourth output module OUT4. For example, when the clock signals received by the first pole of the second output module OUT2 and the first pole of the fourth output module OUT4 are different, if the clock signal received by the second output module OUT2 jumps low while the clock signal received by the fourth output module OUT4 has not jumped low, then the second output transistor T2 in the fourth output module OUT4 will stabilize the gate of the second output transistor T2 in the second output module OUT2, so that the gate potential of the second output transistor T2 in the second output module OUT2 will not be pulled down to a more ideal state, so that the switching accuracy of the second output transistor T2 in the second output module OUT2 decreases. Similarly, the gate of the second output transistor T2 in the fourth output module OUT4 will also be affected by similar situations.

[0071] Therefore, in the embodiment of the present application, the first protection transistor T3 is prepared in the second output module OUT2 of the shift register VSR and in the fourth output module OUT4, and the second electrode of the first protection transistor T3 in the second output module OUT2 is electrically connected to the second node N2, and the second electrode of the first protection transistor T3 in the fourth output module OUT4 is electrically connected to the gate of the second output transistor T2, which is conducive to the control signal output by the second node N2 of the control module V10 being transmitted from the first protection transistor T3 in the two modules to the gate of the corresponding second output transistor T2 in the two modules. Then, when the first scanning control unit A40 and the second output unit A50 are turned on, the gate of the second output transistor T2 in the second output module OUT2 and the gate of the second output transistor T2 in the fourth output module OUT4 will not be directly connected, but will be separated by the first protection transistor T3, thereby reducing the risk of mutual interference. Therefore, the present solution is also applicable to the case where the clock signal used in the second output module OUT2 is different from the clock signal used in the fourth output module OUT4. It is conducive to improving the reliability of the technical solution of the present application and improving the scope of application of the technical solution of the present application.

[0072] It should be noted that the first protection transistor T3 is a P-type transistor, the gate of the first protection transistor T3 is electrically connected to the first power supply voltage signal VGL, and when the second output transistor T2 is turned off, the first protection transistor T3 is normally turned on to keep the gate potential of the second output transistor T2 stable. When the second output transistor T2 is coupled by the first voltage stabilizing capacitor C1 to pull the gate down, the gate of the second output transistor T2 is electrically connected to the first electrode of the first protection transistor T3, and when the gate potential of the second output transistor T2 is coupled and pulled down to less than the first power supply voltage signal VGL, the first protection transistor T3 is turned off, which is conducive to stabilizing the gate potential of the second output transistor T2.

[0073] Figure 8 A schematic diagram of another shift register provided in an embodiment of the present application, Fig. 9 This is a schematic plan view of another area E1 provided in an embodiment of the present application.

[0074] In one embodiment of the present application, Figure 8 , Fig. 9As shown, the display panel 100 further includes a third scanning control unit A60 and a fourth scanning control unit A70. In the 1st to Nth stage shift registers VSR cascaded along the first scanning direction J1, the third scanning control unit A60 is connected between the output terminal OUT of the previous stage and the trigger terminal IN of the next stage. In the embodiment of the present application, the first scanning line SL1 transmits the control signal S1 and the second scanning line transmits the control signal S2 as an example for explanation. Then, in a plurality of cascaded shift registers VSR, the trigger terminal IN of the next stage shift register VSR receives the control signal S1 outputted from the output terminal OUT of the previous stage shift register VSR, which is conducive to transmitting the signal outputted from the output terminal of the previous stage shift register VSR to the trigger terminal IN of the next stage shift register VSR as the cascade signal of the next stage shift register VSR, so that it starts to work.

[0075] The fourth scanning control unit A70 is connected between the output terminal OUT of the next stage and the trigger terminal IN of the previous stage. In the embodiment of the present application, the first scanning line SL1 transmits the control signal S1 and the second scanning line transmits the control signal S2 as an example for explanation. Then, in a plurality of cascaded shift registers VSR, the trigger terminal IN of the previous stage shift register VSR receives the control signal S1 output by the output terminal OUT of the next stage shift register VSR, which is conducive to transmitting the signal output by the output terminal of the next stage shift register VSR to the trigger terminal IN of the previous stage shift register VSR as the cascade signal of the previous stage shift register VSR, so that it starts to work.

[0076] It should be noted that if Fig. 9 As shown, taking N=6, m=1 as an example, Fig. 9 S1(n) represented in the figure is a control signal S1 outputted from the output terminal OUT of the n-th stage shift register VSR(n), and the value range of n is an integer between 1 and 6. Fig. 9 The S2(i) represented in the figure is the control signal S2 outputted from the output terminal of the i-th auxiliary unit A30(i), and the value range of i is an integer between 1-4.

[0077] In the embodiment of the present application, a third scan control unit A60 is set to be turned on when the scan direction of the first scan drive circuit A20 is the first scan direction J1, and a fourth scan control unit A70 is used to be turned on when the scan direction of the first scan drive circuit A20 is the second scan direction J2, which is conducive to realizing a scheme of cascading the 1st to Nth stage shift registers VSR along the first scan direction J1 or cascading along the second scan direction J2, and using the third scan control unit A60 and the fourth scan control unit A70 to be turned on in different cascade modes, respectively, is conducive to improving the stability and accuracy of the driving operation in the display panel 100.

[0078] In one embodiment of the present application, continue to refer to the combination Figure 8 , Fig. 9 As shown, the control end of the first scanning control unit A40 and the control end of the third scanning control unit A60 are electrically connected to the same control signal line, and the control end of the second scanning control unit A50 and the control end of the fourth scanning control unit A70 are electrically connected to the same control signal line. Optionally, the signal transmitted by the third control signal line SL3 is used to control the third scanning control unit A60, and the signal transmitted by the fourth scanning control signal line SL4 is used to control the fourth scanning control unit A70.

[0079] In the embodiment of the present application, the control end of the first scanning control unit A40 and the control end of the third scanning control unit A60 are electrically connected to the same control signal line, and the control end of the second scanning control unit A50 and the control end of the fourth scanning control unit A70 are electrically connected to the same control signal line, which is conducive to ensuring that when the 1st to Nth stage shift registers VSR are cascaded along the first scanning direction J1, the first scanning control unit A40 and the third scanning control unit A60 can be turned on at the same time, and it is conducive to ensuring that when the 1st to Nth stage shift registers VSR are cascaded along the second scanning direction J2, the second scanning control unit A50 and the fourth scanning control unit A70 can be turned on at the same time, which is conducive to ensuring that the work between the 1st to Nth stage shift registers VSR and the 1st to N-2mth auxiliary units A30 is stable. In addition, it is also conducive to saving the number of prepared control signal lines and reducing the preparation cost of the display panel 100.

[0080] In one embodiment of the present application, continue to refer to Figure 8 , Fig. 9 As shown, the first scanning control unit A40 includes a first control transistor T4, and the third scanning control unit A60 includes a second control transistor T5. The first control transistor T4 and the second control transistor T5 are of the same type, which is conducive to using the same control signal line to simultaneously control the first scanning control unit A30 and the third scanning control unit A60, and using the same type of control transistors is conducive to improving the switching synchronization of the first control transistor T4 and the second control transistor T5, and reducing the switching error caused by the difference in transistors. It should be noted that the first scanning control unit A40 includes the first control transistor T4 here, which can mean that the first subunit A401 and the second subunit A402 in the first scanning control unit A40 include the same first control transistor T4.

[0081] The second scanning control unit A50 includes a third control transistor T6, and the fourth scanning control unit A70 includes a fourth control transistor T7. The third control transistor T3 is of the same type as the fourth control transistor T4, which is conducive to using the same control signal line to simultaneously control the second scanning control unit A50 and the fourth scanning control unit A70, and using the same type of control transistors is conducive to improving the switching synchronization of the third control transistor T6 and the fourth control transistor T7, and reducing the switching error caused by transistor differences. It should be noted that the second scanning control unit A50 includes the second control transistor T6 here, which can mean that the third subunit A501 and the fourth subunit A502 in the second scanning control unit A50 include the same second control transistor T6.

[0082] In one embodiment of the present application, continue to refer to Figure 2 As shown, the first module 10 in the pixel circuit A10 is a data voltage writing module, and the data writing module is used to transmit the data voltage to the driving transistor Md. The second module 20 is a reset module, and the reset module is used to reset the gate of the driving transistor Md and transmit the first reset voltage Vref1 to the gate of the driving transistor Md. In a working cycle of the pixel circuit A10, the reset module works before the data writing module. The reset module first resets the gate of the driving transistor Md to ensure the accuracy of the data signal received by the driving transistor Md during the data writing stage. Then the data writing module starts to work and writes the data signal to the driving transistor Md.

[0083] Of course, in some other embodiments, the first module 10 and the second module 20 proposed in the embodiment of the present application may also be a threshold voltage writing module 30 and a reset module 20, respectively, or the first module 10 and the second module 20 may also be two modules with different opening times such as a light-emitting module 40 and a data voltage writing module, respectively.

[0084] It should be supplemented that the pixel circuit A10 includes a threshold voltage writing module 30 for compensating the threshold voltage of the gate of the driving transistor Md. The pixel circuit A10 also includes a light-emitting module 40 for turning on after receiving the light-emitting control signal EM during the light-emitting stage, so that the light-emitting driving current can pass and be transmitted to the light-emitting element 200. The pixel circuit A10 also includes a second reset module 50, which is used to provide a second reset voltage Vref2 for the light-emitting element 200.

[0085] Fig.10 A schematic diagram of a display device provided in an embodiment of the present application.

[0086] The present application embodiment provides a display device 300, such as Fig.10As shown, the display device 300 includes the display panel 100 proposed in any of the above embodiments. Optionally, the display device 300 can be a device for display such as a computer, a television, a mobile phone, a camera, etc.

[0087] In the display device 300, the display panel 100 is provided with not only a shift register VSR for outputting control signals required by circuits such as the pixel circuit A10, but also an auxiliary unit A30 for outputting control signals required by circuits such as the pixel circuit A10, which is conducive to using the auxiliary unit A30 to reduce the number of scan drive circuits required to be prepared in the display panel 100. In addition, the number of auxiliary units A30 arranged along the first direction X1 is 2m less than the number of shift registers VSR, and there is an electrical connection between the auxiliary unit A30 and the shift register VSR, which is conducive to providing feasible conditions for the shift register VSR to provide a drive signal to the auxiliary unit A30, providing a feasible condition for reducing the preparation of the drive unit in the display panel 100, and being conducive to reducing the number of prepared drive circuits when the display panel 100 is provided along the first scanning direction X1 and the second scanning direction X2, thereby achieving a narrow frame of the display panel 100 or saving the space area of ​​the display panel 100.

[0088] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel circuits, each pixel circuit comprising a driving transistor, a first module and a second module, wherein at least one of the first module and the second module is electrically connected to the driving transistor; In one working cycle of the pixel circuit, the first module is turned on later than the second module; a plurality of first scan lines and a plurality of second scan lines, wherein the first scan lines are electrically connected to the control end of the first module, and the second scan lines are electrically connected to the control end of the second module; A first scan driving circuit comprises a first to an Nth stage shift register cascaded along a first scan direction, wherein an output end of the shift register is electrically connected to the first scan line; The 1st to (N-2m)th auxiliary units are arranged along a first direction, and the output ends of the auxiliary units are electrically connected to the second scanning line; the first direction is parallel to the first scanning direction; A plurality of first scanning control units, wherein the i-th auxiliary unit arranged along the first direction is electrically connected to the i-m+1-th stage of the shift register cascaded along the first scanning direction through the first scanning control unit; the first scanning control unit is used to be turned on when the scanning direction of the first scanning driving circuit is the first scanning direction; A plurality of second scanning control units, wherein the j-th auxiliary unit arranged along the first direction is electrically connected to the j+m+1-th stage shift register cascaded along the second scanning direction through the second scanning control unit; the second scanning control unit is used to be turned on when the scanning direction of the first scanning driving circuit is the second scanning direction, and the second scanning direction is opposite to the first scanning direction; 1≤i≤(N-2m), 1≤j≤(N-2m), m≥1.

2. The display panel according to claim 1, characterized in that: m＝1。 3. The display panel according to claim 1, characterized in that: The output ends of the first to mth stages and the N-m+1th to Nth stages shift registers are not electrically connected to the first scan line; and the m+1th to Nmth stages shift registers are electrically connected to the first scan line.

4. The display panel according to claim 1, characterized in that: The shift register comprises a control module and an output module, wherein the control module is electrically connected to a control terminal of the output module and is used to control the output module to output an enable signal and a disable signal; The first scanning control unit is connected between the control terminal of the auxiliary unit and the control module of the shift register; The second scanning control unit is connected between the control terminal of the auxiliary unit and the control module of the shift register.

5. The display panel according to claim 4, characterized in that: The control module includes a first node and a second node, the output module includes a first output module and a second output module, the first output module and the second output module are electrically connected to the first node and the second node respectively, the first scanning control unit is connected to the first node and the second node, and the second scanning control unit is electrically connected to the first node and the second node.

6. The display panel according to claim 5, characterized in that: The auxiliary unit includes a third output module and a fourth output module, the first scanning control unit includes a first subunit and a second subunit, the second scanning control unit includes a third subunit and a fourth subunit, the first subunit and the third subunit are both electrically connected between the first node and the control end of the third output module, and the second subunit and the fourth subunit are both electrically connected between the second node and the control end of the fourth output module.

7. The display panel according to claim 6, characterized in that: The third output module has the same structure as the first output module, and the fourth output module has the same structure as the second output module.

8. The display panel according to claim 6, characterized in that: The first output module and the third output module both include a first output transistor, a first electrode of the first output transistor in the first output module is electrically connected to the output end of the shift register, and a first electrode of the first output transistor in the third output module is electrically connected to the output end of the auxiliary unit; The second output module and the fourth output module both include a second output transistor and a first voltage-stabilizing capacitor; the two plates of the first voltage-stabilizing capacitor are electrically connected to the first electrode and the gate of the second output transistor, respectively; the first electrode of the second output transistor in the second output module is also electrically connected to the output end of the shift register, and the first electrode of the second output transistor in the fourth output module is also electrically connected to the output end of the auxiliary unit.

9. The display panel according to claim 8, characterized in that: The second output module and the fourth output module also include a first protection transistor, a first electrode of the first protection transistor is electrically connected to the gate of the second output transistor; the second electrode of the first protection transistor in the second output module is electrically connected to the second node, and the second electrode of the first protection transistor in the fourth output module is multiplexed as the control end of the fourth output module.

10. The display panel according to claim 1 or 6, characterized in that: The display panel further includes a third scanning control unit and a fourth scanning control unit. In the first to Nth stage shift registers cascaded along the first scanning direction, the third scanning control unit is connected between the output end of the previous stage and the trigger end of the next stage, and the fourth scanning control unit is connected between the output end of the next stage and the trigger end of the previous stage. The third scan control unit is used to be turned on when the scan direction of the first scan driving circuit is the first scan direction, and the fourth scan control unit is used to be turned on when the scan direction of the first scan driving circuit is the second scan direction.

11. The display panel according to claim 10, characterized in that: The control end of the first scanning control unit and the control end of the third scanning control unit are electrically connected to the same control signal line, and the control end of the second scanning control unit and the control end of the fourth scanning control unit are electrically connected to the same control signal line.

12. The display panel according to claim 11, characterized in that: The first scanning control unit includes a first control transistor, and the third scanning control unit includes a second control transistor, and the first control transistor and the second control transistor are of the same type; The second scan control unit includes a third control transistor, and the fourth scan control unit includes a fourth control transistor, and the third control transistor is of the same type as the fourth control transistor.

13. The display panel according to claim 1, characterized in that: The first module is a data voltage writing module, and the data writing module is used to transmit a data voltage to the driving transistor; the second module is a reset module, and the reset module is used to reset the gate of the driving transistor.

14. A display device, characterized in that: A display panel comprising any one of claims 1-13.

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