A display panel and display device

Abstract

This application provides a display panel and display device. The display panel includes cascaded shift registers of levels 1 to N, and auxiliary units of levels 1 to (N-2m) arranged along a first direction. The i-th auxiliary unit is electrically connected to the (i-m+1)-th cascaded shift registers along the first scanning direction via a first scan control unit. The first scan control unit is activated when the scanning direction of the first scan driving circuit is the first scan direction. The j-th auxiliary unit is electrically connected to the (j+m+1)-th cascaded shift registers along a second scan direction via a second scan control unit. The second scan control unit is activated when the scanning direction of the first scan driving circuit is the second scan direction, which is opposite to the first scan direction. This application embodiment helps to reduce the number of driving circuits, thereby achieving a narrow bezel of the display panel or saving space area of ​​the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] A display panel includes multiple driving units. The operation of a display panel requires various driving signals to perform different working processes, thus necessitating the use of a large number of driving units. The fabrication of multiple driving units tends to occupy a significant amount of space in the display panel, which is detrimental to achieving narrow bezels, improving display panel space utilization, and increasing screen-to-body ratio. Summary of the Invention

[0003] In view of this, this application provides a display panel and a display device to help solve the above problems.

[0004] In a first aspect, embodiments of this application provide a display panel, including:

[0005] Multiple pixel circuits, each pixel circuit including a driving transistor, a first module, and a second module, wherein at least one of the first module and the second module is electrically connected to the driving transistor; during one operating cycle of the pixel circuit, the turn-on time of the first module is later than the turn-on time of the second module.

[0006] Multiple first scan lines and multiple second scan lines, the first scan lines are electrically connected to the control terminal of the first module, and the second scan lines are electrically connected to the control terminal of the second module;

[0007] The first scan driving circuit includes a first-stage to Nth-stage shift register cascaded along the first scan direction, and the output terminal of the shift register is electrically connected to the first scan line;

[0008] The first to (N-2m)th auxiliary units are arranged along the first direction, and the output terminals of the auxiliary units are electrically connected to the second scan line; the first direction is parallel to the first scan direction;

[0009] Multiple first scanning control units are provided, and the i-th auxiliary unit arranged along the first direction is electrically connected to the i-m+1-th stage shift register cascaded along the first scanning direction through the first scanning control unit; the first scanning control unit is used to activate when the scanning direction of the first scanning drive circuit is the first scanning direction;

[0010] Multiple second scanning control units are provided. The j-th auxiliary unit, arranged along the first direction, is electrically connected to the (j+m+1)-th stage shift register cascaded along the second scanning direction via the second scanning control unit. The second scanning control unit is activated when the scanning direction of the first scanning drive circuit is the second scanning direction, which is opposite to the first scanning direction.

[0011] 1≤i≤(N-2m), 1≤j≤(N-2m), m≥1.

[0012] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0013] In this embodiment, the display panel includes not only shift registers for outputting control signals required by circuits such as pixel circuits, but also auxiliary units for outputting control signals required by circuits such as pixel circuits. This is beneficial for reducing the number of scanning drive circuits that need to be fabricated in the display panel by utilizing the auxiliary units. Furthermore, the number of auxiliary units arranged along the first direction is 2m fewer than the number of shift registers, and there is an electrical connection between the auxiliary units and the shift registers. This facilitates the provision of drive signals from the shift registers to the auxiliary units, providing feasible conditions for reducing the fabrication of drive units in the display panel. This is beneficial for reducing the number of drive circuits fabricated along the first and second scanning directions in the display panel, thereby achieving a narrow bezel or saving space in the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a plan view of a display panel provided in an embodiment of this application;

[0016] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0017] Figure 3 A schematic diagram of a shift register circuit provided in an embodiment of this application;

[0018] Figure 4 A schematic diagram of an auxiliary unit provided in an embodiment of this application;

[0019] Figure 5 An embodiment provided in this application Figure 1 A schematic diagram of the central region E1;

[0020] Figure 6 A timing diagram of a display panel provided in an embodiment of this application;

[0021] Figure 7 A timing diagram of another display panel provided in an embodiment of this application;

[0022] Figure 8 A schematic diagram of yet another shift register provided in an embodiment of this application;

[0023] Figure 9 A plan view of another region E1 provided in an embodiment of this application;

[0024] Figure 10 This is a plan view of a display device provided in an embodiment of this application. Detailed Implementation

[0025] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0027] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0028] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0030] It should be understood that although terms such as "first," "second," etc., may be used to describe modules, scan lines, control transistors, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish modules, scan lines, control transistors, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first module may also be referred to as a second module, and similarly, a second module may also be referred to as a first module. Through meticulous and in-depth research, the applicant of this application provides a solution to the problems existing in the prior art.

[0031] Figure 1 This is a plan view of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 3 This is a schematic diagram of a shift register circuit provided in an embodiment of this application. Figure 4 This is a schematic diagram of an auxiliary unit provided in an embodiment of this application. Figure 5 An embodiment provided in this application Figure 1 A schematic diagram of the central region E1.

[0032] This application embodiment provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes multiple pixel circuits A10. Combined with... Figure 2 As shown, the pixel circuit A10 includes a driving transistor Md, a first module 10, and a second module 20. The driving transistor Md can generate a light-emitting driving current to drive the light-emitting element 200 to emit light. At least one of the first module 10 and the second module 20 in the pixel circuit A10 is electrically connected to the driving transistor Md. During one operating cycle of the pixel circuit A10, the turn-on time of the first module 10 is later than the turn-on time of the second module 20.

[0033] The display panel 100 also includes multiple first scan lines SL1 and multiple second scan lines SL2. The first scan lines SL1 are electrically connected to the control terminal 101 of the first module 10, and the second scan lines SL2 are electrically connected to the control terminal 201 of the second module 20. Given that the first module 10 turns on later than the second module 20 within one working cycle of the pixel circuit A10, the transmission times of the effective signals by the first scan lines SL1 and SL2 are different, resulting in different turn-on times for the first module 10 and the second module 20. Furthermore, within one working cycle of the pixel circuit A10, the transmission time of the effective signal by the first scan line SL1 is later than the transmission time of the effective signal by the second scan line SL2.

[0034] Combination Figure 3 As shown, the display panel 100 also includes a first scan drive circuit A20. The first scan drive circuit A20 includes a first-stage to an Nth-stage shift register VSR cascaded along the first scan direction J1. Optionally, the first scan drive circuit A20 includes N cascaded shift registers VSR. The output terminal of the shift register VSR is electrically connected to the first scan line SL1, so the shift register VSR can output a drive signal for controlling the operation of the first module 10.

[0035] In related technologies, shift registers that can be cascaded in both forward and reverse directions are included according to the operational requirements of the display panel. However, the fabrication of this function adds a driving unit to the display panel, which tends to occupy a large area of ​​the display panel, making it difficult to achieve a narrow bezel or squeezing the space of other circuit units. Therefore, in order to reduce the area occupied by the driving unit in the display panel 100 when including forward and reverse scanning functions, the technical solution of this application is proposed.

[0036] Combination Figure 4 As shown, the display panel 100 also includes the first to (N-2m)th auxiliary units A30 arranged along the first direction X1, thus including (N-2m) auxiliary units A30 along the first direction X1. The output terminal of the auxiliary unit A30 is electrically connected to the second scan line SL2, and the auxiliary unit A30 can be used to output the drive signal for controlling the operation of the second module 20. This saves the need to separately prepare the scan drive circuit for outputting the drive signal for controlling the operation of the second module 20, reducing the number of drive circuits prepared in the display panel. The first direction X1 is parallel to the first scan direction J1. Therefore, the N cascaded shift registers VSR in the first scan drive circuit A20 can also be arranged along the first direction X1, in the same way as the (N-2m) auxiliary units A30 arranged along the first direction X1.

[0037] The display panel 100 also includes a plurality of first scanning control units A40. The i-th auxiliary unit A30(i) arranged along the first direction X1 is electrically connected to the i-m+1-th stage shift register VSR (i-m+1) cascaded along the first scanning direction J1 through the first scanning control unit A40, where 1≤i≤(N-2m) and m≥1. This facilitates the use of the first scanning control unit A40 to electrically connect the auxiliary unit A30 to the shift register VSR, thereby enabling the auxiliary unit A30 to use part of the circuit in the shift register VSR to complete the function of outputting the control signal required by the second module 20. This also helps to save part of the circuit structure in the drive unit that needs to be prepared to output the control signal required by the second module 20.

[0038] Based on the above, the first scan driving circuit A20 includes N cascaded shift registers VSR, and (N-2m) auxiliary units A30 are arranged in the first direction X1. Among the multiple auxiliary units A30 and shift registers VSR arranged in the first direction X1, the number of auxiliary units A30 is 2m fewer than the number of shift registers VSR. Therefore, setting the i-th auxiliary unit A30(i) and the (i-m+1)-th stage shift register VSR(i-m+1) helps reduce the number of auxiliary units A30 to be prepared. The signal in the (i-m+1)-th stage shift register VSR(i-m+1) drives the auxiliary unit A30, avoiding the need for additional circuitry to provide the drive signal for the auxiliary unit A30. Furthermore, it facilitates the operation of the i-m+1th level shift register VSR(i-m+1) when the i-m+1th level shift register starts working, thus enabling the i-th auxiliary unit A30(i) to start working before the i+mth level shift register VSR(i+m) starts working. This ensures that in one working cycle of the pixel circuit A10, the second scan signal line SL2 transmits a valid signal before the first scan signal line SL1, thereby making the start time of the first module 10 later than the start time of the second module 20.

[0039] The first scan control unit A40 is configured to be turned on when the scan direction of the first scan drive circuit A20 is the first scan direction J1. That is, when the cascading direction of the multiple shift registers VSR of the first scan drive circuit A20 is the first scan direction J1, the first scan control unit A40 is turned on, so that the multiple auxiliary units A30 arranged along the first direction X1 are also turned on along the first scan direction J1.

[0040] In addition, the display panel 100 also includes multiple second scanning control units A50. The j-th auxiliary unit A30, arranged along the first direction X1, is electrically connected to the (j+m+1)-th stage shift register VSR (j+m+1) cascaded along the first scanning direction J1 through the second scanning control unit A50. The second scanning control unit A50 is activated when the scanning direction of the first scanning drive circuit A20 is the second scanning direction J2, which is opposite to the first scanning direction J1. In this embodiment, the first scanning direction J1 is described as the forward scanning direction, and the second scanning direction X2 is described as the reverse scanning direction. When the drive unit in the display panel 100 is in reverse scanning mode, it is advantageous to use the second scanning control unit A50 to electrically connect the auxiliary unit A30 to the shift register VSR. This allows the auxiliary unit A30 to use part of the circuitry in the shift register VSR to complete the function of outputting the control signals required by the second module 20, thereby saving part of the circuitry in the drive unit that needs to be prepared to output the control signals required by the second module 20.

[0041] Based on the above, setting the j-th auxiliary unit A30(j) and the (j+m+1)-th shift register VSR(j+m+1), 1≤j≤(N-2m), m≥1, helps to reduce the number of auxiliary units A30 to be prepared. The auxiliary unit A30 is driven by the signal in the (j+m+1)-th shift register VSR(j+m+1), avoiding the need for additional circuitry to provide the drive signal for the auxiliary unit A30. This structure helps reduce the need to prepare additional auxiliary units A30 when scanning along the second scanning direction J2. Furthermore, it facilitates the operation of the j+m+1 level shift register VSR(j+m+1) when the j-th auxiliary unit A30(j) also starts working, thus ensuring that the j-th auxiliary unit A30(j) starts working before the j+m level shift register VSR(j+m) starts working. This ensures that in one working cycle of the pixel circuit A10, the second scanning signal line SL2 transmits a valid signal before the first scanning signal line SL1, thereby making the start time of the first module 10 later than the start time of the second module 20.

[0042] In this embodiment, the display panel 100 includes not only a shift register VSR for outputting control signals required by circuits such as the pixel circuit A10, but also an auxiliary unit A30 for outputting control signals required by circuits such as the pixel circuit A10. This is beneficial for reducing the number of scan driving circuits that need to be fabricated in the display panel 100 by utilizing the auxiliary unit A30. Furthermore, the number of auxiliary units A30 arranged along the first direction X1 is 2m fewer than the number of shift registers VSR, and there is an electrical connection between the auxiliary units A30 and the shift registers VSR. This facilitates the provision of driving signals from the shift registers VSR to the auxiliary units A30, and provides feasible conditions for reducing the fabrication of driving units in the display panel 100. This is beneficial for reducing the number of driving circuits fabricated when the display panel 100 is arranged along the first scan direction X1 and the second scan direction X2, thereby achieving a narrow bezel of the display panel 100 or saving space area of ​​the display panel 100.

[0043] Figure 6 This is a timing diagram of a display panel provided in an embodiment of this application. Figure 7 This is a timing diagram of another display panel provided in an embodiment of this application.

[0044] In one embodiment of this application, combined with Figure 1 , Figure 5 As shown, m=1 is set.

[0045] Taking N=6, that is, taking the same first scan drive circuit A20 including shift registers VSRs from the first stage to the sixth stage, as an example, the number of auxiliary units A30 arranged along the first direction X1 needs to be 2m less, that is, the number of auxiliary units A30 arranged along the first direction X1 can be set to 4. It can be seen that the number of shift registers VSRs arranged along the first direction X1 is 2 more than the number of auxiliary units A30. Optionally, the extra shift registers VSRs can be used to provide trigger signals for the cascading of multiple shift registers VSRs and the start of auxiliary units A30.

[0046] It should be noted that, as Figure 6 , Figure 7 As shown, taking N=6 and m=1 as an example, in Figure 6 , Figure 7 S1(n) represents the control signal S1 output from the output terminal OUT of the nth stage shift register VSR(n), where n is an integer between 1 and 6. Figure 6 , Figure 7 S2(i) in the middle represents the control signal S2 output from the output terminal of the i-th auxiliary unit A30(i), and the value of i is an integer between 1 and 4.

[0047] For example, combined Figure 6As shown, optionally, the signals output by the first scan line SL1 and the second scan line SL2 are effective when they are low. The first to sixth level shift register circuits VSR are scanned along the first scan direction J1. When i=1, the first auxiliary unit A30(1) is electrically connected to the first level shift register circuit VSR(1) through the first scan control unit A40. Similarly, when i=2, the second auxiliary unit A30(2) is electrically connected to the second level shift register circuit VSR(2), ..., when i=4, the fourth auxiliary unit A30(2) is electrically connected to the fourth level shift register circuit VSR(2). It should be noted that, optionally, the trigger terminal IN of the first level shift register VSR(1) can receive the first trigger signal, and the signal S1(1) generated by the output terminal OUT of the first level shift register VSR(1) can be used to provide a trigger signal for the second level shift register VSR(2). The second-level shift register VSR (2) is electrically connected to the first auxiliary unit A30 (1) in the same row as the pixel circuit A10. The third-level shift register VSR (3) is electrically connected to the second auxiliary unit A30 (2) in the same row as the pixel circuit A10. The fourth-level shift register VSR (4) is electrically connected to the third auxiliary unit A30 (3) in the same row as the pixel circuit A10. The fifth-level shift register VSR (5) is electrically connected to the fourth auxiliary unit A30 (4) in the same row as the pixel circuit A10. Therefore, when the first-level shift register VSR (1) is working, the first auxiliary unit A30 (1) also starts working. The pixel circuit A10 in the pixel row electrically connected to the first auxiliary unit A30 (1) receives the valid control signal transmitted by the second scan line SL2, and the second module 20 in the pixel circuit A10 is turned on. In the cascaded shift registers VSR, the output of the previous shift register VSR is electrically connected to the trigger of the next shift register VSR. When the output of the previous shift register VSR outputs a signal, it triggers the next shift register VSR to start working. Therefore, the second shift register VSR (2) starts working after receiving the trigger signal provided by the first shift register VSR (1). The second shift register VSR (2) is electrically connected to the second auxiliary unit A30 (2). When the second shift register VSR (2) starts working, the pixel circuit A10 in the pixel row electrically connected to the second shift register VSR (2) receives the valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the second module 20 of the pixel circuit A10 in the same pixel row electrically connected to the second shift register VSR (2) and the first auxiliary unit A30 (1) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the second auxiliary unit A30 (2) also starts working.Similarly, when the third-level shift register VSR (3) starts working, the pixel circuit A10 in the pixel row electrically connected to the third-level shift register VSR (3) receives the valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the third-level shift register VSR (3) and the second auxiliary unit A30 (2) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the third auxiliary unit A30 (3) also starts working. When the fourth-level shift register VSR (4) starts working, the pixel circuit A10 in the pixel row electrically connected to the fourth-level shift register VSR (4) receives a valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fourth-level shift register VSR (4) and the third auxiliary unit A30 (3) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the fourth auxiliary unit A30 (4) also starts working. When the fifth-level shift register VSR (5) starts working, the pixel circuit A10 in the pixel row electrically connected to the fifth-level shift register VSR (5) receives a valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fifth-level shift register VSR (5) and the fourth auxiliary unit A30 (4) completes the work of the second module 20 and the first module 10. Optionally, the sixth-level shift register VSR (6) can be used to receive the trigger signal output by the fifth-level shift register VSR (5) to test the normal operation of the cascaded operation of multiple shift registers VSR in the first scan drive circuit A20.

[0048] For example, combined Figure 7As shown, optionally, the signals output by the first scan line SL1 and the second scan line SL2 are effective when they are low. The first to sixth level shift register circuits VSR are scanned along the second scan direction J2. When j=4, the fourth auxiliary unit A30 (4) and the sixth level shift register circuit VSR (6) are electrically connected through the second scan control unit A50. Similarly, when j=3, the third auxiliary unit A30 (3) and the fifth level shift register circuit VSR (5) are electrically connected. ..., when j=1, the first auxiliary unit A30 (1) and the third level shift register circuit VSR (2) are electrically connected. It should be noted that, optionally, the trigger terminal IN of the sixth-level shift register VSR (6) can receive the second trigger signal STV2, and the control signal S1 (6) output by the output terminal OUT of the sixth-level shift register VSR (6) can be used to provide the trigger signal to the fifth-level shift register VSR (5). The fifth-level shift register VSR (5) is electrically connected to the pixel circuit A10 in the same row as the fourth auxiliary unit A30 (4), the fourth-level shift register VSR (4) is electrically connected to the pixel circuit A10 in the same row as the third auxiliary unit A30 (3), the third-level shift register VSR (3) is electrically connected to the pixel circuit A10 in the same row as the second auxiliary unit A30 (2), and the second-level shift register VSR (2) is electrically connected to the pixel circuit A10 in the same row as the first auxiliary unit A30 (1). Therefore, when the sixth-level shift register VSR (6) is working, the fourth auxiliary unit A30 (4) also starts working. The pixel circuit A10 in the pixel row, which is electrically connected to the fourth auxiliary unit A30 (1), receives a valid control signal from the second scan line SL2, and the second module 20 in the pixel circuit A10 is turned on. In the cascaded shift register VSR, the output terminal of the previous shift register VSR is electrically connected to the trigger terminal of the next shift register VSR. When the output terminal of the previous shift register VSR outputs a signal, it triggers the next shift register VSR to start working. Therefore, the fifth-level shift register VSR (5) starts working after receiving the trigger signal provided by the sixth-level shift register VSR (6). The fifth-level shift register VSR (5) is electrically connected to the third auxiliary unit A30 (3). When the fifth-level shift register VSR (5) starts working, the pixel circuit A10 in the pixel row electrically connected to the fifth-level shift register VSR (5) receives the first scan line SL1 and transmits a valid control signal. The first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fifth-level shift register VSR (5) and the fourth auxiliary unit A30 (4) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the third auxiliary unit A30 (3) also starts working.Similarly, when the fourth-level shift register VSR (4) starts working, the pixel circuit A10 in the pixel row electrically connected to the fourth-level shift register VSR (4) receives the valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the fourth-level shift register VSR (4) and the third auxiliary unit A30 (3) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the second auxiliary unit A30 (2) also starts working. When the third-level shift register VSR(3) starts working, the pixel circuit A10 in the pixel row electrically connected to the third-level shift register VSR(3) receives a valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the third-level shift register VSR(3) and the second auxiliary unit A30(2) completes the work of the second module 20 and the first module 10. At this time, the second module 20 of the pixel circuit A10 in the pixel row electrically connected to the first auxiliary unit A30(1) also starts working. When the second-level shift register VSR(2) starts working, the pixel circuit A10 in the pixel row electrically connected to the second-level shift register VSR(2) receives a valid control signal transmitted by the first scan line SL1, and the first module 10 in the pixel circuit A10 is turned on. At this time, the pixel circuit A10 in the same pixel row electrically connected to the second-level shift register VSR(2) and the first auxiliary unit A30(1) completes the work of the second module 20 and the first module 10. Optionally, the first-stage shift register VSR (1) can be used to receive the trigger signal output by the second-stage shift register VSR (2) to test the normal operation of the cascaded operation of multiple shift registers VSR in the first scan drive circuit A20.

[0049] It should be noted that in some other embodiments, m can also be set to other positive integers, such as m=2. In this case, the time interval between the start-up time of the first module 10 and the second module 20 in the same pixel circuit A10 is the time interval for scanning 2 rows of pixels.

[0050] In one embodiment of this application, reference continues to be made to... Figure 1 , Figure 5As shown, the output terminals of the shift registers VSR from the first level to the m-th level and from the N-m+1-th level to the N-th level are not electrically connected to the first scan line SL1; and the shift registers VSR from the (m+1)-th level to the Nm-th level are electrically connected to the first scan line SL1. Based on the above embodiment, it can be seen that the number of N cascaded shift registers VSR in the same first scan driving circuit A20 is 2m more than the number of auxiliary units A30 arranged along the first direction X1. Since both the first module 10 and the second module 20 in the pixel circuit A10 need to receive control signals, the number of auxiliary units A30 can be equal to the number of pixel rows in the display panel 100 to ensure the stable operation of the first module 10 and the second module 20 of the pixel circuit A10 in each pixel row.

[0051] The shift registers VSRs in the first to m-th and N-m+1 to N-th stages are all not electrically connected to the first scan line SL1. Therefore, the number of shift registers VSRs in the first to m-th and N-m+1 to N-th stages is 2m more than that in the auxiliary unit A30. Optionally, the shift registers VSRs in the first to m-th and j+m to N-th stages may not be electrically connected to the pixel circuit A10. These shift registers VSRs can be virtual shift registers used to provide trigger signals for the shift registers VSRs electrically connected to the pixel circuit A10. For example, when the multiple cascaded shift registers VSRs in the first scan drive circuit A20 scan along the first scan direction J1, the shift registers VSRs in the first to m-th stages provide drive signals to the auxiliary unit A30, causing the second module 20 to start scanning m lines earlier than the first module 10. For example, when multiple cascaded shift registers VSR in the first scan drive circuit A20 are scanned along the second scan direction J2, the N-m+1th to Nth level shift registers VSR are used to provide drive signals to the auxiliary unit A30, so that the second module 20 starts the scan time of m lines earlier than the first module 10. For example, when N=6, m=1, and multiple cascaded shift registers VSR in the first scan drive circuit A20 are scanned along the first scan direction J1, the first level shift register VSR (1) and the sixth level shift register VSR (6) are not electrically connected to the first scan line SL1, and the second level shift register VSR (2) to the fifth level shift register VSR (5) are electrically connected to the first scan line SL1.

[0052] In this embodiment, the output terminals of the shift registers VSR from the first level to the m-th level and from the N-m+1-th level to the N-th level are not electrically connected to the first scan line SL1; and the shift registers VSR from the m+1-th level to the Nm-th level are electrically connected to the first scan line SL1. This is beneficial for using the circuit signals in the shift registers VSR as driving signals for the auxiliary unit A30, and also for ensuring that the pixel circuit A10 in the pixel row, which is electrically connected to both the auxiliary unit A30 and the shift registers VSR, can receive the signal transmitted by the second scan line SL2 first and then the signal transmitted by the first scan line SL1, which is beneficial for the stable operation of the pixel circuit A10.

[0053] In one embodiment of this application, reference continues to be made to... Figure 1 , Figures 3-5 As shown, the shift register VSR includes a control module V10 and an output module V20. The control module V10 is electrically connected to the control terminal of the output module V20 and is used to control the output module V20 to output enable and disable signals. Optionally, the high-level signal VGH is the disable signal.

[0054] The control module V10 includes transistors M1 to M5, which are used to jointly control the output module V20 to output enable and disable signals.

[0055] The first scan control unit A40 is connected between the control terminal of the auxiliary unit A30 and the control module V10 of the shift register VSR. As described above, the auxiliary unit A30 outputs the enable and disable signals transmitted by the second scan line SL2, thereby controlling the opening and closing of the second module 20 in the pixel circuit A10. Optionally, the signal received by the control terminal of the auxiliary unit A30 can be used to control the auxiliary unit A30 to output an enable or disable signal. Electrically connecting the control module V10 of the shift register VSR to the control terminal of the auxiliary unit A30 using the first scan control unit A40 facilitates the multiplexing of the signals generated by the control module V10 in the shift register VSR into a control unit that controls the auxiliary unit A30 to transmit enable or disable signals. Furthermore, in multiple pixel rows in the display panel 100, to save scanning time, other stages of work, such as the reset stage and data signal writing stage, are typically completed before the current pixel row enters the light-emitting operation. Therefore, when multiple shift registers VSR scan along the first scan direction J1, correspondingly, multiple pixel circuits A10 electrically connected to the shift registers VSR also sequentially start emitting light along the first scan direction J1. It can be understood that in the multiple working stages before the light-emitting stage, the pixel circuits A10 in multiple pixel rows also sequentially start different working stages along the first scan direction J1. Therefore, when the first scan control unit A40 is electrically connected between the (i-m+1)th level shift register VSR (i-m+1) and the i-th auxiliary unit A30(i), the pixel row electrically connected to the (i-m+1)th level shift register VSR (i-m+1) enters the light-emitting stage before the pixel row electrically connected before the i-th auxiliary unit A30(i). This is beneficial because when the enable signal transmitted by the shift register VSR(i-m+1) of the i-m+1 stage controls the operation of the first module 10, after the pixel circuit A10 electrically connected to the i-th auxiliary unit A30(i) receives a valid signal, the second module 20 is turned on and enters another working stage before the first module 10 is turned on. In this stage, the second module 20 in the pixel circuit A10 electrically connected to the i-th auxiliary unit A30(i) is turned on, ensuring that the turn-on time of the second module 20 in the same pixel circuit A10 is earlier than the turn-on time of the first module 10.

[0056] The second scan control unit A50 is connected between the control terminal of the auxiliary unit A30 and the control module V10 of the shift register VSR. Similarly, when the second scan control unit A50 electrically connects the control module V10 of the shift register VSR to the auxiliary unit A30, it allows the signal generated by the control module V10 of the shift register VSR to not only control the output module V20 in the shift register VSR to output enable and disable signals, but also to be multiplexed into a control unit that controls the output enable and disable signals of the auxiliary unit A30. This reduces the need for a separate control circuit to work with the auxiliary unit A30, thus saving on circuit structure. When multiple shift registers VSR scan along the second scan direction J2, correspondingly, multiple pixel circuits A10 electrically connected to the shift registers VSR also sequentially begin emitting light along the second scan direction J2. It can be understood that in the multiple operating stages before the light-emitting stage, the pixel circuits A10 in multiple pixel rows also sequentially activate different operating stages along the second scan direction J2. Therefore, when the first scanning control unit A40 is electrically connected between the (j+m+1)th level shift register VSR(j+m+1) and the jth auxiliary unit A30(j), the pixel row electrically connected to the (j+m+1)th level shift register VSR(j+m+1) enters the light-emitting stage before the pixel row electrically connected to the jth auxiliary unit A30. This is beneficial because when the enable signal transmitted by the (j+m+1)th level shift register VSR(j+m+1) controls the first module 10 to work, after the pixel circuit A10 electrically connected to the jth auxiliary unit A30(j) receives a valid signal, the second module 20 starts and enters another working stage before the first module 10 starts. In this stage, the second module 20 in the pixel circuit A10 electrically connected to the jth auxiliary unit A30(j) starts working, ensuring that the start time of the second module 20 in the same pixel circuit A10 is earlier than the start time of the first module 10.

[0057] In this embodiment, the first scanning control unit A40 is activated when multiple shift registers VSR are cascaded along the first scanning direction J1, and the control module V10 of the shift registers VSR is electrically connected to the control terminal of the auxiliary unit A30. The second scanning control unit A50 is activated when multiple shift registers VSR are cascaded along the second scanning direction J2, and the control module V10 of the shift registers VSR is electrically connected to the control terminal of the auxiliary unit A30. This reduces the circuit structure fabricated in the display panel 100 and the driving circuit fabricated when the display panel 100 includes forward and reverse scanning functions. This improves the space utilization and circuit utilization of the display panel 100, increases the possibility of fabricating other functional modules in the display panel 100, and reduces the fabrication cost of the display panel 100.

[0058] In one embodiment of this application, reference continues to be made to... Figure 3 As shown, the control module V10 includes a first node N1 and a second node N2, the output module V20 includes a first output module OUT1 and a second output module OUT2, the first output module OUT1 and the second output module OUT2 are electrically connected to the first node N1 and the second node N2 respectively, the first scan control unit A40 is connected to the first node N1 and the second node N2, and the second scan control unit A50 is electrically connected to the first node N1 and the second node N2.

[0059] Optionally, in the first output module V20, one of the first output module OUT1 and the second output module OUT2 outputs an enable signal, and the other outputs a disable signal. In this embodiment, the example of the first output module OUT1 outputting a disable signal and the second output module OUT2 outputting an enable signal is used for explanation. Optionally, the first node N1 is electrically connected to the control terminal of the first output module OUT1, and the second node N2 is electrically connected to the control terminal of the second output module OUT2. This facilitates the use of this circuit to receive and realize the synchronous control of the auxiliary unit V30 by the control module V10.

[0060] In one embodiment of this application, reference continues to be made to... Figure 4 , Figure 5 As shown, the auxiliary unit A30 includes a third output module OUT3 and a fourth output module OUT4, the first scan control unit A40 includes a first subunit A401 and a second subunit A402, and the second scan control unit A50 includes a third subunit A501 and a fourth subunit A502. Optionally, one of the third output module OUT3 and the fourth output module OUT4 in the auxiliary unit A30 outputs an enable signal and the other outputs a disable signal; in this embodiment, the example of the third output module OUT3 outputting a disable signal and the fourth output module OUT4 outputting an enable signal is used for illustration.

[0061] The first subunit A401 and the third subunit A501 are both electrically connected between the first node N1 and the control terminal of the third output module OUT3. The second subunit A402 and the fourth subunit A502 are both electrically connected between the second node N2 and the control terminal of the fourth output module OUT4.

[0062] When multiple shift registers (VSRs) are cascaded along the first scan direction J1, the first scan control unit A40 is turned on. Therefore, the first sub-unit A401 and the second sub-unit A402 are also turned on. Using the first sub-unit A401 to electrically connect the first node N1 to the third output module OUT3 facilitates the control module V10 in controlling the first output module OUT1 to output a disabled signal, and simultaneously controls the third output module OUT3 of the auxiliary unit A30 to output a disabled signal. Using the second sub-unit A402 to electrically connect the second node N2 to the fourth output module OUT4 facilitates the control module V10 in controlling the second output module OUT2 to output an enabled signal, and simultaneously controls the fourth output module OUT4 of the auxiliary unit A30 to output an enabled signal.

[0063] When multiple shift registers (VSRs) are cascaded along the second scan direction J2, the second scan control unit A50 is turned on. Then, both the third subunit A501 and the fourth subunit A502 are turned on. Using the third subunit A501 to electrically connect the first node N1 to the third output module OUT3 facilitates the control module V10 in controlling the first output module OUT1 to output a disabled signal, and simultaneously controls the third output module OUT3 of the auxiliary unit A30 to output a disabled signal. Using the fourth subunit A502 to electrically connect the second node N2 to the fourth output module OUT4 facilitates the control module V10 in controlling the second output module OUT2 to output an enabled signal, and simultaneously controls the fourth output module OUT4 of the auxiliary unit A30 to output an enabled signal.

[0064] In one embodiment of this application, combined with Figures 3-5 As shown, the third output module OUT3 has the same circuit structure as the first output module OUT1, and the fourth output module OUT4 has the same circuit structure as the second output module OUT2.

[0065] In this embodiment, the circuit structure of the third output module OUT3 in the auxiliary unit A30 is the same as that of the first output module OUT1 in the shift register VSR. This improves the feasibility of the control module V10 driving the first output module OUT3 and the first output module OUT1 simultaneously. Furthermore, the circuit structure of the fourth output module OUT4 in the auxiliary unit A30 is the same as that of the second output module OUT2 in the shift register VSR. This improves the feasibility of the control module V10 driving the second output module OUT2 and the fourth output module OUT4 simultaneously. This also reduces the difficulty of fabricating multiple driving units in the display panel 100 and lowers the fabrication cost of the display panel 100.

[0066] In one embodiment of this application, reference continues to be made to... Figures 3-5As shown, both the first output module OUT1 and the third output module OUT3 include a first output transistor T1. The first terminal of the first output transistor T1 in the first output module OUT2 is electrically connected to the output terminal of the shift register VSR, and the first terminal of the first output transistor T1 in the third output module OUT3 is electrically connected to the output terminal of the auxiliary unit A30. This facilitates the use of the first output transistor T1 to output enable signals for both the first output module OUT1 and the third output module OUT3. The gate of the first output transistor T1 in the first output module OUT1 can be reused as the control terminal of the first output module OUT1, and the gate of the first output transistor T1 is electrically connected to the first node N1. The gate of the first output transistor T1 in the second output module OUT2 can be reused as the control terminal of the third output module OUT3, and the gate of the first output transistor T1 is electrically connected to the first scan control unit A40 and the second scan control unit A50. Optionally, the first output transistor T1 is a P-type transistor.

[0067] Both the second output module OUT2 and the fourth output module OUT4 include a second output transistor T2 and a first voltage-stabilizing capacitor C1. The two plates of the first voltage-stabilizing capacitor C1 are electrically connected to the first terminal and gate of the second output transistor T2, respectively. Optionally, the second terminal of the second output transistor T2 is used to receive a clock signal, which can be a square wave signal. It should be noted that the shift register VSR can receive a first clock signal CK1 and a second clock signal CK2. The clock signal receiving terminals in adjacent shift register VSR stages alternately receive the first clock signal CK1 and the second clock signal CK2. Optionally, the second output transistor T2 is a P-type transistor, which conducts when it receives a low-level signal. When the clock signal received at the second terminal of the second output transistor T2 jumps low, the first voltage-stabilizing capacitor C1 can pull the gate of the second output transistor T2 low through coupling, thereby driving the second output transistor T2 to turn on. The first terminal of the second output transistor T2 in the second output module OUT2 is also electrically connected to the output terminal of the shift register VSR. At this time, the second output module OUT2 transmits an enable signal to the first module 10 of the pixel circuit A10.

[0068] The first terminal of the second output transistor T2 in the fourth output module OUT4 is also electrically connected to the output terminal of the auxiliary unit A30. Similarly, in the fourth output module OUT4, the second terminal of the second output transistor T2 is also electrically connected to the clock signal. Optionally, the second output transistor T2 is a P-type transistor, which conducts when it receives a low-level signal. When the clock signal received at the second terminal of the second output transistor T2 goes low, the first voltage regulator capacitor C1 can pull the gate of the second output transistor T2 low through coupling, thereby driving the second output transistor T2 to turn on. At this time, the fourth output module OUT4 outputs an enable signal from its first terminal to the output terminal of the auxiliary unit A30.

[0069] In one embodiment of this application, reference continues to be made to... Figures 3-5 As shown, both the second output module OUT2 and the fourth output module OUT4 include a first protection transistor T3. The first terminal of the first protection transistor T3 is electrically connected to the gate of the second output transistor T2. The second terminal of the first protection transistor T3 in the second output module OUT2 is electrically connected to the second node N2. The second terminal of the first protection transistor T3 in the fourth output module OUT4 is multiplexed as the control terminal of the fourth output module OUT4.

[0070] When the second output transistor T2 in both the second output module OUT2 and the fourth output module OUT4 is turned on, the first voltage-regulating capacitor C1 in the second output module OUT2 is located between the first terminal and the gate of the second output transistor T2, and the first voltage-regulating capacitor C1 and the second output transistor T2 in the fourth output module OUT4 are also located between the first terminal and the gate of the second output transistor T2. Therefore, when the electrical connection between the second output module OUT2 and the fourth output module OUT4 is established, the gate of the second output transistor T2 in the second output module OUT2 will be simultaneously affected by the coupling of the first voltage-regulating capacitor C1 in both the second output module OUT2 and the fourth output module OUT4. Similarly, the gate of the second output transistor T2 in the fourth output module OUT2 will also be simultaneously affected by the coupling of the first voltage-regulating capacitor C1 in both the second output module OUT2 and the fourth output module OUT4. For example, when the clock signals received by the first terminal of the second output module OUT2 and the first terminal of the fourth output module OUT4 are different, if the clock signal received by the second output module OUT2 drops while the clock signal received by the fourth output module OUT4 has not yet dropped, then the second output transistor T2 in the fourth output module OUT4 will regulate the gate voltage of the second output transistor T2 in the second output module OUT2. This prevents the gate potential of the second output transistor T2 in the second output module OUT2 from being pulled down to a more ideal state, thus reducing the switching accuracy of the second output transistor T2 in the second output module OUT2. Similarly, the gate of the second output transistor T2 in the fourth output module OUT4 will also be affected by a similar situation.

[0071] Therefore, in this embodiment, a first protection transistor T3 is fabricated in both the second output module OUT2 and the fourth output module OUT4 of the shift register VSR. The second terminal of the first protection transistor T3 in the second output module OUT2 is electrically connected to the second node N2, and the second terminal of the first protection transistor T3 in the fourth output module OUT4 is electrically connected to the gate of the second output transistor T2. This facilitates the transmission of the control signal output from the second node N2 of the control module V10 to the gate of the corresponding second output transistor T2 in each module via the first protection transistor T3 in both modules. When the first scan control unit A40 and the second output unit A50 are turned on, the gates of the second output transistor T2 in the second output module OUT2 and the second output transistor T2 in the fourth output module OUT4 are not directly connected, but are separated by the first protection transistor T3, reducing the risk of mutual interference. This also makes the solution applicable to situations where the clock signal used in the second output module OUT2 is different from the clock signal used in the fourth output module OUT4. This improves the reliability and applicability of the technical solution in this application.

[0072] It should be noted that the first protection transistor T3 is a P-type transistor, and its gate is electrically connected to the first power supply voltage signal VGL. When the second output transistor T2 is off, the first protection transistor T3 is normally open to maintain the gate potential of the second output transistor T2. When the second output transistor T2 is pulled low by the coupling effect of the first voltage regulator capacitor C1, its gate is electrically connected to the first terminal of the first protection transistor T3. When the gate potential of the second output transistor T2 is pulled down to a level lower than the first power supply voltage signal VGL, the first protection transistor T3 is turned off, which helps to stabilize the gate potential of the second output transistor T2.

[0073] Figure 8 This is a schematic diagram of yet another shift register provided in an embodiment of this application. Figure 9 This is a plan view of another region E1 provided in an embodiment of this application.

[0074] In one embodiment of this application, combined with Figure 8 , Figure 9As shown, the display panel 100 also includes a third scan control unit and a fourth scan control unit A60 and A70. In the cascaded shift registers VSRs from the first to the Nth stage along the first scan direction J1, the third scan control unit A60 is connected between the output terminal OUT of the previous stage and the trigger terminal IN of the next stage. In this embodiment, the first scan line SL1 transmits the control signal S1 and the second scan line transmits the control signal S2 as an example. In the multiple cascaded shift registers VSRs, the trigger terminal IN of the next stage shift register VSR receives the control signal S1 output from the output terminal OUT of the previous stage shift register VSR. This facilitates the transmission of the signal output from the output terminal of the previous stage shift register VSR to the trigger terminal IN of the next stage shift register VSR, serving as the cascade signal for the next stage shift register VSR to begin operation.

[0075] The fourth scan control unit A70 is connected between the output terminal OUT of the next stage and the trigger terminal IN of the previous stage. In this embodiment, the first scan line SL1 transmits the control signal S1 and the second scan line transmits the control signal S2 as an example. In a series of cascaded shift registers (VSRs), the trigger terminal IN of the previous stage's shift register receives the control signal S1 output from the output terminal OUT of the next stage's shift register. This facilitates the transmission of the signal output from the output terminal of the next stage's shift register to the trigger terminal IN of the previous stage's shift register, serving as the cascade signal for the previous stage's shift register, thus initiating its operation.

[0076] It should be noted that, as Figure 9 As shown, taking N=6 and m=1 as an example, in Figure 9 S1(n) is the control signal S1 output from the output terminal OUT of the nth stage shift register VSR(n), where n is an integer between 1 and 6. Figure 9 S2(i) is the control signal S2 output from the output terminal of the i-th auxiliary unit A30(i), and the value of i is an integer between 1 and 4.

[0077] In this embodiment, a third scanning control unit A60 is configured to be activated when the scanning direction of the first scanning drive circuit A20 is the first scanning direction J1, and a fourth scanning control unit A70 is configured to be activated when the scanning direction of the first scanning drive circuit A20 is the second scanning direction J2. This facilitates the implementation of a scheme in which the first to Nth level shift registers VSR are cascaded along the first scanning direction J1 or along the second scanning direction J2. Furthermore, the use of the third scanning control unit A60 and the fourth scanning control unit A70 to be activated in different cascading modes is beneficial to improving the stability and accuracy of the driving operation in the display panel 100.

[0078] In one embodiment of this application, reference continues to be made to... Figure 8 , Figure 9 As shown, the control terminals of the first scan control unit A40 and the third scan control unit A60 are electrically connected to the same control signal line, and the control terminals of the second scan control unit A50 and the fourth scan control unit A70 are electrically connected to the same control signal line. Optionally, the signal transmitted by the third control signal line SL3 is used to control the third scan control unit A60, and the signal transmitted by the fourth scan control signal line SL4 is used to control the fourth scan control unit A70.

[0079] In this embodiment, the control terminals of the first scanning control unit A40 and the third scanning control unit A60 are electrically connected to the same control signal line, and the control terminals of the second scanning control unit A50 and the fourth scanning control unit A70 are also electrically connected to the same control signal line. This facilitates ensuring that when the first to Nth level shift registers VSR are cascaded along the first scanning direction J1, the first scanning control unit A40 and the third scanning control unit A60 can be turned on simultaneously. It also facilitates ensuring that when the first to Nth level shift registers VSR are cascaded along the second scanning direction J2, the second scanning control unit A50 and the fourth scanning control unit A70 can be turned on simultaneously. This also facilitates stable operation between the first to Nth level shift registers VSR and the first to N-2m auxiliary units A30. Furthermore, it helps to reduce the number of control signal lines required, thus lowering the manufacturing cost of the display panel 100.

[0080] In one embodiment of this application, reference continues to be made to... Figure 8 , Figure 9 As shown, the first scan control unit A40 includes a first control transistor T4, and the third scan control unit A60 includes a second control transistor T5. The first control transistor T4 and the second control transistor T5 are of the same type, which facilitates the simultaneous control of the first scan control unit A40 and the third scan control unit A60 using the same control signal line. Furthermore, using the same type of control transistor improves the switching synchronization of the first control transistor T4 and the second control transistor T5, reducing switching errors caused by transistor differences. It should be noted that "the first scan control unit A40 includes the first control transistor T4" here means that the first subunit A401 and the second subunit A402 in the first scan control unit A40 include the same first control transistor T4.

[0081] The second scan control unit A50 includes a third control transistor T6, and the fourth scan control unit A70 includes a fourth control transistor T7. The third control transistor T3 and the fourth control transistor T4 are of the same type. This facilitates the simultaneous control of the second scan control unit A50 and the fourth scan control unit A70 using the same control signal line. Furthermore, using the same type of control transistor improves the switching synchronization of the third control transistor T6 and the fourth control transistor T7, reducing switching errors caused by transistor differences. It should be noted that "the second scan control unit A50 includes the second control transistor T6" can mean that the third subunit A501 and the fourth subunit A502 within the second scan control unit A50 include the same second control transistor T6.

[0082] In one embodiment of this application, reference continues to be made to... Figure 2 As shown, the first module 10 in pixel circuit A10 is a data voltage writing module, which transmits data voltage to the driving transistor Md. The second module 20 is a reset module, which resets the gate of the driving transistor Md by transmitting a first reset voltage Vref1 to the gate of the driving transistor Md. In one operating cycle of pixel circuit A10, the reset module operates before the data voltage writing module. The reset module first resets the gate of the driving transistor Md to ensure the accuracy of the data signal received by the driving transistor Md during the data writing phase. Then, the data voltage writing module starts to operate and writes data signals to the driving transistor Md.

[0083] Of course, in some other embodiments, the first module 10 and the second module 20 proposed in this application embodiment can also be the threshold voltage writing module 30 and the reset module 20, respectively. Alternatively, the first module 10 and the second module 20 can also be two modules with sequential turn-on times, such as the light-emitting module 40 and the data voltage writing module.

[0084] Additionally, the pixel circuit A10 includes a threshold voltage writing module 30 for compensating the threshold voltage of the gate of the driving transistor Md. The pixel circuit A10 also includes a light-emitting module 40 for turning on after receiving the light-emitting control signal EM during the light-emitting stage, so that the light-emitting driving current can pass through and be transmitted to the light-emitting element 200. The pixel circuit A10 also includes a second reset module 50, which provides a second reset voltage Vref2 to the light-emitting element 200.

[0085] Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application.

[0086] This application provides a display device 300, such as... Figure 10As shown, the display device 300 includes the display panel 100 proposed in any of the above embodiments. Optionally, the display device 300 may be a display device such as a computer, television, mobile phone, or camera.

[0087] In the display device 300, the display panel 100 is configured to include not only a shift register VSR for outputting control signals required by circuits such as the pixel circuit A10, but also an auxiliary unit A30 for outputting control signals required by circuits such as the pixel circuit A10. This is beneficial for reducing the number of scan drive circuits that need to be fabricated in the display panel 100 by utilizing the auxiliary unit A30. Furthermore, the number of auxiliary units A30 arranged along the first direction X1 is 2m fewer than the number of shift registers VSR, and there is an electrical connection between the auxiliary units A30 and the shift registers VSR. This facilitates the provision of drive signals from the shift registers VSR to the auxiliary units A30, and provides feasible conditions for reducing the fabrication of drive units in the display panel 100. This is beneficial for reducing the number of drive circuits fabricated when the display panel 100 is set along the first scan direction X1 and the second scan direction X2, thereby achieving a narrow bezel of the display panel 100 or saving space area of ​​the display panel 100.

[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Multiple pixel circuits, each pixel circuit including a driving transistor, a first module and a second module, wherein at least one of the first module and the second module is electrically connected to the driving transistor; Within one working cycle of the pixel circuit, the activation time of the first module is later than that of the second module. Multiple first scan lines and multiple second scan lines, wherein the first scan lines are electrically connected to the control terminal of the first module, and the second scan lines are electrically connected to the control terminal of the second module; The first scan driving circuit includes a first-stage to an Nth-stage shift register cascaded along the first scan direction, and the output terminal of the shift register is electrically connected to the first scan line; The first to (N-2m)th auxiliary units are arranged along the first direction, and the output terminal of the auxiliary unit is electrically connected to the second scan line; the first direction is parallel to the first scan direction; Multiple first scanning control units are provided, and the i-th auxiliary unit arranged along the first direction is electrically connected to the i-m+1-th stage shift register cascaded along the first scanning direction through the first scanning control unit; the first scanning control unit is used to activate when the scanning direction of the first scanning drive circuit is the first scanning direction; Multiple second scanning control units are provided. The j-th auxiliary unit, arranged along the first direction, is electrically connected to the (j+m+1)-th stage shift register cascaded along the second scanning direction via the second scanning control unit. The second scanning control unit is activated when the scanning direction of the first scanning drive circuit is the second scanning direction, which is opposite to the first scanning direction. 1≤i≤(N-2m), 1≤j≤(N-2m), m≥1.

2. The display panel according to claim 1, characterized in that, m=1。 3. The display panel according to claim 1, characterized in that, The outputs of the shift registers from level 1 to level m and from level N-m+1 to level N are not electrically connected to the first scan line; and the shift registers from level m+1 to level Nm are electrically connected to the first scan line.

4. The display panel according to claim 1, characterized in that, The shift register includes a control module and an output module. The control module is electrically connected to the control terminal of the output module and is used to control the output module to output an enable signal and a disable signal. The first scanning control unit is connected between the control terminal of the auxiliary unit and the control module of the shift register; The second scanning control unit is connected between the control terminal of the auxiliary unit and the control module of the shift register.

5. The display panel according to claim 4, characterized in that, The control module includes a first node and a second node, and the output module includes a first output module and a second output module. The first output module and the second output module are electrically connected to the first node and the second node, respectively. The first scanning control unit is connected to the first node and the second node, and the second scanning control unit is electrically connected to the first node and the second node.

6. The display panel according to claim 5, characterized in that, The auxiliary unit includes a third output module and a fourth output module. The first scanning control unit includes a first subunit and a second subunit. The second scanning control unit includes a third subunit and a fourth subunit. The first subunit and the third subunit are electrically connected between the first node and the control terminal of the third output module. The second subunit and the fourth subunit are electrically connected between the second node and the control terminal of the fourth output module.

7. The display panel according to claim 6, characterized in that, The third output module has the same structure as the first output module, and the fourth output module has the same structure as the second output module.

8. The display panel according to claim 6, characterized in that, Both the first output module and the third output module include a first output transistor. The first terminal of the first output transistor in the first output module is electrically connected to the output terminal of the shift register, and the first terminal of the first output transistor in the third output module is electrically connected to the output terminal of the auxiliary unit. Both the second output module and the fourth output module include a second output transistor and a first voltage-stabilizing capacitor; the two plates of the first voltage-stabilizing capacitor are electrically connected to the first terminal and the gate of the second output transistor, respectively; the first terminal of the second output transistor in the second output module is also electrically connected to the output terminal of the shift register, and the first terminal of the second output transistor in the fourth output module is also electrically connected to the output terminal of the auxiliary unit.

9. The display panel according to claim 8, characterized in that, Both the second output module and the fourth output module further include a first protection transistor, the first terminal of which is electrically connected to the gate of the second output transistor; the second terminal of the first protection transistor in the second output module is electrically connected to the second node, and the second terminal of the first protection transistor in the fourth output module is multiplexed as the control terminal of the fourth output module.

10. The display panel according to claim 1 or 6, characterized in that, The display panel also includes a third scanning control unit and a fourth scanning control unit. In the first to Nth stage shift registers cascaded along the first scanning direction, the third scanning control unit is connected between the output terminal of the previous stage and the trigger terminal of the next stage, and the fourth scanning control unit is connected between the output terminal of the next stage and the trigger terminal of the previous stage. The third scanning control unit is activated when the scanning direction of the first scanning drive circuit is the first scanning direction, and the fourth scanning control unit is activated when the scanning direction of the first scanning drive circuit is the second scanning direction.

11. The display panel according to claim 10, characterized in that, The control terminal of the first scanning control unit and the control terminal of the third scanning control unit are electrically connected to the same control signal line, and the control terminal of the second scanning control unit and the control terminal of the fourth scanning control unit are electrically connected to the same control signal line.

12. The display panel according to claim 11, characterized in that, The first scan control unit includes a first control transistor, and the third scan control unit includes a second control transistor, wherein the first control transistor and the second control transistor are of the same type. The second scan control unit includes a third control transistor, and the fourth scan control unit includes a fourth control transistor, wherein the third control transistor and the fourth control transistor are of the same type.

13. The display panel according to claim 1, characterized in that, The first module is a data voltage writing module, which is used to transmit data voltage to the driving transistor; the second module is a reset module, which is used to reset the gate of the driving transistor.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

Images