Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a plurality of cascaded shift register units, and each shift register unit comprises an input module, a level transfer module, an output module and a control module. The level transmission module comprises a first control end and is configured to output a low-level signal based on a signal of the first control end and a first clock signal; the output module comprises a second control end, the output module is configured to output a high-level signal based on a signal of the second control end and a second clock signal, and the first clock signal and the second clock signal are phase inversion signals; one control end of the control module and one output end of the input module are connected to a first node, one of the first control end and the second control end is connected with the output end of the control module, and the other one is connected with the first node. According to the shift driving circuit, the mutual influence between the first clock signal and the second clock signal can be isolated, so that the stage transmission module outputs a stable waveform, and the performance reliability of the shift driving circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Indium Gallium Zinc Oxide (IGZO) is a material used for the channel layer in the new generation of thin film transistor technology, and is a type of metal oxide panel technology. IGZO transistors have the advantages of high mobility and low leakage current, which can better improve display afterimages in applications and reduce costs. Currently, pixel circuits made entirely of metal oxide transistors have become one of the technological development trends, so providing a shift drive circuit that matches them is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a display panel and a display device, so as to provide a shift driving circuit for outputting a high-level scanning signal with high performance reliability, thereby improving product yield.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, the display panel includes a plurality of cascaded shift register units, the shift register units include an input module, a stage transmission module, an output module and a control module; the output end of the stage transmission module in the i-th stage shift register unit is connected to the input end of the input module in the i+1-th stage shift register unit, where i is a positive integer;

[0005] The stage transmission module includes a first control terminal, and the stage transmission module is configured to output a low level signal based on a signal of the first control terminal and a first clock signal;

[0006] The output module comprises a second control terminal, and the output module is configured to output a high level signal based on a signal of the second control terminal and a second clock signal, wherein the first clock signal and the second clock signal are mutually inverted signals;

[0007] A control terminal of the control module and an output terminal of the input module are connected to the first node, and one of the first control terminal and the second control terminal is connected to the output terminal of the control module, and the other is connected to the first node.

[0008] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising a display panel provided by any embodiment of the present invention.

[0009] The display panel and display device provided by the embodiment of the present invention have the following beneficial effects: the shift register unit includes a level transmission module, an output module and a control module, the signal output by the level transmission module is used to transmit to the next level shift register unit to realize cascading, and the signal output by the output module is used as a scanning signal. A control end of the control module is connected to the first node, one of the first control end of the level transmission module and the second control end of the output module is connected to the first node, and the other is connected to the output end of the control module, so that the first control end and the second control end are respectively controlled by their corresponding signal lines. In this way, the mutual influence between the first clock signal received by the level transmission module and the second clock signal received by the output module can be isolated, and the signal jump of the second clock signal will not affect the waveform of the signal at the output end of the level transmission module, thereby improving the performance reliability of the shift drive circuit and improving the yield of the display panel product. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0011] Figure 1 A schematic diagram of a pixel circuit in the related art;

[0012] Figure 2 A schematic diagram of a shift register unit in the related art;

[0013] Figure 3 It is a timing diagram in the related art;

[0014] Figure 4 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 5 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0016] Figure 6 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0017] Figure 7 A schematic diagram of a cascade connection of shift register units provided in an embodiment of the present invention;

[0018] Figure 8 A timing diagram provided for an embodiment of the present invention;

[0019] Fig. 9 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0020] Fig.10 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0021] Fig.11 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0022] Fig.12 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0023] Fig.13 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0024] Fig.14 Another timing diagram provided for an embodiment of the present invention;

[0025] Fig.15 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0026] Fig.16 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0027] Fig.17 Another timing diagram provided for an embodiment of the present invention;

[0028] Fig.18 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0029] Fig.19 A schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0030] Fig. 20 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0033] Figure 1FIG. 1 is a schematic diagram of a pixel circuit in the related art. Figure 1 As shown, the pixel circuit includes a driving transistor DT, a data writing transistor T1, a gate reset transistor T2, a light emitting control transistor T3, an electrode reset transistor T4, and a storage capacitor Cst. The driving transistor DT is a dual-gate structure, including a top gate and a bottom gate, wherein the top gate is connected to the data writing transistor T1, the gate reset transistor T2, and one plate of the storage capacitor Cst, and the bottom gate is connected to the other plate of the storage capacitor Cst. The operation of the pixel circuit also requires a first power supply signal ELVDD, a reset signal Vref, a constant voltage signal Vini, a data signal Data, a light emitting control signal EM1, a scan signal G1, a scan signal G2, and a scan signal G3. The pixel circuit is connected to the first electrode of the light emitting device OLED (Organic Light-Emitting Diode), and the second electrode of the light emitting device OLED is connected to the second power supply signal ELVSS, and Coled represents the parasitic capacitance of the light emitting device OLED itself. The active layer of each transistor in the pixel circuit includes a metal oxide, and the transistor is an n-type transistor. The control signals required by the pixel circuit, such as the light emitting control signal EM1, the scanning signal G1, the scanning signal G2, and the scanning signal G3, have an enable level of a high level, so a shift register unit capable of providing a high level enable level is required.

[0034] Figure 2 Schematic diagram of a shift register unit in the related art, such as Figure 2 As shown, the shift register unit includes an input module 01, an output module 02 and a stage transfer module 03. The output module 02 includes a first output tube M1 and a second output tube M2, and the stage transfer module 03 includes a third output tube M3 and a fourth output tube M4. Each output tube is a p-type transistor. The input module 01 writes signals to the node N1 and the node N2 respectively based on at least the input signal STV. The control ends of the first output tube M1 and the third output tube M3 are connected to the node N1, and the control ends of the second output tube M2 and the fourth output tube M4 are connected to the node N2. Capacitors C1 and C2 are also provided in the shift register unit. The first end of the first output tube M1 receives the clock signal CKA, and the second end is connected to the output end OUT of the output module 02. The first end of the second output tube M2 receives the low level signal VGL, and the second end is connected to the output end OUT of the output module 02. The first end of the third output tube M3 receives the clock signal CKB, and the second end is connected to the output end Next of the stage transmission module 03 . The first end of the fourth output tube M4 receives the high level signal VGH, and the second end is connected to the output end Next of the stage transmission module 03 .

[0035] Figure 3 It is a timing diagram in the related technology, which can be used to drive Figure 2 The shift register unit provided in the embodiment. Figure 3From the perspective of FIG. 1 , in the t01 period, the node N2 is at a high potential and the node N1 is at a low potential. The first output tube M1 is turned on, and the output terminal OUT of the output module 02 outputs a high-level signal provided by the clock signal CKA. The third output tube M3 is turned on, and the output terminal Next of the stage transmission module 03 outputs a low-level signal provided by the clock signal CKB. Since the control terminals of the first output tube M1 and the third output tube M3 are both connected to the node N1, the clock signal CKA and the clock signal CKB are mutually inverted signals. In the t01 period, the clock signal CKA jumps from a low level to a high level, and the clock signal CKB jumps from a high level to a low level. Both of them will affect the potential of the node N1 through the parasitic capacitance, thereby causing the output waveforms to affect each other. In addition, since the signal output by the first output tube M1 is used as a scanning signal, the parasitic capacitance between the gate source of the first output tube M1 is relatively large, and the voltage jump of the clock signal CKA causes the node N1 to be pulled up to a large extent, resulting in an abnormal waveform of the cascade output, which affects the performance reliability of the shift drive circuit.

[0036] In order to solve the problems existing in the related technology, an embodiment of the present invention provides a display panel, which adds an additional control signal in the shift register, so that the first control end of the stage transmission module and the second control end of the output module are respectively controlled by their corresponding signals, thereby isolating the mutual influence between the clock signal received by the stage transmission module and the clock signal received by the output module, thereby improving the performance reliability of the shift drive circuit.

[0037] Figure 4 A schematic diagram of a display panel provided by an embodiment of the present invention, such as Figure 4 As shown, the display panel includes a plurality of shift register units 10, a plurality of scan lines 20 and a plurality of pixel circuits 30. The pixel circuit 30 includes a first functional transistor T0, which is an n-type transistor. At least one transistor in the pixel circuit 30 is an n-type transistor. The embodiment of the present invention does not limit the specific structure of the pixel circuit 30. The first functional transistor T0 may be a light-emitting control transistor in the pixel circuit 30, or a threshold compensation transistor, or a gate reset transistor.

[0038] The pixel circuits 30 are arranged in a pixel circuit row 30H in a first direction x, and the scan line 20 extends along the first direction x and is connected to the control ends of a plurality of first functional transistors T0 in the pixel circuit row 30H. The shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b. The first shift register unit 10a is disposed on one side of the two sides of the scan line 20 in the first direction x, and the second shift register unit 10b is disposed on the other side. The output end of the first shift register unit 10a is connected to one end of the scan line 20, and the output end of the second shift register unit 10b is connected to the other end of the scan line 20. The cascaded plurality of first shift register units 10a constitute a first shift driving circuit 1, and the cascaded plurality of second shift register units 10b constitute a second shift driving circuit 2. The first shift register unit 10a and the second shift register unit 10b respectively provide a scan signal to the scan line 20 from one end of the scan line 20 , and the high level in the scan signal is an enable level to drive the n-type transistor in the pixel circuit 30 . Figure 4 The two groups of shift driving circuits are shown to perform bilateral driving on the pixel circuit row 30H, which can balance the voltage drop difference of the scanning signal at different positions in the first direction x and improve the display uniformity. In other embodiments, the shift register unit 10 is arranged on a single side of the scanning line 20, that is, the pixel circuit row 30H is driven unilaterally, which is not shown in the figure here.

[0039] Figure 5 A schematic diagram of a shift register unit provided by an embodiment of the present invention, Figure 6 A schematic diagram of a shift register unit provided by an embodiment of the present invention, Figure 7 Schematic diagram of cascade connection of shift register units provided in an embodiment of the present invention. Figure 5 and Figure 6 As shown, the shift register unit 10 includes an input module 11, a stage transmission module 12, an output module 13 and a control module 14. The stage transmission module 12 includes a first control terminal D1, and the stage transmission module 12 is configured to output a low-level signal based on the signal of the first control terminal D1 and the first clock signal CK1; the output module 13 includes a second control terminal D2, and the output module 13 is configured to output a high-level signal based on the signal of the second control terminal D2 and the second clock signal CK2, and the first clock signal CK1 and the second clock signal CK2 are mutually inverted signals. The input module 11 writes a voltage to the first node Q1 based on the signal of the input terminal IN. One control terminal of the control module 14 and one output terminal of the input module 11 are connected to the first node Q1, and the output terminal of the control module 14 is connected to one of the first control terminal D1 and the second control terminal D2. Figure 5 It is shown that the second control terminal D2 is connected to the output terminal of the control module 14, and the first control terminal D1 is connected to the first node Q1. Figure 6 It is shown that the first control terminal D1 is connected to the output terminal of the control module 14, and the second control terminal D2 is connected to the first node Q1.

[0040] Figure 7 by Figure 5 The schematic structure is used as an example to illustrate the cascade mode of the shift register unit 10. Figure 7 As shown, the output terminal Next of the transmission module 12 in the i-th shift register unit 10(i) is connected to the input terminal IN of the input module 11 in the i+1-th shift register unit 10(i+1), where i is a positive integer. The signal output by the transmission module 12 is used to provide to the shift register unit 10 of the next stage, so as to realize the cascade connection of multiple shift register units 10. The signal output by the output module 13 is used as a scanning signal to drive the pixel circuit row 30H, wherein the high-level signal output by the output module 13 is an enable signal. Figure 4 From the perspective of FIG. 1 , the output terminal OUT of the output module 13 is connected to the scan line 20 , and then the n-type transistor in the pixel circuit 30 is driven by the high-level enable signal.

[0041] In the embodiment of the present invention, the shift register unit 10 includes a stage transmission module 12, an output module 13 and a control module 14. The signal output by the stage transmission module 12 is used to transmit to the next stage shift register unit 10 to realize cascading, and the signal output by the output module 13 is used as a scanning signal. A control end of the control module 14 is connected to the first node Q1, and one of the first control end D1 of the stage transmission module 12 and the second control end D2 of the output module 13 is connected to the first node Q1, and the other is connected to the output end of the control module 14, so that the first control end D1 and the second control end D2 are respectively controlled by their corresponding signal lines. In this way, the mutual influence between the first clock signal CK1 received by the stage transmission module 12 and the second clock signal CK2 received by the output module 13 can be isolated, and the signal jump of the second clock signal CK2 will not affect the waveform of the output end signal of the stage transmission module 12, thereby improving the performance reliability of the shift drive circuit and improving the yield of the display panel product.

[0042] Figure 8 A timing diagram provided in an embodiment of the present invention can be used to drive Figure 5 or Figure 6 The shift register unit provided. Figure 8As shown, the operation of the shift register unit includes a fifth period t5 and a first period t1. In the fifth period t5, the input module 11 writes a low-level signal to the first node Q1 based on at least the input signal of the input terminal IN and the third clock signal CK3, and the first node Q1 is at a low potential; in the first period t1, the first node Q1 maintains a low potential. In the first period t1: the control module 14 is turned on under the control of the first node Q1, and provides a control signal K1 to one of the first control terminal D1 and the second control terminal D2. During this period, the control signal K1 and the potential of the first node Q1 are in phase; that is, in the first period t1, the first control terminal D1 and the second control terminal D2 are both at a low potential. Among them, the stage transmission module 12 is turned on under the control of the first control terminal D1 signal, and the output terminal Next outputs the low-level signal provided by the first clock signal CK1, and the output module 13 is turned on under the control of the second control terminal D2 signal, and the output terminal OUT outputs the high-level signal provided by the second clock signal CK2. In the embodiment of the present invention, a control module 14 is added to the shift register unit 10, the input end of the control module 14 is connected to the first node Q1, and the output signal of the control module 14 and the potential of the first node Q1 are set to be in phase in the first time period t1. In this way, the output signal of the first node Q1 and the control module 14 can be used to control the stage transmission module 12 to output a low level and the output module 13 to output a high level, respectively, to avoid the mutual influence between the first clock signal CK1 and the second clock signal CK2, and the signal jump from low to high of the second clock signal CK2 will not affect the waveform of the output end signal of the stage transmission module 12, which can improve the performance reliability of the shift drive circuit and improve the yield rate of display panel products.

[0043] In other embodiments, Fig. 9 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the other output terminal of the input module 11 is connected to the second node Q2, and the input module 11 is configured to write voltages to the first node Q1 and the second node Q2 respectively based on at least the input signal of the input terminal IN and the third clock signal CK3. One control terminal of the control module 14 is connected to the first node Q1, and the other control terminal is connected to the second node Q2. The output terminal of the control module 14 and one of the first control terminal D1 and the second control terminal D2 are connected to the third node Q3. Fig. 9 In the figure, the output end of the control module 14 and the second control end D2 are connected to the third node Q3 for illustration. In addition, the stage transmission module 12 further includes the third control end D3, and the stage transmission module 12 inputs a high level signal under the control of the third control end D3; the output module 13 further includes the fourth control end D4, and the output module 13 inputs a low level signal under the control of the fourth control end D4. The third control end D3 and the fourth control end D4 are respectively connected to the second node Q2.

[0044] The control module 14 is configured to write a low level signal to the third node Q3 based on the voltage of the first node Q1 and the first voltage signal VG1, and is also configured to write a high level signal to the third node Q3 based on the voltage of the second node Q2, the first clock signal CK1 and the second voltage signal VG2. Optionally, the first voltage signal VG1 is a low level signal VGL, and the second voltage signal VG2 is a high level signal VGH.

[0045] In the embodiment of the present invention, the input module 11 is configured to write signals to the first node Q1 and the second node Q2 respectively, one control terminal in the control module 14 is connected to the first node Q1, the other control terminal is connected to the second node Q2, and the output terminal of the control module 14 and one of the first control terminal D1 and the second control terminal D2 are connected to the third node Q3. In this way, the control module 14 can write a high potential to the third node Q3, and can also write a low potential to the third node Q3, so as to achieve complete control of the control terminal connected to the control module 14. For example, when the second control terminal D2 is connected to the third node Q3, the control module 14 writes a low potential to the third node Q3, and the second control terminal D2 controls the output terminal OUT to output the signal provided by the second clock signal CK2; the control module 14 writes a high potential to the third node Q3, and the second control terminal D2 controls the output terminal OUT to stop outputting the signal provided by the second clock signal CK2.

[0046] In some embodiments, Fig.10 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.10 As shown, the control module 14 includes a first transistor T1, a second transistor T2 and a third transistor T3; the control end of the first transistor T1 is connected to the first node Q1, the first end receives the first voltage signal VG1, and the second end is connected to the output end of the control module 14; the control end of the second transistor T2 is connected to the second node Q2, the first end receives the second voltage signal VG2, and the second end is connected to the first end of the third transistor T3; the control end of the third transistor T3 receives the first clock signal CK1, and the second end is connected to the output end of the control module 14.

[0047] Combination Figure 8 From the timing diagram, the operation of the shift register unit includes a first period t1 and a second period t2; in the first period t1, the first node Q1 is at a low potential, and in the second period t2, the second node Q2 is at a low potential. In the first period t1, the control module 14 is turned on under the control of the first node Q1 and writes a low-level signal of the first voltage signal VG1 to the third node Q3. Specifically, the low potential of the first node Q1 controls the first transistor T1 to turn on and write the low-level signal of the first voltage signal VG1 to the third node Q3, and the third node Q3 is at a low potential.

[0048] In the second period t2, the control module 14 is turned on and writes the high level signal of the second voltage signal VG2 to the third node Q3 under the control of the second node Q2 and the first clock signal CK1. Specifically, the low potential of the second node Q2 controls the second transistor T2 to turn on, and the low level of the first clock signal CK1 controls the third transistor T3 to turn on, and writes the high level signal provided by the second voltage signal VG2 to the third node Q3, so that the third node Q3 is at a high potential.

[0049] For the module controlled by the third node Q3, Fig.10 Take the example of connecting a control terminal of the output module 13 to the third node Q3. In the first period t1, the third node Q3 is at a low potential, and the control output module 13 outputs a high level signal provided by the second clock signal CK2. In the second period t2, the third node Q3 is at a high potential, and the corresponding output tube in the control output module 13 is turned off.

[0050] like Fig.10 As shown, the output module 13 includes a first output tube M1 and a second output tube M2; the stage transmission module 12 includes a third output tube M3 and a fourth output tube M4. The control end of the first output tube M1 is the second control end D2 (combined with Fig. 9 The first end receives the second clock signal CK2, and the second end is connected to the output end OUT of the output module 13; the control end of the second output tube M2 (is Fig. 9 The fourth control terminal D4 shown in the figure is connected to the second node Q2, the first terminal receives the third voltage signal VG3, and the second terminal is connected to the output terminal OUT of the output module 13. The control terminal of the third output tube M3 is the first control terminal D1, the first terminal receives the first clock signal CK1, and the second terminal is connected to the output terminal Next of the stage transmission module 12; the control terminal of the fourth output tube M4 (is Fig. 9 The third control terminal D3 shown in FIG. 1 is connected to the second node Q2, the first terminal receives the second voltage signal VG2, and the second terminal is connected to the output terminal Next of the stage transmission module 12. The third voltage signal VG3 is a low level signal, and the second voltage signal VG2 is a high level signal.

[0051] Fig.10 The shift register unit shown in FIG. 1 further includes a first voltage-stabilizing capacitor C01, one plate of which is connected to the output terminal OUT of the output module 13, and the other plate is connected to the control terminal of the first output terminal M1. The shift register unit further includes a second voltage-stabilizing capacitor C02, one plate of which is connected to the output terminal Next of the stage transmission module 12, and the other plate is connected to the control terminal of the third output terminal M3.

[0052] Combination Figure 8From the timing diagram, in the first time period t1, the first node Q1 is at a low potential, and the second node Q2 is at a high potential. In the first time period t1: the first node Q1 controls the third output tube M3 in the stage transmission module 12 to turn on, and provides the low level of the first clock signal CK1 to the output terminal Next of the stage transmission module 12, and the output terminal Next of the stage transmission module 12 outputs a low level signal; the first node Q1 controls the first transistor T1 in the control module 14 to turn on, and provides the low level of the first voltage signal VG1 to the output terminal of the control module 14, and the third node Q3 is written with a low level signal, and the low potential of the third node Q3 controls the first output tube M1 in the output module 13 to turn on, and provides the high level signal of the second clock signal CK2 to the output terminal OUT of the output module 13, and the output terminal OUT of the output module 13 outputs a high level signal. In this way, the output signals of the first node Q1 and the control module 14 are used to control the stage transmission module 12 to output a low level and the output module 13 to output a high level, respectively, to avoid the mutual influence between the first clock signal CK1 and the second clock signal CK2. The signal jump from low to high of the second clock signal CK2 will not affect the waveform of the output terminal signal of the stage transmission module 12, which can improve the performance reliability of the shift drive circuit and improve the yield rate of the display panel product. In addition, the jump from high to low of the first clock signal CK1 in the first time period t1 can pull down the potential of the first node Q1, so that the third output tube M3 is opened to a better degree, thereby making the output terminal Next of the stage transmission module 12 output a low-level signal better.

[0053] In addition, in the second period t2, the first node Q1 is at a high level and the second node Q2 is at a low potential. In the second period t2: the second node Q2 controls the fourth output tube M4 in the stage transmission module 12 to turn on, and provides the high level of the second voltage signal VG2 to the output terminal Next of the stage transmission module 12, and the output terminal Next of the stage transmission module 12 outputs a high level signal; the second node Q2 controls the second transistor T2 in the control module 14 to turn on, and the low level of the first clock signal CK1 controls the third transistor T3 to turn on, and provides the high level of the second voltage signal VG2 to the third node Q3, and the third node Q3 is at a high potential to control the first output tube M1 to turn off; in addition, the second node Q2 also controls the second output tube M2 in the output module 13 to turn on, and provides the low level of the third voltage signal VG3 to the output terminal OUT of the output module 13, and the output terminal OUT of the output module 13 outputs a low level signal.

[0054] In some embodiments, the first voltage signal VG1 and the third voltage signal VG3 both provide low-level signals, the voltage value of the first voltage signal VG1 is VGL1, and the voltage value of the third voltage signal VG3 is VGL2, wherein VGL1≤VGL2. In the embodiment of the present invention, the signal output by the output module 13 is used as a scanning signal, and VGL1≤VGL2 is set, so that the second output terminal M2 can be closed more completely during the period when the control terminal of the first output terminal M1 is at a low potential and the control terminal of the second output terminal M2 is at a high potential. Then the high-level signal outputted from the output terminal OUT of the output module 13 is more stable, and then the shift register unit drives the pixel circuit more stably, which can improve the performance reliability of the display panel.

[0055] In other embodiments, Fig.11 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.11 As shown, the shift register unit includes a first protection transistor M5, which is connected between the output terminal of the control module 14 and the third node Q3, and the control terminal of the first protection transistor M5 receives the first voltage signal VG1. The first protection transistor M5 can protect the transistor that writes the signal to the output terminal of the control module 14 and prevent the transistor from being broken down when the potential of the third node Q3 is too low.

[0056] like Fig.11 As shown, the shift register unit includes a second protection transistor M6, which is connected between the second node Q2 and another control terminal of the output module 13, and the control terminal of the second protection transistor M6 receives the first voltage signal VG1. The second protection transistor M6 can protect the transistor that writes the signal to the second node Q2 and prevent the transistor from being broken down when the potential of the second output tube M2 is too low.

[0057] In some embodiments, Fig.11 As shown, the shift register unit further includes a third protection transistor M7, which is connected between the output terminal of the input module 11 and the first node Q1, and the control terminal of the third protection transistor M7 receives the first voltage signal VG1.

[0058] In some embodiments, Fig.12 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.12As shown, one control end of the control module 14 is connected to the first node Q1, and the other control end is connected to the second node Q2. The output end of the control module 14 and the control end of the third output tube M3 in the stage transmission module 12 are connected to the third node Q3. The control end of the first output tube M1 in the output module 13 is connected to the first node Q1. The control end of the third output end M3 is the first control end, and the control end of the first output tube M1 is the second control end, that is, the first control end is connected to the output end of the control module 14, and the second control end is connected to the first node Q1. Fig.12 Can be used Figure 8 The timing shown is used for driving, and the working process of the control module 14 is not described in detail here. In this embodiment, the high level of the second clock signal CK2 is provided to the output terminal OUT of the output module 13 by the first node Q1 control, so that the output module 13 outputs a high level signal, and the low level of the first clock signal CK1 is provided to the output terminal Next of the stage transmission module 12 by the output signal control of the control module 14, so that the stage transmission module 12 outputs a low level signal. In this way, the mutual influence between the first clock signal CK1 received by the stage transmission module 12 and the second clock signal CK2 received by the output module 13 can be isolated, and the signal jump of the second clock signal CK2 will not affect the waveform of the signal at the output terminal of the stage transmission module 12, thereby improving the performance reliability of the shift drive circuit and improving the yield of the display panel product.

[0059] In some embodiments, Fig.10 As shown, the input module 11 includes a first submodule 111, a second submodule 112 and a third submodule 113. Among them, the first submodule 111 is configured to write a voltage to the first node Q1 based on the input signal IN (using the same label as the input terminal IN) and the third clock signal CK3. The second submodule 112 is configured to write a voltage to the second node Q2 based on the third clock signal CK3, the output signal of the first submodule 111, and the first voltage signal VG1. The third submodule 113 is configured to write a high level to the first node Q1 based on the output signal of the second submodule 112, the first clock signal CK1, and the second voltage signal VG2. In the embodiment of the present invention, the input module 11 is configured to include three submodules, and the three submodules are used to cooperate with the input signal and the clock signal to write voltage signals to the first node Q1 and the second node Q2 respectively.

[0060] like Fig.10As shown, the first submodule 111 includes a tenth transistor T10, the control end of the tenth transistor T10 receives the third clock signal CK3, the first end receives the input signal IN, and the second end is connected to the first node Q1. The second submodule 112 includes an eleventh transistor T11 and a twelfth transistor T12, the control end of the eleventh transistor T11 receives the third clock signal CK3, the first end receives the first voltage signal VG1, and the second end is connected to the second node Q2, the control end of the twelfth transistor T12 is connected to the second end of the tenth transistor T10 (i.e., connected to the output end of the first submodule 111), the first end receives the third clock signal CK3, and the second end is connected to the second node Q2. The third submodule 113 includes a thirteenth transistor T13 and a fourteenth transistor T14, the control end of the thirteenth transistor T13 is connected to the second node Q2 (i.e., connected to the output end of the second submodule 112), the first end receives the second voltage signal VG2, the second end is connected to the first end of the fourteenth transistor T14, the control end of the fourteenth transistor T14 receives the first clock signal CK1, and the second end is connected to the first node Q1.

[0061] Fig.10 The shift register unit 10 provided in the embodiment can be used Figure 8 The timing provided is driven. Figure 8 The working process of the input module 10 is described. The working of the shift register unit 10 includes a first period t1 (t2), a second period t2, a third period t3 and a fifth period t5. In a time period when the shift register unit outputs a scan signal, the fifth period t5, the first period t1, the third period t3 and the second period t2 are arranged in chronological order.

[0062] In the fifth period t5, the tenth transistor T10 writes the low level of the input signal IN to the first node Q1 under the low level control of the third clock signal CK3, the eleventh transistor T11 writes the low level of the first voltage signal VG1 to the second node Q2 under the low level control of the third clock signal CK3, and the twelfth transistor T12 writes the low level of the third clock signal CK3 to the second node Q2 under the control of the first node Q1. That is, in this period, the first submodule 111 writes a low level signal to the first node Q1 based on the input signal IN and the third clock signal CK3; the second submodule 112 writes a low level signal to the second node Q2 based on the third clock signal CK3, the output signal of the first submodule 111, and the first voltage signal VG1. In the fifth period t5, the first node Q1 is at a low potential, and the second node Q2 is at a low potential.

[0063] In the first period t1, the tenth transistor T10 and the eleventh transistor T11 are turned off under the control of the high level of the third clock signal CK3, the first node Q1 is at a low potential, and the twelfth transistor T12 writes the high level of the third clock signal CK3 to the second node Q2 under the control of the first node Q1. In this period, the first sub-input module 111 is turned off, and the second sub-input module 112 writes a high potential to the second node Q2 based on the potential of the output end of the first sub-input module 111 and the third clock signal CK3. In the first period t1, the first node Q1 maintains a low potential, and the second node Q2 is written with a high potential.

[0064] In the third period t3, the tenth transistor T10 writes the high level of the input signal IN to the first node Q1 under the low level control of the third clock signal CK3, the eleventh transistor T11 writes the low level of the first voltage signal VG1 to the second node Q2 under the low level control of the third clock signal CK3, the thirteenth transistor T13 is turned on under the control of the second node Q2, and the fourteenth transistor T14 is turned off under the high level control of the first clock signal CK1. In this period, the first submodule 111 writes a high level signal to the first node Q1 based on the input signal IN and the third clock signal CK3; the second submodule 112 writes a low level signal to the second node Q2 based on the third clock signal CK3 and the first voltage signal VG1, and the third submodule 113 is still in the off state. In the third period t3, the first node Q1 is at a high potential, and the second node Q2 is at a low potential.

[0065] In the second period t2, the tenth transistor T10 and the eleventh transistor T11 are turned off under the high level control of the third clock signal CK3, the first node Q1 is at a high potential, the second node Q2 is at a low potential, the thirteenth transistor T13 is turned on under the control of the second node Q2, the fourteenth transistor T14 is turned on under the low level control of the first clock signal CK1, and the high level of the second voltage signal VG2 is written into the first node Q1. In this period, the first submodule 111 and the second submodule 112 are turned off, the third submodule 113 is turned on based on the low potential of the second node Q2 and the low level signal of the first clock signal CK1, and the high level signal of the second voltage signal VG2 is written into the first node Q1. In the second period t2, the first node Q1 is at a high potential, and the second node Q2 is at a low potential.

[0066] Fig.11 and Fig.12 The structure of the input module 11 is Fig.10 The same as in the above description, its working process can be understood by referring to the above description.

[0067] In other embodiments, Fig.13 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.13As shown, the output module 13 includes a first output tube M1 and a second output tube M2; the control end of the first output tube M1 is connected to the output end of the control module 14, the first end receives the second clock signal CK2, and the second end is connected to the output end OUT of the output module 13; the control end of the second output tube M2 is connected to the second node Q2, the first end receives the third voltage signal VG3, and the second end is connected to the output end OUT of 13. The shift register unit includes a coupling module 15, a control end of the coupling module 15 and the control end of the second output tube M2 are connected to the fourth node Q4, and the coupling module 15 is configured to couple and pull down the potential of the fourth node Q4 at least during the period when the fourth node Q4 is at a low potential. During the period when the fourth node Q4 is at a low potential, the second output tube M2 is turned on to provide the low-level signal of the third voltage signal VG3 to the output end OUT, and the output module 13 outputs a low-level signal. In the embodiment of the present invention, a coupling module 15 is provided to act on the potential of the fourth node Q4, so that the potential of the fourth node Q4 is lower during the low potential period, thereby ensuring that the second output tube M2 is opened more completely, and the output low-level signal of the output module 13 is more complete, so that the performance of the shift drive circuit is more reliable.

[0068] Fig.13 In the embodiment where the second control end (the control end of the first output tube M1) is connected to the output end of the control module 14 and the first control end (the control end of the third output end M3) is connected to the first node Q1, the coupling module 15 is provided as an example. In other embodiments, the first control end (the control end of the third output end M3) is connected to the output end of the control module 14 and the second control end (the control end of the first output tube M1) is connected to the first node Q1, such as Fig.12 In the embodiment, a coupling module 15 may also be added, which is not illustrated in the figure here.

[0069] Optional, Fig.12 In the embodiment, a second protection transistor M6 is provided, and the second protection transistor M6 is connected between the second node Q2 and the control end of the second output tube M2.

[0070] Optional, Fig.12 A first protection transistor M5 is provided in the control module 14 and is connected between the third node Q3 and the output end of the control module 14 .

[0071] Fig.14 Another timing diagram provided by an embodiment of the present invention. Fig.14As shown, the operation of the shift register unit includes a third period t3 and a fourth period t4; the fourth node Q4 is at a low potential during the third period t3 and the fourth period t4. A second protection transistor M6 is connected between the second node Q2 and the fourth node Q4, and the potentials of the second node Q2 and the fourth node Q4 are in phase. During the third period t3, the coupling module 15 writes the high level signal of the first clock signal CK1 to the fifth node Q5 in the coupling module 15 under the control of the fourth node Q4. During the fourth period t4, the coupling module 15 writes the low level signal of the first clock signal CK1 to the fifth node Q5 under the control of the fourth node Q4, and pulls down the potential of the fourth node Q4 based on the potential change of the fifth node Q5.

[0072] In the embodiment of the present invention, a fifth node Q5 is set in the coupling module 15, a low level is written to the fifth node Q5 in the third period t3, a high level is written to the fifth node Q5 in the fourth period t4, and the potential change of the fifth node Q5 is used to pull down the potential of the fourth node Q4. This makes the potential of the fourth node Q4 lower in at least part of the period of low potential, thereby ensuring that the second output tube M2 is opened more completely, the output low-level signal of the output module 13 is more complete, and the performance of the shift drive circuit is more reliable.

[0073] like Fig.14 As shown, the operation of the shift register unit includes a first period t1, in which the first node Q1 is at a low potential and the fourth node Q4 is at a high potential. In the first period t1, the coupling module 15 writes the high potential of the second voltage signal VG2 to the fifth node Q5 under the control of the first node Q1. Resetting the fifth node Q5 in the coupling module 15 in the first period t1 can ensure the normal periodic operation of the coupling module 15.

[0074] In some embodiments, Fig.15 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.15 The coupling module shown includes a fourth transistor T4, a fifth transistor T5 and a first capacitor C1. The control end of the fourth transistor T4 and the control end of the second output tube M2 are connected to the fourth node Q4, the control end of the fifth transistor T5 is connected to the first node Q1, the first end of the fourth transistor T4 receives the first clock signal CK1, the second end of the fourth transistor T4, the second end of the fifth transistor T5, and one plate of the first capacitor C1 are connected to the fifth node Q5, the first end of the fifth transistor T5 receives the second voltage signal VG2; the other plate of the first capacitor C1 is connected to the control end of the fourth transistor T4. The second voltage signal VG2 provides a high level signal.

[0075] Combination Fig.14 Schematic timing pair Fig.15 The working condition of the coupling module 15 in the embodiment is described. Fig.14 As shown, the operation of the shift register unit includes a first period t1, a third period t3 and a fourth period t4; in the third period t3 and the fourth period t4, the second node Q2 and the fourth node Q4 are at a low potential; in the first period t1, the first node Q1 is at a low potential and the fourth node Q4 is at a high potential.

[0076] In the first period t1, the fifth transistor T5 is turned on under the control of the low potential of the first node Q1, and the high potential of the second voltage signal VG2 is written into the fifth node Q5. The fifth node Q5 is reset in this period.

[0077] In the third period t3, the fourth transistor T4 is turned on under the control of the low potential of the fourth node Q4, and writes the high level signal of the first clock signal CK1 into the fifth node Q5. In this period, the voltage value of the fourth node Q4 is V1.

[0078] In the fourth period t4, the fourth transistor T4 writes the low level signal of the first clock signal CK1 into the fifth node Q5 under the control of the low potential of the fourth node Q4, and pulls down the potential of the fourth node Q4 based on the potential change of the fifth node Q5. The voltage value of the fourth node Q4 in this period is V2, V2 <V1。

[0079] Understandably, Fig.14 At the moment after the fourth period t4 shown in the figure, the third clock signal CK3 is at a low level, the input module 11 writes the low level of the first voltage signal VG1 to the second node Q2, and the potential of the fourth node Q4 also changes accordingly, and the potential of the fourth node Q4 returns to the low potential in the third period t3. Therefore, the potential of the fourth node Q4 will fluctuate between high and low during its low potential maintenance period.

[0080] In addition, Fig.15 When the coupling module 15 and the control module 14 are provided at the same time in the embodiment, the coupling module 15 mainly works when the fourth node Q4 is at a low potential (also when the second node Q2 is at a low potential), and in the partial period when the first node Q1 is at a low potential, it is necessary to reset the nodes in the coupling module 15. The control module 14 mainly works when the first node Q1 is at a low potential, but it also performs certain work during the period when the second node Q2 is at a low potential.

[0081] Combination Fig.14From the perspective of FIG. 1 , in the first time period t1, the first node Q1 is at a low potential, the second node Q2 is at a high potential, and the fourth node Q4 is at a high potential. The fifth transistor T5 in the coupling module 15 is turned on to write the high level to the fifth node Q5 and reset the fifth node Q5. The first transistor T1 in the control module 14 is turned on under the control of the first node Q1 and outputs the low level signal of the first voltage signal VG1. The third node Q3 is at a low potential. The low potential of the third node Q3 controls the first output tube M1 in the output module 13 to turn on, outputting the high level signal of the second clock signal CK2, and the output terminal OUT of the output module 13 outputs a high level. Fig.14 It can be seen that in the first period t1, the voltage of the second clock signal CK2 jumps from low to high, which will pull up the potential coupling of the third node Q3, and in the subsequent period, the voltage of the second clock signal CK2 jumps from high to low, which will pull down the potential of the third node Q3 again, that is, the low potential of the third node Q3 has a certain degree of potential fluctuation. In addition, in this period, the low potential of the first node Q1 controls the third output tube M3 in the stage transmission module 12 to turn on, and provide the low level of the first clock signal CK1 to the output end, and the output end Next of the stage transmission module 12 outputs a low level, and the voltage of the first clock signal CK1 jumps from high to low to pull down the potential of the first node Q1.

[0082] Fig.15 Node Q1′ and node Q3′ are also indicated. The potential of node Q1′ is the same as the output terminal potential of output module 11, and the potential of node Q3′ is the same as the output terminal potential of control module 14. In the first period t1, node Q1′ is at a low potential, and node Q3′ is at a low potential.

[0083] In the third period t3, the first node Q1 is at a high potential, the second node Q2 is at a low potential, and the fourth node Q4 is at a low potential. The fourth transistor T4 in the coupling module 15 is turned on under the low potential control of the fourth node Q4, and the high level of the first clock signal CK1 is written to the fifth node Q5. The first transistor T1 in the control module 14 is turned off under the control of the first node Q1, the second transistor T2 is turned on under the control of the second node Q2, and the third transistor T3 is turned off under the high level control of the first clock signal CK1. The output end of the control module 14 maintains a low potential, and the node Q3′ and the third node Q3 are both at a low potential. In this period, the low potential of the second node Q2 controls the fourth output tube M4 in the stage transmission module 12 to turn on, and the stage transmission module 12 outputs a high level signal, and the low potential of the fourth node Q4 controls the second output tube M2 in the output module 13 to turn on, and the output module 13 outputs a low level signal.

[0084] In the fourth period t4, the first node Q1 is at a high potential, the second node Q2 is at a low potential, and the fourth node Q4 is at a low potential. The fourth transistor T4 in the coupling module 15 is turned on under the control of the low potential of the fourth node Q4, and the low level of the first clock signal CK1 is written to the fifth node Q5, and the fifth node Q5 jumps from a high potential to a low potential, and the potential coupling of the fourth node Q4 is pulled down by the coupling effect of the first capacitor C1. In this period, the first clock signal CK1 is a low-level signal, the second transistor T2 in the control module 14 is turned on under the control of the second node Q2, and the third transistor T3 is turned on under the control of the low level of the first clock signal CK1, and the high level of the second voltage signal VG2 is provided to the output end of the control module 14, so that the node Q3' and the third node Q3 are both at a high potential.

[0085] Combined with the above Figure 8 Timing diagram and Fig.10 The relevant description of the working period of the control module 14 in the embodiment can be understood that the working condition of the control module 14 in the fourth period t4 is similar to that in the fourth period t4. Figure 8 The working conditions in the second time period t4 in the timing diagram are the same. The fourth time period t4 is the second time period t2 of the control module 14.

[0086] in addition, Fig.15 The input module 11 is used to write voltages to the first node Q1 and the second node Q2 respectively. The working process of the input module 11 is shown in FIG. Figure 8 and Fig.10 The relevant descriptions in the embodiments are not repeated here.

[0087] In other embodiments, Fig.16 Schematic diagram of another shift register unit provided by an embodiment of the present invention. Fig.16As shown, the coupling module 15 includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1, a sixth transistor T6 and a sub-input module 151. The control end of the fourth transistor T4 is connected to the fourth node Q4 through the sixth transistor T6, the control end of the fifth transistor T5 is connected to the first node Q1, the first end of the fourth transistor T4 receives the first clock signal CK1, the second end of the fourth transistor T4, the second end of the fifth transistor T5, and one plate of the first capacitor C1 are connected to the fifth node Q5, and the first end of the fifth transistor T5 receives the second voltage signal VG2; the other plate of the first capacitor C1 is connected to the control end of the fourth transistor T4. The control end of the sixth transistor T6 is connected to the control end of the fourth transistor T4, the first end of the sixth transistor T6 and its control end are connected to the sixth node Q6, and the second end of the sixth transistor T6 is connected to the fourth node Q4; that is, the first end of the sixth transistor T6 and its control end, and one plate of the first capacitor C1 are connected to the sixth node Q6. The output end of the sub-input module 151 is connected to the sixth node Q6 , and the sub-input module 151 is configured to write a voltage to the sixth node Q6 based on the first voltage signal VG1 , the third clock signal CK3 , and the potential of the first node Q1 .

[0088] Fig.17 Another timing diagram provided by the embodiment of the present invention can be used to drive Fig.16 The shift register unit provided. Fig.17 As shown, the operation of the shift register unit includes a first period t1, a third period t3 and a fourth period t4; in the third period t3 and the fourth period t4, the fourth node Q4 is at a low potential and the first node Q1 is at a high potential, and in the first period t1, the first node Q1 is at a low potential and the fourth node Q4 is at a high potential; a second protection transistor M6 is connected between the second node Q2 and the fourth node Q4, and the potentials of the second node Q2 and the fourth node Q4 are in phase. The operation of the coupling module 15 includes the following process:

[0089] In the first period t1, the fifth transistor T5 writes the high potential of the second voltage signal VG2 to the fifth node Q5 under the control of the low potential of the first node Q1. The sub-input module 151 writes the high potential to the sixth node Q6 under the control of the first node Q1.

[0090] In the third period t3, the sub-input module 151 is turned on under the low level control of the third clock signal CK3, and the low level of the first voltage signal VG1 is written into the sixth node Q6, the fourth transistor T4 writes the high level signal of the first clock signal CK1 into the fifth node Q5 under the control of the sixth node Q6, and the sixth transistor T6 conducts the path between the fourth node Q4 and the sixth node Q6 under the control of the sixth node Q6. The voltage value of the fourth node Q4 in this period is V1.

[0091] In the fourth period t4, the sub-input module 151 is closed under the high level control of the third clock signal CK3, the sixth node Q6 maintains a low potential, the fourth transistor T4 writes the low level signal of the first clock signal CK1 to the fifth node Q5 under the control of the sixth node Q6, due to the effect of the first capacitor C1, the potential change of the fifth node Q5 pulls down the potential of the sixth node Q6, and the sixth transistor T6, under the control of the sixth node Q6, turns on the path between the fourth node Q4 and the sixth node Q6 and pulls down the potential of the fourth node Q4. The voltage value of the fourth node Q4 during this period is V2, which is less than V1.

[0092] In this embodiment, the control end of the sixth transistor T6 and the first end of the sixth transistor T6 are connected to the sixth node Q6, and the sixth transistor T6 forms a diode-like structure, so that it has a unidirectional conduction characteristic. In the period t6 when the first clock signal CK1 is at a high level after the fourth period t4, the low potential of the sixth node Q6 controls the fourth transistor T4 to write the high-level signal of the first clock signal CK1 into the fifth node Q5, and the potential change of the fifth node Q5 pulls up the potential of the sixth node Q6. At this time, the sixth node Q6 is at a low potential, but the potential will be higher than its potential in the fourth period t4. Since the sixth transistor T6 forms a diode-like structure, it can prevent the sixth node Q6 from discharging to the fourth node Q4, so that the fourth node Q4 is still at a lower low potential. In this way, the low potential stability of the fourth node Q4 is better, and the output module 13 can output a more complete low-level signal.

[0093] In addition, the operation of the control module 14 in this embodiment can refer to the above Fig.15 The embodiments are for understanding only and will not be described in detail here.

[0094] In other embodiments, Fig.18 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.18As shown, the sub-input module 151 includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9; the control end of the seventh transistor T7 receives the third clock signal CK3, the first end receives the first voltage signal VG1, and the second end is connected to the first end of the eighth transistor T8, and the control end of the eighth transistor T8 receives the first voltage signal VG1, and the second end is connected to the sixth node Q6. The control end of the ninth transistor T9 is connected to the first node Q1, the first end receives the third clock signal CK3, and the second end is connected to the second end of the seventh transistor T7. In the first period t1, the ninth transistor T9 is turned on under the control of the low level of the first node Q1 to write the high level signal provided by the third clock signal CK3 to the seventh node Q7, and writes the high level to the sixth node Q6 through the eighth transistor T8, so that the sixth node Q6 is a high potential. In the third period t3, the low level of the third clock signal CK3 controls the seventh transistor T7 to turn on, and the low level of the first voltage signal VG1 controls the eighth transistor T8 to turn on, and writes the low level signal of the first voltage signal VG1 to the sixth node Q6. In the fourth period t4 , the high level of the third clock signal CK3 controls the seventh transistor T7 to be turned off, and the sixth node Q6 maintains a low level signal.

[0095] like Fig.18 As shown, the shift register unit includes a third protection transistor M7, a control end of the third protection transistor M7 receives the first voltage signal VG1, a first end is connected to an output end of the input module 11, and a second end is connected to the first node Q1. When the potential of the first node Q1 is too low, the third protection transistor M7 can protect the transistor connected to its first end to prevent the transistor from being broken down.

[0096] In other embodiments, Fig.19 A schematic diagram of another shift register unit provided by an embodiment of the present invention is shown in FIG. Fig.19 As shown, an output terminal of the input module 11 is connected to the node Q1′, the third protection transistor M7 is connected between the node Q1′ and the first node Q1, and the control terminal of the fifth transistor T5 in the coupling module 15 is connected to the node Q1′, that is, connected to the first terminal of the third protection transistor M7. Such an arrangement can ensure that the potential of the control terminal of the fifth transistor T5 is not affected by the potential jump of the first clock signal CK1.

[0097] Fig.19 The shift register unit provided in the embodiment can adopt Fig.17 The timing provided is used for driving, and its working process can be understood by referring to the above-mentioned related embodiments, which will not be repeated here.

[0098] In some implementations, each transistor in the shift register unit provided by the present invention is a p-type transistor.

[0099] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig. 20 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Fig. 20 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, an electronic device such as a mobile phone, a tablet, a television, a smart wearable product, etc.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of cascaded shift register units, each of which includes an input module, a stage transmission module, an output module and a control module; the output end of the stage transmission module in the i-th stage shift register unit is connected to the input end of the input module in the i+1-th stage shift register unit, where i is a positive integer; The stage transmission module comprises a first control terminal, and the stage transmission module is configured to output a low level signal based on a signal of the first control terminal and a first clock signal; The output module comprises a second control terminal, and the output module is configured to output a high level signal based on a signal of the second control terminal and a second clock signal, wherein the first clock signal and the second clock signal are mutually inverted signals; A control terminal of the control module and an output terminal of the input module are connected to a first node, and one of the first control terminal and the second control terminal is connected to the output terminal of the control module, and the other is connected to the first node.

2. The display panel according to claim 1, characterized in that: The operation of the shift register unit includes a first period; In the first time period: the control module is opened under the control of the first node and provides a control signal to one of the first control end and the second control end; the transmission module is opened under the control of the first control end signal and outputs a low-level signal provided by the first clock signal; the output module is opened under the control of the second control end signal and outputs a high-level signal provided by the second clock signal.

3. The display panel according to claim 1, characterized in that: Another output terminal of the input module is connected to a second node, another control terminal of the control module is connected to the second node, and an output terminal of the control module and one of the first control terminal and the second control terminal are connected to a third node; The control module is configured to write a low level signal to the third node based on the voltage of the first node and the first voltage signal, and is also configured to write a high level signal to the third node based on the voltage of the second node, the first clock signal and the second voltage signal.

4. The display panel according to claim 3, characterized in that: The operation of the shift register unit includes a first period and a second period; In the first period, the control module opens and writes a low level signal of the first voltage signal to the third node under the control of the first node; In the second period, the control module is turned on and writes a high level signal of the second voltage signal to the third node under the control of the second node and the first clock signal.

5. The display panel according to claim 3, characterized in that: The control module includes a first transistor, a second transistor and a third transistor; The control end of the first transistor is connected to the first node, the first end receives the first voltage signal, and the second end is connected to the output end of the control module; the control end of the second transistor is connected to the second node, the first end receives the second voltage signal, and the second end is connected to the first end of the third transistor; the control end of the third transistor receives the first clock signal, and the second end is connected to the output end of the control module.

6. The display panel according to claim 3, characterized in that: The second control end is connected to the third node; The shift register unit comprises a first protection transistor, the first protection transistor is connected between the output terminal of the control module and the third node, and the control terminal of the first protection transistor receives the first voltage signal; And / or, the shift register unit includes a second protection transistor, the second protection transistor is connected between the second node and a control terminal of the output module, and the control terminal of the second protection transistor receives the first voltage signal.

7. The display panel according to claim 3, characterized in that: The output module includes a first output tube and a second output tube; The control end of the first output tube is the second control end, the first end receives the second clock signal, and the second end is connected to the output end of the output module; the control end of the second output tube is connected to the second node, the first end receives the third voltage signal, and the second end is connected to the output end of the output module.

8. The display panel according to claim 7, characterized in that: The voltage value of the first voltage signal is VGL1, and the voltage value of the third voltage signal is VGL2, wherein VGL1≤VGL2.

9. The display panel according to claim 1, characterized in that: The output module comprises a first output tube and a second output tube; the control end of the first output tube is the second control end, the first end receives the second clock signal, and the second end is connected to the output end of the output module; the control end of the second output tube is connected to the second node, the first end receives the third voltage signal, and the second end is connected to the output end of the output module; The shift register unit includes a coupling module, a control end of the coupling module and a control end of the second output tube are connected to a fourth node, and the coupling module is configured to couple and pull down the potential of the fourth node at least during a period when the fourth node is at a low potential.

10. The display panel according to claim 9, characterized in that: The operation of the shift register unit includes a third period and a fourth period; during the third period and the fourth period, the fourth node is at a low potential; In the third period, the coupling module writes a high level signal of the first clock signal into a fifth node in the coupling module under the control of the fourth node; In the fourth time period, the coupling module writes a low level signal of the first clock signal into the fifth node under the control of the fourth node, and pulls down the potential of the fourth node based on the potential change of the fifth node.

11. The display panel according to claim 10, characterized in that: The operation of the shift register unit includes a first period, during which the first node is at a low potential and the fourth node is at a high potential; During the first period, the coupling module writes a high potential of a second voltage signal into the fifth node under the control of the first node.

12. The display panel according to claim 9, characterized in that: The coupling module includes a fourth transistor, a fifth transistor and a first capacitor; The control end of the fourth transistor and the control end of the second output tube are connected to the fourth node, the control end of the fifth transistor is connected to the first node, the first end of the fourth transistor receives the first clock signal, the second end of the fourth transistor, the second end of the fifth transistor, and one plate of the first capacitor are connected to the fifth node, the first end of the fifth transistor receives the second voltage signal; the other plate of the first capacitor is connected to the control end of the fourth transistor.

13. The display panel according to claim 12, characterized in that: The operation of the shift register unit includes a first period, a third period and a fourth period; the fourth node is at a low potential in the third period and the fourth period, and the first node is at a low potential and the fourth node is at a high potential in the first period; In the first period, the fifth transistor writes a high potential of the second voltage signal into the fifth node under the control of the first node; In the third period, the fourth transistor writes a high level signal of the first clock signal into the fifth node under the control of the fourth node; In the fourth period, the fourth transistor writes a low level signal of the first clock signal into the fifth node under the control of the fourth node, and pulls down the potential of the fourth node based on the potential change of the fifth node.

14. The display panel according to claim 12, characterized in that: The coupling module further includes a sixth transistor and a sub-input module; The control end of the fourth transistor is connected to the fourth node through the sixth transistor, the control end of the sixth transistor is connected to the control end of the fourth transistor, the first end and the control end of the sixth transistor are connected to the sixth node, and the second end of the sixth transistor is connected to the fourth node; The output end of the sub-input module is connected to the sixth node, and the sub-input module is configured to write a voltage to the sixth node based on the first voltage signal, the third clock signal, and the potential of the first node.

15. The display panel according to claim 14, characterized in that: The operation of the shift register unit includes a first period, a third period and a fourth period; the fourth node is at a low potential in the third period and the fourth period, and the first node is at a low potential and the fourth node is at a high potential in the first period; In the first period, the fifth transistor writes the high potential of the second voltage signal to the fifth node under the control of the first node, and the sub-input module is turned on to write the high potential to the sixth node under the control of the first node; In the third period, the sub-input module is turned on under the control of the low level of the third clock signal, and writes the low level of the first voltage signal into the sixth node; the fourth transistor writes the high level signal of the first clock signal into the fifth node under the control of the sixth node; and the sixth transistor conducts the path between the fourth node and the sixth node under the control of the sixth node; In the fourth time period, the sub-input module is closed under the high level control of the third clock signal, the fourth transistor writes the low level signal of the first clock signal to the fifth node under the control of the sixth node, and pulls down the potential of the sixth node based on the potential change of the fifth node, and the sixth transistor, under the control of the sixth node, turns on the path between the fourth node and the sixth node and pulls down the potential of the fourth node.

16. The display panel according to claim 14, characterized in that: The sub-input module includes a seventh transistor, an eighth transistor and a ninth transistor; The control end of the seventh transistor receives the third clock signal, the first end receives the first voltage signal, and the second end is connected to the first end of the eighth transistor; the control end of the eighth transistor receives the first voltage signal, and the second end is connected to the sixth node; The control end of the ninth transistor is connected to the first node, the first end receives the third clock signal, and the second end is connected to the second end of the seventh transistor.

17. The display panel according to claim 12, characterized in that: The shift register unit includes a third protection transistor, a control end of the third protection transistor receives a first voltage signal, a first end is connected to an output end of the input module, and a second end is connected to the first node.

18. The display panel according to claim 3, characterized in that: The stage transmission module includes a third output tube and a fourth output tube; The control end of the third output tube is the first control end, the first end receives the first clock signal, and the second end is connected to the output end of the stage transmission module; the control end of the fourth output tube is connected to the second node, the first end receives the second voltage signal, and the second end is connected to the output end of the stage transmission module.

19. The display panel according to claim 3, characterized in that: The input module includes a first submodule, a second submodule and a third submodule; The first submodule is configured to write a voltage to the first node based on an input signal and a third clock signal; The second submodule is configured to write a voltage to the second node based on the third clock signal, the output signal of the first submodule, and the first voltage signal; The third submodule is configured to write a high level to the first node based on the output signal of the second submodule, the first clock signal, and the second voltage signal.

20. The display panel according to claim 19, characterized in that: The first submodule includes a tenth transistor, a control end of the tenth transistor receives the third clock signal, a first end of the tenth transistor receives the input signal, and a second end of the tenth transistor is connected to the first node; The second submodule includes an eleventh transistor and a twelfth transistor, wherein the control end of the eleventh transistor receives the third clock signal, the first end receives the first voltage signal, and the second end is connected to the second node, and the control end of the twelfth transistor is connected to the second end of the tenth transistor, the first end receives the third clock signal, and the second end is connected to the second node; The third submodule includes a thirteenth transistor and a fourteenth transistor, the control end of the thirteenth transistor is connected to the second node, the first end receives the second voltage signal, and the second end is connected to the first end of the fourteenth transistor, the control end of the fourteenth transistor receives the first clock signal, and the second end is connected to the first node.

21. The display panel according to claim 20, characterized in that: The operation of the shift register unit includes a first period, a second period, a third period, and a fifth period; In the fifth period, the tenth transistor writes the low level of the input signal into the first node under the control of the low level of the third clock signal, the eleventh transistor writes the low level of the first voltage signal into the second node under the control of the low level of the third clock signal, and the twelfth transistor writes the low level of the third clock signal into the second node under the control of the first node; In the first period, the tenth transistor and the eleventh transistor are turned off under the control of the high level of the third clock signal, the first node is at a low potential, and the twelfth transistor writes the high level of the third clock signal into the second node under the control of the first node; In the third period, the tenth transistor writes the high level of the input signal into the first node under the control of the low level of the third clock signal, the eleventh transistor writes the low level of the first voltage signal into the second node under the control of the low level of the third clock signal, the thirteenth transistor is turned on under the control of the second node, and the fourteenth transistor is turned off under the control of the high level of the first clock signal; In the second time period, the tenth transistor and the eleventh transistor are turned off under the control of the high level of the third clock signal, the first node is at a high potential, the second node is at a low potential, the thirteenth transistor is turned on under the control of the second node, the fourteenth transistor is turned on under the control of the low level of the first clock signal, and the high level of the second voltage signal is written to the first node.

22. The display panel according to claim 1, characterized in that: The display panel comprises a scan line and a plurality of pixel circuits, wherein the pixel circuit comprises a first functional transistor, and the first functional transistor is an n-type transistor; The pixel circuits are arranged in a pixel circuit row in a first direction, and the scan line extends along the first direction and is connected to the control ends of a plurality of the first functional transistors in the pixel circuit row; The shift register unit includes a first shift register unit and a second shift register unit, the first shift register unit and the second shift register unit are located on both sides of the scan line in the first direction, the output end of the first shift register unit is connected to one end of the scan line, and the output end of the second shift register unit is connected to the other end of the scan line.

23. A display device, characterized in that: A display panel comprising any one of claims 1 to 22.

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