Display panel, driving method thereof and display module

Abstract

The invention discloses a display panel, a driving method thereof and a display module, and relates to the technical field of display. The display panel comprises at least one first pixel circuit, and the first pixel circuit comprises a first-type transistor and a driving transistor; a first electrode of the first-type transistor is connected with a grid electrode of the driving transistor, a second electrode of the first-type transistor is used for transmitting data signals, a first grid electrode of the first-type transistor is connected with a first signal line, and a second grid electrode of the first-type transistor is connected with a second signal line; in a first state, the first signal line transmits a first voltage signal, and the first type transistor is turned off; in the second state, the first signal line transmits a second voltage signal, and the first type of transistors are controlled to be turned on or turned off by the voltage of the second signal line. According to the embodiment of the invention, the use performance of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display module. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a driving method thereof, and a display module, which are beneficial to improving the performance of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising

[0006] comprising at least one first pixel circuit, the first pixel circuit comprising a first type transistor and a driving transistor;

[0007] The first electrode of the first type of transistor is connected to the gate of the driving transistor, the second electrode of the first type of transistor is used to transmit a data signal, the first gate of the first type of transistor is connected to the first signal line, and the second gate of the first type of transistor is connected to the second signal line;

[0008] In the first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off;

[0009] In the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line.

[0010] In some implementations of the first aspect, there are multiple first pixel circuits, and at least two first pixel circuits are located in the same row.

[0011] In some implementations of the first aspect, all pixel circuits included in the display panel are first pixel circuits.

[0012] In some implementations of the first aspect, the second gates of the first pixel circuits in the same row are all connected to the second signal line, and the first gates of the first pixel circuits in the same column are all connected to the first signal line.

[0013] In some embodiments of the first aspect, in the first state, a refresh rate of a signal on the second signal line connected to the first pixel circuit is equal to a refresh rate of a signal on the second signal line connected to the first pixel circuit in the second state.

[0014] In some embodiments of the first aspect, the first type of transistor includes a threshold compensation transistor, the threshold compensation transistor is a dual-gate transistor,

[0015] The first gate of the threshold compensation transistor is a top gate, and the second gate of the threshold compensation transistor is a bottom gate; or, the first gate of the threshold compensation transistor is a bottom gate, and the second gate of the threshold compensation transistor is a top gate.

[0016] In some embodiments of the first aspect, the threshold compensation transistor is an N-type transistor;

[0017] In some embodiments of the first aspect, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, a second electrode of the threshold compensation transistor is connected to a first electrode of the driving transistor, a first gate of the threshold compensation transistor is connected to a first signal line, and a second gate of the threshold compensation transistor is connected to a second signal line.

[0018] In some embodiments of the first aspect, the first pixel circuit further includes a first initialization transistor, a third gate of the first initialization transistor is connected to the third signal line, a fourth gate of the first initialization transistor is connected to the fourth signal line, a first electrode of the first initialization transistor is connected to the gate of the driving transistor, and a second electrode of the first initialization transistor is connected to the first initialization signal line;

[0019] In the first state, the third signal line transmits a third voltage signal, and the first initialization transistor is turned off;

[0020] In the second state, the third signal line transmits a fourth voltage signal, and the first initialization transistor is turned on or off by the voltage control of the fourth signal line.

[0021] In some implementations of the first aspect, the fourth gates of the first pixel circuits in the same row are all connected to the fourth signal line, and the third gates of the first pixel circuits in the same column are all connected to the third signal line.

[0022] In some embodiments of the first aspect, the first initialization transistor is a dual-gate transistor.

[0023] In some embodiments of the first aspect, the third gate of the first initialization transistor is a top gate, and the fourth gate of the first initialization transistor is a bottom gate; or, the third gate of the first initialization transistor is a bottom gate, and the fourth gate of the first initialization transistor is a top gate.

[0024] In some embodiments of the first aspect, the first initialization transistor is an N-type transistor.

[0025] In some embodiments of the first aspect, in the first state, a refresh rate of a signal on the fourth signal line connected to the first pixel circuit is equal to a refresh rate of a signal on the fourth signal line connected to the first pixel circuit in the second state.

[0026] In some embodiments of the first aspect, the driving transistor is a P-type transistor.

[0027] In some embodiments of the first aspect, the first type of transistor includes a threshold compensation transistor, and the threshold compensation transistor and the first initialization transistor are both N-type transistors;

[0028] The voltage value of the signals on the second signal line and the fourth signal line when they are at the on level is VGH1, and the voltage value of the signals on the second signal line and the fourth signal line when they are at the off level is VGL1, 7V≤VGH1-VGL1≤11V.

[0029] In some embodiments of the first aspect, VGH1 - VGL1 = 10V.

[0030] In some implementations of the first aspect, -4V≤VGH1≤-2V, -13V≤VGL1≤-11V.

[0031] In some implementations of the first aspect, voltage values ​​of the first voltage signal and the third voltage signal are both VGL2, voltage values ​​of the second voltage signal and the fourth voltage signal are both VGH2, and VGH2-VGL2≤VGH1-VGL1.

[0032] In some embodiments of the first aspect, VGH2 - VGL2 = 5V.

[0033] In some implementations of the first aspect, 7V≤VGH2-VGH1≤9V, 11V≤VGL2-VGL1≤13V.

[0034] In some implementations of the first aspect, VGH2 - VGH1 = 8V, VGL2 - VGL1 = 12V.

[0035] In some implementations of the first aspect, the display panel includes a plurality of data lines, and the first signal line and the third signal line are both arranged in parallel with the data lines.

[0036] In some implementations of the first aspect, the first signal line, the third signal line, and the data line are all located in the same film layer.

[0037] In some implementations of the first aspect, the first pixel circuit further includes a data writing transistor, a light emission control transistor, a second initialization transistor, and a storage capacitor;

[0038] The gate of the data writing transistor is connected to the fifth signal line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the second electrode of the driving transistor;

[0039] The light-emitting control transistor includes a first light-emitting control transistor and a second light-emitting control transistor, a gate of the first light-emitting control transistor and a gate of the second light-emitting control transistor are both connected to a light-emitting control signal line, a first electrode of the first light-emitting control transistor is connected to a first power line, a second electrode of the first light-emitting control transistor is connected to a second electrode of the driving transistor, a first electrode of the second light-emitting control transistor is connected to a first electrode of the driving transistor, and a second electrode of the second light-emitting control transistor is connected to a light-emitting element;

[0040] The gate of the second initialization transistor is connected to the sixth signal line, the first electrode of the second initialization transistor is connected to the second initialization signal line, and the second electrode of the second initialization transistor is connected to the light emitting element;

[0041] The storage capacitor is connected to the first power line and the gate of the driving transistor.

[0042] Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a method for driving a display panel, wherein the display panel includes at least one first pixel circuit, and the first pixel circuit includes a first type of transistor and a driving transistor;

[0043] The first electrode of the first type of transistor is connected to the gate of the driving transistor, the second electrode of the first type of transistor is used to transmit a data signal, the first gate of the first type of transistor is connected to the first signal line, and the second gate of the first type of transistor is connected to the second signal line;

[0044] Drive methods include:

[0045] In the first state, the first signal line is controlled to transmit a first voltage signal so as to turn off the first type of transistor;

[0046] In the second state, the first signal line is controlled to transmit a second voltage signal, so that the first type of transistor is turned on or off by the voltage control of the second signal line.

[0047] Based on the same inventive concept, in a third aspect, an embodiment of the present application further provides a display module, comprising the display panel of the first aspect.

[0048] In some implementations of the third aspect, the display panel includes a plurality of display areas, and the display module further includes a timing control module;

[0049] The display panel or display module also includes a level conversion circuit, and the level conversion circuit is connected to the timing control module;

[0050] The timing control module is used to parse the display area information, obtain parsed data, and transmit the parsed data line by line to the level conversion circuit when receiving the display area information, wherein the display area information includes at least one of the number of display areas, position information, and refresh rate;

[0051] The level conversion circuit is used for converting the parsed data into a first voltage signal or a second voltage signal, and transmitting the first voltage signal or the second voltage signal to the first signal line.

[0052] In some implementations of the third aspect, the display panel or display module further includes a shift register, the shift register is connected to both the level conversion circuit and the timing control module, and the timing control module is further used to transmit the parsed data to the shift register line by line;

[0053] The shift register is used to transmit the parsed data to the level conversion circuit in parallel when receiving the parsed data.

[0054] In some implementations of the third aspect, the number of binary digits included in the parsed data is equal to the number of pixels included in the display panel.

[0055] According to the display panel, display panel driving method and display module provided by the embodiments of the present application, on the one hand, by connecting the first gate of the first type of transistor to the first signal line, in the first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off, so that the voltage data of the first pixel circuit is not refreshed, thereby achieving low refresh rate display.

[0056] On the other hand, by connecting the second gate of the first type of transistor to the second signal line, in the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line. For example, when the first type of transistor is turned on by the voltage control of the second signal line, the data voltage of the first pixel circuit can be refreshed; for another example, when the first type of transistor is turned off by the voltage control of the second signal line, the data voltage of the first pixel circuit can be not refreshed. In other words, the embodiment of the present application can control the data voltage of the first pixel circuit to be refreshed or not, thereby providing the possibility for the display panel to perform zoned and frequency-refresh display according to different columns in the same period, which is conducive to improving the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0058] Figure 1A schematic diagram showing a display panel provided by an embodiment of the present application;

[0059] Figure 2 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0060] Figure 3 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0061] Figure 4 Another schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0062] Figure 5 A characteristic test curve diagram of an oxide thin film transistor provided by an embodiment of the present application is shown;

[0063] Figure 6 Another characteristic test curve diagram of the oxide thin film transistor provided by an embodiment of the present application is shown;

[0064] Figure 7 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0065] Figure 8 Another schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0066] Fig. 9 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0067] Fig.10 Another schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0068] Fig.11 A schematic diagram showing the working sequence of the display panel provided by an embodiment of the present application;

[0069] Fig.12 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0070] Fig.13 A schematic diagram showing a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0071] Fig.14 A schematic diagram showing a display module provided in an embodiment of the present application;

[0072] Fig.15 Another schematic diagram of a display module provided in an embodiment of the present application is shown;

[0073] Fig.16 Another schematic diagram of a display module provided in an embodiment of the present application is shown;

[0074] Fig.17 Another schematic diagram showing a display panel provided by an embodiment of the present application;

[0075] Fig.18 Another schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0076] Fig.19 Another schematic diagram of a display module provided in an embodiment of the present application is shown;

[0077] Fig. 20 Another schematic diagram of a display module provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0078] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0079] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0080] The term "connection" may mean "electrical connection" or "not electrically connected through an intermediate transistor". The term "insulation" may mean "electrical insulation" or "electrical isolation". The term "drive" may mean "control" or "operation". The term "part" may mean "local". The term "pattern" may mean "component". The term "end" may mean "end segment" or "end edge". The display panel may be a display module or a module / part of a display module.

[0081] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0082] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the problems existing in the related technologies are first described in detail:

[0083] Active Matrix Organic Light Emitting Diode (AMOLED) display panels use organic materials to make light-emitting devices and use thin-film transistors (TFT) to build pixel circuits. Pixels are arranged in an array, and the display panel is refreshed in a row-by-row scanning manner. After the low-temperature polycrystalline oxide (LTPO) technology entered mass production, AMOLED display technology was further upgraded. Based on the LTPO technology, a refresh rate control technology for display panels was developed, that is, the display panel is divided into multiple display areas, and the refresh rate of each display area is different, which is called partition multi-frequency technology. This technology will determine the actual refresh rate required for each display area based on the actual display content. Display areas that do not require high-frequency refresh will be reduced to low-frequency refresh, thereby reducing the power consumption of the display panel.

[0084] However, in the related art, pixels in the same row of a display panel are controlled by a scan signal on the same scan line, which results in the display panel being unable to be partitioned and displayed according to different columns, and thus the performance of current OLED display products needs to be improved.

[0085] To solve the above problems, the embodiments of the present application provide a display panel and a driving method thereof, and a display module. The embodiments of the display panel and a driving method thereof, and the display module will be described below in conjunction with the accompanying drawings.

[0086] Then, the display panel provided by the embodiment of the present application is introduced.

[0087] like Figure 1As shown, the display panel 100 provided in the embodiment of the present application may include at least one first pixel circuit 10a. In the case where the display panel 100 includes one first pixel circuit 10a, the display panel may also include at least one second pixel circuit 10b. The at least one first pixel circuit 10a and the at least one second pixel circuit 10b may be arranged in an array.

[0088] The at least one second pixel circuit 10 b may be a 2T1C pixel circuit, a 7T1C pixel circuit, an 8T1C pixel circuit, etc. in the related art, and the number of the second pixel circuits is not limited herein.

[0089] like Figures 2 to 4 As shown, the first pixel circuit 10a includes a first type transistor 11 and a driving transistor T1. The first electrode of the first type transistor 11 is connected to the gate of the driving transistor T1, and the second electrode of the first type transistor 11 is used to transmit a data signal.

[0090] In some embodiments, the driving transistor T1 may be a P-type transistor. Of course, in other embodiments, the driving transistor T1 may also be an N-type transistor, which is not limited here.

[0091] Exemplarily, the second electrode of the driving transistor T1 is connected to the first power line ELVDD, wherein the first power line ELVDD can be used to provide a positive polarity voltage.

[0092] It can be understood that when the voltage values ​​of two data signals continuously transmitted to the gate of the driving transistor T1 through the second electrode of the first type of transistor 11 are different, it can be considered that the gate signal of the driving transistor T1 is refreshed; when the voltage values ​​of two data signals continuously transmitted to the gate of the driving transistor T1 through the second electrode of the first type of transistor 11 are the same, it can be considered that the gate signal of the driving transistor T1 is not refreshed.

[0093] The first gate of the first type transistor 11 is connected to the first signal line CCl1, and the second gate of the first type transistor 11 is connected to the second signal line SCAN_N1. The first gate of the first type transistor 11 is used to adjust the threshold voltage (Vth) of the first type transistor 11 under the control of the signal on the first signal line CCl1. The second gate of the first type transistor 11 is used to be turned on or off under the control of the signal on the second signal line SCAN_N1.

[0094] Exemplarily, the second signal line SCAN_N1 may be a scan signal line in the related art. It should be noted that the first gate and the second gate of the first type of transistor 11 both have a control effect on the channel current of the first type of transistor 11. The embodiment of the present application is described by taking the first type of transistor 11 as an oxide thin film transistor as an example. Figure 5 to Figure 6 As shown, Figure 5The figure shows the corresponding relationship between the gate voltage VG and the channel current Id of the oxide thin film transistor when the source voltage of the oxide thin film transistor is 0V, the top gate (TG) voltage is 0V, and the bottom gate (BG) voltage is -10V to +10V. Figure 6 The corresponding relationship between the gate voltage VG and the channel current Id of the oxide thin film transistor is shown when the source voltage of the oxide thin film transistor is 0V, the top gate voltage is 5V, and the bottom gate voltage is -20V to +10V. Figure 5 and Figure 6 It can be seen that the voltage of the top gate has a translation effect on the device curve of the oxide thin film transistor, that is, it has a translation effect on the threshold voltage of the oxide thin film transistor.

[0095] In the first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off.

[0096] Exemplarily, in the first state, the first signal line transmits a first voltage signal to the first gate of the first type transistor 11. At this time, regardless of whether the second signal line transmits an on level or an off level to the second gate of the first type transistor 11, the first type transistor 11 is turned off.

[0097] In the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line.

[0098] Exemplarily, in the second state, the first signal line transmits a second voltage signal to the first gate of the first type transistor 11, and when the second signal line transmits a turn-on level to the second gate of the first type transistor 11, the first type transistor 11 is turned on; or, when the second signal line transmits a turn-off level to the second gate of the first type transistor 11, the first type transistor 11 is turned off.

[0099] According to the display panel provided by the embodiment of the present application, on the one hand, by connecting the first gate of the first type of transistor to the first signal line, in the first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off, so that the voltage data of the first pixel circuit is not refreshed, thereby achieving low refresh rate display.

[0100] On the other hand, by connecting the second gate of the first type of transistor to the second signal line, in the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line. For example, when the first type of transistor is turned on by the voltage control of the second signal line, the data voltage of the first pixel circuit can be refreshed; for another example, when the first type of transistor is turned off by the voltage control of the second signal line, the data voltage of the first pixel circuit can be not refreshed. In other words, the embodiment of the present application can control the data voltage of the first pixel circuit to be refreshed or not, thereby providing the possibility for the display panel to perform zoned and frequency-refresh display according to different columns in the same period, which is conducive to improving the performance of the display panel.

[0101] In some embodiments, Figure 7 As shown, there are multiple first pixel circuits 10a, and at least two first pixel circuits 10a are located in the same row.

[0102] In this embodiment, at least two first pixel circuits are located in the same row, that is, at least two first pixel circuits in the same row can independently control their own data voltage to refresh or not refresh, thereby realizing zoned and frequency-controlled refresh display according to different columns in the same period.

[0103] It should be noted that, when there are multiple first pixel circuits 10a, the display panel may further include at least one second pixel circuit 10b.

[0104] In other embodiments, Figure 8 As shown, the pixel circuits included in the display panel are all first pixel circuits 10a.

[0105] That is, the display panel only includes the first pixel circuit 10a, but not the second pixel circuit 10b. In this way, all pixel circuits in the entire display panel can independently control their own data voltages to refresh or not refresh, thereby further realizing zoned and frequency refresh display according to different columns in the same period.

[0106] In some embodiments, Fig. 9 As shown, the second gates of the first pixel circuits 10a in the same row are all connected to the second signal line SCAN_N1, and the first gates of the first pixel circuits 10a in the same column are all connected to the first signal line CC11.

[0107] In this embodiment, the second gates of the first pixel circuits in the same row are all connected to the second signal line, which can reduce the number of second signal lines and thus save the cost of the display panel; similarly, the first gates of the first pixel circuits in the same column are all connected to the first signal line, which can reduce the number of first signal lines and thus save the cost of the display panel.

[0108] In some embodiments, in the first state, the refresh rate of the signal on the second signal line connected to the first pixel circuit is equal to the refresh rate of the signal on the second signal line connected to the first pixel circuit in the second state. In this way, the timing of the signal on the second signal line in the display panel can be simplified.

[0109] Exemplarily, in the first state, the refresh rate of the signal on the second signal line connected to the first pixel circuit and in the second state, the refresh rate of the signal on the second signal line connected to the first pixel circuit can both be the maximum refresh rate of the display panel.

[0110] Exemplarily, the gate driving circuit (GIP) that provides a signal to the second signal line may be a gate driving circuit in the related art.

[0111] In some embodiments, the first type of transistor 11 includes a threshold compensation transistor T2, and the threshold compensation transistor T2 is a dual-gate transistor. The dual-gate transistor may be a transistor including two gates, a bottom gate and a top gate.

[0112] In some embodiments, the first gate of the threshold compensation transistor T2 is a top gate, and the second gate of the threshold compensation transistor T2 is a bottom gate; or, the first gate of the threshold compensation transistor T2 is a bottom gate, and the second gate of the threshold compensation transistor T2 is a top gate.

[0113] As an example, Figure 3 As shown, the first gate of the threshold compensation transistor T2 is a top gate, and the second gate of the threshold compensation transistor T2 is a bottom gate. In this way, the signal on the first signal line CC11 has a strong translation effect on the threshold voltage of the threshold compensation transistor T2.

[0114] As another example, Figure 2 As shown, the first gate of the threshold compensation transistor T2 is a bottom gate, and the second gate of the threshold compensation transistor T2 is a top gate. In this way, compared with the first gate of the threshold compensation transistor T2 being a bottom gate and the second gate of the threshold compensation transistor T2 being a top gate, the threshold voltage shifting effect of the signal on the first signal line CC11 on the threshold compensation transistor T2 becomes weaker, so that the threshold voltage shift amount of the threshold compensation transistor T2 becomes smaller, thereby increasing the voltage value of the signal on the second signal line SCAN_N1.

[0115] In some embodiments, the threshold compensation transistor T2 is an N-type transistor. Of course, in some other embodiments, the threshold compensation transistor T2 may also be a P-type transistor, which is not limited here.

[0116] In some embodiments, the first electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T1, the second electrode of the threshold compensation transistor T2 is connected to the first electrode of the driving transistor T1, the first gate of the threshold compensation transistor T2 is connected to the first signal line CCl1, and the second gate of the threshold compensation transistor is connected to the second signal line SCAN_N1. The threshold compensation transistor T2 can be used to perform threshold compensation on the driving transistor T1 under the control of the signals on the first signal line CCl1 and the second signal line SCAN_N1.

[0117] Exemplarily, when the control signal on the first control signal line CCl1 in the first pixel circuit 10a is a first voltage signal, regardless of whether the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is at an on level or an off level, the threshold compensation transistor T2 in the first pixel circuit 10a is turned off, so that a low refresh rate display of the display panel can be achieved.

[0118] Exemplarily, when the signal on the first signal line CCl1 in the first pixel circuit 10a is the second voltage signal, and the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is at the on level, the threshold compensation transistor T2 in the first pixel circuit 10a is turned on, thereby performing threshold compensation on the driving transistor T1; when the signal on the first signal line CCl1 in the first pixel circuit 10a is the second voltage signal, and the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is at the off level, the threshold compensation transistor T2 in the first pixel circuit 10a is turned off, so that a high refresh rate display of the display panel can be achieved. The high refresh rate may be the maximum refresh rate or the preset refresh rate of the display panel.

[0119] In some embodiments, the first pixel circuit 10a further includes a first initialization transistor T3, a third gate of the first initialization transistor T3 is connected to the third signal line CCl2, a fourth gate of the first initialization transistor T3 is connected to the fourth signal line SCAN_N2, a first electrode of the first initialization transistor T3 is connected to the gate of the driving transistor T1, and a second electrode of the first initialization transistor T3 is connected to the first initialization signal line Vref1;

[0120] In the first state, the third signal line CC12 transmits a third voltage signal, and the first initialization transistor T3 is turned off;

[0121] In the second state, the third signal line CC12 transmits a fourth voltage signal, and the first initialization transistor T3 is turned on or off by the voltage control of the fourth signal line SCAN_N2.

[0122] Exemplarily, when the signal on the third signal line CCl2 in the first pixel circuit 10a is a third voltage signal, regardless of whether the signal on the fourth signal line SCAN_N2 in the first pixel circuit 10a is at an on level or an off level, the first initialization transistor T3 in the first pixel circuit 10a is turned off, so that a low refresh rate display of the display panel can be achieved.

[0123] Exemplarily, when the signal on the third signal line CCl2 in the first pixel circuit 10a is a fourth voltage signal and the signal on the fourth signal line SCAN_N2 in the first pixel circuit 10a is at an on-level, the first initialization transistor T3 in the first pixel circuit 10a is turned on, thereby performing threshold compensation on the driving transistor T1; when the signal on the third signal line CCl2 in the first pixel circuit 10a is a fourth voltage signal and the signal on the fourth signal line SCAN_N2 in the first pixel circuit 10a is at an off-level, the first initialization transistor T3 in the first pixel circuit 10a is turned off, so that a high refresh rate display of the display panel can be achieved.

[0124] In some embodiments, the first initialization transistor is a dual-gate transistor.

[0125] In some embodiments, the third gate of the first initialization transistor is a top gate, and the fourth gate of the first initialization transistor is a bottom gate; or, the third gate of the first initialization transistor is a bottom gate, and the fourth gate of the first initialization transistor is a top gate.

[0126] As an example, Figure 3 As shown, the third gate of the first initialization transistor T3 is a top gate, and the fourth gate of the first initialization transistor T3 is a bottom gate. In this way, the signal on the third signal line CC12 has a strong translation effect on the threshold voltage of the first initialization transistor T3.

[0127] As another example, Figure 2 As shown, the third gate of the first initialization transistor T3 is a bottom gate, and the fourth gate of the first initialization transistor T3 is a top gate. In this way, compared with the third gate of the first initialization transistor T3 being a top gate and the fourth gate of the first initialization transistor T3 being a bottom gate, the signal on the third signal line CC12 has a weaker effect on the threshold voltage shift of the first initialization transistor T3, so that the threshold voltage shift amount of the first initialization transistor T3 becomes smaller, thereby increasing the voltage value of the signal on the fourth signal line SCAN_N2.

[0128] In some embodiments, the first initialization transistor T3 is an N-type transistor. Of course, in some other embodiments, the first initialization transistor T3 may also be a P-type transistor, which is not limited here.

[0129] In some examples, such as Fig. 9 As shown, the fourth gates of the first pixel circuits 10a in the same row are all connected to the fourth signal line SCAN_N2, and the third gates of the first pixel circuits 10a in the same column are all connected to the third signal line CCl2.

[0130] In this embodiment, the fourth gates of the first pixel circuits in the same row are all connected to the fourth signal line, which can reduce the number of fourth signal lines and thus save the cost of the display panel; similarly, the third gates of the first pixel circuits in the same column are all connected to the third signal line, which can reduce the number of third signal lines and thus save the cost of the display panel.

[0131] In some embodiments, in the first state, the refresh rate of the signal on the fourth signal line connected to the first pixel circuit is equal to the refresh rate of the signal on the fourth signal line connected to the first pixel circuit in the second state. In this way, the timing of the signal on the fourth signal line in the display panel can be simplified.

[0132] Exemplarily, in the first state, the refresh rate of the signal on the fourth signal line connected to the first pixel circuit and in the second state, the refresh rate of the signal on the fourth signal line connected to the first pixel circuit can both be the maximum refresh rate of the display panel.

[0133] Exemplarily, the gate driving circuit (GIP) that provides a signal to the fourth signal line may be a gate driving circuit in the related art.

[0134] In some embodiments, Figure 3 As shown, the first signal line CCl1 is multiplexed into the third signal line CCl2. In this way, the number of control signal lines in the display panel can be reduced, thereby reducing the cost of the display panel and improving the resolution of the display panel. Figure 4 As shown, the first type of transistor 11 may include a data writing transistor T8.

[0135] The first gate of the data writing transistor T8 is connected to the first signal line CCl1, the second gate of the data writing transistor T8 is connected to the second signal line SCAN_N1, the first electrode of the data writing transistor T8 is connected to the data line Data, and the second electrode of the data writing transistor T8 is connected to the gate of the driving transistor T1. The data writing transistor T8 is used to write the data signal on the data line Data into the gate of the driving transistor T1 under the control of the scanning signal on the second signal line SCAN_N1 and the signal on the first signal line CCl1.

[0136] Exemplarily, when the signal on the first signal line CCl1 in the first pixel circuit 10a is a first voltage signal, no matter the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is an on level or an off level, the data write transistor T8 in the first pixel circuit 10a is turned off. Exemplarily, when the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is an on level and the signal on the first signal line CCl1 in the first pixel circuit 10a is a second voltage signal, the data write transistor T8 in the first pixel circuit 10a is turned on, and then the data signal on the data line Data is written into the gate of the driving transistor T1; when the signal on the second signal line SCAN_N1 in the first pixel circuit 10a is an off level and the signal on the first signal line CCl1 in the first pixel circuit 10a is a second voltage signal, the data write transistor T8 in the first pixel circuit 10a is turned off.

[0137] The following takes the example that the threshold compensation transistor T2 and the first initialization transistor T3 are both N-type transistors to illustrate the partition display principle of the display panel provided by the embodiment of the present application. Fig.10 As shown, the display panel includes a first display area AA1 and a second display area AA2, and the refresh rate of the first display area AA1 is greater than the refresh rate of the second display area AA2. Pixel A is located in the first display area AA1, and pixels B, C, and D are located in the second display area AA2. Pixel A and pixel C are located in the same row, pixel B and pixel D are in the same row, pixel A and pixel B are located in the same column, and pixel C and pixel D are located in the same column. When the row-by-row scanning signal scans the row where pixel A is located and the row where pixel B is located, the working timing diagram of the display panel is shown in FIG11.

[0138] For details, please refer to Figure 2 , Fig. 9 and Fig.11, taking the refresh rate of the display panel as 60 Hz as an example, when the row where pixel A is located is scanned, the signals on the first signal line CCl1(n) and the third signal line CC12(n) of pixel A are high level, and the threshold compensation transistor T2 and the first initialization transistor T3 of the first pixel circuit 10a in pixel A can be turned on or off under the control of the signals on the second signal line Scan_N1(A) and the fourth signal line SCAN_N2(A); the signal on the signal line CCl(9) of pixel C is low level, no matter whether the signals on the second signal line and the fourth signal line of pixel C are high level or low level, the threshold compensation transistor T2 and the first initialization transistor T3 of the first pixel circuit 10a in pixel C are turned off. When the row where pixel B is located is scanned, the signals on the first signal line CCl1(n) and the third signal line CC12(n) of pixel B are at a low level, and the threshold compensation transistor T2 and the first initialization transistor T3 of the first pixel circuit 10a in pixel B are turned off regardless of whether the signals on the second signal line Scan_N1(B) and the fourth signal line SCAN_N2(B) of pixel B are at a high level or a low level; the signals on the first signal line CCl1(9) and the third signal line CC12(9) of pixel D are at a low level, and the threshold compensation transistor T2 and the first initialization transistor T3 of the first pixel circuit of pixel D are turned off regardless of whether the signals on the second signal line and the fourth signal line of pixel D are at a high level or a low level.

[0139] It can be seen that according to the display panel provided by the embodiment of the present application, by adding the first signal line and the third signal line, and replacing the three-terminal thin film transistor in the related art with a four-terminal thin film transistor, the first signal line and the third signal line can be used to control the data voltage of the first pixel circuit to be refreshed or not refreshed, thereby realizing the partitioned and frequency display of any row and any column of pixels, and realizing the partition setting with any partition position, any partition size, and adjustable signals on the first signal line and the third signal line. In addition, the display panel provided by the embodiment of the present application only adds the first signal line and the third signal line, and does not need to add other transistors, which is conducive to reducing the cost of the display panel and improving the resolution of the display panel.

[0140] In some embodiments, Figure 2 As shown, the first type of transistor 11 includes a threshold compensation transistor T2, the threshold compensation transistor T2 and the first initialization transistor T3 are both N-type transistors, the voltage value of the signal on the second signal line SCAN_N1 and the fourth signal line SCAN_N2 when it is at the on level is VGH1, the voltage value of the signal on the second signal line SCAN_N1 and the fourth signal line SCAN_N2 when it is at the off level is VGL1, 7V≤VGH1-VGL1≤11V.

[0141] In this embodiment, by setting 7V≤VGH1-VGL1≤11V, the switching speed of the threshold compensation transistor T2 and the first initialization transistor T3 is improved.

[0142] In some embodiments, VGH1 - VGL1 = 10V.

[0143] In this embodiment, by setting VGH1 - VGL1 = 10V, it is beneficial to take into account the switching speed of the threshold compensation transistor T2 and the first initialization transistor T3 and the power consumption of the display panel.

[0144] In some examples, -4V≤VGH1≤-2V, -13V≤VGL1≤-11V.

[0145] Exemplarily, VGH1 = -3V, VGL1 = -12V.

[0146] In some embodiments, the voltage values ​​of the first voltage signal and the third voltage signal are both VGL2, the voltage values ​​of the second voltage signal and the fourth voltage signal are both VGH2, and VGH2-VGL2≤VGH1-VGL1.

[0147] The first voltage signal and the second signal can be used to adjust the threshold voltage of the threshold compensation transistor T2, and the third voltage signal and the fourth voltage signal can be used to adjust the threshold voltage of the first initialization transistor T3. In this embodiment, by setting VGH2-VGL2≤VGH1-VGL1, it is beneficial to reasonably shift the threshold voltages of the threshold compensation transistor T2 and the first initialization transistor T3.

[0148] In some embodiments, VGH2 - VGL2 = 5V.

[0149] Exemplarily, VGH2=5V, VGL2=0V.

[0150] In some embodiments, 7V≤VGH2-VGH1≤9V, 11V≤VGL2-VGL1≤13V.

[0151] Exemplarily, VGH2 - VGH1 = 8V, VGL2 - VGL1 = 12V.

[0152] For ease of understanding, take VGH2 = 5V, VGL2 = 0V, VGH1 = -3V, VGL1 = -12V, and the threshold compensation transistor and the first initialization transistor are both N-type transistors as an example for explanation. Figure 5As shown, when VGH2 = 5V, the threshold voltages of the threshold compensation transistor and the first initialization transistor are both about -10V, when VGH1 = -3V, the threshold compensation transistor and the first initialization transistor are both turned on, and when VGL1 = -12V, the threshold compensation transistor and the first initialization transistor are both turned off. Figure 6 As shown, when VGH2 = 0V, the threshold voltages of the threshold compensation transistor and the first initialization transistor are both about 0V, and when VGH1 = -3V or VGL1 = -12V, the threshold compensation transistor and the first initialization transistor are both turned off. The above values ​​are only used for examples and are not used to limit the present application.

[0153] In some embodiments, Fig. 9 As shown, the display panel includes a plurality of data lines Data, and the first signal line CCl1 and the third signal line CCl2 are both arranged in parallel with the data line Data. That is, the first signal line CCl1 is arranged in parallel with the data line Data, and the third signal line CCl2 is arranged in parallel with the data line Data, which can improve the signal crosstalk problem between the first signal line CC1 and the data line Data, and can improve the signal crosstalk problem between the third signal line CCl2 and the data line Data.

[0154] In some examples, the first signal line CCl1, the third signal line CCl2 and the data line Data are all located in the same film layer, so that it is easier to arrange the first signal line CCl1 and the data line Data in parallel, and easier to arrange the third signal line CCl2 and the data line Data in parallel.

[0155] like Fig.12 As shown, in the thickness direction Z of the display panel, a substrate 01 and an auxiliary film layer M0, a first metal film layer M1, a second metal film layer M2 and a third metal film layer M3 are stacked. As an example, the first signal line CCl1, the third signal line CCl2 and the data line Data can be located in the auxiliary film layer M0. As another example, the first signal line CCl1, the third signal line CCl2 and the data line Data can be located in the third metal film layer M3.

[0156] In some embodiments, Figure 2 and Figure 3 As shown, the first pixel circuit 10a further includes a data writing transistor T4, a light emitting control transistor and a second initialization transistor T7.

[0157] A gate of the data writing transistor T4 is electrically connected to the fifth signal line SCAN_N3 , a first electrode of the data writing transistor T4 is electrically connected to the data line Data, and a second electrode of the data writing transistor T4 is connected to the second electrode of the driving transistor T1 .

[0158] The data writing transistor T4 may be used to write the data signal on the data line Data into the driving transistor T1 under the control of the signal on the fifth signal line SCAN_N3 .

[0159] The light emission control transistor includes a first light emission control transistor T5 and a second light emission control transistor T6, the gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6 are both connected to the light emission control signal line EM, the first electrode of the first light emission control transistor T5 is connected to the first power line ELVDD, the second electrode of the first light emission control transistor T5 is connected to the second electrode of the driving transistor T1, the first electrode of the second light emission control transistor T6 is connected to the first electrode of the driving transistor T1, and the second electrode of the second light emission control transistor T6 is connected to the light emitting element D. The light emitting element D can also be electrically connected to the second power line ELVSS, and the second power line ELVSS can be used to provide a negative polarity voltage.

[0160] The first light emission control transistor T5 and the second light emission control transistor T6 are used to control the light emitting element D to emit light under the control of the light emission control signal on the light emission control signal line EM.

[0161] The gate of the second initialization transistor T7 is electrically connected to the sixth signal line SCAN_N4 , the first electrode of the second initialization transistor T7 is connected to the second initialization signal line Vref2 , and the second electrode of the second initialization transistor T7 is connected to the light emitting element D.

[0162] The second initialization transistor T7 is used to transmit the initialization signal on the second initialization signal line Vref2 to the anode of the light emitting element D under the control of the scan signal on the sixth signal line SCAN_N4, so as to initialize the anode of the light emitting element D.

[0163] The storage capacitor Cst is connected to the first power line ELVDD and the gate of the driving transistor T1.

[0164] The storage capacitor Cst can be used to maintain the potential of the gate of the driving transistor T1 .

[0165] It can be understood that in the first state, when the signals on the first signal line CCl1 and the third signal line CCl2 in the first pixel circuit 10a are at the cut-off level, the threshold compensation transistor T2 and the first initialization transistor T3 in the first pixel circuit 10a are both turned off, and the voltage value of the data signal on the data line Data will not be transmitted to the gate of the driving transistor T1, and thus the storage capacitor Cst will not be charged.

[0166] Based on the same inventive concept, an embodiment of the present application further provides a method for driving a display panel. The method for driving a display panel provided by an embodiment of the present application is described below in conjunction with the accompanying drawings.

[0167] The display panel includes at least one first pixel circuit, the first pixel circuit including a first type transistor and a driving transistor;

[0168] The first electrode of the first type of transistor is connected to the gate of the driving transistor, the second electrode of the first type of transistor is used to transmit the data signal, the first gate of the first type of transistor is connected to the first signal line, and the second gate of the first type of transistor is connected to the second signal line.

[0169] like Fig.13 As shown, the driving method of the display panel provided in the embodiment of the present application includes:

[0170] Drive methods include:

[0171] S1310. In a first state, control the first signal line to transmit a first voltage signal to turn off the first type of transistor.

[0172] S1320. In the second state, control the first signal line to transmit a second voltage signal, so that the first type of transistor is turned on or off by the voltage control of the second signal line.

[0173] According to the driving method of the display panel provided in the embodiment of the present application, on the one hand, by connecting the first gate of the first type of transistor to the first signal line, in the first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off, so that the voltage data of the first pixel circuit is not refreshed, thereby achieving low refresh rate display.

[0174] On the other hand, by connecting the second gate of the first type of transistor to the second signal line, in the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line. For example, when the first type of transistor is turned on by the voltage control of the second signal line, the data voltage of the first pixel circuit can be refreshed; for another example, when the first type of transistor is turned off by the voltage control of the second signal line, the data voltage of the first pixel circuit can be not refreshed. In other words, the embodiment of the present application can control the data voltage of the first pixel circuit to be refreshed or not, thereby providing the possibility for the display panel to perform zoned and frequency-refresh display according to different columns in the same period, which is conducive to improving the performance of the display panel.

[0175] The driving method of the display panel provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0176] Based on the same inventive concept, the embodiment of the present application further provides a display module, and the display module provided by the embodiment of the present application is described below with reference to the accompanying drawings.

[0177] like Fig.14 As shown, the display module 1000 provided in the embodiment of the present application includes the display panel 100 in any of the above embodiments.

[0178] In some embodiments, the display panel includes a plurality of display areas, and the display module further includes a timing control module;

[0179] The display panel or display module further includes a level conversion circuit, and the level conversion circuit is connected to the timing control module;

[0180] The timing control module is used to parse the display area information, obtain parsed data, and transmit the parsed data line by line to the shift register when receiving the display area information, wherein the display area information includes at least one of the number of display areas, position information, and refresh rate;

[0181] The level conversion circuit is used for converting the parsed data into a first voltage signal or a second voltage signal, and transmitting the first voltage signal or the second voltage signal to the first signal line.

[0182] For example, Fig.15 As shown, the embodiment of the present application is illustrated by taking the display module 1000 including the timing control module 1410 and the level conversion circuit 1430 as an example.

[0183] In the embodiment of the present application, through the level conversion circuit, the display area information can be parsed in the timing control module to obtain parsed data, and the parsed data can be transmitted to the level conversion circuit. The level conversion circuit can convert the parsed data into a first voltage signal or a second voltage signal, and transmit the first voltage signal or the second voltage signal to the first signal line, thereby providing a basis for the second gate of the first type of transistor in the first pixel circuit to access the first voltage signal or the second voltage signal. By connecting the second gate of the first type of transistor to the second signal line, in the second state, the first signal line transmits the second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line. For example, when the first type of transistor is turned on by the voltage control of the second signal line, the data voltage of the first pixel circuit can be refreshed; for another example, when the first type of transistor is turned off by the voltage control of the second signal line, the data voltage of the first pixel circuit can be not refreshed. In other words, the embodiment of the present application can control the data voltage of the first pixel circuit to be refreshed or not, thereby providing the possibility for the display panel to perform zone-by-zone frequency refresh display according to different columns in the same period, which is conducive to improving the performance of the display panel.

[0184] In the embodiment of the present application, the multiple display areas included in the display panel can be divided into rows, columns, or both rows and columns, which is not limited here.

[0185] In some embodiments, the display panel or display module further includes a shift register, the shift register is connected to the level conversion circuit and the timing control module, and the timing control module is further used to transmit the parsed data to the shift register line by line;

[0186] The shift register is used to transmit the parsed data to the level conversion circuit in parallel when receiving the parsed data.

[0187] It should be noted that transmitting the parsed data to the level conversion circuit in parallel may be transmitting the data included in the parsed data through multiple data channels at the same time, which can improve the transmission efficiency of the parsed data.

[0188] For example, Fig.15 As shown, the embodiment of the present application is illustrated by taking the display module 1000 including a timing control module 1410 , a shift register 1420 and a level conversion circuit 1430 as an example.

[0189] In the embodiment of the present application, the shift register 1420 and the level conversion circuit 1430 may both be located on the display panel, or may both be located on a flexible printed circuit board (FPC) or a printed circuit board (PCB) in the display module 1000, which is not limited here.

[0190] Taking an electronic device including a display module as an example, when the electronic device is in use, an application processor (AP) or a host in the electronic device can obtain the current display information of the electronic device. The current display information may be the content information currently displayed by the electronic device. For example, the current display information may include display types, such as video, image, and text interface. The application processor or the host may generate display area information according to the current display information and send the display area information to the timing control module.

[0191] The display area information may include at least one of the number of display areas, position information, and refresh rate. For example, the position information may be the coordinates of each display area. Fig.17As shown, the display panel may include a first display area AA3 and a second display area AA4, the first display area AA3 includes a first sub-display area AA31 and a second sub-display area AA32, the coordinates of the first sub-display area AA31 are D11 (x11, y11), D12 (x12, y12), D13 (x13, y13), and D14 (x14, y14); the coordinates of the second sub-display area AA32 are D21 (x21, y21), D22 (x22, y22), D23 (x23, y23), and D24 (x24, y24), and the other area except the first display area AA3 is the second display area AA4.

[0192] The refresh rate may be the refresh rate of each display area. For example, the refresh rate of the first sub-display area AA31 and the second sub-display area AA32 is 60 Hz, and the refresh rate of the second display area AA4 is 120 Hz.

[0193] In some embodiments, Fig.18 As shown, the multiple display areas include a first display area AA3 and a second display area AA4, and the parsed data includes multiple binary digits, each of which is used to represent the state of a pixel; the first display area AA3 includes a binary number "0", and the second display area AA4 includes a binary number "1", or the first display area AA3 includes a binary number "1", and the second display area AA4 includes a binary number "1". In this way, the display of different pixel circuits in the column direction can be controlled by changing the value of the parsed data in the shift register, thereby realizing the partitioning of the display panel in the column direction.

[0194] For example, a "1" in a binary number may be used to indicate that the refresh rate of the corresponding pixel is a high refresh rate, and a "0" in a binary number may be used to indicate that the refresh rate of the corresponding pixel is a low refresh rate.

[0195] As an example, Fig.18 As shown, the first display area AA3 includes a first sub-display area AA31 and a second sub-display area AA32, the first sub-display area AA31 and the second sub-display area AA32 include a binary number "1", and the second display area AA4 includes a binary number "0". That is, the first display area AA3 is a display area with a high refresh rate, and the second display area AA4 is a display area with a low refresh rate.

[0196] As another example, the first display area AA3 includes a binary number "0", and the second display area AA4 includes a binary number "1". That is, the first display area AA3 is a display area with a low refresh rate, and the second display area AA4 is a display area with a high refresh rate.

[0197] In some examples, shift register 1420 may also store parsed data.

[0198] In some embodiments, the number of binary digits included in the parsed data is equal to the number of pixels included in the display panel. The number of pixels included in the display panel is also the resolution of the display panel.

[0199] In some examples, the level conversion circuit 1430 may be connected to the first signal line. The level conversion circuit 1430 may be used to convert the parsed data into a first voltage signal and transmit the first voltage signal to the first signal line, or convert the parsed data into a second voltage signal and transmit the second voltage signal to the first signal line.

[0200] In other examples, the level conversion circuit 1430 may be connected to the third signal line. The level conversion circuit 1430 may be used to convert the parsed data into a third voltage signal and transmit the third voltage signal to the third signal line, or convert the parsed data into a fourth voltage signal and transmit the fourth voltage signal to the third signal line. As an example, Fig.19 As shown, taking the display panel including the first display area AA3 and the second display area AA4, the refresh rate of the first display area AA3 is greater than the refresh rate of the second display area AA4, the first display area AA3 includes the second sub-display area AA32, the top gate of the first type of transistor is connected to the first signal line, and the bottom gate of the first type of transistor is connected to the second signal line as an example, Fig.17 The red line a in the figure indicates the row position where the current scanning action of the display panel is located. After each row of pixels is scanned, the value of the shift register is updated once according to the upstream information. The upstream information can be data or signals input into the electronic device. When the current scanning row is in the second display area AA4, the value of the shift register 1420 is all "0" in the binary number, and the first type of transistor in the first pixel circuit in the second display area AA4 is turned off; when the current scanning row is in both the second display area AA4 and the second sub-display area AA32, the first type of transistor in the first pixel circuit in the second display area AA4 is turned off, and the first type of transistor in the first pixel circuit in the second sub-display area AA32 is turned on. Among them, the value of the shift register 1420 determines the voltage of the top gate of the first type of transistor in the pixel at the row position where the current scanning action is located. Exemplarily, the value of the shift register 1420 is "1" in the binary number, indicating that the voltage of the top gate of the first type of transistor is the first voltage signal, and the value of the shift register 1420 is "0" in the binary number, indicating that the voltage of the top gate of the first type of transistor is the second voltage signal.

[0201] As another example, Fig. 20As shown, taking the first display area AA3 and the second display area AA4 of the display panel, the refresh rate of the first display area AA3 is greater than the refresh rate of the second display area AA4, the first display area AA3 includes the first sub-display area AA31 and the second sub-display area AA32, the top gate of the first type of transistor is connected to the first signal line, and the bottom gate of the first type of transistor is connected to the second signal line as an example, Fig. 20 The red line a in the figure indicates the row position of the current scanning action of the display panel. After each row of pixels is scanned, the value of the shift register 1420 is updated once according to the upstream information. When the current scanning row is in the second display area AA4, the value of the shift register is all "0" in the binary number, and the first type of transistors of the pixel circuit in the second display area AA4 are turned off; when the current scanning row is in the first sub-display area AA31, the second sub-display area AA32 and the second display area AA4, the first type of transistors of the first pixel circuit in the second display area AA4 are turned off, and the first type of transistors of the first pixel circuit in the first sub-display area AA31 and the second sub-display area AA32 are turned on.

[0202] In some examples, the display module may further include a driving chip and a gate driving circuit. Both the driving chip and the gate driving circuit may be electrically connected to the timing control module.

[0203] The display module provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display module, or other display module with a display function, and the present application does not impose any specific restrictions on this.

[0204] The display module provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0205] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are disconnected. For a P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0206] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: comprising at least one first pixel circuit, wherein the first pixel circuit comprises a first type transistor and a driving transistor; The first electrode of the first type of transistor is connected to the gate of the driving transistor, the second electrode of the first type of transistor is used to transmit a data signal, the first gate of the first type of transistor is connected to a first signal line, and the second gate of the first type of transistor is connected to a second signal line; In a first state, the first signal line transmits a first voltage signal, and the first type of transistor is turned off; In the second state, the first signal line transmits a second voltage signal, and the first type of transistor is turned on or off by the voltage control of the second signal line.

2. The display panel according to claim 1, characterized in that: There are a plurality of first pixel circuits, and at least two of the first pixel circuits are located in the same row; Preferably, all pixel circuits included in the display panel are the first pixel circuits; Preferably, the second gates of the first pixel circuits in the same row are all connected to the second signal line, and the first gates of the first pixel circuits in the same column are all connected to the first signal line; Preferably, in the first state, a refresh rate of a signal on the second signal line connected to the first pixel circuit is equal to a refresh rate of a signal on the second signal line connected to the first pixel circuit in the second state.

3. The display panel according to claim 1, characterized in that: The first type of transistors includes a threshold compensation transistor, wherein the threshold compensation transistor is a dual-gate transistor, The first gate of the threshold compensation transistor is a top gate, and the second gate of the threshold compensation transistor is a bottom gate; or the first gate of the threshold compensation transistor is a bottom gate, and the second gate of the threshold compensation transistor is a top gate; Preferably, the threshold compensation transistor is an N-type transistor; Preferably, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, the second electrode of the threshold compensation transistor is connected to the first electrode of the driving transistor, the first gate of the threshold compensation transistor is connected to the first signal line, and the second gate of the threshold compensation transistor is connected to the second signal line.

4. The display panel according to claim 1, characterized in that: The first pixel circuit further includes a first initialization transistor, a third gate of the first initialization transistor is connected to a third signal line, a fourth gate of the first initialization transistor is connected to a fourth signal line, a first electrode of the first initialization transistor is connected to the gate of the driving transistor, and a second electrode of the first initialization transistor is connected to the first initialization signal line; In the first state, the third signal line transmits a third voltage signal, and the first initialization transistor is turned off; In the second state, the third signal line transmits a fourth voltage signal, and the first initialization transistor is turned on or off by the voltage control of the fourth signal line; Preferably, the fourth gates of the first pixel circuits in the same row are all connected to the fourth signal line, and the third gates of the first pixel circuits in the same column are all connected to the third signal line; Preferably, the first initialization transistor is a dual-gate transistor; Preferably, the third gate of the first initialization transistor is a top gate, and the fourth gate of the first initialization transistor is a bottom gate; or, the third gate of the first initialization transistor is a bottom gate, and the fourth gate of the first initialization transistor is a top gate; Preferably, the first initialization transistor is an N-type transistor; Preferably, in the first state, a refresh rate of a signal on the fourth signal line connected to the first pixel circuit is equal to a refresh rate of a signal on the fourth signal line connected to the first pixel circuit in the second state.

5. The display panel according to claim 4, characterized in that: The driving transistor is a P-type transistor; Preferably, the first type of transistors includes a threshold compensation transistor, and both the threshold compensation transistor and the first initialization transistor are N-type transistors; When the signals on the second signal line and the fourth signal line are at an on-level, the voltage value is VGH1; when the signals on the second signal line and the fourth signal line are at an off-level, the voltage value is VGL1, 7V≤VGH1-VGL1≤11V; Preferably, VGH1-VGL1=10V; Preferably, -4V≤VGH1≤-2V, -13V≤VGL1≤-11V; Preferably, the voltage values ​​of the first voltage signal and the third voltage signal are both VGL2, the voltage values ​​of the second voltage signal and the fourth voltage signal are both VGH2, and VGH2-VGL2≤VGH1-VGL1; Preferably, VGH2-VGL2=5V; Preferably, 7V≤VGH2-VGH1≤9V, 11V≤VGL2-VGL1≤13V; Preferably, VGH2 - VGH1 = 8V, VGL2 - VGL1 = 12V.

6. The display panel according to claim 4, characterized in that: The display panel comprises a plurality of data lines, and the first signal line and the third signal line are both arranged in parallel with the data lines; Preferably, the first signal line, the third signal line and the data line are all located in the same film layer.

7. The display panel according to claim 1, characterized in that: The first pixel circuit further includes a data writing transistor, a light emission control transistor, a second initialization transistor and a storage capacitor; The gate of the data writing transistor is connected to the fifth signal line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the second electrode of the driving transistor; The light-emitting control transistor includes a first light-emitting control transistor and a second light-emitting control transistor, the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control signal line, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the second electrode of the driving transistor, the first electrode of the second light-emitting control transistor is connected to the first electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting element; The gate of the second initialization transistor is connected to the sixth signal line, the first electrode of the second initialization transistor is connected to the second initialization signal line, and the second electrode of the second initialization transistor is connected to the light emitting element; The storage capacitor is connected to the first power line and the gate of the driving transistor.

8. A method for driving a display panel, characterized in that: The display panel includes at least one first pixel circuit, wherein the first pixel circuit includes a first type transistor and a driving transistor; The first electrode of the first type of transistor is connected to the gate of the driving transistor, the second electrode of the first type of transistor is used to transmit a data signal, the first gate of the first type of transistor is connected to a first signal line, and the second gate of the first type of transistor is connected to a second signal line; The driving method comprises: In a first state, controlling the first signal line to transmit a first voltage signal to turn off the first type of transistor; In the second state, the first signal line is controlled to transmit a second voltage signal, so that the first type of transistor is turned on or off by the voltage control of the second signal line.

9. A display module, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 7.

10. The display module according to claim 9, characterized in that: The display panel includes a plurality of display areas, and the display module also includes a timing control module; The display panel or the display module further includes a level conversion circuit, and the level conversion circuit is connected to the timing control module; The timing control module is used to parse the display area information, obtain parsed data, and transmit the parsed data line by line to the level conversion circuit when receiving the display area information, wherein the display area information includes at least one of the number, position information and refresh rate of the display area; The level conversion circuit is used for converting the parsed data into a first voltage signal or a second voltage signal, and transmitting the first voltage signal or the second voltage signal to the first signal line; Preferably, the display panel or the display module further comprises a shift register, the shift register is connected to both the level conversion circuit and the timing control module, and the timing control module is further used to transmit the parsed data to the shift register line by line; The shift register is used to transmit the parsed data to the level conversion circuit in parallel when receiving the parsed data; Preferably, the number of binary digits included in the parsed data is equal to the number of pixels included in the display panel.

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