Display device

Abstract

A display device may include: a display panel including a display area in which a plurality of pixels are disposed and a non-display area disposed around the display area; a light emission control driver configured to receive a first start signal and a first clock signal and provide a light emission control signal to the display panel; at least one scan driver configured to receive a second start signal and a second clock signal and provide a scan signal to the display panel; and a controller configured to control the display panel to operate individually in a refresh period or a hold period based on a refresh rate. The hold period may have a portion that may output each of the first start signal and the second start signal at a fixed voltage level. Each of the first clock signal and the second clock signal can be continuously switched in each of the refresh period and the hold period.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, for example, to a display device using a VRR (Variable Refresh Rate) mode in which operating conditions are changed based on operating frequency to improve operating stability in a high temperature or high humidity environment, but is not limited thereto. Background Art

[0002] A display device using a light emitting element such as an organic light emitting diode may operate at various operating frequencies.

[0003] Recently, as one of the various functions required in a display device, VRR (Variable Refresh Rate) is required. VRR mode is a technology in which a display device operates at a constant frequency and increases the refresh rate when high-speed operation is required. In VRR mode, the refresh rate is reduced when low power consumption or low-speed operation is required.

[0004] When operating at a low frequency for a long period of time, a signal pad defect may occur due to moisture penetration in a high temperature or high humidity environment, resulting in signal abnormality. Therefore, there is a need for a display device that performs stable operation even in a high temperature or high humidity environment.

[0005] The description of related art should not be regarded as prior art simply because it is mentioned in this section or is associated with this section. The description of related art includes information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the invention

[0006] An object of the present invention is to provide a display device using a VRR (Variable Refresh Rate) mode in which an operating condition is changed based on an operating frequency to improve operating stability in a high temperature or high humidity environment.

[0007] The purpose according to the present invention is not limited to the above-mentioned purpose. Other purposes and advantages according to the present invention that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments of the present invention. In addition, it will be easily understood that the purposes and advantages according to the present invention can be achieved by the methods shown in the claims or their combinations.

[0008] In order to achieve the above-mentioned purpose, a display device according to one aspect of the present invention includes: a display panel, the display panel including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a light-emitting control driver, the light-emitting control driver being configured to receive a first start signal and a first clock signal and provide a light-emitting control signal to the display panel; at least one scan driver, the scan driver being configured to receive a second start signal and a second clock signal and provide a scan signal to the display panel; and a controller, the controller being configured to control the display panel to operate separately in a refresh period or a holding period based on a refresh rate, wherein the holding period has a portion for outputting each of the first start signal and the second start signal at a fixed voltage level, wherein each of the first clock signal and the second clock signal is used to continuously switch in each of the refresh period and the holding period.

[0009] The display device according to the exemplary embodiment of the present invention controls each of a start signal and a clock signal applied to a gate driver so that the display device stably operates even in a high temperature or high humidity environment in a low speed operation.

[0010] The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

[0011] In addition to the above-described effects, specific effects of the present invention will be described together with specific details for implementing the present invention.

[0012] Additional features, advantages and aspects of the present invention are set forth in part in the following description, will become clear in part from the disclosure of the present invention, or may be learned from the practice of the inventive concepts provided herein. Other features, advantages and aspects of the present invention may be realized and obtained by the description provided in the present invention or its derivatives and its claims and drawings. All of these features, advantages and aspects are intended to be included in this specification, fall within the scope of the present invention, and are protected by the appended claims. Nothing in this section should be construed as a limitation on the claims. Further aspects and advantages are discussed below in conjunction with embodiments of the present invention.

[0013] It is to be understood that both the foregoing description and the following description of the present invention are examples, which are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this invention, illustrate several aspects and embodiments of the invention and together with the description serve to explain the principles and examples of the invention.

[0015] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

[0016] Figure 2 is a cross-sectional view illustrating a stack structure of a display device according to an exemplary embodiment of the present invention.

[0017] Figure 3A is a bottom plan view of an IC package according to an exemplary embodiment of the present invention, Figure 3B It shows that the setting Figure 3A a cross-sectional view of an output bump in an output bump region; Figure 3C yes Figure 3A A magnified view of the output bump area.

[0018] Figure 4 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present invention.

[0019] Figure 5 It is used to illustrate Figure 4 FIG. 1 is a diagram showing application of a scanning signal and a light emission control signal in a refresh period and a hold period in a pixel circuit shown in FIG.

[0020] Figure 6 is a diagram showing a configuration of a gate driver in a display device according to an exemplary embodiment of the present invention.

[0021] Fig. 7A is a diagram showing a configuration of a shift register of a gate driver according to an exemplary embodiment of the present invention, Figure 7B yes Fig. 7A An example of a driver circuit for a shift register in FIG.

[0022] Fig. 8A is a diagram showing a configuration of a shift register of another gate driver according to an exemplary embodiment of the present invention, Figure 8B yes Fig. 8A An example of a driver circuit for a shift register in FIG.

[0023] Fig. 9 7 and 8 are signal waveform diagrams of the start signal and the clock signal applied to the gate driver.

[0024] Throughout the drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements and their depictions may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0025] The advantages and features of the present invention and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The embodiments described in detail below will become clear. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are set forth only to make the disclosure of the present invention complete and fully convey the scope of the present invention to ordinary technicians in the technical field to which the present invention belongs. The present invention is limited only by the scope of the claims.

[0026] For the sake of simplicity and clarity of illustration, the elements in the accompanying drawings do not have to be drawn to scale. The same reference numerals in different figures represent the same or similar elements, and thus perform similar functions. In addition, for the sake of simplicity of description, the description and details of known steps and elements are omitted. In addition, in the following detailed description of the present invention, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood that the present invention can be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessary obscurity of multiple aspects of the present invention. The examples of various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutes, modifications and equivalents that may be included in the spirit and scope of the present invention as defined in the appended claims.

[0027] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present invention are exemplary, and the embodiments of the present invention are not limited thereto.

[0028] The terms used herein are intended to describe only the purpose of specific embodiments and are not intended to limit the present invention. As used herein, singular compositions are intended to also include plural compositions, unless the context clearly indicates otherwise. It will be further understood that the terms "include", "comprise", "have", "contain" used in this specification indicate the presence of the features, integers, operations, elements and / or components mentioned, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Expressions such as "at least one of" before the list of elements can modify the entire list of elements, rather than modifying the individual elements of the list. When explaining numerical values, even if there are no other clear descriptions, there may also be errors or tolerances therein.

[0029] The symbol “ / ” may represent “or.” The term “source / drain” may represent a source or a drain.

[0030] In addition, it will be understood that when a first element or layer is referred to as being present on a second element or layer, the first element may be directly disposed on the second element or layer, or may be indirectly disposed on the second element or layer with a third element or layer disposed between the first element or layer and the second element or layer. It will be understood that when an element or layer is referred to as being connected or joined to another element or layer, it may be directly located on the other element or layer or directly connected or directly joined to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will be understood that when an element or layer is referred to as being between two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0031] Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed on or on top of another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly on or on top of another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed under or below another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly under or below another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter.

[0032] When using terms such as “after”, “subsequently”, “before”, etc. to describe a temporal relationship, such as the temporal sequence between two events, other events may occur in between unless it is stated as “directly after”, “directly subsequent” or “directly before”.

[0033] When a certain embodiment can be implemented differently, the function or operation indicated in a specific block may occur in an order different from the order indicated in the flow chart. For example, two consecutive blocks may actually be executed substantially simultaneously, or, depending on the function or operation involved, the two blocks may be executed in reverse order.

[0034] It will be understood that although the text may use the terms "first", "second", "third", etc. to describe various elements, components, regions, layers and / or time periods, these elements, components, regions, layers and / or time periods should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or time period from another element, component, region, layer or time period. Therefore, without departing from the spirit and scope of the present invention, the first element, component, region, layer or time period described below may be referred to as the second element, component, region, layer or time period.

[0035] The features of the various embodiments of the present invention may be combined with each other in part or in whole, may be technically related to each other or may operate with each other. The embodiments may be implemented independently of each other, or may be implemented together in an associated relationship.

[0036] When interpreting numerical values, even if there is no explicit description thereof separately, the values ​​are interpreted as including the error range.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with that in the context of the relevant art and should not be interpreted in an idealized or over-formal sense unless explicitly defined as such herein.

[0038] As used herein, "embodiment," "example," "aspect," etc. should not be construed as implying that any aspect or design described is superior or advantageous over other aspects or designs.

[0039] Additionally, the term "or" means an inclusive or rather than an exclusive or. That is, unless specified otherwise or clear from the context, the expression "x employs a or b" means any of the natural inclusive permutations.

[0040] The terms used in the following description are selected as common and general terms in the relevant technical field. However, there may be other terms besides these terms according to the development and / or change of technology, protocol, preference of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical concept, but should be understood as examples of terms used to illustrate the implementation mode.

[0041] In addition, in specific cases, the applicant may arbitrarily select terms, in which case their detailed meanings will be described in the corresponding description of this document. Therefore, the terms used in the following description should not be simply understood based on the names of the terms, but also based on the meaning and content of the terms throughout the specific description.

[0042] When describing a signal flow, for example, when a signal is transmitted from node A to node B, it may include a case where the signal is transmitted from node A to node B via another node unless the phrase “immediately transmitted” or “directly transmitted” is used.

[0043] Hereinafter, a display device according to some embodiments will be described.

[0044] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

[0045] Reference Figure 1 The display device 10 includes: a display panel 100 including a plurality of pixels P; a controller 200; a gate driver 300 that provides a gate signal to each of the plurality of pixels P; a data driver 400 that provides a data signal to each of the plurality of pixels P; and a power supply 500 that provides power required for operation to each of the plurality of pixels P.

[0046] The display panel 100 includes a display area where pixels P are located (see Figure 2 AA) and the non-display area surrounding the display area AA (see Figure 2 The gate driver 300 and the data driver 400 are disposed in the non-display area NA.

[0047] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL intersect each other, and each of a plurality of pixels P is connected to the gate line GL and the data line DL. Specifically, one pixel P receives a gate signal from a gate driver 300 via the gate line GL, receives a data signal from a data driver 400 via the data line DL, and receives a high potential driving voltage EVDD and a low potential driving voltage EVSS from a power source 500 via a driving power line PL.

[0048] In this regard, the gate line GL provides a scan signal SC and a light emission control signal EM to the pixel, and the data line DL provides a data voltage Vdata to the pixel. In addition, according to various embodiments, the gate line GL may include a plurality of scan lines SCL providing the scan signal SC and a light emission control signal line EML providing the light emission control signal EM. In addition, the plurality of pixels P may additionally include at least one power line VL, and may receive a bias voltage Vobs and initialization voltages Vini and Var via the at least one power line VL.

[0049] In addition, if Figure 2 As shown, each pixel P includes a light emitting element EL and a pixel circuit for controlling the operation of the light emitting element EL. In this regard, the light emitting element EL is composed of an anode 171, a cathode 173, and a light emitting layer 172 located between the anode 171 and the cathode 173.

[0050] The pixel circuit includes a plurality of switching elements, a driving element and a capacitor. In this regard, each of the switching element and the driving element may be implemented as a thin film transistor. In the pixel circuit, the driving element controls the amount of current supplied to the light emitting element EL based on the data voltage to adjust the amount of light emitted from the light emitting element EL. In addition, the plurality of switching elements receive a scanning signal SC supplied via a plurality of scanning lines SCL and a light emitting control signal EM supplied via a light emitting control line EML, and operate the pixel circuit based on the scanning signal SC and the light emitting control signal EM.

[0051] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual object in the background is visible to a viewer in front of the display device. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0052] The pixel P may include a red pixel, a green pixel, and a blue pixel to emit light of corresponding colors. The pixel P may further include a white pixel. Each pixel P includes a pixel circuit.

[0053] The touch sensor may be provided on the display panel 100. A touch input may be sensed using a separate touch sensor, or the touch input may be sensed via the pixel P. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor built into the display panel 100.

[0054] The controller 200 processes the image data RGB input from an external source such as a host system to make it suitable for the size and resolution of the display panel 100, and provides the processed image data to the data driver 400. The controller 200 generates a gate control signal GCS and a data control signal DCS based on synchronization signals such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync input from an external source, and provides the generated gate control signal GCS and data control signal DCS to the gate driver 300 and the data driver 400, respectively, thereby controlling the gate driver 300 and the data driver 400.

[0055] The controller 200 may be configured to interface to various processors such as a microprocessor, a mobile processor, an application processor, etc., according to the type of device on which the controller is mounted.

[0056] The host system may be any of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0057] The controller 200 multiplies the input frame rate by i, and uses frame rate=input frame rate×i (i is a positive integer greater than 0) Hz to control the operation timing of each of the gate driver 300 and the data driver 400. The input frame rate is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the Phase Alternation Line (PAL) system.

[0058] The controller 200 generates a signal to enable the pixel to operate at various refresh rates. That is, the controller 200 generates an operation-related signal so that the pixel can operate in a variable refresh rate (VRR) mode, or its refresh rate can be switched between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the rate of the clock signal, can generate a synchronization signal to generate a horizontal blank or a vertical blank, or can operate the gate driver 300 in a mask manner so that the pixel P can operate at various refresh rates.

[0059] Based on the timing signals Vsync, Hsync, and DE received from the host system, the controller 200 generates a gate control signal GCS for controlling the operation timing of the gate driver 300 and a data control signal DCS for controlling the operation timing of the data driver 400. The controller 200 controls the timing of the gate driver 300 and the data driver 400 so that the gate driver 300 and the data driver 400 are synchronized with each other.

[0060] The level shifter (not shown) converts the voltage level of the gate control signal GCS output from the controller 200 into gate on voltages VGL and VEL and gate off voltages VGH and VEH, which are then provided to the gate driver 300 via the driving power line PL. The level shifter converts the low level voltage of the gate control signal GCS into the gate low voltage VGL, and converts the high level voltage of the gate control signal GCS into the gate high voltage VGH. The gate control signal GCS includes a start pulse and a shift clock.

[0061] The gate driver 300 supplies the scan signal SC to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driver 300 may be disposed at one or each of two opposite sides of the display panel 100 in a GIP (gate in panel) manner.

[0062] The gate driver 300 sequentially outputs gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 shifts the gate signals using a shift register and sequentially provides the shifted gate signals to the gate lines GL.

[0063] The gate signal may include a scan signal SC and a light emission control signal EM in an organic light emitting display device. The scan signal SC includes a scan pulse swinging between a gate-on voltage VGL and a gate-off voltage VGH. The light emission control signal may include a light emission control signal pulse swinging between a gate-on voltage VEL and a gate-off voltage VEH.

[0064] The scan pulse is synchronized with the data voltage Vdata to select pixels of a line into which data is to be written. The light emission control signal defines the light emission time of each pixel.

[0065] The gate driver 300 may include a light emission control driver 310 and at least one scan driver 320 .

[0066] The light emission control driver 310 outputs a light emission control signal pulse in response to a start pulse and a shift clock received from the controller 200 , and sequentially shifts the light emission control signal pulse according to the shift clock timing.

[0067] Each of the at least one scan driver 320 outputs a scan signal in response to a start pulse and a shift clock received from the controller 200, and shifts the scan signal according to the shift clock timing.

[0068] The data driver 400 converts the image data RGB into a data voltage Vdata according to a data control signal DCS received from the controller 200 , and provides the converted data voltage Vdata to the pixel P through the data line DL.

[0069] exist Figure 1 , it is shown that one data driver 400 is disposed at one side of the display panel 100. However, the number and position of the data driver 400 are not limited thereto.

[0070] That is, the data driver 400 may be implemented as a plurality of integrated circuits (ICs) that may be provided at one side of the display panel 100 and may be separately arranged along the side.

[0071] The power supply 500 uses a direct current (DC)-DC converter to generate DC power required for operating the pixel array of the display panel 100 and the display panel driver including the gate driver 300 and the data driver 400. The DC-DC converter may include a charge pump, a rectifier, a buck converter, a boost converter, etc. The power supply 500 receives a DC input voltage applied from a host system (not shown) and generates DC voltages such as gate-on voltages VGL and VEL, gate-off voltages VGH and VEH, a high potential driving voltage EVDD, a low potential driving voltage EVSS, etc. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH are provided to a level shifter (not shown) and the gate driver 300. Each of the high potential driving voltage EVDD and the low potential driving voltage EVSS is commonly provided to the pixel.

[0072] In addition, refer to Figure 1 , at least one optical area OA1 and OA2 may be disposed in the display area AA.

[0073] At least one optical area OA1 and OA2 may be positioned to overlap with at least one optical electronic device such as a photographing device such as a camera (image sensor) and a detection sensor such as a proximity sensor and a brightness sensor.

[0074] For the operation of the optical electronic device, at least one optical area OA1 and OA2 may have a light-transmitting structure and thus may have a transmittance equal to or greater than a predetermined value. In other words, the number of pixels P per unit area in at least one optical area OA1 and OA2 may be smaller than the number of pixels P per unit area in the general area of ​​the display area AA except for the at least one optical area OA1 and OA2. That is, the resolution of at least one optical area OA1 and OA2 may be lower than the resolution of the general area of ​​the display area AA.

[0075] The light-transmitting structure of at least one optical area OA1 and OA2 may be formed by patterning the cathode in the area where the pixel P is not disposed. At this time, a portion of the patterned cathode may be removed using a laser. Alternatively, the cathode may be selectively formed so as to be patterned using a material such as a cathode deposition preventing layer.

[0076] Alternatively, the light-transmitting structure of at least one optical area OA1 and OA2 may be formed by forming the light-emitting element EL and the pixel circuit in a separate manner in the pixel P. In other words, the light-emitting element EL of the pixel P may be located on at least one optical area OA1 and OA2, and a plurality of transistors TFT constituting the pixel circuit may be disposed around the at least one optical area OA1 and OA2, and the light-emitting element EL and the pixel circuit may be electrically connected to each other via a transparent metal layer.

[0077] Figure 2 is a cross-sectional view illustrating a stack structure of a display device according to an exemplary embodiment of the present invention.

[0078] Reference Figure 2 , the display panel 100 includes a display area AA where pixels P are located and a non-display area NA surrounding the display area AA. The gate driver 300 and the data driver 400 are disposed in the non-display area NA.

[0079] The display panel 100 according to the exemplary embodiment of the present invention includes a substrate 101 , thin film transistors TFT1 and TFT2 , a bank layer 165 , a light emitting element EL, an encapsulation layer 180 , a touch layer 190 , a touch protection film 197 , a dam DAM, and a pad 198 .

[0080] The thin film transistor TFT1 may be disposed on the substrate 101. The thin film transistor TFT1 drives the light emitting element EL of the display area AA.

[0081] The substrate 101 supports the components of the display panel 100. The substrate 101 may be made of a transparent insulating material such as glass or plastic. When the substrate 101 is made of plastic, the substrate may be referred to as a plastic film or a plastic substrate. For example, the substrate 101 may be in the form of a film including one of a polyimide-based polymer, a polyester-based polymer, a silicone-based polymer, an acrylic-based polymer, a polyolefin-based polymer, and a copolymer thereof. However, embodiments of the present invention are not limited thereto.

[0082] The thin film transistor TFT1 may include a semiconductor layer 115, a gate electrode 125, and a source / drain electrode 140. The thin film transistor TFT1 is a driving transistor ( Figure 4 1). The semiconductor layer 115 may be made of polycrystalline silicon (p-Si). In this case, a predetermined region thereof may be doped with impurities. In addition, the semiconductor layer 115 may be made of amorphous silicon a-Si or various organic semiconductor materials such as pentacene. The semiconductor layer 115 may be made of an oxide. The embodiments of the present invention do not limit the material constituting the semiconductor layer 115. The semiconductor layer 115 may be an active layer. However, the embodiments of the present invention are not limited thereto.

[0083] The gate 125 may be disposed on the top of the semiconductor layer 115. The gate 125 may be made of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, etc. However, embodiments of the present invention are not limited thereto.

[0084] The gate insulating layer may be disposed between the semiconductor layer 115 and the gate 125. The gate insulating layer may be a layer that insulates the semiconductor layer 115 and the gate 125 from each other, and may be made of an insulating material. For example, the gate insulating layer may be composed of a single layer or a double layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of the present invention are not limited thereto.

[0085] The source / drain 140 may be electrically connected to the semiconductor layer 115 and the source and drain may be separated from each other. The source / drain 140 may be disposed on the insulating layer. Each of the source / drain 140 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. However, the embodiments of the present invention are not limited thereto.

[0086] The capacitor Cst may be disposed on the substrate 101. The capacitor Cst may include a first gate electrode 142 and a second gate electrode 144. The gate insulating layer 124 may be disposed between the first gate electrode 142 and the second gate electrode 144. At least one of the first gate electrode 142 and the second gate electrode 144 may be connected to an electrode of the thin film transistor TFT1. The capacitor Cst may be connected to the thin film transistor TFT1 via a connection electrode 157.

[0087] Another thin film transistor TFT2 may be disposed on the substrate 101. The thin film transistor TFT2 may include a semiconductor layer 116, a gate electrode 126, and a source / drain electrode 112. The thin film transistor TFT2 may be the first to seventh transistors T1 to T7 (see Figure 4 The gate insulating layer 122 may be disposed between the semiconductor layer 116 and the gate 126 .

[0088] An interlayer insulating layer 128 may be disposed between the thin film transistor TFT1 and the capacitor Cst, or between the thin film transistor TFT1 and another thin film transistor TFT2.

[0089] For the convenience of illustration, among various thin film transistors that may be included in the display device 10, only the thin film transistor TFT1 and the thin film transistor TFT2 are shown. However, other thin film transistors may be included in the display panel 100. In addition, an example in which the thin film transistor has a coplanar structure is described. However, the thin film transistor may be implemented to have other structures such as a staggered structure. The present invention is not limited thereto.

[0090] The thin film transistor TFT1 may receive a high potential driving voltage EVDD in response to a data voltage Vdata supplied to the gate electrode 125 of the thin film transistor TFT1 to control the amount of current supplied to the light emitting element EL, thereby adjusting the amount of light emitted from the light emitting element EL. The thin film transistor TFT1 may provide a constant current based on the voltage charged in the capacitor Cst to maintain the light emission of the light emitting element EL until the data voltage Vdata of the next frame is supplied. The high potential power line may extend in parallel with the data line.

[0091] The thin film transistor TFT1 may include: a semiconductor layer 115 disposed on an interlayer insulating layer 128 ; a gate electrode 125 overlapping the semiconductor layer 115 with a second insulating layer 120 interposed therebetween; and a source / drain electrode 140 formed on a third insulating layer 135 and contacting the semiconductor layer 115 .

[0092] The semiconductor layer 115 may be used as a region for forming a channel during operation of the thin film transistor TFT1. The semiconductor layer 115 may be made of an oxide semiconductor, or may be made of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or pentacene. The present invention is not limited thereto. The semiconductor layer 115 may be formed on the interlayer insulating layer 128. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap with the gate 125 under the condition that the second insulating layer 120 is interposed therebetween. The channel region may be formed between the source electrode 140 and the drain electrode 140. The source region may be electrically connected to the source electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135.

[0093] The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 116 and the substrate 101. The buffer layer 105 may delay diffusion of moisture and / or oxygen intruding into the substrate 101. The first insulating layer 110 may protect the semiconductor layer 116 and may block various types of defects introduced from the substrate 101.

[0094] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of a material having different etching characteristics from each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of one of silicon nitride (SiNx) and silicon oxide (SiOx). Each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of the other of silicon nitride (SiNx) and silicon oxide (SiOx). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiNx), and each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon oxide (SiOx). The present invention is not limited thereto.

[0095] The gate 125 may be formed on the second insulating layer 120 and may overlap with the channel region of the semiconductor layer 115 with the second insulating layer 120 interposed therebetween. The gate 125 may be made of a first conductive material, and may be implemented as a single layer or a multilayer made of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0096] The source electrode 140 may be connected to the exposed source region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may be opposite to the source electrode 140 and may be connected to the drain region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. Each of the source electrode 140 and the drain electrode 140 may be made of a second conductive material and may be implemented as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present invention is not limited thereto.

[0097] The connection electrode 155 may be disposed between the third intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be connected to the drain electrode 140 via a connection electrode contact hole 156 extending through the protective film 145 and the first intermediate layer 150. The connection electrode 155 may be made of a material having low resistivity and being the same as or similar to that of the drain electrode 140. The present invention is not limited thereto.

[0098] The reference voltage line VrefL may be a sub-power line branched from a reference voltage bus of at least one power line VL, and may be provided in the same layer as the source / drain 140 of the thin film transistor TFT1. The embodiment of the present invention is not limited thereto, and the reference voltage line VrefL may be provided on the interlayer insulating layer 128 or the second insulating layer 120.

[0099] The light emitting element EL including the light emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light emitting element 170 may include an anode 171, at least one light emitting layer 172 formed on the anode 171, and a cathode 173 formed on the light emitting layer 172.

[0100] The anode 171 may be electrically connected to an exposed portion of the connection electrode 155 disposed on the first intermediate layer 150 and facing the second intermediate layer 160 via a contact hole extending through the second intermediate layer 160 .

[0101] The anode 171 of each pixel is not covered by the bank layer 165. The bank layer 165 may be made of an opaque material (e.g., a black material) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light shielding material having at least one of a color pigment, organic black, and carbon black. The present invention is not limited thereto.

[0102] At least one light-emitting layer 172 may be formed on a portion of the anode 171 corresponding to the light-emitting region defined by the bank layer 165. At least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer on the anode 171. The stacking order of the hole transport layer, the hole injection layer, the hole blocking layer, the light-emitting layer 172, the electron injection layer, the electron blocking layer, and the electron transport layer may be based on the light emission direction. In addition, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other, and the charge generation layer is interposed between the first light-emitting stack and the second light-emitting stack. In this case, the light-emitting layer 172 of one of the first light-emitting stack and the second light-emitting stack may generate blue light, and the light-emitting layer 172 of the other of the first light-emitting stack and the second light-emitting stack may generate yellow-green light, so that white light may be generated based on the combination of the first light-emitting stack and the second light-emitting stack. White light generated based on the combination of the first light-emitting stack and the second light-emitting stack may be incident on a color filter located above or below the light-emitting layer 172, so that a color image may be realized. In another example, each light-emitting layer 172 may generate light of each color corresponding to each pixel without a separate color filter, so that a color image may be presented. For example, the light-emitting layer 172 of a red (R) pixel emits red light, the light-emitting layer 172 of a green (G) pixel emits green light, and the light-emitting layer 172 of a blue (B) pixel emits blue light.

[0103] The cathode 173 may be formed to face the anode 171 with the light emitting layer 172 disposed between the anode 171 and the cathode 173 , and the cathode 173 may receive a high potential driving voltage EVDD.

[0104] The encapsulation layer 180 can block external moisture or oxygen from penetrating into the light emitting element EL that is susceptible to external moisture or oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The present invention is not limited thereto. In the present invention, as an example, a structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked is described.

[0105] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 is formed. The third encapsulation layer 183 and the first encapsulation layer 181 may surround the top surface, the bottom surface and the side surface of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent the penetration of external moisture or oxygen into the light emitting element EL. Each of the first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or oxide (Al2O3) that can be deposited at low temperature. Each of the first encapsulation layer 181 and the third encapsulation layer 183 is deposited in a low temperature atmosphere. Thus, in the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183, damage to the light emitting element EL that is susceptible to the high temperature atmosphere can be prevented.

[0106] The second encapsulation layer 182 is used as a vibration absorbing layer to relieve the stress between the layers caused by the bending of the display device 10, and the steps between the layers can be flattened. The second encapsulation layer 182 can be made of a non-photosensitive organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, polyethylene or a silicon carbide oxide (SiOC) or a photosensitive organic insulating material such as an optical acrylic (photoacryl). The present invention is not limited to this. When the second encapsulation layer 182 is formed using an inkjet method, the weir DAM can be set to prevent the liquid second encapsulation layer 182 from diffusing to the edge of the substrate 101. The weir DAM can be closer to the edge of the substrate 101 than the second encapsulation layer 182. The weir DAM can prevent the liquid second encapsulation layer 182 from diffusing to the pad area where the conductive pad is provided, wherein the conductive pad is provided at the outermost side of the substrate 101.

[0107] The weir DAM is designed to prevent diffusion of the second encapsulation layer 182. However, when the second encapsulation layer 182 overflows the weir DAM during the process, the second encapsulation layer 182 as an organic layer may be exposed to the outside, so that moisture or the like may invade the light emitting element. Therefore, in order to prevent the invasion, at least ten weir DAMs may be stacked.

[0108] The bank DAM may be disposed on the interlayer insulating layer located on the third insulating layer 135 and in the non-display area NA. However, in this embodiment of the present invention, the interlayer insulating layer may be the third insulating layer 135.

[0109] In addition, the weir DAM, the first intermediate layer 150 and the second intermediate layer 160 may be formed simultaneously. The lower layer of the weir DAM and the first intermediate layer 150 may be formed simultaneously. The upper layer of the weir DAM and the second intermediate layer 160 may be formed simultaneously. Therefore, the weir DAM may have a double-layer structure.

[0110] Therefore, the weir DAM may be made of the same material as each of the first intermediate layer 150 and the second intermediate layer 160. However, embodiments of the present invention are not limited thereto.

[0111] The bank DAM may overlap the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed in a layer located below the bank DAM and in the non-display area NA.

[0112] The gate driver 300 in the form of a gate in panel (GIP) and a low potential drive power line VSS may surround the periphery of the display panel. The low potential drive power line VSS may be arranged outwardly relative to the gate driver 300. In addition, the low potential drive power line VSS may be connected to the anode 171 to apply a common voltage thereto. The gate driver 300 is simply shown in the plan and cross-sectional views. However, the gate driver 300 may be configured using a thin film transistor TFT having the same structure as the thin film transistor TFT of the display area AA.

[0113] The low potential driving power line VSS is arranged outwardly relative to the gate driver 300. The low potential driving power line VSS is arranged outwardly relative to the gate driver 300 and surrounds the display area AA. The low potential driving power line VSS may be made of the same material as each of the source and drain electrodes 140 of the thin film transistor TFT1. The present invention is not limited thereto. For example, the low potential driving power line VSS may be made of the same material as the gate electrode 125.

[0114] In addition, a low potential driving power line VSS may be electrically connected to the anode 171. The low potential driving power line VSS may provide a low potential driving voltage EVSS to a plurality of pixels in the display area AA.

[0115] The low potential driving power line VSS may be disposed on the third insulating layer 135. Alternatively, the low potential driving power line VSS may be disposed on a layer of the gate electrode 125 or the source / drain electrode 140 of the thin film transistor TFT1. However, the embodiments of the present invention are not limited thereto.

[0116] At least one power line VL may be provided between the gate driver 300 and the display area AA. At least one power line VL may be provided in the same layer as the source / drain 140 of the thin film transistor TFT1. However, the embodiments of the present invention are not limited thereto. The at least one power line VL is shown in a simple manner in the cross-sectional view. However, the initialization voltage bus ViniL (see Figure 6 ) and the reference voltage bus VrefL may be arranged side by side and may be arranged in the same layer. Optionally, the initialization voltage bus ViniL and the reference voltage bus VrefL may be arranged in different layers in an overlapping or non-overlapping manner. The initialization voltage bus ViniL may provide a second initialization voltage Vini to a plurality of pixels in the display area AA. The reference voltage bus VrefL may provide a reference voltage Vref to a plurality of pixels in the display area AA. At least one power line VL is illustrated as being arranged between the gate driver 300 and the display area AA. However, embodiments of the present invention are not limited thereto.

[0117] The touch layer 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer film 191 may be located between a touch sensor metal including touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 and a cathode 173 of the light emitting element EL.

[0118] The touch buffer film 191 can prevent chemicals (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal provided on the touch buffer film 191 or moisture from the outside from intruding into the light emitting layer 172 including the organic material. Therefore, the touch buffer film 191 can prevent damage to the light emitting layer 172 that is susceptible to chemicals or moisture.

[0119] The touch buffer film 191 may be made of an organic insulating material that can be formed at a low temperature lower than or equal to a certain temperature (e.g., 100 degrees Celsius) to prevent damage to the light emitting layer 172 including an organic material that is easily affected by high temperature, and has a low dielectric constant of 1 to 3. For example, the touch buffer film 191 may be made of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film 191 made of an organic insulating material and having a planarization property can prevent damage to the encapsulation layer 180 due to bending of the organic light emitting display device and cracking of a touch sensor metal formed on the touch buffer film 191.

[0120] According to a touch sensor structure based on mutual capacitance, the touch electrodes 195 and 196 may be disposed on the touch buffer film 191 , and the touch electrodes 195 and 196 may be disposed to cross each other.

[0121] The touch electrode connection lines 192 and 194 may electrically connect the touch electrodes 195 and 196 to each other. The touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 may be located on different layers while interposing the touch insulation film 193 therebetween.

[0122] The touch electrode connection lines 192 and 194 may overlap the bank layer 165 , thereby preventing the aperture ratio from being reduced.

[0123] In one example, a portion of the touch electrode connection line 192 may extend along the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam DAM, and then may be electrically connected to a touch driver circuit (not shown) via a pad 198. Thus, the touch electrodes 195 and 196 may be electrically connected to the touch driver circuit.

[0124] A portion of the touch electrode connection line 192 may receive a touch driving signal from a touch driver circuit and transmit it to the touch electrodes 195 and 196 ; and may receive a touch sensing signal from the touch electrodes 195 and 196 and transmit it to the touch driver circuit.

[0125] The touch protection film 197 may be provided on the touch electrodes 195 and 196. In the drawings, it is shown that the touch protection film 197 is provided only on the touch electrodes 195 and 196. However, the embodiments of the present invention are not limited thereto. The touch protection film 197 may extend to the inner end or the outer end of the weir DAM, and thus may also be provided on the touch electrode connection line 192.

[0126] In addition, a color filter (not shown) may be further disposed on the encapsulation layer 180 , and the color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190 .

[0127] Figure 3A is a bottom plan view showing an IC package according to an exemplary embodiment of the present invention, Figure 3B It shows that the setting Figure 3A a cross-sectional view of an output bump in an output bump region; Figure 3C yes Figure 3A A magnified view of the output bump area.

[0128] Reference Figure 3A , the IC package 401 includes an input bump area PAD-In and an output bump area PAD-Out spaced apart from the input bump area PAD-In by a predetermined distance.

[0129] The input bump region PAD-In is located on the top of the IC package 401 in the second direction Y. The input bump region PAD-In includes a plurality of bumps BUMP. The plurality of bumps BUMP transmit input signals from the circuit board to the integrated circuit of the IC package 401. The plurality of bumps BUMP may be as follows: Figure 3A As shown, they are arranged in a row along the first direction X. However, the embodiments of the present invention are not limited thereto.

[0130] The output bump region PAD-Out is located below the IC package 401 in the second direction Y. The output bump region PAD-Out includes a plurality of bumps BUMP. The plurality of bumps BUMP transmit the signal output from the integrated circuit of the IC package 401 to the signal line of the display panel 100. The plurality of bumps BUMP may be as follows: Figure 3A As shown, they are arranged in three rows along the first direction X. However, embodiments of the present invention are not limited thereto.

[0131] Reference Figure 3B The substrate 101 of the display panel 100 may be a PI (polyimide) film substrate. A plurality of signal pads PAD are formed on the substrate 101 .

[0132] IC package 401 includes D-IC. IC package 401 includes a plurality of bumps BUMP arranged in an input bump area PAD-In and an output bump area PAD-Out located below D-IC. Each of the plurality of bumps BUMP can be connected to each of the plurality of signal pads PAD via a conductive ball B of an adhesive layer ACF. The plurality of bumps BUMP can be formed to have the same thickness. Data driver 400 may include a plurality of bumps BUMP.

[0133] The signal pad PAD connected to each of the multiple bumps BUMP may include a combination of the same material as each of the gates 125 and 126 of the thin film transistor used in the pixel circuit, the same material as the source 140 and the drain 140 of the thin film transistor used in the pixel circuit, the same material as the connecting electrode 155, and the same material as the touch electrode connecting line 194 and the touch electrodes 195 and 196. That is, the signal pad PAD may include: gate layers 125 and 126 made of the same material as the gates 125 and 126 and disposed in the same layer as the gates 125 and 126; a first source / drain layer 140 made of the same material as the source or drain 140 and disposed in the same layer as the source or drain 140; a second source / drain layer 155 made of the same material as the connecting electrode 155 and disposed in the same layer as the connecting electrode 155; and touch electrode layers 194, 195 and 196 made of the same material as the touch electrode connecting line 194 and the touch electrodes 195 and 196 and disposed in the same layer as the touch electrode connecting line 194 and the touch electrodes 195 and 196.

[0134] The signal pad PAD may be formed as a structure in which the gate layers 125 and 126, the first source and drain layers 140, the second source and drain layers 155, and the touch electrode layers 194, 195, and 196 overlap each other. Each of the plurality of bumps BUMP may overlap the gate, the first source / drain, the second source / drain, and the touch electrode in the bump area. In this regard, the insulating layer may not be formed between the first source and drain layer 140 and the second source and drain layer 155. In addition, the second source and drain layer 155 may be formed to have a greater width than the width of the first source and drain layer 140 to cover the top surface and side surface of the first source and drain layer 140. In this regard, the first intermediate layer 150 or the second intermediate layer 160 may be formed to cover the side surface of the second source and drain layer 155 and at least a portion of the top surface.

[0135] Different signals may be applied to the plurality of signal pads PAD, respectively, or the same signal may be applied to the plurality of signal pads PAD. In other words, at least some of the plurality of bumps BUMP may be electrically connected to each other via the plurality of signal pads PAD.

[0136] Reference Figure 3C , the gate signal line GSL and the plurality of power supply lines VL connected to the gate driver 300 may be connected to each of the plurality of signal pads PAD. The gate signal line GSL includes a plurality of start signal lines VSTL and a plurality of clock signal lines CLKL.

[0137] The plurality of start signal lines VSTL are respectively connected to the light emission control driver 310 and the plurality of scan drivers 320 included in the gate driver 300. The plurality of clock signal lines CLKL are respectively connected to the light emission control driver 310 and the plurality of scan drivers 320 included in the gate driver 300. In other words, at least one start signal line VSTL and at least one clock signal line CLKL may be connected to the light emission control driver 310. At least one start signal line VSTL and at least one clock signal line CLKL may be connected to each of the plurality of scan drivers 320.

[0138] A plurality of clock signal lines CLKL respectively connected to the light emission control driver 310 and the plurality of scan drivers 320 may be disposed adjacent to each other. For example, a clock signal line connected to the light emission control driver 310 to apply the first light emission clock signal EM_GCLK1 and a clock signal line connected to the light emission control driver 310 to apply the second light emission clock signal EM_GCLK2 may be disposed adjacent to each other.

[0139] At least some of the plurality of start signal lines VSTL respectively connected to the light emission control driver 310 and each scan driver 320 may be disposed adjacent to each other. Figure 6 ) to apply the second start signals SC2_O_VST and SC2_E_VST and a start signal line connected to the light emitting control driver 310 to apply the light emitting control start signal EM_VST may be adjacent to each other.

[0140] The plurality of power lines VL may include a bias voltage bus VOBS, a first initialization voltage bus VAR, and a second initialization voltage bus VINI. At least one power line VL may be disposed inwardly relative to the gate signal line GSL. In other words, the signal pad PAD to which the power line VL is connected may be connected to a bump BUMP disposed in the central region of the IC package 401. The first clock signal or the second clock signal may be applied via bumps BUMP adjacent to each other, respectively.

[0141] In this regard, some of the plurality of signal pads PAD arranged adjacent to each other may cause defects such as shielding abnormality depending on operating conditions. In other words, when the same signal is continuously applied to the signal pads PAD during a hold frame in a low-speed operation, a film peeling phenomenon may occur. In order to prevent this situation, the present invention proposes appropriate operating conditions, which will be described later with reference to FIG. Figures 6 to 9 Describe together with the description of .

[0142] Figure 4 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present invention.

[0143] Figure 4 For the sake of illustration, only an example of a pixel circuit is shown. The structure of the pixel circuit is not particularly limited as long as its structure can apply a light emitting control signal EM(n) to the pixel to control the light emitting element EL. For example, the pixel circuit may include: a switching thin film transistor connected to an additional scanning signal; and a switching thin film transistor to which an additional initialization voltage is applied. The connection relationship of the switching element or the connection position of the capacitor may be changed. In the following, for the convenience of description, a pixel circuit having Figure 4 A display device with a pixel circuit structure.

[0144] Reference Figure 4 , each of the plurality of pixels P may include a pixel circuit including a driving transistor DT and a light emitting element EL connected to the pixel circuit.

[0145] The pixel circuit may control a driving current flowing through the light emitting element EL to drive the light emitting element EL. The pixel circuit may include a driving transistor DT, first to seventh transistors T1 to T7, and a capacitor Cst. Each of the transistors DT and T1 to T7 may include a first electrode, a second electrode, and a gate. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0146] Each of the transistors DT and T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. Figure 4 In the embodiment of the present invention, the first transistor T1 and the seventh transistor T7 are implemented as N-type thin film transistors, and the remaining transistors DT and T2 to T6 are implemented as P-type thin film transistors. However, the embodiments of the present invention are not limited thereto. According to an exemplary embodiment, each of the transistors DT and all or some of T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. In addition, the N-type thin film transistor may be implemented as an oxide thin film transistor. The P-type thin film transistor may be implemented as a polysilicon thin film transistor.

[0147] Hereinafter, an example is described in which the first transistor T1 and the seventh transistor T7 are implemented as N-type thin film transistors, and the remaining transistors DT and T2 to T6 are implemented as P-type thin film transistors. Therefore, each of the first transistor T1 and the seventh transistor T7 can be turned on when a high voltage is applied. Each of the remaining transistors DT and T2 to T6 can be turned on when a low voltage is applied.

[0148] According to one example, the first transistor T1 constituting the pixel circuit may be used as a compensation transistor, the second transistor T2 may be used as a data supply transistor, each of the third transistor T3 and the fourth transistor T4 may be used as a light emission control transistor, the second transistor T2 may be used as a data supply transistor, each of the third transistor T3 and the fourth transistor T4 may be used as a light emission control transistor, the fifth transistor T5 may be used as a bias transistor, and each of the sixth transistor T6 and the seventh transistor T7 may be used as an initialization transistor.

[0149] The light emitting element OLED may include an anode and a cathode. The anode of the light emitting element OLED may be connected to the fifth node N5, and the cathode thereof may be connected to the low potential driving voltage EVSS.

[0150] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate connected to the first node N1. The driving transistor DT may provide a driving current Id to the light emitting element OLED based on a voltage of the first node N1 or a data voltage stored in the capacitor Cst, which will be described later.

[0151] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate receiving the first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n) so that a diode connection between the first node N1 and the third node N3 is established to sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0152] The capacitor CST may be connected to the first node N1 and the fourth node N4 and disposed between the first node N1 and the fourth node N4. The capacitor CST may store or maintain the supplied high potential driving voltage EVSS therein.

[0153] The second transistor T2 may include: a first electrode connected to the data line DL or receiving the data voltage Vdata; a second electrode connected to the second node N2; and a gate receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n), thereby transmitting the data voltage Vdata to the second node N2. The second transistor T2 may be a data supply transistor.

[0154] The third transistor T3 and the fourth transistor T4 (or the first light emission control transistor and the second light emission control transistor) can be connected to the high potential driving voltage EVDD and the light emitting element OLED and arranged between the high potential driving voltage EVDD and the light emitting element OLED, and can establish a current flow path through which the driving current Id generated by the driving transistor DT flows.

[0155] The third transistor T3 may include: a first electrode connected to the fourth node N4 to receive the high potential driving voltage EVDD; a second electrode connected to the second node N2; and a gate receiving the light emitting control signal EM(n).

[0156] The fourth transistor T4 may include: a first electrode connected to the third node N3; a second electrode connected to the fifth node N5 (or the anode of the light emitting element OLED); and a gate receiving the light emitting control signal EM(n).

[0157] Each of the third transistor T3 and the fourth transistor T4 may be turned on in response to the light emission control signal EM(n). In this case, the driving current Id may be provided to the light emitting element OLED so that the light emitting element OLED may emit light corresponding to the brightness level of the driving current Id.

[0158] The fifth transistor T5 may include: a first electrode receiving the bias voltage Vobs; a second electrode connected to the second node N2; and a gate receiving the third scan signal SC3 (n). The fifth transistor T5 may be a bias transistor.

[0159] The sixth transistor T6 may include: a first electrode receiving the first initialization voltage Var; a second electrode connected to the fifth node N5; and a gate receiving the third scan signal SC3(n).

[0160] Before (or after) the light emitting element OLED emits light, the sixth transistor T6 may be turned on in response to the third scan signal SC3(n), so that the anode (or pixel electrode) of the light emitting element OLED may be initialized based on the first initialization voltage Var.

[0161] The light emitting element OLED may have a parasitic capacitor generated between the anode and the cathode. Thus, while the light emitting element OLED emits light, the parasitic capacitor may be charged so that the anode of the light emitting element OLED may have a specific voltage. Therefore, the amount of charge accumulated in the light emitting element OLED may be initialized by applying the first initialization voltage Var to the anode of the light emitting element OLED via the sixth transistor T6.

[0162] In the present invention, the fifth transistor T5 and the sixth transistor T6 are configured such that the gate of the fifth transistor T5 and the gate of the sixth transistor T6 receive the third scan signal SC3(n) together. However, the embodiments of the present invention are not necessarily limited thereto, and the fifth transistor T5 and the sixth transistor T6 may be configured such that the gate of the fifth transistor T5 and the gate of the sixth transistor T6 receive separate scan signals, thereby the fifth transistor T5 and the sixth transistor T6 operate independently.

[0163] The seventh transistor T7 may include: a first electrode receiving the second initialization voltage Vini; a second electrode connected to the first node N1; and a gate receiving the fourth scan signal SC4(n).

[0164] The seventh transistor T7 may be turned on in response to the fourth scan signal SC4 (n), so that the gate of the driving transistor DT may be initialized using the second initialization voltage Vini. Unnecessary charges remain in the gate of the driving transistor DT due to the high potential driving voltage EVDD stored in the capacitor CST. Therefore, the amount of residual charge may be initialized by applying the second initialization voltage Vini to the gate of the driving transistor DT via the seventh transistor T7.

[0165] Figure 5 It is used to illustrate Figure 4 FIG. 1 is a diagram showing application of a scanning signal and a light emission control signal in a refresh period and a hold period in a pixel circuit shown in FIG.

[0166] The display device according to an exemplary embodiment of the present invention may be operated as a VRR mode display device. In the VRR mode, the display device operates at a constant frequency; and when high-speed operation is required, the refresh rate at which the data voltage Vdata is updated increases. Thus, the pixels operate at an increased refresh rate. When low power consumption or low-speed operation is required, the refresh rate is reduced so that the pixels operate at a reduced refresh rate.

[0167] Each of the plurality of pixels P may be operated based on a combination of a refresh frame and a hold frame. In other words, when the device is operated at a high speed such as 120 Hz or a normal speed such as 60 Hz, only the refresh period may be repeated. However, when the device is operated at a low speed such as 1 Hz or 10 Hz, the refresh period and the hold period may be arranged in an alternating manner with each other.

[0168] In the refresh frame, a new data voltage Vdata is charged to apply the new data voltage Vdata to the driving transistor DT. In the hold frame, the data voltage Vdata of the previous frame is held. In this regard, the hold frame may be referred to as a skip period in the sense that the process of applying the new data voltage Vdata to the driving transistor DT is omitted in the hold frame.

[0169] Each of the plurality of pixels P may initialize the voltage charged or remaining in the pixel circuit during the refresh frame. Specifically, each of the plurality of pixels P may eliminate the influence of the data voltage Vdata and the high potential driving voltage EVDD stored in the previous frame during the refresh frame. Therefore, each of the plurality of pixels P may display an image corresponding to the new data voltage Vdata in the hold frame.

[0170] During the holding frame, each of the plurality of pixels P may provide a driving current corresponding to the data voltage Vdata to the light emitting element OLED to display an image, and may maintain the on state of the light emitting element OLED.

[0171] Reference Figure 5 , the refresh frame may include at least one bias period Tobs1 and Tobs2, an initialization period Ti, a sampling period Ts, and a light emitting period Te. However, this is only an example, and the embodiments of the present invention are not necessarily limited to this order.

[0172] At least one bias period Tobs1 and Tobs2 refers to a period in which an on-bias stress (OBS) operation is performed (in which a bias voltage Vobs is applied). In at least one bias period, the light emission control signal EM(n) is at a high voltage, and the third transistor T3 and the fourth transistor T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are at a low voltage, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2(n) is at a high voltage, and the second transistor T2 is turned off.

[0173] In at least one bias period Tobs1 and Tobs2, the third scan signal SC3(n) of low voltage is inputted so that the fifth transistor T5 and the sixth transistor T6 are turned on. As the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the driving transistor DT connected to the second node N2.

[0174] In this regard, the bias voltage Vobs is provided to the second node N2 as the source of the driving transistor DT. Therefore, in the light emission period, the charging time or charging delay of the voltage of the fifth node N5 as the anode of the light emitting element OLED can be reduced. The driving transistor DT is maintained in a stronger saturation state.

[0175] In this regard, the magnitude of the drain-source current Id flowing through the driving transistor DT can be reduced, and the stress of the driving transistor DT can be reduced in the positive bias stress situation, thereby solving the charging delay of the voltage of the third node N3. In other words, the hysteresis of the driving transistor DT can be alleviated by performing a turn-on bias stress operation on the driving transistor DT before sampling the threshold voltage Vth of the driving transistor DT.

[0176] Reference Figure 5 , the pixel circuit may operate so that the initialization period Ti is included in the refresh frame. The initialization period Ti refers to a period during which the voltage of the gate of the driving transistor DT is initialized.

[0177] In the initialization period Ti, each of the first to fourth scan signals SC1(n) to SC4(n) and the light emitting control signal EM(n) is at a high voltage, and the first transistor T1 and the seventh transistor T7 are turned on. The second to sixth transistors T2, T3, T4, T5, and T6 are turned off. As the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the driving transistor DT connected to the first node N1 are initialized with the second initialization voltage Vini.

[0178] Reference Figure 5 , the pixel circuit may operate so that the sampling period Ts is included in the refresh frame. The sampling period refers to a period during which the threshold voltage Vth of the driving transistor DT is sampled.

[0179] In the sampling period Ts, each of the first scan signal SC1(n), the third scan signal SC3(n) and the light emitting control signal EM(n) is at a high voltage, and the second scan signals SC2_O(n) and SC2_E(n) of low voltage and the fourth scan signal SC4(n) are input. Therefore, the third to seventh transistors T3, T4, T5, T6 and T7 are turned off, the first transistor T1 is kept in the on state, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on, so that the data voltage Vdata is applied to the driving transistor DT, thereby establishing a diode connection between the first node N1 and the third node N3, so that the threshold voltage Vth of the driving transistor DT can be sampled.

[0180] Reference Figure 5 , the pixel circuit can be operated so that the light emitting period Te is included in the refresh frame. The light emitting period Te refers to a period in which the sampled threshold voltage Vth of the driving transistor DT is offset and the light emitting element OLED emits light at a driving current corresponding to the sampled data voltage Vdata.

[0181] In the light emitting period Te, the light emitting control signal EM(n) is at a low voltage, and the third transistor T3 and the fourth transistor T4 are turned on.

[0182] As the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 can be applied to the first electrode of the driving transistor DT connected to the second node N2 via the third transistor T3. The driving current Id provided to the light emitting element OLED from the driving transistor DT via the fourth transistor T4 can depend on the value of the data voltage Vdata, regardless of the value of the threshold voltage Vth of the driving transistor DT. Therefore, the threshold voltage Vth of the driving transistor DT is compensated.

[0183] Reference Figure 5 , describing the operation of the pixel circuit and the light-emitting element in the hold frame.

[0184] The hold frame may include at least one bias period Tobs3 and a light emitting period Te'. Description of the same operation of the pixel circuit in the hold frame as that in the refresh frame will be omitted.

[0185] As described above, in the refresh frame, a new data voltage Vdata is charged to apply the new data voltage Vdata to the gate of the driving transistor DT. However, in the hold frame, the data voltage Vdata of the refresh frame is held. Therefore, unlike the refresh frame, the hold frame does not require an initialization period Ti and a sampling period Ts.

[0186] Reference Figure 5 , the difference between the driving signal in the above refresh frame and the driving signal in the hold frame is about the second scan signal SC2(n) and the fourth scan signal SC4(n). In the hold frame, the initialization period Ti and the sampling period Ts are unnecessary. Therefore, unlike the refresh frame, in the hold frame, the second scan signals SC2_O(n) and SC2_E(n) are always at a high voltage, and the fourth scan signal SC4(n) is always at a low voltage. That is, the second transistor T2 and the seventh transistor T7 are always turned off.

[0187] Figure 6 is a diagram showing a configuration of a gate driver in a display device according to an exemplary embodiment.

[0188] Reference Figure 6, the gate driver 300 includes a light emission control driver 310 and a scan driver 320. The scan driver 320 may include first to fourth scan drivers 321, 322, 323, 324. In addition, the second scan driver 322 may be composed of an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E. In other words, each stage STG1 to STG(n) of the shift register may include: each of the first scan signal generators 321(1) to 321(n); each of the second scan signal generators 322_O(1) to 322_O(n) and 322_E(1) to 322_E(n); each of the third scan signal generators 323(1) to 323(n); each of the fourth scan signal generators 324(1) to 324(n); and each of the light emission control signal generators 310(1) to 310(n).

[0189] The gate driver 300 may include shift registers that may be symmetrically disposed on opposite sides of the display area AA, respectively. The second scan drivers 322_O and 322_E, the fourth scan driver 324, and the light emission control driver 310 may be disposed in a side region around the display area AA. The first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323 may be disposed in the other side region around the display area. However, embodiments of the present invention are not limited thereto; according to an exemplary embodiment, at least one of the second scan drivers 322_O and 322_E, the fourth scan driver 324, and the light emission control driver 310 may be disposed in the other side region around the display area AA, and at least one of the first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323 may be disposed in a side region around the display area AA.

[0190] In a side area around the display area AA, the second scan drivers 322_O and 322_E may be disposed adjacent to the display area AA, the fourth scan driver 324 may be disposed in the outermost area, and the light emission control driver 310 may be disposed between the second scan drivers 322_O and 322_E and the fourth scan driver 324.

[0191] Alternatively, according to an exemplary embodiment, the light emission control driver 310 may be disposed in the outermost area.

[0192] In addition, in the other side area around the display area AA, the second scan drivers 322_O and 322_E can be arranged adjacent to the display area AA, the first scan driver 321 can be arranged in the outermost area, and the third scan driver 323 can be arranged between the second scan drivers 322_O and 322_E and the first scan driver 321.

[0193] Alternatively, according to an exemplary embodiment, the third scan driver 323 may be disposed in the outermost area.

[0194] In addition, the second scan drivers 322_O and 322_E may be divided into an odd-numbered scan driver 322_O and an even-numbered scan driver 322_E. The odd-numbered scan driver 322_O may be respectively arranged on opposite sides of the display area AA. The even-numbered scan driver 322_E may be respectively arranged on opposite sides of the display area AA. When the second scan driver operates so that the odd-numbered scan driver 322_O and the even-numbered scan driver 322_E operate separately, sufficient time required for sampling the data voltage Vdata may be ensured. In addition, the odd-numbered scan driver 322_O is respectively arranged on opposite sides of the display area AA, and the even-numbered scan driver 322_E is respectively arranged on opposite sides of the display area AA, thereby reducing the difference between the sampling times of the data voltage Vdata in the pixel. Therefore, when the second scan drivers 322_O and 322_E operate, sufficient time for sampling may be ensured, and the difference between the sampling times of the pixels may be reduced when sampling the data voltage Vdata, thereby improving the image quality of the display panel.

[0195] Each of the light emission control driver 310 and the first to fourth scan drivers 321 to 324 operates in response to reception of each of a start signal and a clock signal applied via each of a plurality of start signal lines VSTL and a plurality of clock signal lines CLKL.

[0196] In this regard, the clock signal may have different phases, multiple clock signals may be applied via multiple different clock signal lines, and the clock signals applied to the same gate driver may be applied via adjacent clock signal lines CLKL, respectively. In other words, in response to the reception of a start signal and a clock signal, each of the light emitting control driver 310 and the first to fourth scan drivers 321 to 324 may output a gate signal to the pixel circuit. The clock signal includes a first clock signal and a second clock signal. The first clock signal and the second clock signal are applied via adjacent clock signal lines CLKL, respectively, and adjacent clock signal lines CLKL may form a pair. The controller 200 may control the display panel to operate separately in a refresh period or a holding period based on a refresh rate. The holding period may have a portion in which each of the first start signal and the second start signal is output at a fixed voltage level. Each of the first clock signal and the second clock signal may be continuously switched (toggle) in each of the refresh period and the holding period. The first clock signal, the second clock signal, the first start signal and the second start signal may be applied via the data driver 400. The first start signal and the second start signal may be applied via different signal lines, respectively.

[0197] Reference Figure 6 , power lines VL such as the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL may be disposed in the link area LA between the gate driver 300 and the display area AA. The power lines VL may be disposed adjacent to the display area in the following order: the bias voltage bus VobsL, the second initialization voltage bus ViniL, and the first initialization voltage bus VarL. However, the arrangement order is not limited thereto, and it may be varied according to design.

[0198] The power line VL can provide the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini as a DC voltage DC from the power supply 500 to the pixel circuit via power connection lines branched from the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL, respectively.

[0199] In the drawings, it is shown that the power lines VL are arranged on opposite sides of the display area AA in a symmetrical manner. However, the embodiments of the present invention are not limited thereto, and the power lines VL may be located only on the left or right side of the display area AA. Alternatively, the power lines may be located only on the upper side or the lower side of the display area AA.

[0200] The power line VL and the source or drain electrode 140 may be made of the same material and may be disposed in the same layer. The power line VL and the connection electrode 155 may be made of the same material and may be disposed in the same layer.

[0201] At least a portion of the power connection line and the gate electrodes 125 and 126 may be made of the same material and may be arranged in the same layer. Optionally, at least a portion of the power connection line and the touch electrode layers 194, 195, 196 may be made of the same material and may be arranged in the same layer. Optionally, at least a portion of the power connection line and the semiconductor layers 115 and 116 may be made of the same material and may be arranged in the same layer. In addition, at least a portion of the power connection line and the shielding metal layer not shown in the figure may be made of the same material and may be arranged in the same layer.

[0202] Fig. 7A is a diagram showing a configuration of a shift register of a gate driver according to an exemplary embodiment of the present invention, Figure 7B yes Fig. 7A An example of a driver circuit for a shift register in FIG.

[0203] Reference Fig. 7AThe light emission control signal generators 310(1) to 310(n) of the light emission control driver 310 may receive the light emission control start signal EVST, the first light emission control clock signal ECLK1, and the second light emission control clock signal ECLK2, and may output light emission control signals EM(1) to EM(n) via a plurality of light emission control lines EML. The light emission control driver 310 may apply the same signal to odd pixel rows and even pixel rows.

[0204] The first scan signal generators 321(1) to 321(n) of the first scan driver 321 may receive the first start signal SC1_VST, the (1-1)th clock signal SC1_GCLK1, and the (1-2)th clock signal SC1_GCLK2, and may output a plurality of first scan signals SC1(1) to SC1(n) through a plurality of first scan lines SCL1.

[0205] The fourth scan signal generators 324(1) to 324(n) of the fourth scan driver 324 may receive the fourth start signal SC4_VST, the (4-1)th clock signal SC4_GCLK1, and the (4-2)th clock signal SC4_GCLK2, and may output a plurality of fourth scan signals SC4(1) to SC4(n) via a plurality of fourth scan lines SCL4.

[0206] The shift register structure of each of the first scan driver 321 and the fourth scan driver 324 may be the same as the shift register structure of the light emission control driver 310 .

[0207] The clock signal lines CLKL corresponding to the light emission control signal generators 310(1) to 310(n) may be alternately connected to the odd-numbered stages and the even-numbered stages so that each of the light emission control signal generators 310(1) to 310(n) may receive only one clock signal. Fig. 7A As shown, the first light emitting control clock signal ECLK1 may be applied to odd-numbered stages, and the second light emitting control clock signal ECLK2 may be applied to even-numbered stages.

[0208] As in the light emitting control driver 310, the clock signal line CLKL corresponding to the scan signal generator of each of the first scan driver 321, the third scan driver 323 and the fourth scan driver 324 can be alternately connected to the odd stages and the even stages, so that each scan signal generator of each of the first scan driver 321, the third scan driver 323 and the fourth scan driver 324 can receive only one clock signal.

[0209] The gate signal output from each signal generator of each of the light emission control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be affected by the start signal instead of the clock signal. Therefore, only one clock signal may be applied.

[0210] In addition, the light emitting control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be arranged on the left or right side of the display area AA, and may provide corresponding gate signals to a plurality of pixels P connected thereto via corresponding gate lines GL. This mechanism may be a single feeding scheme. However, the embodiments of the present invention are not limited thereto. The light emitting control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be arranged in a symmetrical structure on opposite sides of the display area AA, and may provide the same signal to the corresponding gate lines GL. This mechanism may be a dual feeding scheme.

[0211] In addition, the same gate signal output from each of the light emission control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be applied to two pixel rows arranged in the display area AA. This structure may be a dual row sharing structure.

[0212] In addition, it is shown that the clock signal line CLKL for applying the first and second emission control clock signals ECLK1 and ECLK2 is disposed outwardly with respect to the start signal line VSTL for applying the emission control start signal EVST. However, the embodiments of the present invention are not limited thereto.

[0213] exist Fig. 7A In FIG. 1 , ERO represents an output terminal for outputting a light emitting signal, and Carry represents an enable terminal for inputting a light emitting signal at a previous stage as an enable signal at a subsequent stage.

[0214] Figure 7B The driver circuit of the light emission control driver 310 is shown. Its configuration can be applied to the driver circuit of each of the first scan driver 321, the third scan driver 323, and the fourth scan driver 324.

[0215] Reference Figure 7B, the driver circuit of the light emitting control driver 310 may include: a (1-1)th gate transistor T11, a (1-2)th gate transistor T12, a (1-3)th gate transistor T13, a (1-4)th gate transistor T14, a (1-5)th gate transistor T15, a (1-6)th gate transistor T16, a first transfer transistor TA, a first capacitor CQ1, a second capacitor CQB1 and a third capacitor CC1.

[0216] The (1-1)th gate transistor T11 can pull up the output in response to the signal of the Q1 node, and the (1-2)th gate transistor T12 can pull down the output in response to the signal of the QB1 node. The (1-3)th gate transistor T13 provides the start signal EVST or the output signal EM[n-1] at the previous stage to the Q12 node in response to the clock signal ECLK. The (1-4)th gate transistor T14 transmits the high potential voltage VEH to the Q11 node in response to the start signal EVST or the output signal EM[n-1] at the previous stage. The (1-5)th gate transistor T15 provides the clock signal ECLK to the QB1 node in response to the voltage of the Q11 node. The (1-6)th gate transistor T16 transmits the high potential voltage VEH to the QB1 node in response to the voltage of the Q12 node.

[0217] The first transfer transistor TA transfers the charge of the Q12 node to the Q1 node in response to the low potential voltage VEL. The first transfer transistor TA may be connected to the Q12 node and the Q1 node and disposed between the Q12 node and the Q1 node, and serves as a buffer to prevent a sudden change in the voltage applied to the Q1 node. The first transfer transistor TA continuously electrically connects the Q1 node and the Q12 node to each other. Therefore, the voltage of the Q12 node may be maintained equal to the voltage of the Q1 node.

[0218] The first capacitor CQ1 may be coupled to and disposed between the Q1 node and the output terminal. The second capacitor CQB1 may be coupled to and disposed between the QB1 node and the high potential voltage VEH. The third capacitor CC1 may be coupled to and disposed between the clock signal ECLK and the drain of the transistor T14, and coupled to and disposed between the clock signal ECLK and the gate of the transistor T15.

[0219] The first capacitor CQ1 and the second capacitor CQB1 may operate as a bootstrap capacitor, and the third capacitor CC1 may operate as a stabilization capacitor.

[0220] In addition, the third capacitor CC1 may be designed to have a larger capacity than that of the first capacitor CQ1 or the second capacitor CQB1. In other words, the third capacitor CC1 may occupy a larger area than that of the first capacitor CQ1 or the second capacitor CQB1.

[0221] Fig. 8A is a diagram showing a configuration of a shift register of another gate driver according to an exemplary embodiment of the present invention, Figure 8B yes Fig. 8A An example of a driver circuit for a shift register in FIG.

[0222] Reference Fig. 8A The second scan signal generators 322(1) to 322(n) of the second scan driver 322 can receive the second start signal SC2_GVST, the (2-1)th clock signal SC2_GCLK1 and the (2-2)th clock signal SC2_GCLK2, and can output a plurality of second scan signals SC2(n-1) to SC2(n+2) via a plurality of second scan lines SCL2.

[0223] The clock signal lines CLKL corresponding to the second scan signal generators 322(1) to 322(n) may be connected to the respective stages so that each of the second scan signal generators 322(1) to 322(n) receives two clock signals. Fig. 8A As shown, the second scan signal generator 322 (n) may be composed of an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E. The odd-numbered (2-1)th clock signal SC2_O_GCLK1 and the odd-numbered (2-2)th clock signal SC2_O_GCLK2 may be applied to the odd-numbered second scan driver 322_O disposed in the odd-numbered stage. The even-numbered (2-1)th clock signal SC2_E_GCLK1 and the even-numbered (2-2)th clock signal SC2_E_GCLK2 may be applied to each even-numbered second scan driver 322_E disposed in the even-numbered stage. In other words, a plurality of clock signal lines CLKL may be alternately connected to the odd-numbered stage and the even-numbered stage.

[0224] The gate signal output from each of the scan signal generators of the second scan driver 322 may be affected by the clock signal instead of the start signal. Therefore, at least two clock signals may be applied.

[0225] In addition, the second scan driver 322 may be symmetrically arranged on opposite sides of the display area AA, respectively, and may provide the same signal to one gate line GL. This mechanism may be a dual-feed mechanism. However, the embodiments of the present invention are not limited thereto. The second scan driver 322 may be arranged on the left or right side of the display area AA, and may provide gate signals to a plurality of pixels P connected thereto via one gate line GL. This mechanism may be a single-feed mechanism.

[0226] In addition, the same gate signal output from the second scan driver 322 may be provided to one pixel row arranged in the display area AA. The second scan driver 322 may be respectively disposed on opposite sides of the display panel and apply the same signal to the same pixel row. This configuration may be a single row sharing structure.

[0227] In addition, it is shown that the clock signal line CLKL to which the even-numbered (2-1)th clock signal SC2_E_GCLK1 and the even-numbered (2-2)th clock signal SC2_E_GCLK2 are applied is arranged outwardly relative to the clock signal line CLKL to which the odd-numbered (2-1)th clock signal SC2_O_GCLK1 and the odd-numbered (2-2)th clock signal SC2_O_GCLK2 are applied. However, the embodiments of the present invention are not limited thereto.

[0228] Hereinafter, for the convenience of description, the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished from each other, but are collectively referred to as one second scan driver 322. Clock signals respectively input to the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished from each other, but are collectively referred to as one clock signal. Start signals respectively input to the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished from each other, but are collectively referred to as one start signal.

[0229] exist Fig. 8A In FIG. 1 , SRO_O and SRO_E represent output terminals for outputting the second scan signal SC2 , and Carry represents an enable terminal for inputting the second scan signal SC2 at a previous stage as an enable signal at a subsequent stage.

[0230] Reference Figure 8B , the driver circuit of the second scan driver 322 may include a plurality of gate transistors T21, T22, T23, T24, T25, T26, T27, and TB and at least one capacitor CQ2, CQB2, and CC2.

[0231] The driver circuit of the second scan driver 322 may include: a fourth capacitor CQ2, which is electrically connected to the Q2 node and the output terminal of the gate signal and is arranged between the Q2 node and the output terminal of the gate signal; and a fifth capacitor CQB2, which is electrically connected to the QB2 node and the input terminal of the second gate drive voltage VGH2 and is arranged between the QB2 node and the input terminal of the second gate drive voltage VGH2.

[0232] The fourth capacitor CQ2 and the fifth capacitor CQB2 may operate as bootstrap capacitors.

[0233] In addition, the driver circuit of the second scan driver 322 may include a sixth capacitor CC2 electrically connected to the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1 and disposed between the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1.

[0234] The capacity of the sixth capacitor CC2 may be set to a capacity such that the sixth capacitor can stably control the voltage level of the Q21 node. Therefore, the sixth capacitor may operate as a stabilizing capacitor.

[0235] The capacity of the sixth capacitor CC2 may be the same as or different from the capacity of the fourth capacitor CQ2 or the fifth capacitor CQB2. In other words, the sixth capacitor CC2 may be designed to have a larger capacity than the capacity of the fourth capacitor CQ2 or the fifth capacitor CQB2, and may occupy an area larger than the area occupied by the fourth capacitor CQ2 or the fifth capacitor CQB2.

[0236] The input terminal of the (2-1)th clock signal SC2_GCLK1 may refer to the input terminal of the (2-1)th clock signal SC2_GCLK1 electrically connected to the gate node of the (2-4)th gate transistor T24. Alternatively, the input terminal of the (2-1)th clock signal SC2_GCLK1 may refer to the input terminal of the (2-1)th clock signal SC2_GCLK1 electrically connected to the (2-1)th gate transistor T21.

[0237] A line for supplying the (2-1)th clock signal SC2_GCLK1 to the (2-4)th gate transistor T24 and a line for supplying the (2-1)th clock signal SC2_GCLK1 to the (2-6)th gate transistor T26 may be the same as or different from each other.

[0238] Due to the sixth capacitor CC2, capacitance may be generated between the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1. The voltage level of the Q21 node may vary according to the voltage level of the (2-1)th clock signal SC2_GCLK1.

[0239] Therefore, since the (2-1)th clock signal SC2_GCLK1 of a low level is provided at the time when the low level scan signal is output, the voltage level of the Q21 node may be maintained at a low level.

[0240] In addition, since the low level of the Q21 node is maintained by the sixth capacitor CC2, the on state of the (2-5)th gate transistor T25 can be maintained.

[0241] Since the turn-on state of the (2-5)th gate transistor T25 is maintained, the (2-2)th clock signal SC2_GCLK2 of a high level may be normally provided to the QB2 node.

[0242] Since the high level voltage is normally charged to the QB2 node, the (2-3)th gate transistor T23 and the (2-7)th gate transistor T27 may maintain a turned-off state.

[0243] Therefore, the voltage level of each of the Q22 node and the Q2 node can be stably maintained, and a low-level gate signal can be normally output via the output terminal.

[0244] Fig. 9 7 and 8 are signal waveform diagrams of the start signal and the clock signal applied to the gate driver.

[0245] Reference Fig. 9 Each of the light emission control driver 310 and the first to fourth scan drivers 321 to 324 can be individually operated in the refresh period and the hold period according to the operating frequency. The start signal and the clock signal applied via the plurality of start signal lines VSTL and the plurality of clock signal lines CLKL can be applied according to the operating frequency.

[0246] In other words, during the refresh period, the start signal and the clock signal may be applied so that the pixel circuit operates separately in at least one bias period Tobs1 and Tobs2, the initialization period Ti, the sampling period Ts, and the light emitting period Te. During the holding period, the pixel circuit does not need the initialization period Ti and the sampling period Ts. Thus, during the holding period, only some start signals at the on level may be applied only in the bias period Tobs3, or may be applied only in the light emitting period Te'. The remaining start signals may be applied at a fixed voltage level. At this time, all clock signals applied to each of the light emitting control driver 310 and the plurality of scanning drivers 320 may be continuously switched during the holding period.

[0247] In a high temperature or high humidity environment, due to moisture penetration, OH-charge may be generated in the display panel 100 and the IC package 401. However, all clock signals may be switched so that charge migration between adjacent bumps of the IC package 401 may be reduced. In addition, film peeling between insulating layers due to charge migration may be reduced.

[0248] Each of the start signal and the clock signal applied to the gate driver 300 may be controlled in such a manner that the display device may be stably operated even in a high temperature or high humidity environment in a low speed operation.

[0249] A display device according to various aspects and features of the present invention can be described as follows.

[0250] One aspect of the present invention provides a display device, comprising: a display panel, the display panel including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a light-emitting control driver, the light-emitting control driver being configured to receive a first start signal and a first clock signal and provide a light-emitting control signal to the display panel; at least one scan driver, the scan driver being configured to receive a second start signal and a second clock signal and provide a scan signal to the display panel; and a controller, the controller being configured to control the display panel to operate separately in a refresh period or a holding period based on a refresh rate, wherein the holding period has a portion for outputting each of the first start signal and the second start signal at a fixed voltage level, wherein each of the first clock signal and the second clock signal is used to continuously switch in each of the refresh period and the holding period.

[0251] According to some features of the display device of the present invention, the first clock signal, the second clock signal, the first start signal and the second start signal are applied via a data driver.

[0252] According to some features of the display device of the present invention, the data driver includes a plurality of bumps, and the plurality of bumps include input bumps and output bumps.

[0253] According to some features of the display device of the present invention, the input bumps are arranged in one row, and the output bumps are arranged in three rows.

[0254] According to some features of the display device of the present invention, each of the plurality of bumps overlaps the gate, the first source / drain, the second source / drain, and the touch electrode in the bump region.

[0255] According to some features of the display device of the present invention, in the bump region, the second source / drain has a width greater than that of the first source / drain.

[0256] According to some features of the display device of the present invention, in the bump region, the second source / drain covers the first source / drain.

[0257] According to some features of the display device of the present invention, a planarization layer is formed in the bump region to cover at least a portion of the second source / drain.

[0258] According to some features of the display device of the present invention, in the bump region, there is no insulating layer between the first source / drain and the second source / drain.

[0259] According to some features of the display device of the present invention, the first clock signal or the second clock signal is applied via bumps adjacent to each other respectively.

[0260] According to some features of the display device of the present invention, the first clock signal is applied via a first clock signal line, and the second clock signal is applied via a second clock signal line.

[0261] According to some features of the display device of the present invention, at least some of the plurality of bumps are used to be electrically connected to each other.

[0262] According to some features of the display device of the present invention, the first start signal and the second start signal are applied via different signal lines respectively.

[0263] According to some features of the display device of the present invention, the first clock signal or the second clock signal includes a plurality of clock signals with different phases.

[0264] According to some features of the display device of the present invention, the plurality of clock signals are applied via a plurality of different clock signal lines respectively.

[0265] According to some features of the display device of the present invention, at least some of the plurality of different clock signal lines are adjacent to each other to form a pair.

[0266] According to some features of the display device of the present invention, the scan driver includes a plurality of scan drivers configured to respectively output a plurality of different scan signals.

[0267] According to some features of the display device of the present invention, the scan driver includes a first scan driver, a second scan driver, a third scan driver and a fourth scan driver.

[0268] According to some features of the display device of the present invention, the second scan driver includes a plurality of second scan drivers, which are respectively arranged on opposite sides of the display panel and are configured to apply the same signal to the same pixel row.

[0269] According to some features of the display device of the present invention, the light emission control driver is configured to apply the same signal to the odd pixel rows and the even pixel rows.

[0270] Although the embodiments of the present invention are described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, but can be implemented in various forms. It can be recognized by a person skilled in the art that the present invention can be practiced in other specific forms without changing the technical spirit or essential characteristics of the present invention. Therefore, it should be recognized that the above-described embodiments are not restrictive, but exemplary in all aspects. The scope of protection of the present invention should not be interpreted solely based on the attached claims, and all technical features within their equivalent ranges should be interpreted as being included within the scope of the present invention.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a light emission control driver configured to receive a first start signal and a first clock signal and provide a light emission control signal to the display panel; at least one scan driver configured to receive a second start signal and a second clock signal and provide a scan signal to the display panel; as well as a controller configured to control the display panel to operate separately in a refresh period or a hold period based on a refresh rate, wherein the holding period has a portion for outputting each of the first start signal and the second start signal at a fixed voltage level, Each of the first clock signal and the second clock signal is configured to switch continuously in each of the refresh period and the hold period. 2 . The display device according to claim 1 , wherein the first clock signal, the second clock signal, the first start signal, and the second start signal are applied via a data driver. 3 . The display device of claim 2 , wherein the data driver comprises a plurality of bumps, the plurality of bumps comprising input bumps and output bumps. 4 . The display device according to claim 3 , wherein the input bumps are arranged in one row, and the output bumps are arranged in three rows. 5 . The display device according to claim 3 , wherein each of the plurality of bumps overlaps a gate, a first source / drain, a second source / drain, and a touch electrode of a transistor located in a pixel circuit of a pixel among the plurality of pixels and in a bump region. 6 . The display device according to claim 5 , wherein in the bump region, the second source / drain has a width greater than that of the first source / drain. 7 . The display device according to claim 5 , wherein in the bump region, the second source / drain covers the first source / drain. 8 . The display device according to claim 5 , wherein in the bump region, a planarization layer is formed to cover at least a portion of the second source / drain. 9 . The display device according to claim 5 , wherein in the bump region, there is no insulating layer between the first source / drain and the second source / drain. 10 . The display device according to claim 3 , wherein the first clock signal or the second clock signal is applied via bumps adjacent to each other. 11 . The display device according to claim 10 , wherein the first clock signal is applied via a first clock signal line, and the second clock signal is applied via a second clock signal line. 12 . The display device according to claim 3 , wherein at least some of the plurality of bumps are used to be electrically connected to each other. 13 . The display device according to claim 1 , wherein the first start signal and the second start signal are applied via different signal lines, respectively. 14 . The display device according to claim 1 , wherein the first clock signal or the second clock signal comprises a plurality of clock signals having different phases. 15 . The display device according to claim 14 , wherein the plurality of clock signals are applied via a plurality of different clock signal lines respectively. 16 . The display device according to claim 15 , wherein at least some of the plurality of different clock signal lines are adjacent to each other to form a pair. 17 . The display device according to claim 1 , wherein the scan driver comprises a plurality of scan drivers configured to respectively output a plurality of different scan signals. 18 . The display device of claim 17 , wherein the scan driver comprises a first scan driver, a second scan driver, a third scan driver, and a fourth scan driver.

19. The display device according to claim 18, wherein the second scan driver comprises a plurality of second scan drivers, The plurality of second scan drivers are respectively disposed on opposite sides of the display panel and are configured to apply the same signal to the same pixel row. 20 . The display device according to claim 17 , wherein the light emission control driver is configured to apply the same signal to odd-numbered pixel rows and even-numbered pixel rows.

21. The display device according to claim 3, wherein the plurality of bumps have the same thickness.

22. The display device according to claim 18, wherein in a side area around the display area, the second scan driver is arranged adjacent to the display area, the fourth scan driver is arranged in an outermost area, and the light emitting control driver is arranged between the second scan driver and the fourth scan driver. 23 . The display device according to claim 18 , wherein the light emission control driver is disposed in an outermost area in a side area around the display area.

24. The display device according to claim 22, wherein in the other side area around the display area, the second scan driver is arranged adjacent to the display area, the first scan driver is arranged in the outermost area, and the third scan driver is arranged between the second scan driver and the first scan driver. 25 . The display device of claim 22 , wherein in the other side region around the display area, the third scan driver is disposed in an outermost region.

26. The display device according to claim 18, wherein the light emitting control driver, the first scanning driver, the third scanning driver and the fourth scanning driver are arranged on the left side or the right side of the display area, and are configured to provide corresponding gate signals to a plurality of connected pixels via corresponding gate lines of the display panel.

27. The display device according to claim 18, wherein the light emitting control driver, the first scanning driver, the third scanning driver and the fourth scanning driver are arranged in a symmetrical structure on opposite sides of the display area and are configured to provide the same signal to the corresponding gate lines of the display panel.

28. The display device according to claim 19, wherein the second scan driver comprises a plurality of odd-numbered scan drivers and a plurality of even-numbered scan drivers, The odd-numbered scan drivers are respectively arranged on opposite sides of the display area, the even-numbered scan drivers are respectively arranged on opposite sides of the display area, and the odd-numbered scan drivers and the even-numbered scan drivers are configured to operate separately.

29. The display device according to claim 5, further comprising a power supply line for providing a bias voltage and an initialization voltage to the pixel circuit, The power line and the first source / drain are made of the same material and are arranged in the same layer.

30. The display device according to claim 29, wherein the power line is configured to provide the bias voltage and the initialization voltage via a power connection line, At least a portion of the power connection line and the gate electrode or the touch electrode are made of the same material and are arranged in the same layer.

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