A storage device, a method for operating the storage device, and a storage system.

Abstract

This application provides a storage device, a storage device operation method, and a storage system, relating to the field of semiconductor chip technology. The storage device includes a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cell array includes a first storage cell and a second storage cell coupled to the same bit line and adjacent to each other. The peripheral circuitry includes a page buffer circuit, which includes: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node and configured to latch the programming state of the first storage cell; a charge / discharge circuit coupled to the sensing node and configured to charge and discharge the sensing node, the discharge duration of which is related to the programming state; and a second latch circuit coupled to the sensing node and configured to latch information on whether the second storage cell has passed programming verification based on the voltage value of the sensing node after the discharge duration. This application shortens the programming time of the storage device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip technology, and in particular relates to a storage device, a storage device operation method, and a storage system. Background Technology

[0002] NAND flash memory, as a non-volatile storage device, has advantages such as low cost, high capacity, and fast rewrite speed. In NAND flash memory, peripheral circuits typically supply power to the storage cells to implement various logical operations, such as read, program, and erase operations. Summary of the Invention

[0003] The embodiments disclosed in this application provide a storage device, a storage device operation method, and a storage system for shortening the programming time of the storage device.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a storage device is provided, comprising a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cell array includes a first storage cell and a second storage cell coupled to the same bit line, the first and second storage cells being adjacent to each other. The peripheral circuitry includes a page buffer circuit, comprising: a sensing node coupled to the bit line; a first latch circuit coupled to the sensing node and configured to latch the programming state of the first storage cell; a charge / discharge circuit coupled to the sensing node and configured to charge and discharge the sensing node; the discharge duration of the sensing node being related to the programming state of the first storage cell; and a second latch circuit coupled to the sensing node and configured to latch information regarding whether the second storage cell has passed programming verification based on the voltage value of the sensing node after the discharge duration.

[0006] This application incorporates a first latch circuit in the page buffer, coupled to a sensing node, configured to latch the programming state of a first memory cell. Therefore, when verifying a second memory cell (adjacent to the first), this application controls the discharge duration of the charging / discharging circuit on the sensing node based on the programming state of the first memory cell latched by the first latch circuit. At the same verification voltage, a longer discharge duration results in more charge released by the sensing node, a greater voltage drop, and greater difficulty for the second memory cell to pass verification. This allows for continued programming of the second memory cell, leading to the storage of more charge. In other words, different discharge durations at the same verification voltage can result in different amounts of charge stored in the second memory cell. For the same programming level, conventional methods use multiple (at least two) different verification voltages for repeated verification of the second memory cell, resulting in varying amounts of charge stored. Therefore, compared to conventional methods, this application uses only one verification voltage to verify the second memory cell for the same programming level, significantly reducing the programming time.

[0007] In some embodiments, the charge / discharge circuit includes a charging circuit and a discharging circuit. A first terminal of the charging circuit is configured to receive an input supply voltage, and a second terminal of the charging circuit is coupled to a sensing node and configured to charge the sensing node. A first terminal of the discharging circuit is coupled to a bit line, and a second terminal of the discharging circuit is coupled to the sensing node and configured to discharge the sensing node. By first charging the sensing node through the charging circuit and then discharging it through the discharging circuit, various bit line voltages are applied to the bit line; for example, a selection programming voltage, a programmable inaccessible voltage, etc.

[0008] In some embodiments, the programming state of the first storage cell includes a first state and a second state, and the threshold voltage of the first storage cell in the first state is greater than the threshold voltage in the second state. When the programming state of the first storage cell is the first state, the discharge duration of the sensing node is a first duration; when the programming state of the first storage cell is the second state, the discharge duration is a second duration; the first duration is less than the second duration. The discharge duration of the sensing node is equal to the difference between the moment when the discharge circuit stops discharging the sensing node and the moment when the charging circuit stops charging the sensing node. Since the programming state of the first storage cell affects the parallel channel charge loss of the second storage cell, after the second storage cell is programmed, if the first storage cell is in the first state, the parallel channel charge loss of the second storage cell is smaller; if the first storage cell is in the second state, the parallel channel charge loss of the second storage cell is larger. Therefore, in the verification stage of the second storage cell, the lower the programming state of the first storage cell, the longer the discharge duration of the sensing node, thereby allowing the second storage cell to store more charge to compensate for the impact of the larger parallel channel charge loss on data retention, thus improving the data retention performance of the storage device.

[0009] In some embodiments, a first latch circuit is coupled to a charging circuit, which includes a first charging sub-circuit and a second charging sub-circuit. A first terminal of the first charging sub-circuit is coupled to a first terminal of the charging circuit, and a second terminal of the first charging sub-circuit is coupled to a second terminal of the charging circuit. A first terminal of the second charging sub-circuit is coupled to a first terminal of the charging circuit, and a second terminal of the second charging sub-circuit is coupled to a second terminal of the charging circuit. When the programming state of the first memory cell is a first state, the first charging sub-circuit charges the sensing node; when the programming state of the first memory cell is a second state, the second charging sub-circuit charges the sensing node. When the charging circuit stops charging the sensing node, the sensing node begins to discharge. The first charging sub-circuit and the second charging sub-circuit stop charging the sensing node at different times, resulting in different times when the sensing node begins to discharge, and ultimately different discharge durations of the sensing node. Specifically, since the first charging sub-circuit stops charging the sensing node after the second charging sub-circuit stops charging the sensing node; that is, the second charging sub-circuit stops charging the sensing node before the first charging circuit. Therefore, the discharge duration of the sensing node in the first state (first duration) is less than the discharge duration of the sensing node in the second state (second duration).

[0010] In some embodiments, the first charging sub-circuit includes a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first terminal of the first charging sub-circuit, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the second transistor is coupled to a second terminal of the first charging sub-circuit, and a control terminal of the second transistor is coupled to an output terminal of a first latch circuit; the peripheral circuit also includes a control logic circuit, the control terminal of the first transistor is coupled to a first output terminal of the control logic circuit; when the programming state of the first memory cell is a first state, the second transistor is turned on; the control logic circuit is configured to: control the first transistor to turn on, so that the first charging sub-circuit charges the sensing node; or, control the first transistor to turn off, so that the first charging sub-circuit stops charging the sensing node. This application controls the on / off state of the second transistor through the programming state of the first memory cell. When the programming state of the first memory cell is a first state, such that the second transistor is turned on, the control logic circuit controls the first transistor to enable the first charging sub-circuit to charge the sensing node.

[0011] In some embodiments, the second charging sub-circuit includes a third transistor. A first terminal of the third transistor is coupled to a first terminal of the second charging sub-circuit, a second terminal of the third transistor is coupled to a second terminal of the second charging sub-circuit, and a control terminal of the third transistor is coupled to a second output terminal of the control logic circuit. When the programming state of the first memory cell is the second state, the second transistor is turned off. The control logic circuit is configured to: control the third transistor to turn on, so that the second charging sub-circuit charges the sensing node; or, control the third transistor to turn off, so that the second charging sub-circuit stops charging the sensing node. This application controls the on / off state of the second transistor through the programming state of the first memory cell. When the programming state of the first memory cell is the second state, causing the second transistor to turn off, the control logic circuit controls the third transistor to enable the second charging sub-circuit to charge the sensing node. Specifically, the third transistor turns off first, followed by the first transistor. This ensures that the second charging sub-circuit stops charging the sensing node before the first charging sub-circuit.

[0012] In some embodiments, a first latch circuit is coupled to a discharge circuit, which includes a first discharge circuit and a second discharge circuit. A first terminal of the first discharge circuit is coupled to a first terminal of the discharge circuit, and a second terminal of the first discharge circuit is coupled to a second terminal of the discharge circuit. A first terminal of the second discharge circuit is coupled to a first terminal of the discharge circuit, and a second terminal of the second discharge circuit is coupled to a second terminal of the discharge circuit. When the programming state of the first memory cell is a first state, the first discharge circuit discharges the sensing node; when the programming state of the first memory cell is a second state, the second discharge circuit discharges the sensing node. The first and second discharge circuits stop discharging the sensing node at different times, resulting in different discharge durations for the sensing node. Specifically, since the second discharge circuit stops discharging the sensing node after the first discharge circuit stops discharging it; that is, the first discharge circuit stops discharging the sensing node before the second discharge circuit. Therefore, the discharge duration of the sensing node in the first state (first duration) is less than the discharge duration of the sensing node in the second state (second duration).

[0013] In some embodiments, the second discharge circuit includes a fourth transistor and a fifth transistor. A first terminal of the fourth transistor is coupled to a first terminal of the first discharge circuit, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor, and a second terminal of the fifth transistor is coupled to a second terminal of the first discharge circuit. The control terminal of the fifth transistor is coupled to the output terminal of the first latch circuit. The peripheral circuit also includes a control logic circuit, with the control terminal of the fourth transistor coupled to a third output terminal of the control logic circuit. When the programming state of the first memory cell is the second state, the fifth transistor is turned on, and the control logic circuit is configured to: control the fourth transistor to turn on, causing the second discharge circuit to discharge the sensing node; or, control the fourth transistor to turn off, causing the second discharge circuit to stop discharging the sensing node. This application controls the on / off state of the fifth transistor through the programming state of the first memory cell. When the programming state of the first memory cell is the second state, such that the fifth transistor is turned on, the control logic circuit controls the fourth transistor to achieve the discharge of the sensing node by the second discharge circuit.

[0014] In some embodiments, the first discharge circuit includes a sixth transistor, with a first terminal coupled to a first terminal of the first discharge circuit and a second terminal coupled to a second terminal of the first discharge circuit; the control terminal of the sixth transistor is coupled to a fourth output terminal of the control logic circuit; when the programming state of the first memory cell is a first state, the fifth transistor is turned off, and the control logic circuit is configured to: control the sixth transistor to turn on, and the first discharge circuit discharges the sensing node; or, control the sixth transistor to turn off, and the first discharge circuit stops discharging the sensing node. This application controls the on / off state of the fifth transistor through the programming state of the first memory cell. When the programming state of the first memory cell is a first state, such that the fifth transistor is turned off, the control logic circuit controls the sixth transistor to achieve the first discharge circuit discharging the sensing node. Specifically, the sixth transistor turns off first, followed by the fourth transistor. This ensures that the first discharge circuit stops discharging the sensing node before the second discharge circuit.

[0015] In a second aspect, a method for operating a storage device is provided. The storage device includes a storage cell array and peripheral circuitry coupled to the storage cell array. The peripheral circuitry includes a page buffer circuit. The method includes: latching the programming state of a first storage cell in the storage cell array; during a stage of verifying the programming of a second storage cell in the storage cell array, discharging a sensing node in the page buffer circuit; wherein the discharge duration of the sensing node is related to the programming state of the first storage cell; the first and second storage cells are adjacent and coupled to the same bit line, and the sensing node is coupled to the bit line; after the discharge duration, latching information on whether the second storage cell has passed the programming verification based on the voltage value of the sensing node.

[0016] In some embodiments, discharging a sensing node in a page buffer circuit includes: charging the sensing node, the sensing node being coupled to a second terminal of a charging circuit, the first terminal of the charging circuit being configured as an input supply voltage; applying a bit line voltage to a bit line, the bit line being coupled to a first terminal of a discharge circuit, the second terminal of the discharge circuit being coupled to the sensing node; stopping charging the sensing node and initiating discharge of the sensing node; and stopping the discharge of the sensing node and ceasing discharge of the sensing node.

[0017] In some embodiments, the programming state of the first storage cell includes a first state and a second state, the threshold voltage of the first storage cell in the first state is greater than the threshold voltage in the second state; when the programming state of the first storage cell is the first state, the discharge duration of the sensing node is a first duration; the discharge duration of the sensing node is equal to the difference between the time when discharging the sensing node stops and the time when charging the sensing node stops; when the programming state of the first storage cell is the second state, the discharge duration is a second duration; the first duration is less than the second duration.

[0018] In some embodiments, the discharge duration of the sensing node is related to the programming state of the first memory cell, including: the time at which charging the sensing node stops is related to the programming state of the first memory cell; wherein, when the programming state of the first memory cell is a first state, the first charging sub-circuit in the charging circuit charges the sensing node; when the programming state of the first memory cell is a second state, the second charging sub-circuit in the charging circuit charges the sensing node; and the time when the first charging sub-circuit stops charging the sensing node is after the time when the second charging sub-circuit stops charging the sensing node.

[0019] In some embodiments, when the programming state of the first memory cell is a first state, the second transistor in the first charging sub-circuit is turned on, and the first charging sub-circuit charges the sensing node, including: turning on the first transistor in the first charging sub-circuit, and the first charging sub-circuit charges the sensing node; turning off the first transistor, and the first charging sub-circuit stops charging the sensing node; the first terminal of the first transistor is configured as an input supply voltage, the second terminal of the first transistor is coupled to the first terminal of the second transistor, and the second terminal of the second transistor is coupled to the sensing node.

[0020] In some embodiments, when the programming state of the first memory cell is the second state, the second transistor in the first charging sub-circuit is turned off, and the second charging sub-circuit charges the sensing node, including: turning on the third transistor in the second charging sub-circuit, and the second charging sub-circuit charges the sensing node; turning off the third transistor, and the second charging sub-circuit stops charging the sensing node; the first terminal u of the third transistor is configured as the input power supply voltage, and the second terminal of the third transistor is configured to be coupled to the sensing node.

[0021] In some embodiments, the moment when the first charging sub-circuit stops charging the sensing node is after the moment when the second charging sub-circuit stops charging the sensing node includes: first disconnecting the third transistor, and then disconnecting the first transistor.

[0022] In some embodiments, the discharge duration of the sensing node is related to the programming state of the first memory cell, including: the time at which the discharge of the sensing node stops is related to the programming state of the first memory cell; wherein, when the programming state of the first memory cell is a first state, the first discharge circuit in the discharge circuit discharges the sensing node; when the programming state of the first memory cell is a second state, the second discharge circuit in the discharge circuit discharges the sensing node; and the time when the second discharge circuit stops discharging the sensing node is after the time when the first discharge circuit stops discharging the sensing node.

[0023] In some embodiments, when the programming state of the first memory cell is the second state, the fifth transistor in the second discharge circuit is turned on, and the second discharge circuit discharges the sensing node, including: turning on the fourth transistor in the second discharge circuit, and the second discharge circuit discharges the sensing node; turning off the fourth transistor, and the second discharge circuit stops discharging the sensing node; the first terminal of the fourth transistor is coupled to the bit line, the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor, and the second terminal of the fifth transistor is coupled to the sensing node.

[0024] In some embodiments, when the programming state of the first memory cell is the first state, the fifth transistor in the second discharge circuit is turned off, and the first discharge circuit discharges the sensing node, including: turning on the sixth transistor in the first discharge circuit, and the first discharge circuit discharges the sensing node; turning off the sixth transistor, and the first discharge circuit stops discharging the sensing node; the first terminal of the sixth transistor is coupled to the bit line, and the second terminal of the sixth transistor is coupled to the sensing node.

[0025] In some embodiments, the moment when the second discharge circuit stops discharging the sensing node is after the moment when the first discharge circuit stops discharging the sensing node includes: first disconnecting the sixth transistor, and then disconnecting the fourth transistor.

[0026] In some embodiments, the operation method further includes: during the programming verification phase of the second memory cell in the memory cell array, discharging the sensing node multiple times; the discharge duration is gradually increased. Thus, in the next programming cycle, different bit line voltages can be applied to the second memory cells with different threshold voltages, achieving accurate programming of the second memory cells.

[0027] Thirdly, a storage system is provided, the storage system including a memory controller and a storage device according to any one of the first aspects above, the memory controller being configured to control the storage device.

[0028] Fourthly, a computer-readable storage medium is provided, which stores computer-executable instructions; when executed, the computer-executable instructions are able to implement any of the methods in the second aspect above.

[0029] Fifthly, a computer device is provided, including a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, enable the implementation of any of the methods in the second aspect above.

[0030] Understandably, the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0032] Figure 1 This is a schematic diagram of the threshold voltage distribution of the memory cell provided in an embodiment of this application;

[0033] Figure 2 A schematic diagram comparing the normal threshold voltage distribution and the threshold voltage distribution after charge loss, provided for embodiments of this application;

[0034] Figure 3 This is a schematic diagram illustrating the effect of the programming state of adjacent memory cells on the charge loss of parallel channels in any memory cell, as provided in an embodiment of this application.

[0035] Figure 4 This is a schematic diagram of the structure of the storage system provided in an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the structure of the storage device provided in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of the structure of a storage cell block provided in an embodiment of this application;

[0038] Figure 7 A partial cross-sectional view of the storage cell string provided in the embodiments of this application;

[0039] Figure 8 This is a schematic diagram of the structure of the storage device and peripheral circuit provided in the embodiments of this application;

[0040] Figure 9 This is a schematic diagram of the structure of one type of page buffer provided in an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of another page buffer provided in an embodiment of this application;

[0042] Figure 11 A flowchart illustrating the operation method of the storage device provided in an embodiment of this application;

[0043] Figure 12 A schematic diagram illustrating the discharge process of the sensing node provided in the embodiments of this application;

[0044] Figure 13 This is a schematic diagram of one specific process of S120 provided in an embodiment of this application;

[0045] Figure 14 A waveform diagram of a control signal for charging and discharging a sensing node, provided in an embodiment of this application;

[0046] Figure 15 This is a schematic diagram of another specific process of S120 provided in an embodiment of this application;

[0047] Figure 16 A waveform diagram of another control signal for charging and discharging a sensing node provided in an embodiment of this application;

[0048] Figure 17 This is a schematic diagram of another specific process of S120 provided in the embodiments of this application;

[0049] Figure 18 This is a schematic diagram of the division region for threshold voltage division of the second memory cell in S130 provided in an embodiment of this application;

[0050] Figure 19 This is a schematic diagram of the programming result of the next programming cycle provided in an embodiment of this application.

[0051] Reference numerals: 100, Memory system; 110, Memory controller; 120, Memory device; 200, Memory cell array; 210, Memory cell block; 220, Memory cell string; 221, Top select transistor; 222, Dummy memory cell; 223, Memory cell; 224, Bottom select transistor; 300, Peripheral circuit; 310, I / O interface; 320, Control logic circuit; 330, Row decoder; 340, Voltage generator; 350, Column decoder; 360, Data bus; 370, Register; 380, Page buffer; 410, Memory stack layer; 411, Gate conductive layer; 412, Dielectric layer; 420, Substrate; 430, Top select line; 440, Word line; 450, Bottom select line 500, First latch circuit; 510, First inverter; 520, Second inverter; 530, Seventh transistor; 540, Eighth transistor; 550, Ninth transistor; 600, Charging / discharging circuit; 610, Charging circuit; 611, First transistor; 612, Second transistor; 613, Third transistor; 620, Discharging circuit; 621, Fourth transistor; 622, Fifth transistor; 623, Sixth transistor; 700, Second latch circuit; 710, Third inverter; 720, Fourth inverter; 730, Tenth transistor; 740, Eleventh transistor; 750, Twelfth transistor; 760, Thirteenth transistor; 810, Fourteenth transistor; 820, Fifteenth transistor; 830, Sixteenth transistor. Detailed Implementation

[0052] The following will combine Figures 1-19 The technical solutions in some embodiments of this application are clearly and completely described. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0055] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0056] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0057] Flash memory is a non-volatile storage device that consists of multiple memory cells that can be electrically erased and reprogrammed. The memory cells are programmed to store electrical charge, and erased to remove the stored charge.

[0058] The electric field generated by a charge can affect the threshold voltage (Vt) of a memory cell. Generally, the more charge a memory cell stores, the higher its threshold voltage and the higher its programming level. Figure 1 As shown, based on different threshold voltage distributions, memory cells can be classified into single-level cell (SLC), multi-level cell (MLC), and trinary-level cell (TLC) types. SLC has two programming levels (L0-L1); MLC has four programming levels (L0-L3); and TLC has eight programming levels (L0-L7).

[0059] During a read operation, the programming level of the memory cell can be identified by reading the voltage, thereby reading the data. Taking SLC as an example, when the threshold voltage of the memory cell is greater than the read voltage, the programming level is identified as L1, and the data "0" is read; when the threshold voltage of the memory cell is less than the read voltage, the programming level is identified as L0, and the data "1" is read.

[0060] Charge loss in storage cells is one of the factors affecting the data retention performance of storage devices. For example... Figure 2 As shown, charge loss reduces the threshold voltage of a memory cell, which is reflected in the threshold voltage distribution diagram as a leftward shift and a broadening of the threshold voltage distribution. As a result, after a long period of data retention, the read voltage will be difficult to identify the programming level of the memory cell, ultimately leading to data corruption.

[0061] Charge loss mainly includes vertical channel charge loss and parallel channel charge loss. Vertical channel charge loss is related to the threshold voltage of the memory cell; the higher the threshold voltage, the more severe the vertical channel charge loss. Parallel channel charge loss is related not only to the threshold voltage of the memory cell but also to the programming level of adjacent memory cells, such as... Figure 3 As shown, for any memory cell, when the adjacent memory cell is at a high programming level, the parallel channel charge loss of the memory cell is smaller, while when the adjacent memory cell is at a low programming level, the parallel channel charge loss of the memory cell is larger.

[0062] To compensate for the impact of significant parallel-channel charge loss on data retention performance, multiple verification voltages are used for each programming level during the post-programming verification phase. Taking MLC as an example, a string of memory cells includes a programmed first memory cell and an unprogrammed second memory cell, which are adjacent to each other. When verifying the second memory cell, if the programming level of the adjacent first memory cell is L0, then the verification voltage V... vfy_1 Verification is performed; if the programming level of the adjacent first memory cell is L1, then the verification voltage V is used. vfy_2 Verification is performed; if the programming level of the adjacent first memory cell is L2, then the verification voltage V is used. vfy_3 Verification is performed; if the programming level of the adjacent first memory cell is L3, then the verification voltage V is used. vfy_4 Verification is performed; the voltage V is verified. vfy_1 Greater than the verification voltage V vfy_2 Greater than the verification voltage V vfy_3 Greater than the verification voltage V vfy_4 .

[0063] In other words, the lower the programming level of the first programmed memory cell, the higher the verification voltage is used to verify the second memory cell among multiple verification voltages. Because a higher verification voltage results in more charge being released by the sensing node (SO) in the page buffer coupled to the second memory cell during the sensing duration Tsense, the voltage of the sensing node is further reduced. If the voltage of the sensing node is lower than the threshold voltage, the second memory cell fails verification. Therefore, in the next programming cycle, the second memory cell can be programmed again to increase its threshold voltage (meaning the second memory cell stores more charge). Thus, at the same programming level, compared to memory cells with less parallel-channel charge loss, a higher verification voltage is used for memory cells with more severe parallel-channel charge loss, allowing them to store more charge after programming. Because more charge is stored after programming, even with severe parallel-channel charge loss, the memory cell can retain data for a longer period without corruption, thereby improving the data retention performance of the storage device.

[0064] Furthermore, based on the programming level of the first memory cell, the first memory cell can be divided into multiple programming states; for example, the first memory cell can be divided into two programming states, namely, a first state and a second state. In some embodiments, if the programming level of the first memory cell is L2 or L3, the programming state of the first memory cell can be the first state; if the programming level of the first memory cell is L0 or L1, the programming state of the first memory cell can be the second state. When verifying the second memory cell, if the adjacent first memory cell is in the first state, it is verified by verification voltage Vvfy_1; if the adjacent first memory cell is in the second state, it is verified by verification voltage Vvfy_2. This reduces the number of verification voltages, improving the data retention performance of the storage device while minimizing the programming time. However, repeatedly verifying the same programming level using multiple (not less than two) verification voltages (e.g., applying verification voltage Vvfy_1 and verification voltage Vvfy_2 sequentially) still significantly increases the programming time of the memory cell.

[0065] This application embodiment includes a first latch circuit in the page buffer for latching the programming level of a first memory cell. The first latch circuit is coupled to a sensing node and a charge / discharge circuit configured to discharge the sensing node. When verifying a second memory cell adjacent to the first memory cell, the discharge duration of the charge / discharge circuit on the sensing node is controlled according to the programming level latched by the first latch circuit. At the same verification voltage, a longer discharge duration results in more charge being released from the sensing node, thus lowering its voltage. If the voltage of the sensing node is less than a threshold voltage, the memory cell fails verification. Programming of the memory cell can then continue in the next programming cycle. Therefore, for the same programming level, this application uses a single verification voltage to verify the second memory cell, improving data retention performance while significantly shortening programming time.

[0066] like Figure 4 As shown, this application embodiment provides a storage system 100, which includes a memory controller 110 and a storage device 120. The memory controller 110 is configured to store data to or read data from the storage device 120. The storage system 100 can be applied to and packaged into different types of electronic devices, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and servers—any electronic device capable of storing data.

[0067] Of course, the memory controller 110 can also perform any other suitable functions, such as formatting the storage device 120; for example, the memory controller 110 can communicate with external devices (e.g., a host) through at least one of various interface protocols. The interface protocol can be at least one of the following: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0068] Specifically, such as Figure 5 As shown, the storage device 120 includes a memory array 200 and peripheral circuitry 300 coupled to the memory array 200.

[0069] In the three-dimensional (3D) NAND storage device 120, the storage cell array 200 may include multiple storage cell blocks 210, such as Figure 6 As shown, each memory cell block 210 may include multiple memory cell strings 220. Each memory cell string 220 may include a top select gate (TSG), a dummy (DMY) memory cell 222, multiple memory cells 223, and a bottom select gate (BSG) stacked in series. The memory cell 223 may be a floating gate transistor or a charge trap field-effect transistor or other device capable of storing data.

[0070] Figure 7A partial cross-sectional schematic diagram of a possible memory cell string 220 according to this application is shown. The memory cell string 220 may extend vertically through the memory stack layer 410 above the substrate 420. The substrate 420 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0071] The memory stack layer 410 may include alternating gate conductive layers 411 and dielectric layers 412. The number of gate conductive layers 411 and dielectric layers 412 in the memory stack layer 410 determines the number of memory cells 223 in the memory cell string 220.

[0072] The gate conductive layer 411 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 411 includes a doped polysilicon layer. Each gate conductive layer 411 may include a control gate surrounding the memory cell 223, and the gate conductive layer 411 at the top of the memory stack 410 may extend laterally as a top select line 430 (string select line, SSL), the gate conductive layer 411 at the bottom of the memory stack 410 may extend laterally as a bottom select line 450 (ground select line, GSL), or the gate conductive layer 411 between the top select line 430 and the bottom select line 450 may extend laterally as a word line 440 (word line, WL).

[0073] It should be understood that, despite Figure 7 Additional components, not shown, but which may form the memory cell string 220, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0074] The peripheral circuit 300 is configured to control the memory cell array 200. For example... Figure 8 As shown, the peripheral circuitry 300 may include an I / O interface 310, control logic circuitry 320, a row decoder 330, a voltage generator 340, a column decoder 350, a data bus 360, a register 370, and a page buffer 380. It should be understood that in some examples, it may also include... Figure 8Additional circuitry not shown. The memory cell array 200 can be coupled to the peripheral circuitry 300 via bit lines, common source lines, top select lines 430, word lines 440, bottom select lines 450, etc.; for example, the bit lines are coupled to the page buffer 380, and the word lines 440 are coupled to the line decoder 330.

[0075] I / O interface 310 can be coupled to control logic circuitry 320 and act as a control buffer to buffer data from memory controller 110 (e.g., ...). Figure 4 The I / O interface 310 receives control commands from the memory controller 110 and relays them to the control logic circuit 320, and buffers status information received from the control logic circuit 320 and relays it to the memory controller 110. The I / O interface 310 can also be coupled to the page buffer 380 via the data bus 360, and acts as a data I / O interface 310 and a data buffer to buffer data and relay it to or from the memory cell array 200.

[0076] The control logic circuit 320 can be coupled to the voltage generator 340, page buffer 380, column decoder 350, row decoder 330, and I / O interface 310, and is configured to control the operation of each peripheral circuit 300. The control logic circuit 320 can generate operation signals in response to commands (CMD) or control signals from the memory controller 110 to control the operation of the row decoder 330, column decoder 350, page buffer 380, and voltage generator 340; wherein the command can be a programming command, a read command, etc.

[0077] The row decoder 330 can supply the word line 440 voltage generated from the voltage generator 340 to the selected word line 440 and the unselected word line 440 of the memory cell array 200 in response to the operation signal of the control logic circuit 320. As described in detail below, the row decoder 330 is configured to perform programming operations on memory cells coupled to one or more selected word lines 440 in the memory cell array 200.

[0078] Voltage generator 340 can use external or internal power supply voltages to generate various voltages for performing erase, program, read, and verify operations on memory cell array 200, such as programming voltage Vpgm, pass voltage Vpass, read voltage Vread, and verification voltage Vvfy applied to word line 440, as well as programming inhibit voltage Vinhibit, programming select voltage Vss applied to bit lines, and combinations thereof.

[0079] The column decoder 350 can select one or more memory cell strings 220 in the memory cell array 200 in response to the operation signal of the control logic circuit 320.

[0080] Register 370 can be coupled to control logic circuit 320 and includes a status register, a command register and an address register to store status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit 300.

[0081] Page buffer 380 can read data from and program (write) data to memory cell array 200 according to operation signals from control logic circuit 320. In one example, page buffer 380 can store programming data to be programmed into memory cell array 200 (write data). In another example, page buffer 380 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 223 coupled to select word line 440. In yet another example, page buffer 380 can also detect a low-power signal from a bit line representing a data bit stored in memory cell 223 and amplify the small voltage to a recognizable logic level during a read operation.

[0082] like Figure 9 or Figure 10 As shown in the embodiment of this application, the page buffer 380 circuit in the storage device may include a sensing node SO, a charging / discharging circuit 600, a first latch circuit 500, and a second latch circuit 700. The sensing node SO is coupled to the storage cell string 220 via a bit line. A capacitor Cso for storing charge may be provided between the sensing node SO and ground GND, or between the sensing node SO and any fixed potential. Alternatively, a parasitic capacitance for storing charge may also be formed between the sensing node SO and ground GND, or between the sensing node SO and any fixed potential. The storage cell string 220 includes a programmed first storage cell and an unprogrammed second storage cell, with the first and second storage cells adjacent to each other.

[0083] It should be understood that the "grounding" described in the embodiments of this application can also be coupled to any fixed potential.

[0084] Specifically, the charging and discharging circuit 600 is coupled to the sensing node SO. The charging and discharging circuit 600 includes a charging circuit 610 configured to charge the sensing node SO and a discharging circuit 620 configured to discharge the sensing node SO.

[0085] In this embodiment, the first latch circuit 500 is configured to latch the programming state of the first memory cell. During the verification phase of the second memory cell, the discharge duration of the sensing node SO is related to the programming state of the first memory cell; wherein, the discharge duration of the sensing node SO is equal to the difference between the time when the discharge circuit 620 stops discharging the sensing node SO and the time when the charging circuit 610 stops charging the sensing node SO. That is, the first latch circuit 500 can be coupled to the charging circuit 610 to control the time when the charging circuit 610 stops charging the sensing node SO; or, the first latch circuit 500 can be coupled to the discharge circuit 620 to control the time when the discharge circuit 620 stops discharging the sensing node SO; or, the first latch circuit 500 can also be coupled to both the charging circuit 610 and the discharge circuit 620 simultaneously to control the times when the discharge circuit 620 stops discharging the sensing node SO and when the charging circuit 610 stops charging the sensing node SO.

[0086] The lower the programming state of the first memory cell, the longer the discharge duration of the sensing node SO is during the verification of the second memory cell. For example, the programming state of the first memory cell includes a first state and a second state, where the threshold voltage of the first memory cell in the first state is greater than the threshold voltage in the second state. When the programming state of the first memory cell is the first state, the discharge duration of the sensing node SO is a first duration; when the programming state of the first memory cell is the second state, the discharge duration is a second duration; the first duration is less than the second duration. After the discharge duration, the voltage value of the sensing node SO is configured to determine whether the second memory cell has passed the programming verification.

[0087] like Figure 9 As shown, in some embodiments, the output of the first latch circuit 500 is coupled to the charging circuit 610, the first terminal of the charging circuit 610 is configured to receive the input supply voltage, and the second terminal of the charging circuit 610 is coupled to the sensing node SO.

[0088] Specifically, the charging circuit 610 may include multiple charging sub-circuits, each corresponding to a different programming state of the first storage unit. For example, the charging circuit 610 may include a first charging sub-circuit and a second charging sub-circuit.

[0089] The first terminal of the first charging sub-circuit is coupled to the first terminal of the charging circuit 610, and the second terminal of the first charging sub-circuit is coupled to the second terminal of the charging circuit 610. The first charging sub-circuit includes a first transistor 611 and a second transistor 612. Specifically, the first terminal of the first transistor 611 is configured to receive the input supply voltage, the second terminal of the first transistor 611 is coupled to the first terminal of the second transistor 612, and the second terminal of the second transistor 612 is coupled to the sensing node SO. The control terminal of the first transistor 611 is coupled to the first output terminal of the control logic circuit 320, and the control terminal of the second transistor 612 is coupled to the output terminal of the first latch circuit 500.

[0090] In this embodiment of the application, the first transistor 611 and the second transistor 612 are P-type transistors; for example, a P-channel metal-oxide-semiconductor field-effect transistor (PMOS).

[0091] The first terminal of the second charging electronic circuit is coupled to the first terminal of the charging circuit 610, and the second terminal of the second charging electronic circuit is coupled to the second terminal of the charging circuit 610; wherein, the second charging electronic circuit includes a third transistor 613. That is, the first terminal of the third transistor 613 is configured to receive the input supply voltage, and the second terminal of the third transistor 613 is coupled to the sensing node SO. The control terminal of the third transistor 613 is coupled to the second output terminal of the control logic circuit 320. In this embodiment, the third transistor 613 is a P-type transistor.

[0092] The control logic circuit 320 is configured to control the first transistor 611 to turn on or off, and to control the third transistor 613 to turn on or off. Furthermore, the control logic circuit 320 first controls the third transistor 613 to turn off, and then controls the first transistor 611 to turn off. In this embodiment, the control logic circuit 320 can control the third transistor 613 and the first transistor 611 to turn on simultaneously. The first latch circuit 500 is configured to control the second transistor 612 to turn on or off. When the programming state of the first memory cell is in the first state, the second transistor 612 turns on, and thus the first charging sub-circuit and the second charging sub-circuit simultaneously charge the sensing node SO. Since the control logic circuit 320 controls the first transistor 611 to turn off after the third transistor 613 turns off, when the second charging sub-circuit stops charging the sensing node SO, the first charging sub-circuit continues to charge the sensing node SO. That is, when the programming state of the first memory cell is in the first state, it is essentially the first charging sub-circuit that charges the sensing node SO. When the programming state of the first memory cell is the second state, the second transistor 612 is turned off, so the second charging sub-circuit can only charge the sensing node SO by turning on the third memory cell 223.

[0093] like Figure 10 As shown, in some embodiments, the output of the first latch circuit 500 is coupled to the discharge circuit 620, the first end of the discharge circuit 620 is coupled to the bit line, and the second end of the discharge circuit 620 is coupled to the sensing node SO.

[0094] Specifically, the discharge circuit 620 may include multiple discharge circuits, each corresponding to a different programming state of the first memory cell. For example, the discharge circuit 620 may include a first discharge circuit and a second discharge circuit.

[0095] The first terminal of the second discharge circuit is coupled to the first terminal of the discharge circuit 620, and the second terminal of the second discharge circuit is coupled to the second terminal of the discharge circuit 620. The second discharge circuit includes a fourth transistor 621 and a fifth transistor 622. Specifically, the first terminal of the fourth transistor 621 is coupled to the bit line, the second terminal of the fourth transistor 621 is coupled to the first terminal of the fifth transistor 622, and the second terminal of the fifth transistor 622 is coupled to the sensing node SO. The control terminal of the fourth transistor 621 is coupled to the third output terminal of the control logic circuit 320, and the control terminal of the fifth transistor 622 is coupled to the output terminal of the first latch circuit 500.

[0096] In this embodiment, the fourth transistor 621 is an N-type MOS transistor, and the fifth transistor 622 may include an N-type MOS transistor and a P-type MOS transistor, which are connected in parallel.

[0097] The first terminal of the first discharge circuit is coupled to the first terminal of the discharge circuit 620, and the second terminal of the first discharge circuit is coupled to the second terminal of the discharge circuit 620; wherein, the first discharge circuit includes a sixth transistor 623. That is, the first terminal of the sixth transistor 623 is coupled to the bit line, and the second terminal of the sixth transistor 623 is coupled to the sensing node SO. The control terminal of the sixth transistor 623 is coupled to the fourth output terminal of the control logic circuit 320. In this embodiment, the sixth transistor 623 is an N-type MOS.

[0098] The control logic circuit 320 is configured to control the fourth transistor 621 to turn on or off, and to control the sixth transistor 623 to turn on or off. Furthermore, the control logic circuit 320 first controls the sixth transistor 623 to turn off, and then controls the fourth transistor 621 to turn off. In this embodiment, the control logic circuit can control the sixth transistor 623 and the fourth transistor 621 to turn on simultaneously. The first latch circuit 500 is configured to control the fifth transistor 622 to turn on or off. When the programming state of the first memory cell is the second state, the fifth transistor 622 turns on, and the sensing node SO applies a bit line voltage to the bit line through the first and second discharge circuits, thereby discharging the sensing node SO. Since the control logic circuit 320 controls the first transistor 611 to turn off after the third transistor 613 turns off, the first charge circuit continues to discharge the sensing node SO even when the second charge circuit stops discharging it. In other words, when the programming state of the first memory cell is the second state, it is essentially the second discharge circuit that discharges the sensing node SO. When the programming state of the first memory cell is in the first state, the fifth transistor 622 is turned off, so the sensing node SO can only be discharged through the first discharge circuit.

[0099] In some embodiments, the first latch circuit 500 is also simultaneously coupled to the charging circuit 610 and the discharging circuit 620; that is, the first latch circuit 500 simultaneously controls the timing at which the charging circuit 610 stops charging the sensing node SO, and controls the timing at which the discharging circuit 620 stops discharging the sensing node SO. Further details are omitted here.

[0100] like Figure 9As shown, a first latch circuit 500 is coupled to a sensing node SO; wherein the first latch circuit 500 includes a first inverter 510, a second inverter 520, a seventh transistor 530, an eighth transistor 540, and a ninth transistor 550. The output terminal of the first inverter 510 is coupled to the input terminal of the second inverter 520, and the input terminal of the first inverter 510 is coupled to the output terminal of the second inverter 520. The first terminal of the seventh transistor 530 is coupled to the output terminal of the first inverter 510, the first terminal of the eighth transistor 540 is coupled to the output terminal of the second inverter 520, and the control terminal of the ninth transistor 550 is coupled to the sensing node SO. The first terminal of the ninth transistor 550 is coupled to the second terminals of the seventh transistor 530 and the eighth transistor 540, and the second terminal of the ninth transistor 550 is grounded to GND. The control terminal of the seventh transistor 530 is configured to receive a set signal and a reset signal.

[0101] For example, in this embodiment, the seventh transistor 530, the eighth transistor 540, and the ninth transistor 550 can all be N-type MOS transistors. When the ninth transistor 550 is turned on under the voltage of the sensing node SO, if the set signal is high, the seventh transistor 530 is turned on, the output of the first inverter 510 is low, and the output of the first inverter 510 is high; if the reset signal is high, the eighth transistor 540 is turned on, the output of the second inverter 520 is low, and the output of the first inverter 510 is high; that is, the programming state of the first memory cell is distinguished by high and low levels. It should be understood that multiple programming states of the first memory cell can be distinguished by setting multiple first latch circuits 500.

[0102] The second latch circuit 700 (also called a sense latch) is coupled to the sensing node SO and is configured to latch information about whether the second memory cell has passed programming verification based on the voltage value of the sensing node after a discharge period. The second latch circuit 700 includes a third inverter 710, a fourth inverter 720, a tenth transistor 730, an eleventh transistor 740, a twelfth transistor 750, and a thirteenth transistor 760. The output of the third inverter 710 is coupled to the input of the fourth inverter 720, and the input of the third inverter 710 is coupled to the output of the fourth inverter 720. The first terminal of the tenth transistor 730 is coupled to the output terminal of the third inverter 710 and is configured to output information on whether the second memory cell has passed programming verification; the first terminal of the eleventh transistor 740 is coupled to the output terminal of the fourth inverter 720; the control terminal of the twelfth transistor 750 is coupled to the sensing node SO; the first terminal of the twelfth transistor 750 is coupled to the second terminal of the tenth transistor 730 and the second terminal of the eleventh transistor 740; the second terminal of the twelfth transistor 750 is grounded to GND; the thirteenth transistor 760 is connected in parallel with the twelfth transistor 750.

[0103] Usually, in Figure 9 Examples of other circuit structures are also shown, such as a fourteenth transistor 810 and a fifteenth transistor 820 coupled between the power supply VDD and the charging circuit 610, and a sixteenth transistor 830 coupled between the bit line and the discharging circuit 620. The fourteenth transistor 810 and the fifteenth transistor 820 are P-type MOS transistors, the sixteenth transistor 830 is an N-type MOS transistor, and the fourteenth transistor 810 is configured to receive information on whether the second memory cell has passed programming verification.

[0104] Since the embodiments of this application do not improve these structures, these structures should not be construed as limitations on this application, but rather as one implementation method. In some examples, these structures may also take other specific circuit forms.

[0105] like Figure 11 As shown, this application embodiment provides an operation method for a storage device, including steps S110-S140, as follows:

[0106] S110, The first latching circuit latches the programming state of the first memory cell in the memory cell array.

[0107] Specifically, the first latch circuit 500 can latch the programming state of the first memory cell before programming the second memory cell. The first and second memory cells are located on the same memory cell string 220 and are adjacent to each other.

[0108] For storage devices 120 of types such as MLC, TLC, and QLC, the first storage cell has multiple programming levels. Therefore, the present application method can divide the first storage cell into multiple programming states according to the programming level of the first storage cell, so as to avoid setting too many first latch circuits 500, which would result in excessive area of ​​the page buffer 380 circuit. For example, the programming states of the first storage cell include a first state and a second state, and the threshold voltage of the first storage cell in the first state is greater than the threshold voltage in the second state. The correspondence between the programming states and programming levels of the first storage cell can be shown in Table 1 below:

[0109] Table 1

[0110]

[0111] S120. During the stage of programming and verifying the second memory cell in the memory cell array, the charging and discharging circuit discharges the sensing node in the page buffer circuit.

[0112] Specifically, after the discharge period, if the voltage value of the sensing node SO is greater than the threshold voltage, the second memory cell passes the programming verification; if the voltage value of the sensing node SO is less than the threshold voltage, the second memory cell fails the programming verification. In this embodiment, during the programming verification stage of the second memory cell, the discharge period of the sensing node SO is related to the programming state of the first memory cell. The lower the programming state of the first memory cell, the longer the discharge period of the sensing node SO is when verifying the second memory cell. Figure 12 As shown, discharging the sensing node SO may include steps S210-S240, as follows:

[0113] S210, the charging circuit charges the sensing node.

[0114] Specifically, the first terminal of the charging circuit 610 is configured to receive the input supply voltage, and the second terminal of the charging circuit 610 is coupled to the sensing node SO. First, the first and second terminals of the charging circuit 610 are turned on, and the charging circuit 610 applies the supply voltage to the sensing node SO to charge it.

[0115] S220, Apply bit line voltage to the bit line.

[0116] Specifically, the bit line is coupled to the first terminal of the discharge circuit 620, and the second terminal of the discharge circuit 620 is coupled to the sensing node SO. Then, the first and second terminals of the discharge circuit 620 are turned on, and the capacitor Cso coupled to the sensing node SO applies a bit line voltage to the bit line. At this time, since the charging circuit 610 is still charging the sensing node SO, the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO has not yet begun to discharge.

[0117] S230, The charging circuit stops charging the sensing node.

[0118] Specifically, the first and second terminals of the charging circuit 610 are then disconnected. At this time, the charging circuit 610 stops charging the sensing node SO, and the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO begins to discharge.

[0119] S240, The discharge circuit stops discharging the sensing node.

[0120] Specifically, the first and second terminals of the discharge circuit 620 are finally disconnected, and the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO stops discharging. That is, the discharge duration of the sensing node SO is equal to the difference between the time when discharging the sensing node SO stops and the time when charging the sensing node SO stops.

[0121] In some embodiments, the programming state of the first memory cell can be related to the moment when the charging circuit 610 stops charging the sensing node SO. Therefore, as... Figure 13 As shown, step S120 may include steps S310-S350, as follows:

[0122] S310, turns on the first transistor in the first charging electronic circuit and the third transistor in the second charging electronic circuit.

[0123] Specifically, such as Figure 9 As shown, the first terminal of the first transistor 611 is configured to receive the input supply voltage, the second terminal of the first transistor 611 is coupled to the first terminal of the second transistor 612, and the second terminal of the second transistor 612 is coupled to the sensing node SO. The first terminal of the third transistor 613 is configured to receive the input supply voltage, and the second terminal of the third transistor 613 is coupled to the sensing node SO.

[0124] The control terminal of the first transistor 611 is configured to receive signal S1 output from the first output terminal of the control logic circuit 320, and the control terminal of the third transistor 613 is configured to receive signal S2 output from the second output terminal of the control logic circuit 320. Specifically, when signal S1 is high, the first transistor 611 is off; when signal S1 is low, the first transistor 611 is on. Similarly, when signal S2 is high, the third transistor 613 is off; when signal S2 is low, the third transistor 613 is on.

[0125] The control terminal of the second transistor 612 is coupled to the output terminal of the first latch circuit 500. Specifically, the second transistor 612 is turned on when the programming state of the first memory cell is in the first state, and turned off when the programming state of the first memory cell is in the second state.

[0126] For example, Figure 14 A waveform diagram of one type of control signal used for charging and discharging a sensing node is shown. For example... Figure 14 As shown, signals S1 and S2 both have falling edges simultaneously; that is, a low level is applied to the gates of the first transistor 611 and the third transistor 613 at the same time, turning on the first transistor 611 and the third transistor 613. Furthermore, the control logic circuit 320 outputs signal S3, causing the fifteenth transistor 820 between the power supply VDD and the first terminal of the charging circuit 610 to turn on.

[0127] In other words, when signals S1 and S2 both have falling edges, if the programming state of the first memory cell is in the first state, then the first charging sub-circuit and the second charging sub-circuit simultaneously charge the sensing node SO; if the programming state of the first memory cell is in the second state, then the second charging sub-circuit can charge the sensing node SO. That is, the charging circuit 610 charges the sensing node SO.

[0128] S320, apply bit line voltage to the bit line.

[0129] Specifically, such as Figure 9 As shown, the bit line is coupled to the first terminal of the discharge circuit 620, and the second terminal of the discharge circuit 620 is coupled to the sensing node SO. When signal S5 is low, the first and second terminals of the discharge circuit 620 are disconnected; when signal S5 is high, the first and second terminals of the discharge circuit 620 are turned on. Furthermore, the control logic circuit 320 outputs signal S4. When signal S4 is low, the sixteenth transistor 830 between the first terminal of the discharge circuit 620 and the bit line is disconnected; when signal S4 is high, the sixteenth transistor 830 between the first terminal of the discharge circuit 620 and the bit line is turned on.

[0130] like Figure 14 As shown, signals S4 and S5 then experience rising edges; that is, a high level is applied to the control terminal of the discharge circuit 620 and the gate of the sixteenth transistor 830. Thus, when signals S4 and S5 experience rising edges, the capacitor Cso coupled to the sensing node SO applies a bit line voltage to the bit line. At this time, since the charging circuit 610 is still charging the sensing node SO, the capacitor Cso (or parasitic capacitance) coupled to the sensing node SO has not yet begun to discharge.

[0131] S330, disconnect the third transistor.

[0132] Specifically, then a rising edge appears on signal S2; that is, a high level is applied to the gate of the third transistor 613, and the third transistor 613 is turned off. At this time, if the programming state of the first memory cell is the first state, turning off the third transistor 613 causes the second charging sub-circuit to stop charging the sensing node SO, while the first charging sub-circuit continues to charge the sensing node SO, and the sensing node SO has not started discharging. If the programming state of the first memory cell is the second state, since only the second charging sub-circuit can charge the sensing node SO, when the third transistor 613 is turned off, the charging circuit 610 stops charging the sensing node SO, and the sensing node SO begins to discharge.

[0133] S340, disconnect the first transistor.

[0134] Specifically, then a rising edge appears in signal S1; that is, a high level is applied to the gate of the first transistor 611, and the first transistor 611 is turned off. If the programming state of the first memory cell is the first state, step S330 turns off the third transistor 613, causing only the second charging sub-circuit to stop charging the sensing node SO, while the first charging sub-circuit continues to charge the sensing node SO. When the first transistor 611 is turned off, the first charging sub-circuit stops charging the sensing node SO, and the sensing node SO begins to discharge. If the programming state of the first memory cell is the second state, since only the second charging sub-circuit can charge the sensing node SO, the sensing node SO begins to discharge when the third transistor 613 is turned off in step S330.

[0135] S350, the discharge circuit stops discharging the sensing node.

[0136] Specifically, when the final signal S5 has a falling edge, a low level is applied to the control terminal of the discharge circuit 620, the first and second terminals of the discharge circuit 620 are disconnected, and the discharge circuit 620 stops discharging to the sensing node SO.

[0137] like Figure 14 As shown, if steps S310-S350 are executed, when the programming state of the first memory cell is the first state, the discharge duration of the sensing node SO is the first duration, which is equal to the difference between the time of executing step S350 and the time of executing step S340; when the programming state of the first memory cell is the second state, the discharge duration of the sensing node SO is the second duration, which is equal to the difference between the time of executing step S350 and the time of executing step S330. It can be seen that the first duration is less than the second duration.

[0138] In some embodiments, the programming state of the first memory cell can also be related to the moment when the discharge circuit 620 stops discharging the sensing node SO. Therefore, as Figure 15As shown, step S120 may also include steps S410-S450, as follows:

[0139] S410, the charging circuit charges the sensing node.

[0140] Specifically, such as Figure 10 As shown, the first terminal of the charging circuit 610 is configured to receive the input supply voltage, and the second terminal of the charging circuit 610 is coupled to the sensing node SO. The charging circuit 610 is configured to receive the signal S8 output by the control logic circuit 320. When the signal S8 is low, the first and second terminals of the charging circuit 610 are turned on; when the signal S8 is high, the first and second terminals of the charging circuit 610 are turned off.

[0141] For example, Figure 16 A waveform diagram of another control signal used to charge and discharge the sensing node is shown. (Example) Figure 16 As shown, firstly, a falling edge appears in signal S8; that is, a low level is applied to the control terminal of charging circuit 610, and the first and second terminals of charging circuit 610 are turned on. Furthermore, control logic circuit 320 outputs signal S3, causing the fifteenth transistor 820 between power supply VDD and the first terminal of charging circuit 610 to turn on. Thus, when a falling edge appears in signal S8, charging circuit 610 charges sensing node SO.

[0142] S420 turns on the fourth transistor in the first discharge circuit and the sixth transistor in the second discharge circuit.

[0143] Specifically, such as Figure 10 As shown, the first terminal of the fourth transistor 621 is coupled to the bit line, the second terminal of the fourth transistor 621 is coupled to the first terminal of the fifth transistor 622, and the second terminal of the fifth transistor 622 is coupled to the sensing node SO. The first terminal of the sixth transistor 623 is coupled to the bit line, and the second terminal of the sixth transistor 623 is coupled to the sensing node SO.

[0144] The control terminal of the fourth transistor 621 is configured to receive signal S6 output from the first output terminal of the control logic circuit 320, and the control terminal of the sixth transistor 623 is configured to receive signal S7 output from the second output terminal of the control logic circuit 320. Specifically, when signal S6 is low, the fourth transistor 621 is off; when signal S6 is high, the fourth transistor 621 is on. Similarly, when signal S6 is low, the sixth transistor 623 is off; when signal S6 is high, the sixth transistor 623 is on.

[0145] The control terminal of the fifth transistor 622 is coupled to the output terminal of the first latch circuit 500. Specifically, the fifth transistor 622 is turned on when the programming state of the first memory cell is the second state, and turned off when the programming state of the first memory cell is the first state.

[0146] like Figure 16 As shown, signals S6 and S7 then experience rising edges; that is, a high level is simultaneously applied to the gates of the fourth transistor 621 and the sixth transistor 623, turning on the fourth transistor 621 and the sixth transistor 623. Furthermore, the control logic circuit 320 outputs signals S4 and S9. When signals S4 and S9 are high, the sixteenth transistor 830 between the bit line and the first terminal of the discharge circuit 620 is turned on.

[0147] At this time, the charging circuit 610 continues to charge the sensing node SO. That is, when signals S6 and S7 both have rising edges, if the programming state of the first memory cell is the second state, the sensing node SO applies a bit line voltage to the bit line through the first and second discharge circuits; if the programming state of the first memory cell is the first state, the sensing node SO can only apply a bit line voltage to the bit line through the first discharge circuit.

[0148] S430, the charging circuit stops charging the sensing node.

[0149] Specifically, then a rising edge appears on signal S8; that is, a high level is applied to the control terminal of charging circuit 610. The first and second terminals of charging circuit 610 are disconnected, charging circuit 610 stops discharging to sensing node SO, and capacitor Cso (or parasitic capacitance) coupled to sensing node SO begins to discharge.

[0150] S440, disconnect the sixth transistor.

[0151] Specifically, a falling edge appears on signal S7; that is, a low level is applied to the gate of the sixth transistor 623, and the sixth transistor 623 is turned off. At this time, if the programming state of the first memory cell is the first state, only the first discharge circuit can discharge the sensing node SO. When the sixth transistor 623 is turned off, the first discharge circuit stops discharging the sensing node SO, thereby the discharge circuit 620 stops discharging the sensing node SO. If the programming state of the first memory cell is the second state, turning off the sixth transistor 623 causes the first discharge circuit to stop discharging the sensing node SO, but the second discharge circuit continues to discharge the sensing node SO; that is, the sensing node SO does not stop discharging.

[0152] S450, disconnect the fourth transistor.

[0153] Specifically, a falling edge appears on signal S6; that is, a low level is applied to the gate of the fourth transistor 621, and the fourth transistor 621 is turned off. At this time, if the programming state of the first memory cell is the first state, since only the first discharge circuit can discharge the sensing node SO, the sensing node SO stops discharging when the sixth transistor 623 is turned off in step S440. If the programming state of the first memory cell is the second state, the sixth transistor 623 is turned off in step S440, causing only the first discharge circuit to stop discharging the sensing node SO, while the second discharge circuit continues to discharge the sensing node SO. The second discharge circuit stops discharging the sensing node SO only when the fourth transistor 621 is turned off, and the sensing node SO stops discharging.

[0154] like Figure 16 As shown, if steps S410-S450 are executed, when the programming state of the first memory cell is the first state, the discharge duration of the sensing node SO is the first duration, which is equal to the difference between the time of executing step S440 and the time of executing step S430; when the programming state of the first memory cell is the second state, the discharge duration of the sensing node SO is the second duration, which is equal to the difference between the time of executing step S450 and the time of executing step S430. It can be seen that the first duration is less than the second duration.

[0155] Furthermore, the programming state of the first memory cell can also be simultaneously related to the moment when the charging circuit 610 stops charging the sensing node SO and the moment when the discharging circuit 620 stops discharging the sensing node SO. Therefore, as Figure 17 As shown, step S120 may further include steps S510-S560; wherein, step S510 is the same as step S310, step S520 is the same as step S420, step S530 is the same as step S330, step S540 is the same as step S340, step S550 is the same as step S440, and step S560 is the same as step S450, which will not be repeated here.

[0156] like Figure 17 As shown, if steps S510-S560 are executed, when the programming state of the first memory cell is the first state, the discharge duration of the sensing node SO is the first duration, which is equal to the difference between the time of executing step S550 and the time of executing step S540; when the programming state of the first memory cell is the second state, the discharge duration of the sensing node SO is the second duration, which is equal to the difference between the time of executing step S560 and the time of executing step S530. It can be seen that the first duration is less than the second duration.

[0157] S130. During the stage of programming and verifying the second memory cell in the memory cell array, the charging and discharging circuit discharges the sensing node multiple times, with the discharge duration increasing each time.

[0158] Specifically, under the same verification voltage, the higher the threshold voltage of the second memory cell, the lower the discharge rate of the sensing node SO. This application, under the same verification voltage, divides the threshold voltage of the second memory cell by discharging the sensing node SO multiple times with progressively increasing discharge durations.

[0159] For example, such as Figure 18 As shown, if the voltage of sensing node SO is less than the threshold voltage after a short discharge time, it indicates that the discharge rate of sensing node SO is high (more charge is released within a short discharge time), and the threshold voltage of the second memory cell is low; that is, the second memory cell is located in... Figure 18 Region a in the text.

[0160] If, after a prolonged discharge period, the voltage of sensing node SO exceeds the threshold voltage, it indicates that the discharge rate of sensing node SO is low (less charge is released during the prolonged discharge period), and the threshold voltage of the second memory cell is high; that is, the second memory cell is located in a state where... Figure 18 Region c in the text.

[0161] If, after a short discharge duration, the voltage of sensing node SO is greater than the threshold voltage, and after a longer discharge duration, the voltage of sensing node SO is less than the threshold voltage, then it indicates that the threshold voltage of the second memory cell is between the threshold voltages in the two aforementioned cases; that is, the second memory cell is located as follows: Figure 18 Region b in the text.

[0162] In this case, the second memory cell located in region c is a verified memory cell. Therefore, during the programming phase of the next programming cycle, different bit line voltages can be applied to the second memory cells located in different regions. For example, for the second memory cell located in region a, a 0V bit line voltage is applied to the bit line coupled to this second memory cell in the next programming cycle to program it; for the second memory cell located in region b, a 0.5V bit line voltage is applied to the bit line coupled to this second memory cell in the next programming cycle to slightly prevent programming; and for the second memory cell located in region c, a 2.2V bit line voltage is applied to the bit line coupled to this second memory cell in the next programming cycle to prevent programming. Figure 19As shown, after the programming phase of the next programming cycle, the threshold voltage of the second memory cell located in region a increases significantly, the threshold voltage of the second memory cell located in region b increases less significantly, and the threshold voltage of the second memory cell located in region c remains unchanged. This is to achieve accurate programming of the second memory cell.

[0163] S140. After the discharge time has elapsed, the second latch circuit latches the information of whether the second storage cell has passed the programming verification based on the voltage value of the sensing node.

[0164] Specifically, if the second memory cell passes verification, the sensing node SO will not experience a significant voltage drop after the discharge period; that is, the voltage of the sensing node is greater than a preset threshold voltage. At this time, the second latch circuit 700 latches the first information indicating that the second memory cell has passed verification. If the second memory cell fails verification, the sensing node SO will experience a significant voltage drop after the discharge period; that is, the voltage of the sensing node is less than a preset threshold voltage. At this time, the second latch circuit 700 latches the second information indicating that the second memory cell has failed verification.

[0165] This application also provides a computer-readable storage medium storing computer-executable instructions; when executed, these computer-executable instructions can implement the various steps in the above method embodiments, such as performing... Figures 11-17 The method shown.

[0166] This application provides a computer device including a processor and a readable storage medium coupled to the processor. The readable storage medium stores executable instructions, which, when executed by the processor, can implement the various steps in the above method embodiments, such as executing... Figures 11-17 The method shown.

[0167] This application provides a storage device, storage device operation method, and storage system. A first latch circuit 500 is provided in a page buffer 380. The first latch circuit 500 is coupled to a sensing node SO and a charge / discharge circuit 600 configured to discharge the sensing node SO, and is configured to latch the programming state of a first storage cell. Therefore, when verifying one of the programming states of a second storage cell (adjacent to the first storage cell), this application controls the discharge duration of the charge / discharge circuit 600 on the sensing node SO based on the programming state of the first storage cell latched by the first latch circuit 500. Under the same verification voltage, a longer discharge duration results in more charge released by the sensing node SO, a greater voltage drop at the sensing node SO, and makes it more difficult for the second storage cell to pass verification. This allows for continued programming of the second storage cell, resulting in the storage of more charge. In other words, under the same verification voltage, different discharge durations can result in different amounts of charge stored in the second storage cell. Compared to traditional methods that use multiple (no fewer than two) different verification voltages for repeated verification, this application uses only one verification voltage to verify the second memory cell, which greatly shortens the programming time.

[0168] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0169] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0170] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0171] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A storage device, characterized in that, It includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a first memory cell and a second memory cell coupled to the same bit line, the first memory cell and the second memory cell being adjacent to each other; The peripheral circuit includes a page buffer circuit, which includes: Sensing nodes are coupled to the bit lines; A first latch circuit, coupled to the sensing node, is configured to latch the programming state of the first memory cell; A charging / discharging circuit, coupled to the sensing node, is configured to charge the sensing node and discharge the sensing node; the discharge duration of the sensing node is related to the programming state of the first memory cell. A second latch circuit, coupled to the sensing node, is configured to latch information about whether the second storage cell has passed programming verification based on the voltage value of the sensing node after the discharge duration.

2. The storage device according to claim 1, characterized in that, The charging and discharging circuit includes: A charging circuit, wherein a first terminal of the charging circuit is configured to receive a power supply voltage, and a second terminal of the charging circuit is coupled to the sensing node and configured to charge the sensing node; A discharge circuit, wherein a first terminal of the discharge circuit is coupled to the bit line and a second terminal of the discharge circuit is coupled to the sensing node, is configured to discharge the sensing node.

3. The storage device according to claim 2, characterized in that, The programming states of the first memory cell include a first state and a second state, and the threshold voltage of the first memory cell in the first state is greater than the threshold voltage in the second state. When the programming state of the first storage unit is the first state, the discharge duration of the sensing node is the first duration; The discharge duration of the sensing node is equal to the difference between the time when the discharge circuit stops discharging the sensing node and the time when the charging circuit stops charging the sensing node. When the programming state of the first storage unit is the second state, the discharge duration is the second duration; The first duration is shorter than the second duration.

4. The storage device according to claim 3, characterized in that, The first latch circuit is coupled to the charging circuit, the charging circuit comprising: A first charging electronic circuit, wherein a first terminal of the first charging electronic circuit is coupled to a first terminal of the charging circuit, and a second terminal of the first charging electronic circuit is coupled to a second terminal of the charging circuit. A second charging electronic circuit, wherein a first terminal of the second charging electronic circuit is coupled to a first terminal of the charging circuit, and a second terminal of the second charging electronic circuit is coupled to a second terminal of the charging circuit; When the first storage unit is programmed in the first state, the first charging sub-circuit charges the sensing node; when the first storage unit is programmed in the second state, the second charging sub-circuit charges the sensing node.

5. The storage device according to claim 4, characterized in that, The first charging sub-circuit includes a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first terminal of the first charging sub-circuit, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the second transistor is coupled to a second terminal of the first charging sub-circuit, and a control terminal of the second transistor is coupled to the output terminal of the first latch circuit. The peripheral circuit also includes a control logic circuit, wherein when the programming state of the first memory cell is the first state, the second transistor is turned on; the control logic circuit is configured to: The first transistor is turned on, and the first charging sub-circuit charges the sensing node; or... The first transistor is turned off, and the first charging sub-circuit stops charging the sensing node.

6. The storage device according to claim 5, characterized in that, The second charging electronic circuit includes a third transistor, the first terminal of which is coupled to the first terminal of the second charging electronic circuit, and the second terminal of which is coupled to the second terminal of the second charging electronic circuit. When the programming state of the first memory cell is the second state, the second transistor is turned off; The control logic circuit is configured as follows: The third transistor is controlled to turn on, and the second charging sub-circuit charges the sensing node; or, The third transistor is turned off, and the second charging sub-circuit stops charging the sensing node.

7. The storage device according to any one of claims 3-6, characterized in that, The first latch circuit is coupled to the discharge circuit, the discharge circuit comprising: A first discharge circuit, wherein a first terminal of the first discharge circuit is coupled to a first terminal of the discharge circuit, and a second terminal of the first discharge circuit is coupled to a second terminal of the discharge circuit. A second discharge circuit, wherein a first terminal of the second discharge circuit is coupled to a first terminal of the discharge circuit, and a second terminal of the second discharge circuit is coupled to a second terminal of the discharge circuit; When the first memory cell is programmed in the first state, the first discharge circuit discharges the sensing node; when the first memory cell is programmed in the second state, the second discharge circuit discharges the sensing node.

8. The storage device according to claim 7, characterized in that, The second discharge circuit includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor is coupled to the first terminal of the first discharge circuit, the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor, the second terminal of the fifth transistor is coupled to the second terminal of the first discharge circuit, and the control terminal of the fifth transistor is coupled to the output terminal of the first latch circuit. The peripheral circuit also includes a control logic circuit. When the programming state of the first memory cell is the second state, the fifth transistor is turned on, and the control logic circuit is configured as follows: The fourth transistor is controlled to turn on, and the second discharge circuit discharges the sensing node; or, The fourth transistor is turned off, and the second discharge circuit stops discharging to the sensing node.

9. The storage device according to claim 8, characterized in that, The first discharge circuit includes a sixth transistor, the first terminal of which is coupled to the first terminal of the first discharge circuit, and the second terminal of which is coupled to the second terminal of the first discharge circuit. When the programming state of the first memory cell is the first state, the fifth transistor is turned off, and the control logic circuit is configured as follows: By controlling the sixth transistor to turn on, the first discharge circuit discharges the sensing node; or... The sixth transistor is disconnected, and the first discharge circuit stops discharging to the sensing node.

10. A method of operating a storage device, characterized in that, The storage device includes a storage cell array and peripheral circuitry coupled to the storage cell array; The peripheral circuit includes a page buffer circuit, and the operation method includes: Latch the programming state of the first memory cell in the memory cell array; During the programming verification stage of the second memory cell in the memory cell array, the sensing node in the page buffer circuit is discharged; wherein, the discharge duration of the sensing node is related to the programming state of the first memory cell; the first memory cell and the second memory cell are adjacent and coupled to the same bit line, and the sensing node is coupled to the bit line; After the discharge duration, information on whether the second storage unit has passed programming verification is latched based on the voltage value of the sensing node.

11. The operating method according to claim 10, characterized in that, Discharging the sensing node in the page buffer circuit includes: Charge the sensing node; Apply a bit line voltage to the bit line; Charging of the sensing node stops, and the sensing node begins to discharge; Stop discharging the sensing node; the sensing node stops discharging.

12. The operating method according to claim 11, characterized in that, The programming states of the first memory cell include a first state and a second state, and the threshold voltage of the first memory cell in the first state is greater than the threshold voltage in the second state. When the programming state of the first storage unit is the first state, the discharge duration of the sensing node is the first duration; the discharge duration of the sensing node is equal to the difference between the time when discharging the sensing node stops and the time when charging the sensing node stops. When the programming state of the first storage unit is the second state, the discharge duration is the second duration; The first duration is shorter than the second duration.

13. The operating method according to claim 12, characterized in that, The discharge duration of the sensing node is related to the programming state of the first memory cell, including: The moment when charging of the sensing node is stopped is related to the programming state of the first storage unit; Wherein, when the programming state of the first storage unit is the first state, the first charging sub-circuit charges the sensing node; when the programming state of the first storage unit is the second state, the second charging sub-circuit charges the sensing node. The first charging sub-circuit stops charging the sensing node after the second charging sub-circuit stops charging the sensing node.

14. The operating method according to claim 13, characterized in that, When the programming state of the first storage cell is the first state, the second transistor in the first charging sub-circuit is turned on, and the first charging sub-circuit charges the sensing node; including: The first transistor in the first charging sub-circuit is turned on, and the first charging sub-circuit charges the sensing node; Disconnecting the first transistor stops the first charging sub-circuit from charging the sensing node.

15. The operating method according to claim 14, characterized in that, When the programming state of the first storage cell is the second state, the second transistor in the first charging sub-circuit is turned off, and the second charging sub-circuit charges the sensing node; including: The third transistor in the second charging sub-circuit is turned on, and the second charging sub-circuit charges the sensing node; Disconnecting the third transistor causes the second charging sub-circuit to stop charging the sensing node.

16. The operating method according to claim 15, characterized in that, The moment when the first charging sub-circuit stops charging the sensing node is after the moment when the second charging sub-circuit stops charging the sensing node includes: First disconnect the third transistor, then disconnect the first transistor.

17. The operating method according to any one of claims 12-16, characterized in that, The discharge duration of the sensing node is related to the programming state of the first memory cell, including: The moment when discharging the sensing node stops is related to the programming state of the first memory cell; Wherein, when the programming state of the first memory cell is the first state, the first discharge circuit discharges the sensing node; when the programming state of the first memory cell is the second state, the second discharge circuit discharges the sensing node. The second discharge circuit stops discharging the sensing node after the first discharge circuit stops discharging the sensing node.

18. The operating method according to claim 17, characterized in that, When the programming state of the first memory cell is the second state, the fifth transistor in the second discharge circuit is turned on, and the second discharge circuit discharges the sensing node; including: The fourth transistor in the second discharge circuit is turned on, and the second discharge circuit discharges the sensing node; Disconnecting the fourth transistor stops the second discharge circuit from discharging the sensing node.

19. The operating method according to claim 18, characterized in that, When the programming state of the first memory cell is the first state, the fifth transistor in the second discharge circuit is turned off, and the first discharge circuit discharges the sensing node, including: The sixth transistor in the first discharge circuit is turned on, and the first discharge circuit discharges the sensing node. Disconnecting the sixth transistor stops the first discharge circuit from discharging the sensing node.

20. The operating method according to claim 19, characterized in that, The second discharge circuit stops discharging the sensing node after the first discharge circuit stops discharging the sensing node, including: First disconnect the sixth transistor, then disconnect the fourth transistor.

21. The operating method according to claim 10, characterized in that, The operation method further includes: During the programming verification stage of the second memory cell in the memory cell array, the sensing node is discharged multiple times; The discharge duration increases successively.

22. A storage system, characterized in that, The device includes a memory controller and a storage device according to any one of claims 1-9, wherein the memory controller is configured to control the storage device.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions; when the computer-executable instructions are executed, they can implement the method described in any one of claims 10-21.

24. A computer device, characterized in that: It includes a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, enable the implementation of the method according to any one of claims 10-21.

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