Memory built-in time sequence adjusting circuit and method and memory

Abstract

The invention discloses a memory built-in time sequence adjusting circuit and method and a memory, and the circuit comprises a time delay adjustable time sequence module which is used for inputting a clock signal and carrying out the time delay output of the clock signal; inputting an external clock signal in a normal working mode; inputting an internal clock signal in a time sequence adjustment mode; the time sequence detection module is used for configuring different time delay parameters for the time delay adjustable time sequence module by using an internal clock signal in a time sequence adjustment mode to carry out time sequence detection and outputting a detection signal; the adjustment result judgment module is used for determining an optimal delay parameter according to the detection signal; the delay configuration module is used for writing the optimal delay parameter into the storage unit; and the delay adjustable time sequence module performs delay output on the external clock signal according to the optimal delay parameter written in the storage unit in a normal working mode so as to control the read-write operation of the memory. According to the scheme, the working frequency of the memory can be optimal, so that the performance of the memory is ensured.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a memory built-in timing adjustment circuit and method, and a memory. Background Art

[0002] The timing circuit structure with fixed delay can support the memory to work in a specific frequency range. If the operating frequency of the memory exceeds this range, timing problems may occur, resulting in functional errors. However, the frequency range of circuit operation is not only affected by the timing circuit, but also by some physical factors, including manufacturing process, temperature, power supply voltage, etc. Therefore, under different environmental conditions, the frequency range in which the circuit can work is not exactly the same.

[0003] In response to the above problems, the existing solution is usually to add a delay adjustable function to the timing circuit of the memory, find the delay configuration corresponding to the frequency range in which the chip can work normally through production testing, and burn the corresponding configuration into the chip. The corresponding configuration can only be burned once and cannot be changed. However, when the working environment (temperature, voltage, etc.) of the chip changes, the timing circuit of this solution cannot make adaptive delay adjustments according to the working environment, resulting in the memory failing to achieve the optimal frequency performance. In addition, the existing timing circuit has the following disadvantages:

[0004] (1) In general, there is a certain range of delay values ​​that can support the normal operation of the circuit. Since the relevant delay configuration will be fixed after production testing and cannot be changed, in order to prevent changes in chip performance caused by environmental changes, etc., the delay value is generally set conservatively and the delay is not configured at the critical point. Therefore, under normal working conditions, the circuit does not actually work at the highest frequency at which it can work normally.

[0005] (2) As the chip ages, the circuit performance will decline. It is possible that the previously fixed delay cannot meet the circuit timing requirements, resulting in functional errors in the circuit. Summary of the invention

[0006] The embodiment of the present invention provides a memory built-in timing adjustment circuit and method, and a memory, so as to optimize the working frequency of the memory and thus ensure the performance of the memory.

[0007] In one aspect, an embodiment of the present invention provides a memory built-in timing adjustment circuit, the circuit comprising:

[0008] The delay adjustable timing module is used to input a clock signal and output the clock signal with a delay; input an external clock signal in a normal working mode; and input an internal clock signal in a timing adjustment mode;

[0009] A timing detection module, used for performing timing detection on the adjustable delay timing module with different delay parameters using an internal clock signal in a timing adjustment mode, and outputting a detection signal;

[0010] An adjustment result judgment module is used to determine the optimal delay parameter according to the detection signal;

[0011] A delay configuration module, used for writing the optimal delay parameter into a storage unit;

[0012] The adjustable-delay timing module delays and outputs the external clock signal according to the optimal delay parameter written in the storage unit in the normal working mode to control the read and write operations of the memory;

[0013] The control module is used to control the state transition during the timing adjustment process.

[0014] Optionally, the adjustable delay timing module includes a timing control unit, and the timing control unit includes a plurality of delay sub-units with different gears;

[0015] The delay subunit is used to generate a delay of a specific length according to the delay parameters in the storage unit, so as to adjust the width of the pulse signal input to the delay adjustable timing module and the interval between different clock signals.

[0016] Optionally, the timing detection module includes: an internal pulse signal generating unit and a pulse shaping unit, and the internal pulse signal generating unit, the adjustable delay timing module, and the pulse shaping unit constitute a ring oscillation test structure; wherein:

[0017] The internal pulse signal generating unit is used to generate an internal clock signal according to the start-up signal and the output of the pulse shaping unit, and output the internal clock signal to the adjustable delay timing module, so that the adjustable timing module outputs a delay signal;

[0018] The adjustable delay timing module is further used to traverse each preset delay parameter in the timing adjustment mode until the adjustment result judgment module determines that the optimal delay parameter is obtained;

[0019] A pulse shaping unit is used to shape the delayed signal into a signal whose frequency is related to the delay of the adjustable delay timing module, output it to the input end of the internal pulse signal generating unit, and output it to the adjustment result judgment module as the detection signal.

[0020] Optionally, the timing detection module further includes: an AND gate, the AND gate is respectively input with the start-up signal and the delay signal, and the output end of the AND gate is connected with the input end of the internal pulse signal generating unit.

[0021] Optionally, the adjustment result judgment module determines that the current delay parameter is the optimal delay parameter when the detection signal is a stable periodic signal.

[0022] Optionally, the control module is further used to control switching between different modes, and the modes include: the timing adjustment mode and the normal working mode.

[0023] Optionally, the control module uses a state machine to control state transitions during the timing adjustment process.

[0024] Optionally, the circuit further comprises: a configuration module, configured to enable or disable the timing adjustment mode;

[0025] The delay adjustable timing module is also used to delay the output of the external clock signal according to the default delay parameters to control the read and write operations of the memory when the configuration module prohibits the timing adjustment mode.

[0026] On the other hand, an embodiment of the present invention further provides a method for adjusting a built-in timing of a memory, wherein a delay adjustable timing module is provided in the memory, and the delay adjustable timing module is used to delay the output of an input clock signal to control the read and write operations of the memory;

[0027] The method comprises:

[0028] Before entering the normal working mode, enter the timing adjustment mode;

[0029] In the timing adjustment mode, the internal clock signal is used to configure different delay parameters of the adjustable delay timing module to perform timing detection, and output a detection signal;

[0030] Determine an optimal delay parameter according to the detection signal;

[0031] In the normal working mode, the adjustable delay timing module is enabled to delay the output of the external clock signal according to the optimal delay parameter to control the read and write operations of the memory.

[0032] Optionally, the method further comprises: utilizing a state machine to control state transitions and switching between different modes during the timing adjustment process.

[0033] Optionally, the method further comprises:

[0034] generating an enable signal, wherein the enable signal is used to enable or disable the timing adjustment mode;

[0035] When the enable signal prohibits the timing adjustment mode, the delay adjustable timing module is enabled to delay the output of the external clock signal according to the default delay parameter to control the read and write operations of the memory.

[0036] On the other hand, an embodiment of the present invention further provides a memory, wherein the memory includes the aforementioned memory built-in timing adjustment circuit.

[0037] The memory built-in timing adjustment circuit and method provided by the embodiment of the present invention sets a delay adjustable timing module in the memory to delay the output of the clock signal. Before entering the normal working mode, first enter the timing adjustment mode, use the internal clock signal to perform timing detection on the delay adjustable timing module, and determine the optimal delay parameters under the current environment. In this way, after entering the normal working mode, the delay adjustable timing module can adjust the timing of the input external clock signal according to the optimal delay parameters to control the read and write operations of the memory. Using the scheme of the present invention, the delay of the timing circuit in the memory can be simply and conveniently adjusted to adapt to the environment, so that the memory can achieve the optimal operating frequency performance.

[0038] Furthermore, by controlling the state transition during the timing adjustment process through a state machine, various control logics can be better implemented.

[0039] Furthermore, by setting the enabling module, the user can decide whether to use the timing adjustment mode according to his or her own needs, thereby better meeting various needs in different application environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of a memory built-in timing adjustment circuit provided by an embodiment of the present invention;

[0041] Figure 2 is a structural schematic diagram of a timing detection module in an embodiment of the present invention;

[0042] Figure 3 yes Figure 2 The control logic diagram of the ring oscillator test circuit composed of the timing detection module and the delay adjustable timing module shown;

[0043] Figure 4 is a flow chart of determining the optimal delay parameter in the timing adjustment mode in an embodiment of the present invention;

[0044] Figure 5 is a schematic diagram of state changes of a state machine in an embodiment of the present invention;

[0045] Figure 6 The present invention provides a flow chart of a method for adjusting the built-in timing of a memory. DETAILED DESCRIPTION

[0046] The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

[0047] In view of the problem that in the existing memory timing circuit, when the working environment (temperature, voltage, etc.) of the chip changes, the adaptive delay adjustment cannot be performed according to the working environment, resulting in the memory being unable to achieve the optimal frequency performance, an embodiment of the present invention provides a memory built-in timing adjustment circuit and method, which is integrated inside the memory. After the memory chip is powered on and before starting normal operation, the circuit is first environmentally adaptively adjusted according to the current working environment to determine the optimal delay parameters, so that during normal operation, the delay adjustable timing module is delayed according to the optimal delay parameters, thereby ensuring that the memory operates in the highest frequency range that can meet the timing requirements in the current working environment, thereby improving the memory's adaptability to different environments.

[0048] like Figure 1 FIG. 1 is a schematic diagram of a structure of a memory built-in timing adjustment circuit provided in an embodiment of the present invention.

[0049] The memory built-in timing adjustment circuit of this embodiment includes:

[0050] The delay adjustable timing module 101 is used to input an external clock signal in the working mode and delay the output of the external clock signal to control the read and write operations of the memory;

[0051] The timing detection module 102 is used to perform timing detection on the adjustable delay timing module 101 with different delay parameters using an internal clock signal in a timing adjustment mode, and output a detection result;

[0052] An adjustment result determination module 103 is used to determine the optimal delay parameter according to the detection result;

[0053] The delay configuration module 104 is used to write the optimal delay parameter into the storage unit 105;

[0054] Accordingly, the adjustable delay timing module 101 delays the external clock signal according to the optimal delay parameter in the working mode;

[0055] The control module 100 is used to control the state transition during the timing adjustment process.

[0056] There are timing circuits in general memories, which are mainly used to control the read and write operations of the memory. When writing or reading data to the storage unit of the memory, a series of operations are performed in sequence, such as address latching, word line decoding, bit line precharging, sense amplifier startup, write and read enable, output latching, etc.

[0057] In order to enable the memory to work normally and achieve higher performance, it is necessary to arrange the order of the above operations reasonably and effectively. To this end, the above-mentioned adjustable delay timing module 101 includes a timing control unit, and the timing control unit includes a plurality of delay sub-units with different gears, and the delay sub-units are used to generate a delay of a specific length to adjust the width of the periodic pulse signal input to the adjustable delay timing module and the spacing between different pulse signals, thereby affecting the frequency of the internal clock signal.

[0058] Multiple delay sub-units combined with corresponding combinational logic can generate timing signals with a fixed sequence, which are subsequently used to control a series of operations with timing requirements.

[0059] Input signals with level changes can generate pulse signals with different timings after delays of different lengths, and then generate control signals with specific timings after combinational logic operations. By adjusting the delay length of the delay subunit, the width of the pulse signal and the spacing between different pulse signals can be adjusted, thereby affecting the performance of the memory such as the maximum operating frequency.

[0060] A typical delay circuit is implemented by an inverter chain. By inserting some logic gates in the inverter chain, the purpose of adjustable delay can be achieved. In a non-limiting embodiment, the delay in the delay subunit can be divided into 8 specific gears, and the delays of different gears correspond to different maximum operating frequencies. The 8 fixed gears are controlled by 3-8 decoding of the corresponding 3-bit control bits. The delay corresponds to the values ​​of the three control bits from 000 to 111 from high to low.

[0061] The delay gear position needs to be controlled and selected by the corresponding control bit (i.e., delay parameter). These control bits are stored in specific storage units. If the built-in timing adjustment function is used, the values ​​in these storage units are determined by the built-in timing adjustment circuit. In other words, the delay subunit is used to generate a delay of a specific length according to the delay parameters in the storage unit to adjust the width of the periodic pulse signal and the spacing between different pulse signals.

[0062] In specific applications, the timing detection module 102 can output the key timing inside the memory through some circuit structures to achieve the purpose of making the key timing signal observable and quantifiable. Through the output results of the timing detection module 102, the delay configuration for the normal operation of the memory and the operating frequency under each configuration are obtained.

[0063] like Figure 2 As shown, the timing detection module 102 includes: an internal pulse signal generating unit 121 and a pulse shaping unit 122, the internal pulse signal generating unit 121, the pulse shaping unit 122 and Figure 1 The adjustable delay timing module 101 in the circuit constitutes a ring oscillation test circuit.

[0064] In the ring oscillator test circuit, the adjustable delay timing module 101 is used as the timing module to be tested, and the optimal delay parameters of the adjustable delay timing module 101 are obtained through the ring oscillator structure.

[0065] The internal pulse signal generating unit 121 is used to generate an internal clock signal according to the start-up signal and the output of the pulse shaping unit 122, and output the internal clock signal to the adjustable delay timing module 101, so that the adjustable timing module 101 outputs a delay signal.

[0066] The adjustable delay timing module 101 traverses each preset delay parameter in the timing adjustment mode until Figure 1 The adjustment result judgment module 103 determines the optimal delay parameter according to the detection result of the delay signal output by the delay adjustable timing module 101 by the timing detection module 102;

[0067] The pulse shaping unit 122 is used to shape the delayed signal into a signal with a frequency related to the delay of the adjustable delay timing module, and output the signal to be fed back to the input end of the internal pulse signal generating unit 121 .

[0068] It should be noted that the shaped delay signal is fed back to the internal pulse signal generating unit 121, and is also output to the adjustment result judgment module 103 as the detection signal. Accordingly, the adjustment result judgment module 103 determines that the current delay parameter is the optimal delay parameter when the detection signal is a stable periodic signal. The adjustment result judgment module 103 can specifically determine whether its period and duty cycle are stable by detecting the width of the high level and low level of the detection signal. A stable period and duty cycle is a stable periodic signal.

[0069] In a specific application, the control module 100 can be implemented by a state machine. Figure 1 and Figure 2 , detailing the timing adjustment process.

[0070] In the timing adjustment mode, in order to reduce the influence of metastable state during circuit state switching, after two clock cycles (clock of the state machine), the state machine sends an oscillation start signal to the timing detection module 102, and the ring oscillation test circuit inside the memory starts working.

[0071] First, the rising edge of the start-up signal is used as the first clock trigger edge to trigger the internal pulse signal generating circuit 121 to generate a series of pulse signals similar to those in normal operation. Afterwards, these pulse signals pass through the adjustable delay timing module 101 to generate key timing signals for controlling the reading and writing of the memory (such as the memory's write data line WL control signal, etc.). Finally, the key timing signal is output to the pulse shaping unit 122 with a fixed delay and is shaped into a signal related to the pulse width and frequency (for the convenience of description, the signal is referred to as a shaped signal). The shaped signal is output to the adjustment result judgment module 103 as a detection signal on the one hand, and is input to the memory circuit as a clock on the other hand, thereby forming a ring oscillation.

[0072] If the delay adjustable timing module 101 is not set properly, the output signal waveform cannot continue to trigger the behavior of the ring oscillation test circuit in the first cycle after passing through the pulse shaping unit 122 with a fixed delay, that is, the ring oscillation cannot be maintained.

[0073] The adjustment result judgment module 103 can determine whether the memory works normally under the current delay configuration by checking whether the shaped signal is a continuous and stable periodic signal; if the memory can work normally, the shaped signal frequency is recorded, and the shaped signal frequency is the highest operating frequency that the memory can achieve under this configuration and environment.

[0074] Since all delay configurations need to be traversed during the timing adjustment process, it is necessary to save whether each delay configuration can work normally and the highest operating frequency for later comparison and selection.

[0075] Further, Figure 1 The control module 100 is also used to control the switching of different modes, which include: a timing adjustment mode and a normal working mode.

[0076] For example, using external control signals to control the switching of different modes, accordingly, Figure 2 One implementation of the control logic of the internal pulse signal generating unit 121 is as follows Figure 3 shown.

[0077] Reference Figure 3The oscillation start signal output by the control module 100 and the shaping signal output by the pulse shaping unit 122 are respectively input into the first AND gate 201, the output of the first AND gate 201 and the external control signal are respectively input into the second AND gate 202, the output of the second AND gate 202 triggers the internal pulse signal generating circuit 121 to generate a series of pulse signals similar to those in normal operation, and the optimal delay parameters are obtained by traversing all delay configurations.

[0078] In the timing adjustment mode, the adjustable delay timing module 101 traverses all delay configurations for the internal clock signal and performs delay according to the configured delay parameters;

[0079] In the normal working mode, the adjustable delay timing module 101 delays the external clock signal according to the optimal delay parameter obtained in the timing adjustment mode, and outputs various clock signals required for the memory operation.

[0080] Continue to refer to Figure 1 The adjustment result determination module 103 determines the most suitable delay configuration under the current working environment, that is, the optimal delay parameter, by comparing the performance parameters of the memory under different delay configurations.

[0081] In the timing adjustment mode, the adjustment result judgment module 103 makes a judgment based on the detection result as follows: Figure 4 As shown, the following steps are included:

[0082] First, in step 401, the current detection result, ie, the output signal of the ring oscillator test circuit, is obtained.

[0083] In step 402, it is determined whether all gears have been traversed, and different gears represent different delay parameters. If not, step 403 is executed; if yes, step 408 is executed.

[0084] In step 403, the gear position is updated.

[0085] In step 404 , it is determined whether the gear storage device is operating normally; if so, step 405 is executed; otherwise, the process returns to step 402 .

[0086] Specifically, whether the memory is working properly can be determined based on whether the output signal of the ring oscillation test circuit is a stable periodic signal. If the output signal is a stable periodic signal with a fixed period, the memory is working properly; if the output signal is not a continuous periodic signal, the memory cannot work properly.

[0087] If it does not work properly, the configuration is discarded. If the configuration traversal has not been completed, the configuration is switched; if the configuration traversal has been completed, the gear data related to the configuration with the best performance recorded before is output.

[0088] In step 405 , it is determined whether the operating frequency of the memory at this gear is currently the highest; if so, step 406 is executed; otherwise, step 407 is executed.

[0089] In step 406 , the current gear position data is recorded; then the process returns to step 402 .

[0090] In step 407 , the previous gear data is maintained; then the process returns to step 402 .

[0091] In step 408, the recorded optimal gear position data is output, and the optimal gear position data is the optimal delay parameter mentioned above.

[0092] It should be noted that after the adjustment result judgment module 103 completes the judgment, it outputs the gear data with the highest operating frequency, and the data includes the specific configuration of the gear and the operating frequency under the gear.

[0093] By outputting the operating frequency under the corresponding gear, the memory performance parameters can be provided to the user to avoid the memory function error caused by the user setting the operating frequency of the memory too high.

[0094] Continue to refer to Figure 1 The delay configuration module 104 can write to the delay-related dedicated configuration storage unit 105, that is, write the optimal configuration into the corresponding configuration unit to complete the configuration of the delay unit in the delay adjustable timing module 101. The configuration at this time is the configuration that enables the memory to work at the best performance under the current working environment.

[0095] Furthermore, in order to facilitate meeting different application requirements, in another non-limiting embodiment, the built-in timing adjustment circuit of the memory may also include a configuration module (not shown) for enabling or disabling the timing adjustment mode. Accordingly, the delay adjustable timing module 101 is also used to delay the output of the external clock signal according to the default delay parameter when the control module prohibits the timing adjustment mode, so as to control the read and write operations of the memory. The default delay parameter can be determined by pre-production testing, etc., and this embodiment of the present invention is not limited to this.

[0096] In the embodiment of the present invention, the control module 100 uses a state machine to control the state transition and the switching of different modes during the timing adjustment process. The state changes of the state machine are as follows: Figure 5 shown.

[0097] Reference Figure 5 , the state changes of the state machine are as follows:

[0098] First, enter the standby state. In this state, if the timing adjustment enable is invalid, the standby state is maintained; if the timing adjustment enable is valid, enter the timing adjustment mode.

[0099] After entering the timing adjustment mode, it enters the timing detection state.

[0100] In the timing detection state, the delay parameters configured by the adjustable delay timing module 101 are traversed, and timing detection is performed under each configured delay parameter, and then the corresponding timing detection result is saved. If all configurations have not been traversed, the timing detection state is maintained; after all configurations have been traversed, the detection result output state is entered.

[0101] In the detection result output state, the optimal delay parameter is obtained according to the traversal result; then the configuration state is entered.

[0102] In the configuration state, the optimal delay parameters are written into the corresponding storage unit; then the normal working mode is entered, and the state machine is restored to the standby state.

[0103] The state machine needs the relevant enable signal to be valid when entering the timing adjustment mode from the standby state, and the enable signal can be generated by the configuration module inside the chip. After completing the download of all chip bit streams, the configuration module sends a timing adjustment enable signal to the memory to enable the memory to enter the timing adjustment mode. After entering the timing adjustment mode, the adjustable delay timing module 101 traverses each delay configuration in turn under the control of the control module 100. For each configuration of a delay parameter, a timing test must be performed under the delay parameter, and the result of the timing test (i.e., whether the memory can work normally and the highest operating frequency under the currently configured delay parameter) is saved. After all configurations are traversed, the timing test results of each group are compared to determine the best delay configuration under the current environment and determine the optimal delay parameter. The determined optimal delay parameter is then written into the corresponding specific storage unit. At this point, the entire timing adjustment process is completed, the corresponding state signal is output and the circuit is switched to the normal working mode. The state machine returns to the standby state.

[0104] The delay parameters written by the state machine to a specific storage unit will be saved until the chip is configured again.

[0105] The memory built-in timing adjustment circuit provided by the embodiment of the present invention has the following advantages:

[0106] (1) The memory built-in timing adjustment circuit proposed by the present invention can help the memory achieve the highest frequency performance under certain process conditions and different working environments.

[0107] (2) The memory built-in timing adjustment circuit proposed in the present invention is integrated inside the memory. When this function is enabled, the memory will automatically perform timing adjustment after the chip is powered on, thereby ensuring that the memory can operate at the highest frequency under current conditions (such as PVT, i.e. process, voltage and temperature, etc.).

[0108] (3) The built-in timing adjustment circuit proposed by the present invention can adjust the timing structure of the circuit according to the current physical state of the chip. Therefore, the maximum frequency of the memory operation can be adjusted by changing the working conditions such as the applied voltage and the ambient temperature in combination with the timing adjustment circuit.

[0109] (4) The built-in timing adjustment circuit proposed in the present invention can extend the service life of the chip in disguise. As time goes by and the number of times the chip is used increases, the circuit performance gradually decreases, resulting in the circuit being unable to meet the fixed timing range and causing functional errors. However, this circuit can adjust the delay of the timing circuit, and can ensure the correct function of the circuit by adjusting the delay of the timing circuit.

[0110] Correspondingly, an embodiment of the present invention further provides a memory, which includes the above-mentioned memory built-in timing adjustment circuit.

[0111] Correspondingly, an embodiment of the present invention further provides a method for adjusting a built-in timing of a memory, wherein a delay-adjustable timing module is provided in the memory, and the delay-adjustable timing module is used to delay the output of an input clock signal to control the read and write operations of the memory.

[0112] like Figure 6 FIG. 1 is a flow chart of a method for adjusting the built-in timing of a memory provided by an embodiment of the present invention, comprising the following steps:

[0113] Step 601, before entering the normal working mode, entering the timing adjustment mode;

[0114] Step 602, in the timing adjustment mode, using the internal clock signal to configure different delay parameters of the adjustable delay timing module to perform timing detection, and output a detection signal;

[0115] Step 603, determining an optimal delay parameter according to the detection signal;

[0116] Step 604 , in the normal working mode, the adjustable delay timing module is enabled to delay the output of the external clock signal according to the optimal delay parameter to control the read and write operations of the memory.

[0117] In specific applications, a state machine can be used to control state transitions and switching between different modes during the timing adjustment process. For details, please refer to the description of the built-in timing adjustment circuit of the memory of the present invention, which will not be repeated here.

[0118] In order to meet different application requirements, in another non-limiting embodiment, the method of the present invention may further include the following steps:

[0119] generating an enable signal, wherein the enable signal is used to enable or disable the timing adjustment mode;

[0120] When the enable signal prohibits the timing adjustment mode, the delay adjustable timing module is enabled to delay the output of the external clock signal according to the default delay parameter to control the read and write operations of the memory.

[0121] By using the scheme of the present invention, the delay of the timing circuit in the memory can be simply and conveniently adjusted to adapt to the environment, so that the memory can achieve the optimal operating frequency performance. Furthermore, the user can decide whether to use the timing adjustment mode according to his own needs, so as to better meet various needs in different application environments.

[0122] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.

[0123] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0124] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory built-in timing adjustment circuit, characterized in that: The circuit comprises: The delay adjustable timing module is used to input a clock signal and output the clock signal with a delay; input an external clock signal in a normal working mode; and input an internal clock signal in a timing adjustment mode; A timing detection module, used for performing timing detection on the adjustable delay timing module with different delay parameters using an internal clock signal in a timing adjustment mode, and outputting a detection signal; An adjustment result judgment module is used to determine the optimal delay parameter according to the detection signal; A delay configuration module, used for writing the optimal delay parameter into a storage unit; The adjustable-delay timing module delays and outputs the external clock signal according to the optimal delay parameter written in the storage unit in the normal working mode to control the read and write operations of the memory; The control module is used to control the state transition during the timing adjustment process.

2. The memory built-in timing adjustment circuit according to claim 1, characterized in that: The adjustable delay timing module includes a timing control unit, and the timing control unit includes a plurality of delay sub-units with different gears; The delay subunit is used to generate a delay of a specific length according to the delay parameters in the storage unit, so as to adjust the width of the pulse signal input to the delay adjustable timing module and the interval between different clock signals.

3. The memory built-in timing adjustment circuit according to claim 1, characterized in that: The timing detection module includes: an internal pulse signal generating unit and a pulse shaping unit, and the internal pulse signal generating unit, the adjustable delay timing module, and the pulse shaping unit constitute a ring oscillation test structure; wherein: The internal pulse signal generating unit is used to generate an internal clock signal according to the start-up signal and the output of the pulse shaping unit, and output the internal clock signal to the adjustable delay timing module, so that the adjustable timing module outputs a delay signal; The adjustable delay timing module is further used to traverse each preset delay parameter in the timing adjustment mode until the adjustment result judgment module determines that the optimal delay parameter is obtained; A pulse shaping unit is used to shape the delayed signal into a signal whose frequency is related to the delay of the adjustable delay timing module, output it to the input end of the internal pulse signal generating unit, and output it to the adjustment result judgment module as the detection signal.

4. The memory built-in timing adjustment circuit according to claim 3, characterized in that: The timing detection module further includes: an AND gate, the AND gate is respectively input with the oscillation start signal and the delay signal, and the output end of the AND gate is connected with the input end of the internal pulse signal generating unit.

5. The memory built-in timing adjustment circuit according to claim 3, characterized in that: The adjustment result judgment module determines that the current delay parameter is the optimal delay parameter when the detection signal is a stable periodic signal.

6. The memory built-in timing adjustment circuit according to any one of claims 1 to 5, characterized in that: The control module is also used to control the switching of different modes, and the modes include: the timing adjustment mode and the normal working mode.

7. The memory built-in timing adjustment circuit according to claim 6, characterized in that: The control module uses a state machine to control state transitions during the timing adjustment process.

8. The memory built-in timing adjustment circuit according to claim 7, characterized in that: The circuit further comprises: A configuration module, used to enable or disable the timing adjustment mode; The delay adjustable timing module is also used to delay the output of the external clock signal according to the default delay parameters to control the read and write operations of the memory when the configuration module prohibits the timing adjustment mode.

9. A method for adjusting built-in timing of a memory, characterized in that: The memory is provided with a time-delay adjustable timing module, and the time-delay adjustable timing module is used to delay the output of the input clock signal to control the read and write operations of the memory; The method comprises: Before entering the normal working mode, enter the timing adjustment mode; In the timing adjustment mode, the internal clock signal is used to configure different delay parameters of the adjustable delay timing module to perform timing detection, and output a detection signal; Determine an optimal delay parameter according to the detection signal; In the normal working mode, the adjustable delay timing module is enabled to delay the output of the external clock signal according to the optimal delay parameter to control the read and write operations of the memory.

10. The memory built-in timing adjustment method according to claim 9, characterized in that: The method further comprises: The state machine is used to control the state transition and switching between different modes during the timing adjustment process.

11. The memory built-in timing adjustment method according to claim 9 or 10, characterized in that: The method further comprises: generating an enable signal, wherein the enable signal is used to enable or disable the timing adjustment mode; When the enable signal prohibits the timing adjustment mode, the delay adjustable timing module is enabled to delay the output of the external clock signal according to the default delay parameter to control the read and write operations of the memory.

12. A memory, characterized in that: The memory comprises the memory built-in timing adjustment circuit as claimed in any one of claims 1 to 8.

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