Memory control method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a memory control method and device, electronic equipment and a readable storage medium. The method comprises the following steps: determining N first data bits of which the anti-interference performance is lower than a preset condition in a memory; wherein N is a positive integer; acquiring eye pattern information of the N first data bits when the memory works, or acquiring antenna transmitting power of the electronic equipment when the memory works; adjusting the power supply voltage of a second data bit according to the eye pattern information of the second data bit; or adjusting the power supply voltage of the N first data bits according to the antenna transmitting power; wherein the second data bit is any data bit in the N first data bits.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and specifically relates to a memory control method, device, electronic device and readable storage medium. Background Art

[0002] With the popularization of the fifth generation mobile communication technology (5G), mobile phones and other electronic devices are equipped with a large number of antennas, and in order to meet the needs of communication signals, multiple-input and multiple-output (MIMO) antennas that transmit and receive multiple antennas at the same time have also appeared. As mobile phones and other electronic devices have more and more functions and their space is becoming more and more compact, the problem of antenna radiation interference in some modules inside electronic devices is becoming increasingly prominent, among which the problem of memory (such as double data rate synchronous dynamic random access memory (Double Data Rate, DDR)) being interfered by antenna radiation and causing bit reversal is particularly prominent (for example, bit reversal may be data 0 being interfered into 1, or data 1 being interfered into 0). In this regard, the commonly used solution is to do a good job of shielding to avoid long gaps that cause shielding leakage, but this method is difficult to implement in the situation where the space of electronic devices is rapidly compact. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a memory control method, device, electronic device and readable storage medium, which can solve the problem that the current method of solving memory interference is difficult to implement in hardware solutions.

[0004] In a first aspect, an embodiment of the present application provides a memory control method, which is applied to an electronic device, and the method includes:

[0005] Determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer;

[0006] Acquire eye diagram information of the N first data bits when the memory is working, or acquire antenna transmission power of the electronic device when the memory is working;

[0007] Adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

[0008] In a second aspect, an embodiment of the present application provides a memory control device, which is applied to an electronic device, including:

[0009] A processing module, used to determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer;

[0010] An acquisition module, used to acquire eye diagram information of the N first data bits when the memory is working, or to acquire antenna transmission power of the electronic device when the memory is working;

[0011] An adjustment module is used to adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or, to adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the memory control method described in the first aspect are implemented.

[0013] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the memory control method described in the first aspect are implemented.

[0014] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the steps of the memory control method described in the first aspect.

[0015] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the memory control method as described in the first aspect.

[0016] In the embodiment of the present application, for the N first data bits whose anti-interference performance is lower than the preset condition in the predetermined memory, the eye diagram information of the N first data bits is collected in real time, so that the power supply voltage of any second data bit in the N first data bits can be adjusted based on the eye diagram information of the second data bit; or the antenna transmission power when the memory is working is collected in real time, and the power supply voltage of the N first data bits whose anti-interference performance is lower than the preset condition in the predetermined memory is adjusted according to the collected antenna transmission power. In this way, the problem of the memory freezing due to antenna radiation interference can be solved, and the memory interference of the electronic device can be avoided when the electronic device is in use, and the problem of reducing the interference mode of the memory based on the hardware improvement solution can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of antenna radiation interfering with DDR according to an embodiment of the present application;

[0018] Figure 2 is one of the flow charts of the memory control method according to an embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of a receiving eye diagram of the LPDDR5 version of DDR in an embodiment of the present application;

[0020] Figure 4 It is a schematic diagram of the change of the eye diagram after the DQ8 to DQ15 are interfered by the antenna radiation in the test of the embodiment of the present application;

[0021] Figure 5 is one of the hardware architecture diagrams of the memory control device according to an embodiment of the present application;

[0022] Figure 6 This is the second flowchart of the memory control method according to the embodiment of the present application;

[0023] Figure 7 This is the second hardware architecture diagram of the memory control device according to the embodiment of the present application;

[0024] Figure 8 This is the third flowchart of the memory control method according to the embodiment of the present application;

[0025] Fig. 9 is a block diagram of a memory control device according to an embodiment of the present application;

[0026] Fig.10 is a block diagram of an electronic device according to an embodiment of the present application;

[0027] Fig.11 It is a schematic diagram of the hardware structure of the electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0029] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0030] The audio data processing method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0031] The following is an introduction to the relevant technologies involved in this application:

[0032] Take DDR memory as an example. Figure 1 As shown in FIG. 1 , a schematic diagram of antenna radiation interference DDR is given. When the antenna 5 is working, it will stimulate the circuit board 1 and the cavity of the middle frame 2 to generate strong electric field interference. Due to the consistency of process assembly and long-term use, such as Figure 1 Circles 11, 12, 13, and 14 may cause the copper foil 3 on top of the DDR to become less sticky and warp, or cause some legs of the shielding cover 4 to be poorly soldered, resulting in long gaps and shielding leakage. The gaps are stimulated to produce potential differences, which in turn generate strong electric and magnetic field interference in the shielding cavity. The internal packaging structure of DDR will be interfered by strong electric and magnetic fields. When the interference exceeds a certain threshold, some data bits of DDR will be reversed and the electronic equipment will crash.

[0033] Considering the problem that it is difficult to implement a hardware solution to solve the problem of antenna radiation interfering with DDR, a software solution is used as a solution to solve the problem of antenna radiation interfering with DDR. For example, an effective measure is to turn off the dynamic voltage and frequency scaling (Dynamic Voltage and Frequency Scaling for VDDQ, DVFSQ) module, especially when the DDR is interfered with during the use of DDR, since the hardware cannot be changed, it is considered to solve the problem of DDR interference by turning off the DVFSQ module. Among them, VDDQ refers to the power supply voltage of the data bit in DDR.

[0034] Specifically, the definition of DVFSQ is as follows: when the DDR operating frequency is high, the data bit power supply voltage is high (for example, VDDQ = 0.5V at this time), and when the DDR operating frequency is low, the data bit power supply voltage is low (for example, VDDQ = 0.3V at this time), so as to save power when the DDR is lightly loaded and the operating frequency is low. When the DDR is working at a low frequency, when the DVFSQ module is turned off, its VDDQ voltage increases, which can improve the antenna's anti-interference ability. However, considering that electronic devices such as mobile phones are often used in light-load scenarios, the DDR operating frequency is low at this time. Turning off the DVFSQ module will cause the VDDQ voltage to increase, that is, the power supply voltage of all data bits will be raised (for example, from 0.3V to 0.5V), which will generate greater power consumption and affect the use time.

[0035] like Figure 2 As shown, an embodiment of the present invention provides a memory control method, which is applied to an electronic device, and the method includes the following steps:

[0036] Step 21: Determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer.

[0037] Optionally, there may be multiple data bits in the memory, for example, DDR may have 16 data bits or other number of data bits, etc., but the embodiments of the present application are not limited thereto.

[0038] The memory may have a bit inversion phenomenon due to antenna radiation interference (i.e., one or more data bits in the memory are bit inverted, such as some data bits change from 0 to 1, or from 1 to 0 after the data enters the memory), and the first data bit whose anti-interference performance is lower than the preset condition is the data bit that is bit inverted due to a certain degree of antenna radiation interference. For example, the N first data bits can be data bits that are bit inverted due to a certain degree of antenna radiation interference determined in advance through testing.

[0039] Optionally, the bit inversion phenomenon can also be represented by the eye diagram information of the data bit. For example, when the eye height value corresponding to the eye diagram information of the data bit is lower than the first eye height threshold, it is determined that the data bit is prone to or has undergone the bit inversion phenomenon, or the anti-interference performance of the data bit is lower than the preset condition, that is, the first data bit whose anti-interference performance is lower than the preset condition is the data bit whose eye height value corresponding to the eye diagram information is lower than the first eye height threshold due to a certain degree of antenna radiation interference. For example, the N first data bits can be data bits that are determined in advance through testing to be lower than the first eye height threshold due to a certain degree of antenna radiation interference.

[0040] Among them, the first eye height threshold can be a standard eye height threshold, or an eye height value corresponding to the eye diagram information of the data bit in the memory when the memory is not interfered by antenna radiation, or an eye height value corresponding to the eye diagram information of the data bit in the memory with anti-interference performance higher than or equal to a preset condition, etc. The embodiments of the present application are not limited to this.

[0041] Step 22: Obtain eye diagram information of the N first data bits when the memory is working, or obtain antenna transmission power of the electronic device when the memory is working.

[0042] Optionally, when the memory is working, the eye diagram information of the N first data bits can be collected in real time (i.e., the eye diagram information of the N first data bits in the memory whose anti-interference performance is lower than the preset condition is collected in real time). Alternatively, when the memory is working, the transmission power value of the antenna in the electronic device is collected in real time.

[0043] Step 23: Adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or, adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

[0044] Optionally, by comparing the eye height value of the eye diagram information of the N first data bits collected in real time with the eye height threshold, the supply voltage of the second data bit that meets the adjustment condition is adjusted. Alternatively, by comparing the antenna transmission power collected in real time with the power threshold, the supply voltage of all data bits in the N first data bits is adjusted when the adjustment condition is met.

[0045] In this embodiment, for the N first data bits whose anti-interference performance is lower than the preset condition in the predetermined memory, the eye diagram information of the N first data bits is collected in real time, so that the power supply voltage of any second data bit in the N first data bits can be adjusted based on the eye diagram information of the second data bit; or the antenna transmission power when the memory is working is collected in real time, and the power supply voltage of the N first data bits whose anti-interference performance is lower than the preset condition in the predetermined memory is adjusted according to the collected antenna transmission power. In this way, the problem of the memory freezing due to antenna radiation interference can be solved, and the memory interference of the electronic device can be avoided when it is in use, and the problem of reducing the memory interference mode based on the hardware improvement solution can be solved.

[0046] Furthermore, in the embodiment of the present application, by determining some data bits (i.e., N first data bits) in the memory whose anti-interference performance is lower than a preset condition, and by real-time acquisition of eye diagram information of these data bits (i.e., N first data bits), or real-time acquisition of the antenna transmission power when the memory is working, the voltage of one or more data bits in these data bits (i.e., N first data bits) is adjusted, thereby avoiding the problem of increased power consumption caused by the software control method of shutting down the DVFSQ module, which causes the voltage of all data bits of the memory to rise. Therefore, compared with the software control method of shutting down the DVFSQ module, this solution can reduce power consumption, increase the use time of the electronic device, and improve the user experience.

[0047] Taking DDR memory as an example to illustrate the implementation principle of the embodiment of the present application: Considering that with the development of technology, the DDR interface frequency continues to increase, and the influence of process, voltage, and temperature is increasing, the timing margin of DDR interface signals is getting smaller and smaller. The DDR eye diagram shape is formed by constructing the transmission waveform at the moment of DDR data transmission. The eye height and eye width of the DDR eye diagram are key parameters for evaluating the stability, timing error, and jitter of the DDR signal.

[0048] In order to ensure the timing margin of DDR, the clock delay and the reference level (Vref) of the receiving end input signal are scanned. That is, different delays are made to the DDR clock, and different Vrefs are adjusted. The normal and abnormal points of DDR reading and writing are marked respectively to form an electronic eye diagram. The optimal parameters are selected according to the formed electronic eye diagram to ensure that DDR transmission has a better timing margin.

[0049] like Figure 3 As shown, it is a schematic diagram of a DDR receiving eye diagram, wherein the marked "Q" (i.e., the area inside the rectangular box) is the JEDEC eye diagram template 31, "O" (i.e., the area outside the rectangular box and adjacent to the rectangular box) indicates that the test at this position is successful, and "-" indicates that the test at this position fails. The more the positions marked "O" exceed the positions marked "Q", the larger the eye width 32 and the eye height (including the upper eye height 33 and the lower eye height 34), indicating that the timing margin is more sufficient.

[0050] The internal chip (die) of DDR is connected to the substrate through metal bonding wires. The reason why DDR is interfered by antenna radiation is that the metal bonding wires are long and the current return loop is large. The DDR current return loop picks up the antenna noise, resulting in insufficient DDR timing margin.

[0051] For example, take the DDR data (DQ) signal with 16 bits or positions (bit) as an example. Due to the internal binding line return loop and the internal PIN pin distribution relationship, a small part of the DDR data bits (such as 1 to 2 data bits in one or more specific positions) are easily interfered with, while most data bits have strong anti-interference capabilities. Due to the working mechanism and transmission characteristics of DDR, the DQ signal is more susceptible to interference when receiving than when sending. Therefore, the receiving signal of a small part of the data bits of DDR (such as 1 to 2 data bits in one or more specific positions) is easily interfered by antenna radiation. Through antenna radiation interference with the DDR electronic eye diagram scanning, before the DDR is interfered and crashed, the eye diagram of some data bits in the DDR will be significantly deteriorated, while the eye diagram of other data bits will change less. For example Figure 4 As shown in the figure, it is a schematic diagram of the changes in the eye diagram after testing DQ8~DQ15 being interfered by antenna radiation, wherein the first row of eye diagrams is the eye diagram collected when the external interference is small, and the second row is the electronic eye diagram collected when the external interference is large. It can be found that only DQ9 has a significant attenuation of the eye height and eye width when the antenna radiation interference is large, while other data bits are less affected.

[0052] Optionally, the determining N first data bits in the memory whose anti-interference performance is lower than a preset condition includes:

[0053] Adding antenna radiation interference to the memory according to a preset step length, and obtaining eye diagram information of each data bit in the memory under different antenna radiation interferences;

[0054] If the eye height value corresponding to the eye diagram information of each acquired data bit is smaller than the first eye height threshold, the data bit corresponding to the eye diagram information having the eye height value smaller than the first eye height threshold is determined as the first data bit.

[0055] For example, the step size refers to the increment of the independent variable from one value to its adjacent value, such as the independent variable X changes from 1 to 2, and its step size is 1. Specifically, adding antenna radiation interference to the memory according to the preset step size, and obtaining the eye diagram information of each data bit in the memory under different antenna radiation interferences means that the antenna radiation interference Y is applied to the memory for the i-th time, and the eye diagram information of each data bit in the memory is obtained when the antenna radiation interference is Y; the antenna radiation interference Y+A is applied to the memory for the i+1th time, and the eye diagram information of each data bit in the memory is obtained when the antenna radiation interference is Y+A; the antenna radiation interference Y+2A is applied to the memory for the i+2th time, and the eye diagram information of each data bit in the memory is obtained when the antenna radiation interference is Y+2A, and the eye diagram information of each data bit in the memory is obtained when the antenna radiation interference is Y+2A, and so on. Wherein, i is a positive integer, and A represents the preset step size. In this way, each time the antenna radiation interference is added to the memory according to the preset step size, the eye diagram information of each data bit can be obtained, thereby obtaining the eye diagram information of each data bit in the memory under different antenna radiation interferences, and by finding the eye diagram information with an eye height value less than the first eye height threshold, the N first data bits in the memory whose anti-interference performance is lower than the preset condition can be determined.

[0056] For another example, consider the case where the eye height value corresponding to the eye diagram information of the data bit is lower than the first eye height threshold, it is determined that the data bit is prone to or has undergone bit inversion, that is, the data "0" is interfered with into "1", or the data "1" is interfered with into "0", and whether bit inversion has occurred is determined by comparing the value of the corresponding data bit before inputting the memory with the value of the corresponding data bit determined by the acquired eye diagram information. For example, if the value of the corresponding data bit before inputting the memory is "1", but the value of the corresponding data bit determined by the eye diagram information is "0", or the value of the corresponding data bit before inputting the memory is "0", but the value of the corresponding data bit determined by the eye diagram information is "1", then it is determined that bit inversion has occurred. In this way, each time the antenna radiation interference is added to the memory according to the preset step size, the eye diagram information of each data bit can be obtained, thereby obtaining the eye diagram information of each data bit in the memory under different antenna radiation interferences. If the eye diagram information of each data bit obtained contains bit-reversed eye diagram information, the data bit corresponding to the eye diagram information with bit reversal is determined as the first data bit. Therefore, by finding the eye diagram information with bit reversal, the N first data bits in the memory whose anti-interference performance is lower than the preset condition can be determined.

[0057] In this embodiment, the N first data bits in the memory whose anti-interference performance is lower than the preset condition can be predicted by adding antenna radiation interference to the memory in advance. Specifically, taking DDR as an example, antenna radiation interference can be added to the memory according to a preset step size. For example, taking DDR with 16 data bits as an example, the eye diagram information of DQ0 to DQ15 before the DDR crashes can be collected to confirm one or more data bits with the largest eye diagram attenuation (data bits corresponding to the eye diagram information with an eye height value less than the first eye height threshold, or data bits corresponding to the eye diagram information with bit inversion), which are the N first data bits.

[0058] Optionally, adjusting the supply voltage of the second data bit according to the eye diagram information of the second data bit includes:

[0059] When the eye height value corresponding to the eye diagram information of the second data bit is greater than or equal to the second eye height threshold, adjusting the supply voltage of the second data bit to the first voltage value;

[0060] When the eye height value corresponding to the eye diagram information of the second data bit is less than the second eye height threshold, adjusting the supply voltage of the second data bit to a second voltage value;

[0061] Wherein, the first voltage value is smaller than the second voltage value.

[0062] For example, taking DDR as an example, the second eye height threshold can be an eye height threshold (for example, a fixed value) determined based on the prediction of the N first data bits in the DDR that are most affected by antenna radiation interference; or it can be an eye height threshold that is updated in real time based on the interference situation when the memory is working, etc. The embodiments of the present application are not limited to this.

[0063] For example: if the eye height value corresponding to the eye diagram information of one or more second data bits among the N first data bits measured in real time is greater than or equal to the second eye height threshold, the supply voltage of the second data bit is adjusted to the first voltage value (for example, adjusted to 0.3V); if the eye height value corresponding to the eye diagram information of one or more second data bits among the N first data bits measured in real time is less than the second eye height threshold, the supply voltage of the second data bit is adjusted to the second voltage value (for example, adjusted to 0.5V). It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the supply voltage for a certain DDR, and the specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiments of the present application are not limited thereto.

[0064] Optionally, the second eye height threshold is determined by:

[0065] When the antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

[0066] or,

[0067] When antenna radiation interference is added to the memory according to a preset step size, if bit inversion occurs in the eye diagram information of N first data bits when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

[0068] For example, taking DDR as an example, antenna radiation interference can be applied to the electronic device according to a preset step length, and the eye diagram information of DDR is collected during the antenna radiation interference, and it is confirmed whether the eye height value corresponding to the eye diagram information of the data bit in DDR is less than the first eye height threshold, or whether the eye diagram information of the data bit in DDR has undergone bit reversal. For example, when the eye height values ​​corresponding to the eye diagram information of N first data bits are less than the first eye height threshold, or the eye diagram information of N first data bits has undergone bit reversal, the eye diagram information collected when the antenna radiation interference was applied last time is extracted. For example, taking DDR with 16 data bits (such as data bits DQ0 to DQ15) as an example, the eye height values ​​of the DQ0 to DQ15 receiving signals can be extracted from the eye diagram information collected when the antenna radiation interference was applied last time, and the N data bits with greater attenuation (that is, the data bits corresponding to the N eye diagram information with eye height values ​​less than the first eye height threshold, or the bit reversal has occurred) are determined. Based on the eye height values ​​corresponding to the eye diagram information of the N data bits, a second eye height threshold is determined (for example, the minimum eye height value among the eye height values ​​corresponding to the eye diagram information of the N data bits can be determined as the second eye height threshold; or, the second eye height threshold is determined by taking the average of the eye height values ​​corresponding to the eye diagram information of the N data bits; or, the eye height value corresponding to the eye diagram information of the data bit that is most interfered by antenna radiation among the N data bits is taken as the second eye height threshold; or other methods besides these can be used, and the embodiments of the present application are not limited thereto).

[0069] Optionally, the second eye height threshold is updated in the following manner:

[0070] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0071] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a first preset threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the first preset threshold.

[0072] Alternatively, the second eye height threshold is updated in the following manner:

[0073] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0074] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a current second eye height threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the current second eye height threshold.

[0075] Alternatively, the second eye height threshold is updated in the following manner:

[0076] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0077] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the acquired eye diagram information of the N first data bits includes bit-reversed eye diagram information, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information with bit reversal.

[0078] For example, due to individual differences and working environment differences of different electronic devices, the eye height thresholds of different states of each electronic device are not exactly the same, and the second eye height threshold can be updated during the use stage of the electronic device. Taking DDR as an example, the second eye height threshold can be determined in the above manner as the initial eye height threshold, and the eye height threshold can be updated in different ways based on the idle state and non-idle state of the data bit. For example: Taking DDR with 16 data bits, these 16 data bits correspond to 4 channels as an example, during the use stage of the electronic device, when the DDR load is light, it only needs to run on 1 channel, and the other 3 channels can take turns to do eye diagram training, and only the above determined N data bits with large attenuation (i.e., the N first data bits whose anti-interference performance is lower than the preset condition) need to be trained in real time to avoid training all the data bits and address signals or chip select signals in these 16 data bits, which results in too long a time consumption.

[0079] Specifically, the eye diagram setting parameters can be pulled biased (i.e., the power supply voltage is determined by gradually reducing or increasing the input signal level of the DDR receiving end) according to the second eye height threshold determined last time, and data is written to the DDR and then read back, and the eye diagram information of each data bit is collected. If there is no eye diagram information with an eye height value less than the first preset threshold in the collected eye diagram information, or there is no eye diagram information with an eye height value less than the current second eye height threshold, the power supply voltage continues to be reduced or increased and the above steps are performed; if there is eye diagram information with an eye height value less than the first preset threshold in the collected eye diagram information, or there is eye diagram information with an eye height value less than the current second eye height threshold, the eye height value corresponding to the eye diagram information with an eye height value less than the first preset threshold, or the eye height value corresponding to the eye diagram information with an eye height value less than the current second eye height threshold is used to replace the current second eye height threshold (i.e., the second eye height threshold determined last time), so as to update the second eye height threshold. Alternatively, the eye diagram setting parameters can be set based on the second eye height threshold determined last time (i.e., the input signal level of the DDR receiving end is gradually reduced or increased to determine the power supply voltage). By writing data to the DDR and then reading the data back, each data bit is compared to see if there is an error. If there is no error, the power supply voltage is further reduced or increased and the above steps are performed. If there is an error, it means that there is a bit inversion. The eye height value at this time is obtained, and the eye height value is used to replace the current second eye height threshold (i.e., the second eye height threshold determined last time), thereby updating the second eye height threshold.

[0080] like Figure 5As shown in the figure, taking DDR with 16 data bits (such as data bits DQ0 to DQ15) as an example, a hardware architecture diagram of a memory control device is given, and the hardware architecture of the memory control device includes: an eye height threshold feedback adjustment system, a data bit eye diagram information real-time acquisition module, an eye height comparison module, a DQ0 to DQ15 power supply control module, etc. Among them, the eye height threshold feedback adjustment system includes a data bit discrimination module with poor anti-interference, an eye diagram training parameter deviation module, and an eye diagram parameter suitability judgment module.

[0081] Among them, the data bit identification module with poor anti-interference is mainly used to collect the eye diagram information of the 16 data bits (i.e., data bits DQ0 to DQ15) before the DDR crashes under different hardware interferences, confirm the data bit with the largest eye attenuation (i.e., the first data bit with anti-interference performance lower than the preset condition), and extract the corresponding eye height value as the initial value of the second eye height threshold. Eye diagram training refers to training the DDR eye diagram parameters to find the best setting parameters. The eye diagram training parameter deviation module is mainly used to deviation the eye diagram setting parameters (such as gradually reducing or increasing the input signal level of the DDR receiving end to determine the power supply voltage) according to the last second eye height threshold. The eye diagram parameter suitability judgment module determines whether there is a bit inversion or whether the eye height value of the eye diagram information is less than the first eye height threshold or whether the eye height value of the eye diagram information is less than the current second eye height threshold. If so, the eye height value at this time is obtained and the second eye height threshold is updated. For example, when DDR is lightly loaded, real-time eye diagram training is performed on the N data bits with greater attenuation (the N first data bits whose anti-interference performance is lower than the preset condition), and the second eye high threshold is updated to avoid the problem of time-consuming training for all the 6 data bits and other address signals or chip select signals.

[0082] The eye height comparison module is mainly used to compare the real-time eye height value of the data bit with the second eye height threshold, and the DQ0~DQ15 power supply control module is composed of two power supply inputs (such as a first voltage value and a second voltage value) and a switching switch. For example: if the real-time eye height value of the data bit is greater than or equal to the second eye height threshold, the power supply control module switches the power supply input of the data bit to the first voltage value (such as 0.3V); or if the real-time eye height value of the data bit is less than the second eye height threshold, the power supply control module switches the power supply input of the data bit to the second voltage value (such as 0.5V). It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the power supply voltage for a certain DDR. The specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiments of the present application are not limited to this.

[0083] like Figure 6 As shown, a flow chart of a memory control method is given, which specifically includes:

[0084] Step 61: collecting eye diagram information of DDR when adding antenna radiation interference to the memory according to a preset step length;

[0085] Step 62: determine whether the eye diagram information collected from the DDR is bit-reversed or whether the eye height value corresponding to the eye diagram information is less than the first eye height threshold; if so, continue to step 63; if not, return to step 61;

[0086] Step 63: extracting the eye diagram information when the antenna radiation interference was applied last time;

[0087] Step 64: extracting the eye height value corresponding to the eye diagram information of 16 data bits (ie, data DQ0 to DQ15), that is, the eye diagram information of each data bit in step 63;

[0088] Step 65: determining an initial second eye height threshold value according to the eye height values ​​of the N data bits with larger eye height value attenuation; the N data bits with larger eye height value attenuation here may be the N data bits where the eye diagram information undergoes bit inversion, or the N data bits where the eye height values ​​corresponding to the eye diagram information are smaller than the first eye height threshold value, that is, the N first data bits whose anti-interference performance is lower than the preset condition in the above embodiment;

[0089] Step 66: Determine whether the DDR is idle; if so, execute step 67; if not, execute step 68;

[0090] Step 67: bias the training parameters and determine whether bit inversion occurs or whether the eye height value of the eye diagram information is less than the first eye height threshold or whether the eye height value of the eye diagram information is less than the current second eye height threshold; if so, extract the eye height value and execute step 69; if not, return to step 66;

[0091] Step 68: collecting eye diagram information of N data bits with large eye height value attenuation in real time, extracting the eye height value, and executing step 69;

[0092] Step 69: Update the second eye high threshold;

[0093] Step 610: determine whether the eye height value corresponding to the eye diagram information of the N data bits collected in real time exceeds the second eye height threshold; if so, execute step 611; if not, execute step 612;

[0094] Step 611: the supply voltage corresponding to the data bit is a first voltage value (eg, VDDQ=0.3V);

[0095] Step 612: The supply voltage corresponding to the data bit is a second voltage value (eg, VDDQ=0.5V).

[0096] In the embodiment of the present application, before the DDR is crashed due to antenna radiation interference, only the eye diagrams of N data bits will be significantly deteriorated. When it is detected that the eye height value corresponding to the eye diagram information of a certain data bit is lower than the second eye height threshold, only the power supply voltage of this data bit is increased from the first voltage value to the second voltage value (for example, from 0.3V to 0.5V), and the other data bits maintain the first voltage value (for example, 0.3V) for power supply. When it is detected that the eye height value of this data signal exceeds the second eye height threshold, the power supply voltage is reduced from the second voltage value to the first voltage value (for example, from 0.5V to 0.3V). In this way, for multiple data bits of DDR, there is no need to adjust the power supply voltage for all data bits, thereby reducing power consumption, and when only this data bit is interfered by antenna radiation, the power supply voltage of this data signal is increased, and because of the real-time detection method, the crash problem of electronic equipment can also be reduced. It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the power supply voltage for a certain DDR. The specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiments of the present application are not limited to this.

[0097] Optionally, adjusting the supply voltage of the N first data bits according to the antenna transmit power includes:

[0098] When the antenna transmission power is less than the power threshold, adjusting the supply voltage of the N first data bits to a first voltage value;

[0099] When the antenna transmission power is greater than or equal to the power threshold, adjusting the supply voltage of the N first data bits to a second voltage value;

[0100] Wherein, the first voltage value is smaller than the second voltage value.

[0101] For example, taking DDR as an example, the power threshold can be based on the antenna transmission power of the electronic device determined when predicting the N first data bits in the DDR that are most affected by antenna radiation interference. If the transmission power of the electronic device measured in real time when the memory is working is greater than or equal to the power threshold, the power supply voltage of all the N first data bits is adjusted to a second voltage value (for example, adjusted to 0.5V); if the transmission power of the electronic device measured in real time when the memory is working is less than the power threshold, the power supply voltage of all the N first data bits is adjusted to a second voltage value (for example, adjusted to 0.3V). It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the power supply voltage for a certain DDR. The specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiments of the present application are not limited to this.

[0102] Optionally, the power threshold is determined in the following manner:

[0103] In the case where antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits when the antenna radiation interference is added for the i-th time is less than the first eye height threshold, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer;

[0104] or,

[0105] When the antenna radiation interference is increased to the memory according to a preset step size, if the eye diagram information of N first data bits is bit inverted when the antenna radiation interference is increased for the i-th time, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is increased for the i-1th time; wherein i is a positive integer.

[0106] For example, taking DDR as an example, antenna radiation interference can be applied to the electronic device according to a preset step size, and the eye diagram information of DDR is collected during the antenna radiation interference, and it is confirmed whether the eye height value corresponding to the eye diagram information of the data bit in DDR is less than the first eye height threshold, or whether the eye diagram information of the data bit in DDR has bit inversion. For example, when the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold, or the eye diagram information of N first data bits has bit inversion, the antenna transmission power when the antenna radiation interference was applied last time is determined as the power threshold.

[0107] like Figure 7 As shown, taking DDR with 16 data bits as an example, a hardware architecture diagram of another memory control device is given, and the hardware architecture of the memory control device includes: a data bit discrimination module with poor anti-interference, a power threshold generation module, an antenna transmission power real-time acquisition module, and an antenna transmission power comparison module.

[0108] Among them, the data bit identification module with poor anti-interference is mainly used to collect the eye diagram information of the 16 data bits (i.e., data bits DQ0~DQ15) before DDR crash when different hardware interferences are added, confirm the data bit with the largest eye diagram attenuation, that is, determine the N first data bits with poor anti-interference, and extract the antenna transmission power of the corresponding external interference as the power threshold of the power threshold generation module.

[0109] The antenna transmission power real-time acquisition module is mainly used for real-time acquisition of the antenna transmission power of the electronic device when the memory is working.

[0110] The antenna transmission power comparison module is mainly used to compare the real-time antenna transmission power with the power threshold, and the DQ0~DQ15 power supply control module consists of two power supply inputs (such as a first voltage value and a second voltage value) and a switching switch. For example: if the real-time antenna transmission power is greater than or equal to the power threshold, the power supply control module switches the power supply input of the data bit to the second voltage value (such as 0.5V); or if the real-time antenna transmission power is less than the power threshold, the power supply control module switches the power supply input of the data bit to the first voltage value (such as 0.3V). It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the power supply voltage for a certain DDR. The specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiments of the present application are not limited to this.

[0111] like Figure 8 As shown, a flowchart of another memory control method is given, which specifically includes:

[0112] Step 8: Collecting eye diagram information of DDR when adding antenna radiation interference to the memory according to a preset step length;

[0113] Step 82: determine whether the eye diagram information collected from the DDR is bit-reversed or whether the eye height value corresponding to the eye diagram information is less than the first eye height threshold; if so, continue to execute step 83; if not, return to step 81;

[0114] Step 83: extracting the eye diagram information when the antenna radiation interference was applied last time;

[0115] Step 84: extracting the eye height value corresponding to the eye diagram information of 16 data bits (ie, data bits DQ0 to DQ15), that is, the eye diagram information of each data bit in step 83;

[0116] Step 85: extracting the antenna transmission power when the eye height value corresponding to the bit reversal or eye diagram information is less than the first eye height threshold as the power threshold;

[0117] Step 86: determining N data bits with greater attenuation based on step 84; the N data bits with greater attenuation of eye height values ​​here may be N data bits where bit inversion occurs in the eye diagram information, or N data bits where the eye height values ​​corresponding to the eye diagram information are less than the first eye height threshold, that is, the N first data bits where the anti-interference performance is lower than the preset condition in the above embodiment;

[0118] Step 87: Collect antenna transmission power in real time;

[0119] Step 88: Determine whether the antenna transmission power collected in real time exceeds the power threshold; if so, execute step 89; if not, execute step 810;

[0120] Step 89: the supply voltage corresponding to the data bit is a second voltage value (eg, VDDQ=0.5V);

[0121] Step 810: The supply voltage corresponding to the data bit is a first voltage value (eg, VDDQ=0.3V).

[0122] In the embodiment of the present application, before the DDR is crashed by antenna radiation interference, only the eye diagram of N data bits will be significantly deteriorated. When the real-time antenna transmission power is detected to be lower than the power threshold, only the power supply voltage of these N data bits is increased from the first voltage value to the second voltage value (for example, from 0.3V to 0.5V), and the other data bits maintain the first voltage value (for example, 0.3V) for power supply. When it is detected that the antenna transmission power exceeds the power threshold, the power supply voltage is reduced from the second voltage value to the first voltage value (for example, from 0.5V to 0.3V). In this way, for multiple data bits of DDR, there is no need to adjust the power supply voltage for all data bits, thereby reducing power consumption, and when only some data bits with poor anti-interference performance are interfered by antenna radiation, the power supply voltage of these data bits is increased, and because of the real-time detection method, the crash problem of electronic equipment can also be reduced. It should be noted here that the first voltage value of 0.3V and the second voltage value of 0.5V are only examples of the power supply voltage for a certain DDR. The specific values ​​of the first voltage value and the second voltage value can be set based on the DDR type, and the embodiment of the present application is not limited to this.

[0123] The memory control method provided in the embodiment of the present application can be executed by a memory control device. In the embodiment of the present application, a method for a memory control device to execute audio data processing is taken as an example to illustrate the memory control device provided in the embodiment of the present application.

[0124] like Fig. 9 As shown, an embodiment of the present application provides a memory control device 900, which is applied to an electronic device, including:

[0125] The processing module 910 is used to determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer;

[0126] An acquisition module 920, configured to acquire eye diagram information of the N first data bits when the memory is working, or acquire antenna transmission power of the electronic device when the memory is working;

[0127] The adjustment module 930 is used to adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or to adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

[0128] Optionally, the processing module 910 includes:

[0129] An acquisition unit, configured to add antenna radiation interference to the memory according to a preset step length, and acquire eye diagram information of each data bit in the memory under different antenna radiation interferences;

[0130] A determining unit is configured to determine, if the eye height value corresponding to the acquired eye diagram information of each data bit is less than a first eye height threshold, the data bit corresponding to the eye diagram information having an eye height value less than the first eye height threshold as the first data bit.

[0131] Optionally, the adjustment module 930 includes:

[0132] A first adjustment unit, configured to adjust the supply voltage of the second data bit to a first voltage value when an eye height value corresponding to the eye diagram information of the second data bit is greater than or equal to a second eye height threshold;

[0133] A second adjustment unit, configured to adjust the supply voltage of the second data bit to a second voltage value when the eye height value corresponding to the eye diagram information of the second data bit is less than a second eye height threshold;

[0134] Wherein, the first voltage value is smaller than the second voltage value.

[0135] Optionally, the memory control device 900 further includes:

[0136] The first determination module is used to determine the eye height threshold in the following manner:

[0137] When the antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

[0138] Optionally, the memory control device 900 further includes:

[0139] An updating module, configured to update the second eye height threshold in the following manner:

[0140] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0141] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a first eye height threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the first eye height threshold.

[0142] Alternatively, the updating module is used to update the second eye height threshold in the following manner:

[0143] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0144] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a current second eye height threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the current second eye height threshold.

[0145] Optionally, the adjustment module 930 includes:

[0146] A third adjustment unit, configured to adjust the supply voltage of the N first data bits to a first voltage value when the antenna transmit power is less than a power threshold;

[0147] a fourth adjustment unit, configured to adjust the supply voltage of the N first data bits to a second voltage value when the antenna transmit power is greater than or equal to a power threshold;

[0148] Wherein, the first voltage value is smaller than the second voltage value.

[0149] Optionally, the memory control device 900 further includes:

[0150] The second determining module is used to determine the power threshold in the following manner:

[0151] When the antenna radiation interference is increased to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is increased for the i-th time, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is increased for the i-1th time; wherein i is a positive integer.

[0152] The device in the embodiment of the present invention collects the eye diagram information of the N first data bits in the memory whose anti-interference performance is lower than the preset condition in real time, so that the power supply voltage of any second data bit in the N first data bits can be adjusted based on the eye diagram information of the second data bit; or collects the antenna transmission power when the memory is working in real time, and adjusts the power supply voltage of the N first data bits in the memory whose anti-interference performance is lower than the preset condition according to the collected antenna transmission power. This can solve the problem of the memory freezing due to antenna radiation interference, avoid the memory being interfered when the electronic device is in use, and solve the problem of the difficulty in reducing the memory interference based on the hardware improvement solution, and avoid the problem of increasing power consumption caused by turning off the software control method of the DVFSQ module, so that the voltage of all data bits of the memory is raised, thereby increasing the use time of the electronic device and improving the user experience.

[0153] The memory control device in the embodiment of the present application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

[0154] The audio data processing device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0155] The audio data processing device provided in the embodiment of the present application can achieve Figures 2 to 8 To avoid repetition, the various processes implemented in the illustrated method embodiment will not be described again here.

[0156] Alternatively, if Fig.10As shown, an embodiment of the present application further provides an electronic device 1000, including a processor 1001 and a memory 1002, wherein the memory 1002 stores a program or instruction that can be executed on the processor 1001, and when the program or instruction is executed by the processor 1001, each step of the above-mentioned audio data processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0157] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0158] Fig.11 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0159] The electronic device 1100 includes but is not limited to: a radio frequency unit 1101, a network module 1102, an audio output unit 1103, an input unit 1104, a sensor 1105, a display unit 1106, a user input unit 1107, an interface unit 1108, a memory 1109, and a processor 1110 and other components.

[0160] Those skilled in the art will appreciate that the electronic device 1100 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1110 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.11 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0161] The processor 1110 is used for:

[0162] Determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer;

[0163] Acquire eye diagram information of the N first data bits when the memory is working, or acquire antenna transmission power of the electronic device when the memory is working;

[0164] Adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

[0165] Optionally, the processor 1110 is further configured to:

[0166] Adding antenna radiation interference to the memory according to a preset step length, and obtaining eye diagram information of each data bit in the memory under different antenna radiation interferences;

[0167] If the eye height value corresponding to the acquired eye diagram information of each data bit is smaller than the eye diagram information of the first eye height threshold, the data bit corresponding to the eye diagram information having the eye height value smaller than the first eye height threshold is determined as the first data bit.

[0168] Optionally, the processor 1110 is further configured to:

[0169] When the eye height value corresponding to the eye diagram information of the second data bit is greater than or equal to the second eye height threshold, adjusting the supply voltage of the second data bit to the first voltage value;

[0170] When the eye height value corresponding to the eye diagram information of the second data bit is less than the second eye height threshold, adjusting the supply voltage of the second data bit to a second voltage value;

[0171] Wherein, the first voltage value is smaller than the second voltage value.

[0172] Optionally, the processor 1110 is further configured to determine the second eye height threshold in the following manner:

[0173] When the antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

[0174] Optionally, the processor 1110 is further configured to update the second eye height threshold in the following manner:

[0175] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0176] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a first eye height threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the first eye height threshold.

[0177] Alternatively, the processor 1110 is further configured to update the second eye height threshold in the following manner:

[0178] When the N first data bits are in a non-idle state, obtaining eye diagram information of the N first data bits, and updating the second eye height threshold according to an eye height value corresponding to the eye diagram information;

[0179] When the N first data bits are in an idle state, the supply voltage of the N first data bits is increased or decreased according to a preset step size, and eye diagram information of the N first data bits is obtained. If the eye diagram information of the N first data bits obtained includes eye diagram information having an eye height value less than a current second eye height threshold, the second eye height threshold is updated according to the eye height value corresponding to the eye diagram information having an eye height value less than the current second eye height threshold.

[0180] Optionally, the processor 1110 is further configured to:

[0181] When the antenna transmission power is less than the power threshold, adjusting the supply voltage of the N first data bits to a first voltage value;

[0182] When the antenna transmission power is greater than or equal to the power threshold, adjusting the supply voltage of the N first data bits to a second voltage value;

[0183] Wherein, the first voltage value is smaller than the second voltage value.

[0184] Optionally, the processor 1110 is further configured to determine the power threshold in the following manner:

[0185] When the antenna radiation interference is increased to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is increased for the i-th time, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is increased for the i-1th time; wherein i is a positive integer.

[0186] The electronic device in the embodiment of the present invention can adjust the power supply voltage of any second data bit in the N first data bits based on the eye diagram information of the second data bit in the N first data bits by collecting the eye diagram information of the N first data bits in the memory in real time for the N first data bits whose anti-interference performance is lower than the preset condition; or can adjust the power supply voltage of the N first data bits whose anti-interference performance is lower than the preset condition in the memory in real time by collecting the antenna transmission power when the memory is working according to the collected antenna transmission power. In this way, the problem of the memory freezing due to the interference of antenna radiation can be solved, and the situation of the memory being interfered when the electronic device is in use can be avoided. It can also solve the problem that it is difficult to reduce the interference mode of the memory based on the hardware improvement scheme, and can avoid the problem of increasing power consumption caused by turning off the software control mode of the DVFSQ module, so that the voltage of all data bits of the memory is raised, thereby improving the use time of the electronic device and the user experience.

[0187] It should be understood that in the embodiment of the present application, the input unit 1104 may include a graphics processor (Graphics Processing Unit, GPU) 11041 and a microphone 11042, and the graphics processor 11041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1106 may include a display panel 11061, and the display panel 11061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1107 includes a touch panel 11071 and at least one of other input devices 11072. The touch panel 11071 is also called a touch screen. The touch panel 11071 may include two parts: a touch detection device and a touch controller. Other input devices 11072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0188] The memory 1109 can be used to store software programs and various data. The memory 1109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1109 may include a volatile memory or a non-volatile memory, or the memory 1109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0189] The processor 1110 may include one or more processing units; optionally, the processor 1110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1110.

[0190] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned audio data processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0191] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0192] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned memory control method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0193] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0194] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned memory control method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0195] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0196] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0197] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory control method, characterized in that: Applied to electronic equipment, the method comprises: Determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer; Acquire eye diagram information of the N first data bits when the memory is working, or acquire antenna transmission power of the electronic device when the memory is working; The power supply voltage of the second data bit is adjusted according to the eye diagram information of the second data bit; or, the power supply voltage of the N first data bits is adjusted according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

2. The memory control method according to claim 1, characterized in that: The determining of N first data bits in the memory whose anti-interference performance is lower than a preset condition comprises: Adding antenna radiation interference to the memory according to a preset step length, and obtaining eye diagram information of each data bit in the memory under different antenna radiation interferences; If the eye height value corresponding to the eye diagram information of each acquired data bit is smaller than the first eye height threshold, the data bit corresponding to the eye diagram information having the eye height value smaller than the first eye height threshold is determined as the first data bit.

3. The memory control method according to claim 1, characterized in that: The step of adjusting the supply voltage of the second data bit according to the eye diagram information of the second data bit comprises: When the eye height value corresponding to the eye diagram information of the second data bit is greater than or equal to the second eye height threshold, adjusting the supply voltage of the second data bit to the first voltage value; When the eye height value corresponding to the eye diagram information of the second data bit is less than the second eye height threshold, adjusting the supply voltage of the second data bit to a second voltage value; Wherein, the first voltage value is smaller than the second voltage value.

4. The memory control method according to claim 3, characterized in that: The second eye height threshold is determined by: When the antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

5. The memory control method according to claim 1, characterized in that: The adjusting the supply voltage of the N first data bits according to the antenna transmission power includes: When the antenna transmission power is less than the power threshold, adjusting the supply voltage of the N first data bits to a first voltage value; When the antenna transmission power is greater than or equal to the power threshold, adjusting the supply voltage of the N first data bits to a second voltage value; Wherein, the first voltage value is smaller than the second voltage value.

6. The memory control method according to claim 5, characterized in that: The power threshold is determined by: When the antenna radiation interference is increased to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is increased for the i-th time, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is increased for the i-1th time; wherein i is a positive integer.

7. A memory control device, characterized in that: Used in electronic equipment, including: A processing module, used to determine N first data bits in the memory whose anti-interference performance is lower than a preset condition; wherein N is a positive integer; An acquisition module, used to acquire eye diagram information of the N first data bits when the memory is working, or to acquire antenna transmission power of the electronic device when the memory is working; An adjustment module is used to adjust the supply voltage of the second data bit according to the eye diagram information of the second data bit; or, to adjust the supply voltage of the N first data bits according to the antenna transmission power; wherein the second data bit is any data bit among the N first data bits.

8. The memory control device according to claim 7, characterized in that: The processing module comprises: An acquisition unit, configured to add antenna radiation interference to the memory according to a preset step length, and acquire eye diagram information of each data bit in the memory under different antenna radiation interferences; A determining unit is configured to determine, if the eye height value corresponding to the acquired eye diagram information of each data bit is less than a first eye height threshold, the data bit corresponding to the eye diagram information having an eye height value less than the first eye height threshold as the first data bit.

9. The memory control device according to claim 7, characterized in that: The adjustment module comprises: A first adjustment unit, configured to adjust the supply voltage of the second data bit to a first voltage value when an eye height value corresponding to the eye diagram information of the second data bit is greater than or equal to a second eye height threshold; A second adjustment unit, configured to adjust the supply voltage of the second data bit to a second voltage value when the eye height value corresponding to the eye diagram information of the second data bit is less than a second eye height threshold; Wherein, the first voltage value is smaller than the second voltage value.

10. The memory control device according to claim 9, characterized in that: Also includes: The first determining module is configured to determine the second eye height threshold in the following manner: When the antenna radiation interference is added to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is added for the i-th time, the second eye height threshold is determined according to the eye height value corresponding to the eye diagram information of the N first data bits when the antenna radiation interference is added for the i-1th time; wherein i is a positive integer.

11. The memory control device according to claim 7, characterized in that: The adjustment module comprises: A third adjustment unit, configured to adjust the supply voltage of the N first data bits to a first voltage value when the antenna transmit power is less than a power threshold; a fourth adjustment unit, configured to adjust the supply voltage of the N first data bits to a second voltage value when the antenna transmit power is greater than or equal to a power threshold; Wherein, the first voltage value is smaller than the second voltage value.

12. The memory control device according to claim 11, characterized in that: Also includes: The second determining module is used to determine the power threshold in the following manner: When the antenna radiation interference is increased to the memory according to a preset step size, if the eye height value corresponding to the eye diagram information of N first data bits is less than the first eye height threshold when the antenna radiation interference is increased for the i-th time, the power threshold is determined according to the antenna transmission power when the antenna radiation interference is increased for the i-1th time; wherein i is a positive integer.

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