8T-SRAM unit, reading circuit of 8T-SRAM unit, operational circuit of 8T-SRAM unit and chip of 8T-SRAM unit

Abstract

The invention discloses an 8T-SRAM unit and a readout circuit, an operational circuit and a chip of the 8T-SRAM unit, the 8T-SRAM unit comprises transistors P1, P2, N1, N2, N3, N4, N5 and N6, P1, P2, N1 and N2 form two cross-coupled phase inverters, inputs of the two phase inverters are respectively used as a storage node Q and a storage node QB, a source electrode of a fifth transistor N3 is connected with the storage node Q, a drain electrode of the fifth transistor N3 is connected with a drain electrode of a sixth transistor N4, and a drain electrode of the sixth transistor N4 is connected with a drain electrode of a fourth transistor N5. The grid electrode of the sixth transistor N4 is connected with the first column word line WWLA, the grid electrode of the sixth transistor N4 is connected with the second column word line WWLB, the source electrode of the sixth transistor N4 is connected with the storage node QB, the grid electrode of the seventh transistor N5 is connected with the storage node QB, the drain electrode of the seventh transistor N5 is connected with the drain electrode of the sixth transistor N4, the source electrode of the seventh transistor N5 is grounded, the grid electrode of the eighth transistor N6 is connected with the row word line WL, the source electrode of the eighth transistor N6 is connected with the drain electrode of the sixth transistor N4, and the drain electrode of the eighth transistor N6 is connected with the bit line RBL. The 8T-SRAM unit provided by the invention can eliminate semi-selective destruction, and the reading circuit provided by the invention can enable the output to be more stable.

Description

Technical Field

[0001] The present invention relates to SRAM, and in particular to an 8T-SRAM unit and a readout circuit, a calculation circuit and a chip of the 8T-SRAM unit. Background Art

[0002] Static Random-Access Memory (SRAM) is a type of random access memory that can save the data stored inside it without the need for a refresh circuit. SRAM generally consists of five parts, namely, a memory cell array, an address decoder, a sense amplifier, a control circuit, and a drive circuit. Each memory cell in the memory cell array shares electrical connections with other cells in rows and columns, where the horizontal connection is called a word line (WL), and the vertical connection for data to flow in and out of the memory cell is called a bit line (BL). A specific word line and bit line can be selected by the input address, and the intersection of the word line and the bit line is the selected memory cell. Each memory cell is uniquely selected in this way, and then read and write operations are performed on it. The memory cell can be a 4T SRAM cell, a 6T SRAM cell, a 7T SRAM cell, an 8T-SRAM cell, etc.

[0003] Although the traditional 8T-SRAM cell has a relatively small operating voltage and good read and write stability, its storage array cannot adopt a column selection (bit cross) structure. The column selection structure is a common layout arrangement structure of the SRAM storage array. It divides the storage array into multiple small columns to realize the layout layout, thereby improving the area efficiency of the storage array. Another important function of the column selection structure is that it can be combined with the error correction code (ECC) circuit to reduce the soft error rate (SER) of the SRAM. However, when the 8T-SRAM cell adopts a column selection structure, it may not only cause read damage, but also semi-selection damage. Semi-selection damage is that during the read / write operation of the SRAM, all the storage cells connected to the same word line are turned on, and the selected cells read / write data. The unselected (semi-selected) cells are pre-charged to a high level, which is equivalent to undergoing a read operation process. During the read operation, these semi-selected cells may experience read damage. In addition, the traditional 8T storage cell introduces a problem that requires precharging, which leads to unstable output. Summary of the invention

[0004] In view of the problems existing in the prior art, the purpose of the present invention is to provide an 8T-SRAM cell that can eliminate semi-selective destruction and a readout circuit, a storage array, an operation circuit, a chip and an electronic device of the 8T-SRAM cell.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] An 8T-SRAM cell comprises a first transistor P1, a second transistor P2, a third transistor N1, a fourth transistor N2, a fifth transistor N3, a sixth transistor N4, a seventh transistor N5 and an eighth transistor N6. The first transistor P1, the second transistor P2, the third transistor N1 and the fourth transistor N2 constitute two cross-coupled inverters, the inputs of the two inverters are respectively used as a storage node Q and a storage node QB. The source of the fifth transistor N3 is connected to the storage node Q, the drain is connected to the drain of the sixth transistor N4, the gate is connected to the first column word line WWLA, the gate of the sixth transistor N4 is connected to the second column word line WWLB, the source is connected to the storage node QB, the gate of the seventh transistor N5 is connected to the storage node QB, the drain is connected to the drain of the sixth transistor N4, and the source is grounded. The gate of the eighth transistor N6 is connected to the row word line WL, the source is connected to the drain of the sixth transistor N4, and the drain is connected to the bit line RBL.

[0007] A readout circuit of the above-mentioned 8T-SRAM unit includes a ninth transistor P3, a tenth transistor P4, an eleventh transistor P5, a twelfth transistor N7, a thirteenth transistor N8, and a fourteenth transistor N9, wherein the gate of the ninth transistor P3 inputs a clock signal, the source is connected to a power supply VDD, and the drain is connected to a bit line RBL, so the gate of the tenth transistor P4 is connected to the bit line RBL, the source is connected to the power supply VDD, and the drain is respectively connected to the drain of the twelfth transistor N7, the gate of the eleventh transistor P5, and the gate of the thirteenth transistor N8, the source of the eleventh transistor P5 is connected to the power supply VDD, and the drain is connected to an output end, the gate of the twelfth transistor N7 inputs a clock signal, the source is connected to the drain of the fourteenth transistor N9, the drain of the thirteenth transistor N8 is connected to the output end, and the source is grounded, and the gate of the fourteenth transistor N9 is connected to the bit line RBL, and the source is grounded.

[0008] An 8T-SRAM memory cell array comprises N*M 8T-SRAM cells according to claim 1, M first column word lines WWLA, M second column word lines WWLB, N row word lines WL and M bit lines RBL, 8T-SRAM cells in the same row are respectively connected to the same row word line WL, 8T-SRAM cells in the same column are respectively connected to the same first column word line WWLA, second column word line WWLB and RBL bit line, and N and M are positive integers.

[0009] An 8T-SRAM operation circuit comprises: the above-mentioned storage array; a timing control circuit for generating various clock signals required for executing data read / write hold operations or logic operation operations; the above-mentioned readout circuit for reading out the bit line signal of the 8T-SRAM unit; an address decoder for decoding the output signal of the storage cell array; and an output circuit for outputting the decoded signal.

[0010] An 8T-SRAM chip is integrated with the above-mentioned 8T-SRAM operation circuit.

[0011] An electronic device comprises the above-mentioned 8T-SRAM chip and an electronic component connected to the chip.

[0012] Compared with the prior art, the present invention has the following beneficial effects: the 8T-SRAM cell proposed in the present invention supports a column selection structure and eliminates the problem of half-selection destruction caused by the traditional 8T-SRAM cell; in addition, in view of the problem that the RBL of the traditional 8T-SRAM needs to be precharged, resulting in unstable output, the readout circuit proposed in the present invention selects the bit line at the falling edge of the clock and obtains the output at the rising edge of the clock from the perspective of the control signal, and the output will remain stable within a clock cycle, thereby improving the stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit diagram of an embodiment of an 8T-SRAM unit provided by the present invention;

[0014] Figure 2 It is a circuit diagram of an embodiment of a readout circuit of an 8T-SRAM unit provided by the present invention. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0016] Example 1

[0017] The embodiment of the present invention provides an 8T-SRAM cell, such as Figure 1As shown, it includes a first transistor P1, a second transistor P2, a third transistor N1, a fourth transistor N2, a fifth transistor N3, a sixth transistor N4, a seventh transistor N5, and an eighth transistor N6. The first transistor P1, the second transistor P2, the third transistor N1, and the fourth transistor N2 constitute two cross-coupled inverters, and the inputs of the two inverters are respectively used as storage nodes Q and storage nodes QB. The source of the fifth transistor N3 is connected to the storage node Q, the drain is connected to the drain of the sixth transistor N4, and the gate is connected to the first column word line WWLA. The gate of the sixth transistor N4 is connected to the second column word line WWLB, and the source is connected to the storage node QB. The gate of the seventh transistor N5 is connected to the storage node QB, the drain is connected to the drain of the sixth transistor N4, and the source is grounded. The gate of the eighth transistor N6 is connected to the row word line WL, the source is connected to the drain of the sixth transistor N4, and the drain is connected to the bit line RBL. Among them, the first transistor P1 and the second transistor P2 are both PMOS transistors. The third transistor N1 , the fourth transistor N2 , the fifth transistor N3 , the sixth transistor N4 , the seventh transistor N5 , and the eighth transistor N6 are all NMOS transistors.

[0018] The working principle of 8T-SRAM cell is:

[0019] Read mode: When the 8T-SRAM cell performs a read operation, WL is high, N6 is turned on, the two column word lines are in the off state, and N3 and N4 are both turned off. When the storage node Q is 0 and QB is 1, N5 is turned on, and the voltage on RBL is pulled down to "0". When the storage node Q is 1 and QB is 0, N5 is turned off, and the voltage on RBL remains unchanged because RBL is precharged to "1", so the voltage on RBL remains "1". Since the two column word lines are in the off state at this time, the storage node Q is isolated from the bit line RBL, that is, there is no half-selection destruction.

[0020] Write mode: When the 8T-SRAM cell performs a write operation, WL is high, N6 is turned on, and the bit line RBL is pulled down to 0. If a write "0" operation is performed, the first column word line WWLA is turned on, the second column word line WWLB is turned off, the node Q is pulled down to "0" by N3 and N6, and the node QB is precharged to "1" through positive feedback. Similarly, if a write "1" operation is performed, the node QB is pulled down to "0" by N4 and N6, and the node Q is precharged to "1" through positive feedback.

[0021] The operational truth tables of the above principle are shown in Tables 1 and 2 below.

[0022] Table 1 Read mode operation truth table

[0023]

[0024] Table 2 Write mode operation truth table

[0025]

[0026] Example 2

[0027] In the conventional technology, the 8T-SRAM cell introduces a problem that a precharge is required, which leads to unstable output. In order to overcome this problem, an embodiment of the present invention provides a readout circuit of an 8T-SRAM cell, such as Figure 2 As shown, it includes a ninth transistor P3, a tenth transistor P4, an eleventh transistor P5, a twelfth transistor N7, a thirteenth transistor N8, and a fourteenth transistor N9, wherein the gate of the ninth transistor P3 inputs a clock signal CLK, the source is connected to the power supply VDD, and the drain is connected to the bit line RBL, so the gate of the tenth transistor P4 is connected to the bit line RBL, the source is connected to the power supply VDD, and the drain is respectively connected to the drain of the twelfth transistor N7, the gate of the eleventh transistor P5, and the gate of the thirteenth transistor N8, the source of the eleventh transistor P5 is connected to the power supply VDD, and the drain is connected to the output terminal, the gate of the twelfth transistor N7 inputs a clock signal CLK, the source is connected to the drain of the fourteenth transistor N9, the drain of the thirteenth transistor N8 is connected to the output terminal OUT, and the source is grounded, and the gate of the fourteenth transistor N9 is connected to the bit line RBL, and the source is grounded. Among them, the ninth transistor P3, the tenth transistor P4, and the eleventh transistor P5 are all PMOS transistors. The twelfth transistor N7, the thirteenth transistor N8, and the fourteenth transistor N9 are all NMOS transistors.

[0028] When the clock signal CLK is at a low level, RBL is precharged. If RBL is at a high level and the clock is at a low level, the signal X is locked. When the clock signal is at a high level, RBL obtains the output of the 8T-SRAM unit, and the RBL potential is the potential of the storage node Q in the 8T-SRAM. At the same time, the signal X is the inversion of the RBL signal. The inverter composed of P5 and N8 placed between the output and the signal X stabilizes the output data. The truth table is shown in Table 3.

[0029] Table 3 Readout circuit truth table

[0030] CLK 1 0 1 0 Q 1 0 0 1 X 0 X 1 X RBL 1 1 0 1 OUT 1 X 0 X

[0031] Example 3

[0032] An embodiment of the present invention provides a storage array of an 8T-SRAM unit, including N*M 8T-SRAM units, M first column word lines WWLA, M second column word lines WWLB, N row word lines WL and M bit lines RBL, 8T-SRAM units in the same row are respectively connected to the same row word line WL, 8T-SRAM units in the same column are respectively connected to the same first column word line WWLA, second column word line WWLB and RBL bit line, and N and M are positive integers.

[0033] Example 4

[0034] The embodiment of the present invention provides an 8T-SRAM operation circuit, which has conventional SRAM storage and reading functions, specifically including:

[0035] The storage array of embodiment 3;

[0036] A timing control circuit, used to generate various clock signals required to perform data read, write, hold operations or logic operation operations;

[0037] The readout circuit of embodiment 2 is used to read out the bit line signal of the 8T-SRAM cell;

[0038] An address decoder, used for decoding an output signal of the memory cell array;

[0039] The output circuit is used to output the decoded signal.

[0040] In addition, the 8T-SRAM operation circuit can also be packaged into an 8T-SRAM chip. The 8T-SRAM chip can be connected with other electronic components to form an electronic device.

[0041] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0042] It should be understood that the above embodiments and descriptions only describe the principles, main features and advantages of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, and these changes and improvements all fall within the scope of protection of the present invention.

Claims

1. An 8T-SRAM cell, comprising a first transistor P1, a second transistor P2, a third transistor N1, a fourth transistor N2, a fifth transistor N3, a sixth transistor N4, a seventh transistor N5, and an eighth transistor N6, wherein the first transistor P1, the second transistor P2, the third transistor N1, and the fourth transistor N2 constitute two cross-coupled inverters, and the inputs of the two inverters are respectively used as a storage node Q and a storage node QB, and characterized in that: The source of the fifth transistor N3 is connected to the storage node Q, the drain is connected to the drain of the sixth transistor N4, the gate is connected to the first column word line WWLA, the gate of the sixth transistor N4 is connected to the second column word line WWLB, the source is connected to the storage node QB, the gate of the seventh transistor N5 is connected to the storage node QB, the drain is connected to the drain of the sixth transistor N4, and the source is grounded, the gate of the eighth transistor N6 is connected to the row word line WL, the source is connected to the drain of the sixth transistor N4, and the drain is connected to the bit line RBL.

2. The 8T-SRAM cell according to claim 1, characterized in that: The first transistor P1 and the second transistor P2 are both PMOS transistors.

3. The 8T-SRAM cell according to claim 1, characterized in that: The third transistor N1 , the fourth transistor N2 , the fifth transistor N3 , the sixth transistor N4 , the seventh transistor N5 , and the eighth transistor N6 are all NMOS transistors.

4. A readout circuit of the 8T-SRAM cell according to claim 1, characterized in that: It includes a ninth transistor P3, a tenth transistor P4, an eleventh transistor P5, a twelfth transistor N7, a thirteenth transistor N8, and a fourteenth transistor N9, wherein the gate of the ninth transistor P3 inputs a clock signal, the source is connected to the power supply VDD, and the drain is connected to the bit line RBL, so the gate of the tenth transistor P4 is connected to the bit line RBL, the source is connected to the power supply VDD, and the drain is respectively connected to the drain of the twelfth transistor N7, the gate of the eleventh transistor P5, and the gate of the thirteenth transistor N8, the source of the eleventh transistor P5 is connected to the power supply VDD, and the drain is connected to the output end, the gate of the twelfth transistor N7 inputs a clock signal, the source is connected to the drain of the fourteenth transistor N9, the drain of the thirteenth transistor N8 is connected to the output end, the source is grounded, and the gate of the fourteenth transistor N9 is connected to the bit line RBL, and the source is grounded.

5. The readout circuit according to claim 4, characterized in that: The ninth transistor P3 , the tenth transistor P4 , and the eleventh transistor P5 are all PMOS transistors.

6. The readout circuit according to claim 4, characterized in that: The twelfth transistor N7 , the thirteenth transistor N8 , and the fourteenth transistor N9 are all NMOS transistors.

7. A storage array of 8T-SRAM cells, characterized in that: The invention comprises N*M 8T-SRAM cells as claimed in claim 1, M first column word lines WWLA, M second column word lines WWLB, N row word lines WL and M bit lines RBL, 8T-SRAM cells in the same row are respectively connected to the same row word line WL, 8T-SRAM cells in the same column are respectively connected to the same first column word line WWLA, second column word line WWLB and RBL bit line, and N and M are positive integers.

8. An 8T-SRAM operation circuit, characterized in that: include: The storage array as claimed in claim 7; A timing control circuit, used to generate various clock signals required to perform data read, write, hold operations or logic operation operations; The readout circuit of claim 4, used to read out the bit line signal of the 8T-SRAM cell; An address decoder, used for decoding an output signal of the memory cell array; The output circuit is used to output the decoded signal.

9. An 8T-SRAM chip, characterized in that: The 8T-SRAM operation circuit as claimed in claim 8 is integrated thereon.

10. An electronic device, characterized in that: The invention comprises the 8T-SRAM chip as claimed in claim 9 and an electronic component connected to the chip.

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