Display panel, driving circuit, shift register and driving method thereof

Abstract

The invention relates to a display panel, a driving circuit, a shift register and a driving method thereof, and relates to the technical field of display. According to the shift register, an input circuit can respond to a first clock signal provided by a first clock signal end and transmit an input signal provided by an input end to a first input node; the voltage stabilizing circuit can transmit a first control signal to the first output node under the control of the voltage of the first input node; the first control circuit can transmit a second control signal to the second output node under the control of a second clock signal provided by a second clock signal end and the voltage of the first input node; the second control circuit can control the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal; the output circuit can output a signal of a second voltage end or a third voltage end from an output end under the control of the first control signal and the second control signal; the voltage of the first voltage end can conduct the second voltage end and the output end.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving circuit, a shift register, and a driving method of the shift register. Background Art

[0002] In a display panel using light-emitting diodes as light-emitting devices, its pixel circuit is usually scanned by using a signal output by a driving circuit, and the driving circuit includes a plurality of shift registers. When the output signal of the existing shift register is switched, there is a signal delay, which also causes a delay in the picture.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a display panel, a driving circuit, a shift register and a driving method of the shift register, which can improve the signal delay problem.

[0005] According to one aspect of the present disclosure, there is provided a shift register, comprising:

[0006] an input circuit connected to the input terminal, the first clock signal terminal and the first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal;

[0007] a voltage stabilizing circuit connected to the first voltage terminal, the first output node and the first input node, and configured to transmit a first control signal to the first output node under the control of the voltage of the first input node;

[0008] a first control circuit connected to the second voltage terminal, the second clock signal terminal, the third voltage terminal, the second output node and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage of the first input node;

[0009] a second control circuit connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal;

[0010] The output circuit is connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal and the output terminal, and is configured to output the signal of the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal; the voltage of the first voltage terminal can turn on the second voltage terminal and the output terminal.

[0011] In an exemplary embodiment of the present disclosure, the first control circuit includes:

[0012] a first control subcircuit connected to the second input node, the second voltage terminal and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal;

[0013] a second control subcircuit connected to the connection node, the first input node and the third voltage terminal, and configured to be turned on or off under the control of the voltage of the first input node;

[0014] The third control subcircuit is connected to the second input node and the connection node, and is configured to be turned on or off under the control of the voltage of the third voltage terminal.

[0015] In an exemplary embodiment of the present disclosure, the first control subcircuit includes a first control transistor, the second control subcircuit includes a second control transistor, and the third control subcircuit includes a third control transistor and a first capacitor;

[0016] The gate of the first control transistor is connected to the second clock signal terminal, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second input node;

[0017] The gate of the second control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the connection node;

[0018] The gate of the third control transistor is connected to the connection node via the first capacitor, the first electrode is connected to the connection node, and the second electrode is connected to the second input node.

[0019] In an exemplary embodiment of the present disclosure, the voltage stabilizing circuit includes a voltage stabilizing transistor and a second capacitor;

[0020] The gate of the voltage stabilizing transistor is connected to the first input node and the second capacitor, the first electrode is connected to the first voltage terminal, and the second electrode is connected to the second capacitor and the first output node.

[0021] In an exemplary embodiment of the present disclosure, the second control circuit includes a fourth control subcircuit and a fifth control subcircuit;

[0022] The fourth control subcircuit is connected to the third voltage terminal, the first input node and the second output node, and is configured to control the second control signal under the control of the voltage of the first input node;

[0023] The fifth control subcircuit is connected to the third voltage terminal, the first output node and the second output node, and is configured to control the first control signal under the control of the voltage of the second output node.

[0024] In an exemplary embodiment of the present disclosure, the fourth control subcircuit includes a fourth control transistor; the fifth control subcircuit includes a fifth control transistor;

[0025] The gate of the fourth control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second output node;

[0026] The gate of the fifth control transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the first output node.

[0027] In an exemplary embodiment of the present disclosure, the input circuit includes an input transistor, a gate of the input transistor is connected to the first clock signal terminal, a first electrode is connected to the input terminal, and a second electrode is connected to the first input node;

[0028] The output circuit includes a first output transistor, a third capacitor, a second output transistor and a fourth capacitor;

[0029] The gate of the first output transistor is connected to the first output node, the first electrode is connected to the second voltage terminal, the second electrode is connected to the output terminal, and the third capacitor is connected to the first output node and the second voltage terminal;

[0030] The gate of the second output transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, the second electrode is connected to the output terminal, and the fourth capacitor is connected to the second output node and the third voltage terminal.

[0031] In an exemplary embodiment of the present disclosure, the shift register further includes:

[0032] The first isolation circuit is connected to the first input node and the voltage stabilizing circuit.

[0033] In an exemplary embodiment of the present disclosure, the shift register further includes:

[0034] The second isolation circuit connects the connection node and the second output node.

[0035] In an exemplary embodiment of the present disclosure, the first isolation circuit includes a first isolation transistor; the second isolation circuit includes a second isolation transistor;

[0036] The gate of the first isolation transistor is connected to the second voltage terminal, the first electrode is connected to the first input node, and the second electrode is connected to the voltage stabilizing circuit;

[0037] The second isolation transistor has a gate connected to the second voltage terminal, a first electrode connected to the connection node, and a second electrode connected to the second output node.

[0038] According to one aspect of the present disclosure, a driving circuit is provided, comprising a plurality of cascaded shift registers, wherein the shift register is any one of the shift registers described above.

[0039] According to one aspect of the present disclosure, a display panel is provided, the display panel comprising:

[0040] A driving backplane, comprising a plurality of pixel circuits and a first driving circuit, wherein the pixel circuits are arranged in an array along the row direction and the column direction; the first driving circuit is any one of the driving circuits described above, and an output end of the first driving circuit is connected to at least one row of the pixel circuits;

[0041] The light emitting devices are arranged in an array on one side of the driving backplane.

[0042] In an exemplary embodiment of the present disclosure, the pixel circuit includes a plurality of transistors; the number of the first driving circuits is two; the display panel further includes a second driving circuit;

[0043] The gates of some transistors in the same pixel circuit are connected to the output end of the first driving circuit, and the gates of another part of the transistors are connected to the output end of the second driving circuit; and the two first driving circuits are connected to the gates of different transistors in the pixel circuit.

[0044] In an exemplary embodiment of the present disclosure, the pixel circuit includes a driving transistor, a writing transistor, a compensating transistor, a first reset transistor, a second reset transistor, a first light emission control transistor, a second light emission control transistor, and a storage capacitor; the first reset transistor and the compensating transistor are N-type metal oxide transistors, and the driving transistor, the writing transistor, the second reset transistor, the first light emission control transistor, and the second light emission control transistor are P-type polysilicon transistors;

[0045] The first electrode of the first light-emitting control transistor is used to receive a first power supply signal, and the second electrode is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting device; the first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate electrode of the driving transistor; the first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the second electrode of the compensation transistor; the first electrode of the second reset transistor is used to receive a second reset signal, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, and the second electrode is connected to the first electrode of the driving transistor; the first plate of the storage capacitor is connected to the gate electrode of the driving transistor, and the second plate is used to receive the first power supply signal;

[0046] The gate of the first reset transistor and the gate of the compensation transistor are connected to an output end of the first driving circuit; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to an output end of another first driving circuit; the gate of the write transistor and the gate of the second reset transistor are connected to an output end of the second driving circuit.

[0047] According to one aspect of the present disclosure, a driving method of a shift register is provided, wherein the shift register is any one of the shift registers described above; the driving method comprises:

[0048] In the first stage, the input circuit is turned on by the first clock signal and the second clock signal, and the first control circuit is turned off; the voltage stabilizing circuit is turned on; the second voltage terminal is controlled to be turned on by the first control signal, and the third voltage terminal is controlled to be turned off by the output terminal;

[0049] In the second stage, the input circuit is turned off and the first control circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned on; the second voltage terminal is controlled to be turned on and off with the output terminal by the voltage of the first voltage terminal, the first control signal and the second control signal, and the third voltage terminal is controlled to be turned on and off with the output terminal;

[0050] In the third stage, the input circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal is controlled to be turned on and off with the output terminal by the voltage of the first voltage terminal, the first control signal and the second control signal, and the third voltage terminal is controlled to be turned on and off with the output terminal;

[0051] In the fourth stage, the input circuit is turned off by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal and the output terminal are turned off and the third voltage terminal and the output terminal are turned on by the voltage at the third voltage terminal, the first control signal and the second control signal.

[0052] In an exemplary embodiment of the present disclosure, an absolute value of a voltage at the first voltage terminal is greater than an absolute value of a voltage at the second voltage terminal.

[0053] In an exemplary embodiment of the present disclosure, the absolute value of the difference between the absolute value of the voltage at the first voltage terminal and the absolute value of the voltage at the second voltage terminal is 3V.

[0054] In an exemplary embodiment of the present disclosure, a pulse width of the input signal is n times that of the first clock signal and the second clock signal, where n is a positive integer.

[0055] The display panel, driving circuit, shift register and driving method disclosed in the present invention can control the conduction and disconnection of the second voltage terminal and the output terminal through an input signal, and at the same time, transmit the voltage of the first voltage terminal to the output circuit through an over-voltage stabilization circuit, so that the second voltage terminal and the output terminal are stably connected; and eliminate the step that occurs when the voltage of the third voltage terminal outputted at the output terminal changes to the voltage of the second voltage terminal. In addition, the above-mentioned step can be eliminated by externally connecting the first voltage terminal.

[0056] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0058] Figure 1 FIG. 1 is a top view of an embodiment of a display panel disclosed herein.

[0059] Figure 2 It is a partial cross-sectional schematic diagram of an embodiment of the display panel disclosed in the present invention.

[0060] Figure 3 FIG. 4 is a schematic diagram of a pixel circuit in an embodiment of a display panel disclosed herein.

[0061] Figure 4 It is a partial schematic diagram of an embodiment of the display panel disclosed in the present invention.

[0062] Figure 5 FIG. 4 is a schematic diagram of a driving circuit in an embodiment of a display panel disclosed herein.

[0063] Figure 6 FIG. 4 is a schematic diagram of an embodiment of a shift register disclosed in the present invention.

[0064] Figure 7 FIG. 1 is a schematic diagram of an embodiment of a shift register disclosed in the present invention in the first stage.

[0065] Figure 8 FIG. 1 is a schematic diagram of an embodiment of a shift register disclosed in the present invention in the second stage.

[0066] Fig. 9 FIG. 4 is a schematic diagram of an embodiment of a shift register disclosed in the present invention in the third stage.

[0067] Fig.10 FIG. 4 is a schematic diagram of an embodiment of a shift register disclosed in the present invention in the fourth stage.

[0068] Fig.11 The present invention discloses a timing diagram of a shift register driving method according to an embodiment of the present invention.

[0069] Fig.12 It is a timing diagram of an implementation of a driving method for multiple shift registers in the present disclosure.

[0070] Fig.13 FIG. 4 is a timing diagram of another embodiment of a driving method of a shift register disclosed in the present invention.

[0071] Fig.14 This is a timing diagram of another embodiment of the driving method of multiple shift registers in the present disclosure.

[0072] Fig.15 FIG. 4 is a timing diagram of another embodiment of the driving method of multiple shift registers in the present disclosure. DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0074] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0075] The row direction X and the column direction Y herein are two intersecting directions, which may be perpendicular to each other. In the drawings of the present disclosure, the row direction X is horizontal and the column direction Y is vertical, but this is not limited thereto. It is known to those skilled in the art that if the display panel is rotated, the actual directions of the row direction X and the column direction Y may change.

[0076] The transistor in this article includes a gate, a first electrode, and a second electrode. The first electrode and the second electrode can be turned on and off by controlling the voltage of the gate; the first electrode can be a source electrode, and the second electrode can be a drain electrode; of course, the first electrode can also be a drain electrode, and the second electrode can also be a source electrode. Specifically, if the signal is input from the first electrode, the first electrode is the source electrode and the second electrode is the drain electrode; if the signal is input from the second electrode, the second electrode is the source electrode and the first electrode is the drain electrode; that is, the source electrode and the drain electrode can be interchanged depending on the change of the input signal.

[0077] For a P-type transistor, when the gate receives a high level, the first and second electrodes are turned off; when the gate receives a low level, the first and second electrodes are turned on. For an N-type transistor, when the gate receives a high level, the first and second electrodes are turned on; when the gate receives a low level, the first and second electrodes are turned off.

[0078] like Figure 1 As shown, the present disclosure provides a display panel which can be divided into multiple areas, including a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous annular area surrounding the display area AA, or a discontinuous area surrounding the display area AA.

[0079] like Figure 2 As shown, the display panel may include a driving backplane BP and a plurality of light emitting devices LD arranged on one side of the driving backplane BP. Each light emitting device LD may be distributed in an array along a row direction X and a column direction Y and located in a display area AA. The light emitting device LD may be driven to emit light through a circuit in the driving backplane BP to display an image.

[0080] like Figure 2As shown, the light-emitting device LD can adopt OLED (organic light-emitting diode) of organic light-emitting materials; it can also adopt LED (light-emitting diode) of inorganic light-emitting materials, for example, Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also adopt devices such as QLED (quantum dot diode), and no special limitation is made on the specific structure of the light-emitting device LD.

[0081] like Figure 2 As shown, taking the light-emitting device LD using OLED as an example, it may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying a first power signal to the first electrode ANO and a second power signal to the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific principle is not described in detail here. At the same time, in order to limit the range of the light-emitting device LD, a pixel definition layer PDL can be set on the driving backplane BP. The pixel definition layer PDL and the first electrode ANO are located on the same surface of the driving backplane BP, and the pixel definition layer PDL may have pixel openings that expose each first electrode ANO, so that the range of the light-emitting device LD can be limited by each pixel opening.

[0082] like Figure 4 As shown, the circuit driving the backplane BP may include a pixel circuit PC and a driving circuit. The pixel circuit PC may be located in the display area AA and arranged in an array along the row direction X and the column direction Y. A pixel circuit PC may be connected to a first electrode ANO of a light emitting device LD. Of course, the same pixel circuit PC may also be connected to the first electrodes ANO of multiple light emitting devices LD. The pixel circuit PC may include multiple transistors and capacitors. It may be a pixel circuit such as 3T1C or 7T1C. nTmC indicates that a pixel circuit PC includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C").

[0083] like Figure 3 As shown, taking the pixel circuit PC of 7T1C structure as an example, it may include a first reset transistor M1, a compensation transistor M2, a drive transistor M3, a write transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset transistor M7 and a storage capacitor Cst. The first electrode and the second electrode may be turned on or off by applying a scan signal to the gate of the transistor. The storage capacitor Cst may include an overlapping first plate and a second plate; wherein:

[0084] like Figure 3As shown, the gate of the first light-emitting control transistor M5 is used to input the light-emitting scanning signal EM, the first electrode is used to input the first power supply signal VDD, and the second electrode is connected to the first electrode of the driving transistor M3. The gate of the driving transistor M3 is connected to the first node N1, the second electrode and the first electrode of the second light-emitting control transistor M6 are connected to the second node N2, the second electrode of the second light-emitting control transistor M6 and the first electrode ANO of a light-emitting device LD are connected to the fourth node N41, and the gate of the second light-emitting control transistor M6 is used to input the light-emitting scanning signal EM. The second electrode CAT of the light-emitting device LD is used to input the second power supply signal VSS.

[0085] The gate of the first reset transistor M1 is used to input the first reset scanning signal RE1 , the first electrode is used to input the first reset signal VI1 , and the second electrode is connected to the gate of the driving transistor M3 .

[0086] The gate of the write transistor M4 is used to input the write scan signal Gate1 , the first electrode is used to input the data signal DA, and the second electrode and the first electrode of the drive transistor M3 and the second electrode of the first light emission control transistor M5 are connected to the third node N31 .

[0087] The gate of the compensation transistor M2 is used to input the compensation scanning signal Gate2, the first electrode is connected to the second node N2, and the second electrode is connected to the first node N1, thereby connecting the second electrode and the gate of the driving transistor M3.

[0088] The gate of the second reset transistor M7 is used to input the second reset scan signal RE2, the first electrode is used to input the second reset signal VI2, and the second electrode is connected to the fourth node N41, that is, connected to the first electrode ANO of the light emitting device and the second electrode of the driving transistor M3.

[0089] The first plate of the storage capacitor Cst is used to input the first power signal VDD, and the second plate is connected to the first node N1, thereby being connected to the gate of the driving transistor M3.

[0090] The working principle of the 7T1C pixel circuit is explained below:

[0091] In the first reset stage: the first reset transistor M1 is turned on by the first reset scan signal RE1, and the first reset signal VI1 is written into the first node N1. The gate of the driving transistor M3 and the second plate of the storage capacitor Cst can be reset.

[0092] In the writing stage: the writing scan signal Gate1 and the compensation scan signal Gate2 are used to turn on the writing transistor M4 and the compensation transistor M2, and the other transistors are turned off; the data signal DA is written to the first node N1 through the third node N31 and the second node N2 until the potential reaches Vdata+vth, where Vdata is the voltage of the data signal DA and Vth is the threshold voltage of the driving transistor M3. The writing scan signal Gate1 and the compensation scan signal Gate2 can be the same scan signal or two synchronized scan signals.

[0093] In the second reset stage: the compensation transistor M2, the write transistor M4, the first light emission control transistor M5 and the second light emission control transistor M6 are turned off. At the same time, the second reset transistor M7 is turned on by the second reset scan signal RE2, and the second reset signal VI2 is transmitted to the first electrode of the second reset transistor M7 to reset the first electrode ANO of the light emitting device LD.

[0094] In the light-emitting stage: the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on by the light-emitting scanning signal EM, and other transistors are turned off; the driving transistor M3 is turned on under the action of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD, and under the action of the first power signal VDD and the second power signal VSS, the light-emitting device LD emits light. Under the action of the storage capacitor Cst, the driving transistor M3 outputs a current, and the output current satisfies the following formula:

[0095] I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0096] I is the output current of the driving transistor M3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor M3, and L is the channel length of the driving transistor M3.

[0097] According to the above formula for the output current of the driving transistor M3, the gate voltage Vdata+Vth and the source voltage VDD of the driving transistor M3 in the pixel circuit of the present invention are substituted into the above formula to obtain: the output current I of the driving transistor M3 = (μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of the pixel circuit has nothing to do with the threshold voltage Vth of the driving transistor M3, but only with Vdata, thereby eliminating the influence of the threshold voltage of the driving transistor M3 on its output current, and the output current can be controlled only by the voltage of the data signal DA, so as to control the brightness of the light-emitting device.

[0098] The transistors of the above 7T1C pixel circuit can all be polysilicon transistors, that is, LTPS (Low Temperature Polycrystalline Silicon) process, or at least a part of the transistors can be metal oxide transistors, for example, LTPO (Low Temperature Polycrystalline Oxide) process can be used, that is, the first reset transistor M1 and the compensation transistor M2 are metal oxide transistors, and the other transistors are polysilicon transistors. The metal oxide transistors can reduce leakage. If the metal oxide transistor is used, it is an N-type transistor, and if the polysilicon transistor is used, it can be a P-type transistor.

[0099] like Figure 4 As shown, the driving circuit WG can be arranged in the peripheral area WA, and can be connected to the light-emitting device LD through the pixel circuit PC, and a first power supply signal is applied to the first electrode ANO of the light-emitting device LD. The number of the driving circuit WG can be multiple, and it can be divided into multiple categories, which are used to scan the transistors in the pixel circuit PC. The driving circuit WG can also be arranged in whole or in part in the display area AA, as long as it can scan the pixel circuit PC. Taking the above-mentioned 7T1C pixel circuit as an example, the driving circuit WG can be divided into two categories, one of which is a gate driving circuit, and is used to scan some transistors in the pixel circuit PC (for example, the first reset transistor M1, the second reset transistor M7, the compensation transistor M2 and the write transistor M4), that is, the first reset scanning signal RE1, the second reset scanning signal RE2, the compensation scanning signal Gate2 and the write scanning signal Gate1 are output to the gates of the first reset transistor M1, the second reset transistor M7, the compensation transistor M2 and the write transistor M4. The other type is a light-emitting driving circuit, which can be used to scan the first light-emitting control transistor M5 and the second light-emitting control transistor M6, that is, the scanning signal (light-emitting scanning signal EM) is output to the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The first reset scan signal RE1, the second reset scan signal RE2, the compensation scan signal Gate2, the write scan signal Gate1 and the light emitting scan signal EM are all scan signals output by the drive circuit WG. The signals output by the gate drive circuit and the light emitting drive circuit can realize the turning on and off of the transistors in the pixel circuit PC, that is, realize the scanning of the pixel circuit PC.

[0100] The peripheral area WA of the display panel may also be provided with a power bus connected to the second electrode CAT of the light emitting device LD, and a second power signal is applied to the second electrode CAT. The current passing through the light emitting device LD can be controlled through the pixel circuit PC, thereby controlling the brightness of the light emitting device LD.

[0101] A driving circuit WG may include a plurality of cascaded shift registers GOA, that is, the output end of the previous shift register GOA is connected to the input end of the next shift register GOA, so that the output signal of the previous shift register GOA serves as the input signal of the next shift register GOA. At the same time, the input signal of the first-stage shift register GOA may be a trigger signal. In addition, in some embodiments, the first-stage shift register GOA may be a dummy register, whose output end is not connected to the pixel circuit PC, but only serves as the input signal of the next-stage shift register GOA. Any shift register GOA may include a plurality of transistors and capacitors, which may be 8T2C, 10T3C and other structures, which are not specifically limited here.

[0102] like Figure 5 As shown, the output signal of the output terminal OUT of the shift register GOA is the above-mentioned scanning signal, and the gates of some transistors of a row of pixel circuits PC can be connected to the output terminal of the first-level shift register GOA; of course, the first-level shift register GOA can be connected to multiple rows of pixel circuits PC to scan multiple rows of pixel circuits PC at the same time, but the output signal of the same shift register GOA may have different effects in different rows of pixel circuits PC. For example, when the pixel circuit PC of the i-th row is in the writing stage, the pixel circuit PC of the i+1-th row is in the first reset stage, and i is a positive integer.

[0103] When controlling the on and off of the transistor of the pixel circuit PC, the output signal of the output terminal of the shift register GOA, i.e., the scanning signal, needs to be switched between a high level and a low level; however, since the on and off of the transistor needs to be responded to, there is a step at the rising edge or falling edge of the scanning signal, which causes a delay in the scanning of the pixel circuit PC, and thus causes a delay in the switching. For example, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are P-type transistors, and when the light-emitting scanning signal EM switches from a high level to a low level, there is a step at the falling edge of the light-emitting scanning signal EM, which causes the first light-emitting control transistor M5 and the second light-emitting control transistor M6 to be turned on with delay, and the light-emitting device LD emits light with delay.

[0104] In order to improve this problem, a large number of transistors and capacitors can be added to the shift register GOA, and the signal can be stabilized inside the shift register by using the principle of bootstrapping, etc., to reduce the above-mentioned steps. However, this will make the shift register have more transistors and capacitors and a more complex structure. Therefore, the inventor proposes that the output signal of the shift register GOA can be controlled by an external voltage to reduce or eliminate the above-mentioned steps, thereby improving the delay. The following is a detailed description:

[0105] like Figure 6 As shown, the shift register GOA may include an input circuit 10, a voltage stabilizing circuit 20, a first control circuit 30, a second control circuit 40 and an output circuit 50, wherein:

[0106] The input circuit 10 is connected to the input terminal IN, the first clock signal terminal CK1 and the first input node N11 and is configured to transmit an input signal provided by the input terminal IN to the first input node N11 in response to a first clock signal provided by the first clock signal terminal CK1.

[0107] The voltage stabilizing circuit 20 is connected to the first voltage terminal VGL_L, the first output node N21 and the first input node N11 , and is configured to transmit a first control signal to the first output node N21 under the control of the voltage of the first input node N11 .

[0108] The first control circuit 30 is connected to the second voltage terminal VGL, the second clock signal terminal CK2, the third voltage terminal VGH, the second output node N22 and the first input node N11, and is configured to transmit a second control signal to the second output node N22 under the control of the second clock signal provided by the second clock signal terminal CK2 and the voltage of the first input node N11.

[0109] The second control circuit 40 is connected to the third voltage terminal VGH, the first input node N11 , the first output node N21 and the second output node N22 , and is configured to control the first control signal and the second control signal under the control of the voltage of the first input node N11 and the second control signal.

[0110] The output circuit 50 is connected to the first output node N21, the second output node N22, the second voltage terminal VGL, the third voltage terminal VGH and the output terminal OUT, and is configured to output the signal of the second voltage terminal VGL or the third voltage terminal VGH from the output terminal OUT under the control of the first control signal and the second control signal; the voltage of the first voltage terminal VGL_L can turn off the second voltage terminal VGL and the output terminal OUT.

[0111] The following is an explanation of the effect of the shift register GOA in combination with its working principle:

[0112] like Figure 6 As shown, in the first stage, the input circuit 10 can be turned on by the first clock signal and the second clock signal, the first control circuit 30 can be turned off, and the input signal can be transmitted to the first input node N11. The input signal can turn on the voltage stabilizing circuit 20, and transmit the first control signal to the first output node N21. The voltage stabilizing circuit 20 can control the first control signal under the voltage control of the first voltage terminal VGL_L, and control the second voltage terminal VGL and the output terminal OUT to be turned on by the first control signal, and the third voltage terminal VGH and the output terminal OUT are turned off; at this time, the voltage of the output signal of the output terminal OUT is the voltage provided by the second voltage terminal VGL.

[0113] In the second stage, the input circuit 10 is turned off by the first clock signal and the second clock signal, the voltage stabilizing circuit 20 remains turned on, the first control circuit 30 is turned on, and the second voltage terminal VGL transmits the second control signal to the second output node N22 through the first control circuit 30; the second voltage terminal VGL and the output terminal OUT are controlled to be turned on by the voltage of the first voltage terminal VGL_L, the first control signal and the second control signal, and the third voltage terminal VGH and the output terminal OUT are turned off; at this time, the voltage of the output signal of the output terminal OUT is the voltage provided by the second voltage terminal VGL.

[0114] In the third stage, the input circuit 10 is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit 20 is turned off; the second voltage terminal VGL and the output terminal OUT are turned on by the voltage of the first voltage terminal VGL_L, the first control signal and the second control signal, and the third voltage terminal VGH and the output terminal OUT are turned off. At this time, the voltage of the output signal of the output terminal OUT is the voltage of the second voltage terminal VGL.

[0115] In the fourth stage, the input circuit 10 is turned off by the first clock signal and the second clock signal; the voltage stabilizing circuit 20 is turned off; the second voltage terminal VGL and the output terminal OUT are turned off by the voltage of the third voltage terminal VGH, the first control signal and the second control signal, and the third voltage terminal VGH and the output terminal OUT are turned on. At this time, the voltage of the output signal of the output terminal OUT is the voltage of the third voltage terminal VGH.

[0116] The above four stages can be a cycle, that is, the next stage of the fourth stage is the first stage of another cycle. The first voltage terminal VGL_L and the second voltage terminal VGL can be used to provide a low level, and the third voltage terminal VGH can be used to provide a high level. It can be seen from the above working principle that on the basis of the first input signal and the first control signal, before the low level is switched to the high level, the second voltage terminal VGL and the output terminal OUT can be continuously connected through the voltage of the first voltage terminal VGL_L. When the high level is switched to the low level, the second voltage terminal VGL and the output terminal OUT can be connected, thereby increasing the switching speed of the signal and eliminating the steps of the rising edge or falling edge of the output signal, thereby improving the delay through the first voltage terminal VGL_L and the voltage stabilizing circuit 20 without setting a bootstrap circuit, which is conducive to simplifying the structure of the shift register GOA.

[0117] The following is an exemplary description of a partial circuit of the shift register GOA:

[0118] In some embodiments of the present disclosure, the first control circuit 30 may transmit a second control signal to the second output node N22 or shut down under the control of the voltages of the first input node N11, the second voltage terminal VGL, and the third voltage terminal VGH. The first control circuit 30 may include a first control subcircuit 301, a second control subcircuit 302, and a third control subcircuit 303, wherein:

[0119] The first control sub-circuit 301 may be connected to the second input node N12 , the second voltage terminal VGL, and the second clock signal terminal CK2 , and may be configured to be turned on or off under the control of the second clock signal.

[0120] The second control sub-circuit 302 may be connected to the connection node N3 , the first input node N11 , and the third voltage terminal VGH, and may be configured to be turned on or off under the control of the voltage of the first input node N11 .

[0121] The third control sub-circuit 303 may be connected to the second input node N12 and the connection node N3 , and may be configured to be turned on or off under the control of the voltage of the third voltage terminal VGH.

[0122] like Figure 6 As shown, in some embodiments of the present disclosure, the second control circuit 40 includes a fourth control subcircuit and a fifth control subcircuit, wherein:

[0123] The fourth control subcircuit is connected to the third voltage terminal VGH, the first input node N11 and the second output node N22, and is configured to control the second control signal under the control of the voltage of the first input node N11;

[0124] The fifth control sub-circuit is connected to the third voltage terminal VGH, the first output node N21 and the second output node N22, and is configured to control the first control signal under the control of the voltage of the second output node N22.

[0125] In some embodiments of the present disclosure, the output circuit 50 may include a first output sub-circuit 501 and a second output sub-circuit 502, wherein:

[0126] The first output sub-circuit 501 may be connected to the first output node N21, the second voltage terminal VGL and the output terminal OUT, and may turn on or off the second voltage terminal VGL and the output terminal OUT under the control of the first control signal. The second output sub-circuit 502 may be connected to the second output node N22, the third voltage terminal VGH and the output terminal OUT, and may turn on or off the third voltage terminal VGH and the output terminal OUT under the control of the second control signal.

[0127] like Figure 6As shown, in some embodiments of the present disclosure, the shift register GOA of the present disclosure may further include a first isolation circuit 60, which may be connected to the first input node N11, the voltage stabilizing circuit 20, and the second voltage terminal VGL. The first isolation circuit 60 may be turned on under the action of the voltage of the second voltage terminal VGL, and may prevent the first output node N21 from leaking to the first input node N11, thereby playing an isolation role.

[0128] Optionally, the shift register GOA may further include a second isolation circuit 70, which may be connected to the connection node N3, the second output node N22 and the second voltage terminal VGL. The second isolation circuit 70 may be turned on under the action of the voltage of the second voltage terminal VGL, and may prevent the second output node N22 from leaking to the second input node N12, thereby playing an isolation role.

[0129] The specific structure of the shift register GOA is exemplarily described below:

[0130] like Figure 6 As shown, in some embodiments of the present disclosure, the input circuit 10 includes an input transistor T1. The first control subcircuit 301 includes a first control transistor T3, the second control subcircuit 30232 includes a second control transistor T6, and the third control subcircuit 303 includes a third control transistor T4 and a first capacitor C1. The voltage stabilizing circuit 20 includes a voltage stabilizing transistor T8 and a second capacitor C2. The fourth control subcircuit includes a fourth control transistor T7; the fifth control subcircuit includes a fifth control transistor T9. The first output subcircuit 501 may include a first output transistor T11 and a third capacitor C3, and the second output subcircuit 502 includes a second output transistor T10 and a fourth capacitor C4. The first isolation circuit 60 includes a first isolation transistor T2, and the second isolation circuit 70 includes a second isolation transistor T5; wherein:

[0131] The input transistor T1 has a gate connected to the first clock signal terminal CK1 , a first electrode connected to the input terminal IN, and a second electrode connected to the first input node N11 .

[0132] The gate of the first control transistor T3 is connected to the second clock signal terminal CK2, the first electrode is connected to the second voltage terminal VGL, and the second electrode is connected to the second input node N12. The gate of the second control transistor T6 is connected to the first input node N11, the first electrode is connected to the third voltage terminal VGH, and the second electrode is connected to the connection node N3. The gate of the third control transistor T4 is connected to the middle node N5 with one plate of the first capacitor C1, the other plate of the first capacitor C1 is connected to the first electrode of the third control transistor T4 and the connection node N3, and the second electrode of the third control transistor T4 is connected to the second input node N12.

[0133] The gate of the voltage-stabilizing transistor T8 is connected to the first input node N11 and one plate of the second capacitor C2, the first electrode is connected to the first voltage terminal VGL_L, and the second electrode is connected to the other plate of the second capacitor C2 and the first output node N21. For example, the gate of the voltage-stabilizing transistor T8 can be connected to the transition node N4, and the transition node N4 can be connected to the first input node N11 through the first isolation transistor T2, so that the gate of the voltage-stabilizing transistor T8 is connected to the first input node N11. Among them, the gate of the first isolation transistor T2 can be connected to the second voltage terminal VGL, the first electrode is connected to the first input node N11, and the second electrode is connected to the transition node N4.

[0134] The gate of the fourth control transistor T7 is connected to the first input node N11, for example, the gate is connected to the transition node N4; the first electrode of the fourth control transistor T7 is connected to the third voltage terminal VGH, and the second electrode is connected to the second output node N22. The gate of the fifth control transistor T9 can be connected to the second output node N22, the first electrode is connected to the third voltage terminal VGH, and the second electrode is connected to the first output node N21.

[0135] The gate of the first output transistor T11 is connected to the first output node N21, the first electrode is connected to the second voltage terminal VGL, the second electrode is connected to the output terminal OUT, one plate of the third capacitor C3 is connected to the first output node N21, and the other plate is connected to the second voltage terminal VGL.

[0136] The gate of the second output transistor T10 is connected to the second output node N22, the first electrode is connected to the third voltage terminal VGH, the second electrode is connected to the output terminal OUT, one plate of the fourth capacitor C4 is connected to the second output node N22, and the other plate is connected to the third voltage terminal VGH.

[0137] The gate of the second isolation transistor T5 is connected to the second voltage terminal VGL, the first electrode is connected to the connection node N3, the second electrode is connected to the second output node N22, and the connection node N3 is connected to the second output node N22 through the second isolation transistor T5.

[0138] Taking the case where all transistors of the shift register GOA are P-type transistors as an example, the driving method thereof is described in detail in combination with the shift register GOA in the above embodiment:

[0139] The voltage outputted by the first voltage terminal VGL_L is a first voltage, and the voltage outputted by the second voltage terminal VGL is a second voltage, both of which are low levels, and the absolute value of the first voltage is greater than the absolute value of the second voltage, for example, the difference between the absolute value of the first voltage and the absolute value of the second voltage is 3 V. The voltage outputted by the third voltage terminal VGH is a third voltage, and the third voltage is a high level.

[0140] like Figure 7 , Fig.11 and Fig.13 As shown, in the first stage, the first clock signal is at a low level, and the input signal is at a low level; the input transistor T1 is turned on, the first isolation transistor T2 is always turned on, and the input signal is transmitted to the first input node N11 and the transition node N4, so that the second control transistor T6, the fourth control transistor T7 and the voltage regulator transistor T8 are turned on; the third voltage terminal VGH can charge the first capacitor C1 through the second control transistor T6 and the connection node N3, at this time, the third control transistor T4 does not meet the turn-on condition and is in the off state; the first voltage terminal VGL_L provides the first voltage to the first output node N21 through the voltage regulator transistor T8, so that the voltage of the output signal of the first output transistor T11 and the output terminal OUT is the first voltage. At the same time, the second clock signal is at a high level, so that the first control transistor T3 is turned off, and the third control transistor T4 is turned off; the third voltage terminal VGH can transmit the third voltage to the second output node N22 through the fourth control transistor T7, so that the fifth control transistor T9 and the second output transistor T10 are turned off.

[0141] like Figure 8 , Fig.11 and Fig.13 As shown, in the second stage, the first clock signal becomes high level, and the input signal is still low level; the input transistor T1 is turned off, and under the action of the second capacitor C2, the second control transistor T6, the voltage stabilizing transistor T8 and the fourth control transistor T7 are continuously turned on, and under the action of the first voltage terminal VGL_L and the third capacitor C3, the first output transistor T11 is continuously turned on, at this time, the voltage of the output signal of the output terminal OUT is still the second voltage of the second voltage terminal VGL. The third voltage terminal VGH continuously controls the voltage of the second output node N22, so that the fifth control transistor T9 and the second output transistor T10 are turned off. At the same time, the second clock signal becomes a low level, the first control transistor T3 is turned on, and under the continuous action of the third voltage terminal VGH, the voltage difference between the connection node N3 and the third control transistor T4 reaches the turn-on condition, that is, the gate-source voltage difference is greater than the threshold voltage of the third control transistor T4, the third control transistor T4 is turned on, and the second voltage of the second voltage terminal VGL is transmitted to the second output node N22 through the normally-on second isolation transistor T5, and the voltage of the second output node N22 is pulled down, but the fifth control transistor T9 and the second output transistor T10 can still be kept turned off.

[0142] like Fig. 9 , Fig.11 and Fig.13As shown, in the third stage, the first clock signal becomes low level, the input signal becomes high level, the input transistor T1 is turned on, the first isolation transistor T2 is always on, and the input signal turns off the second control transistor T6, the fourth control transistor T7 and the voltage stabilizing transistor T8; under the coupling effect of the second capacitor C2, the voltage of the first output node N21 increases due to the high level of the transition node N4, and gradually turns off the first output transistor T11, but the first output transistor T11 can still remain turned on for a period of time. Combined with the effect of the third capacitor C3, the voltage of the output signal of the output terminal OUT can still maintain a low-level second voltage for a period of time. Under the effect of the first capacitor C1, the third control transistor T4 is continuously turned on. At the same time, the second clock signal is high level, which turns off the first control transistor T3, and under the effect of the fourth capacitor C4, the fifth control transistor T9 and the second output transistor T10 remain turned off.

[0143] like Fig.10 , Fig.11 and Fig.13 As shown, in the fourth stage, the first clock signal becomes high level, the input signal becomes low level, the input transistor T1 is turned off, the first isolation transistor T2 is always on, and under the action of the second capacitor C2, the second control transistor T6, the fourth control transistor T7 and the voltage stabilizing transistor T8 are turned off; under the action of the first capacitor C1, the third control transistor T4 is continuously turned on. At the same time, the second clock signal is low level, so that the first control transistor T3 is turned on, the second voltage is written into the second output node N22, the fifth control transistor T9 and the second output transistor T10 are turned on, the third voltage terminal VGH can write the third voltage to the first output node N21 through the fifth control transistor T9, and the first output transistor T11 is turned off; the output signal of the output terminal OUT is the third voltage of high level.

[0144] Based on the above-mentioned driving method, the output signal is switched from the second voltage of the low level to the third voltage of the high level. In this process, under the action of the first voltage terminal VGL_L, the voltage of the first output node N21 can be stabilized to ensure that the output terminal OUT outputs a stable signal. Moreover, by controlling the voltage of the first voltage terminal VGL_L, in particular, the step existing on the falling edge when the high and low levels are switched can be eliminated. Moreover, compared with adding a large number of transistors and capacitors to utilize the bootstrap principle, the step on the falling edge can be eliminated by controlling the internal signal of the shift register. The above-mentioned first voltage of the external first voltage terminal VGL_L can be realized only by the voltage-stabilizing transistor T8 and the second capacitor C2, and the structure is simpler.

[0145] It should be noted that, although the steps of the driving method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0146] like Figure 5 As shown, based on the above driving method, by adjusting the pulse width of the input signal, that is, the width of the high level of the input signal, the duration of the output signal, the pulse width of the input signal, can be controlled. For a driving circuit WG, its multiple shift registers GOA are cascaded, so the input signal of the first stage shift register GOA, that is, the pulse width of the trigger signal STV can be used to control the pulse width of the output signal of each shift register GOA. At the same time, the pulse width of the input signal is n times the first clock signal and the second clock signal, and n is a positive integer, for example, n is 1, 2, 3, etc.

[0147] like Fig.11 and Fig.12 As shown, the pulse width of the trigger signal STV is the same as the pulse width of the first clock signal (the signal of the first clock signal terminal CK1) and the second clock signal (the signal of the second clock signal terminal CK2), that is, n=1. Fig.12 The timing sequence of the output signals of the output terminals OUT of the four cascaded shift registers GOA, ie, the timing sequence of the output signals of the first output terminal OUT1 to the fourth output terminal OUT4 is shown.

[0148] like Fig.13 and Fig.14 As shown, the pulse width of the trigger signal STV is 5 times the pulse width of the first clock signal and the second clock signal, that is, n=5. Fig.14 The timing sequence of the output signals of the output terminals OUT of the four cascaded shift registers GOA, ie, the timing sequence of the output signals of the first output terminal OUT1 to the fourth output terminal OUT4 is shown.

[0149] like Fig.15 As shown, the pulse width of the trigger signal STV is 14 times the pulse width of the first clock signal and the second clock signal, that is, n=14. Fig.15 The timing sequence of the output signals of the output terminals OUT of the four cascaded shift registers GOA, ie, the timing sequence of the output signals of the first output terminal OUT1 to the fourth output terminal OUT4 is shown.

[0150] The shift register GOA can be used not only in gate drive circuits but also in light-emitting drive circuits, and can scan not only P-type transistors but also N-type transistors. The gates of some transistors in the same pixel circuit are connected to the output terminal OUT of the first drive circuit, and the gates of other transistors are connected to the output terminal OUT of the second drive circuit; and the two first drive circuits are connected to the gates of different transistors in the pixel circuit.

[0151] In some embodiments of the present disclosure, for the 7T1C pixel circuit using the LTPO process mentioned above, the driving circuit WG may include two identical first driving circuits WG1 and one second driving circuit WG2, one first driving circuit WG1 is a gate driving circuit, which can be used to scan the first reset transistor M1 and the compensation transistor M2, that is, its output terminal OUT is connected to the gates of the first reset transistor M1 and the compensation transistor M2; the other first driving circuit WG1 is a light-emitting driving circuit, which can be used to scan the first light-emitting control transistor M5 and the second light-emitting control transistor M6, that is, its output terminal OUT is connected to the gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6.

[0152] The second driving circuit WG2 is different from the first driving circuit WG1, that is, the shift register GOA of the second driving circuit WG2 is different from the shift register GOA of the first driving circuit WG1. The second driving circuit WG2 is used to scan the write transistor M4 and the second reset transistor M7, that is, its output terminal OUT is connected to the gate of the write transistor M4 and the second reset transistor M7.

[0153] It should be noted that, in the same pixel circuit, the shift registers GOA connected to the transistors connected to the same driving circuit WG may not be at the same level, and the output terminal OUT of the same shift register GOA may be connected to transistors of multiple rows of pixel circuits.

[0154] In addition, the number of the first voltage terminal VGL_L, the second voltage terminal VGL and the third voltage terminal VGH in this article is not limited to one, as long as the voltages are the same. For example, multiple transistors are connected to the second voltage terminal VGL. Multiple transistors can be connected to the same voltage terminal, or they can be connected to multiple voltage terminals that can output the second voltage.

[0155] The following is an exemplary description of the film layer of the driving backplane:

[0156] like Figure 2As shown, the driving backplane BP may include a substrate SU and a light shielding layer BSM, a first semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, a second semiconductor layer IG, a third gate layer GA3, a first source and drain layer SD1, and a second source and drain layer SD2, which are sequentially distributed in a direction away from the substrate SU, wherein:

[0157] The light shielding layer BSM is disposed on one side of the substrate SU and can be made of metal or other conductive and light shielding materials. The light shielding layer BSM can at least overlap with the driving transistor M3 to prevent the bottom signal and light from affecting the driving transistor M3.

[0158] like Figure 2 As shown, the first semiconductor layer SE is arranged on the side of the light-shielding layer BSM away from the substrate SU, and the material of the first semiconductor layer SE may be polycrystalline silicon, which may include the active parts of the driving transistor M3, the writing transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6 and the active parts of each transistor of the shift register GOA.

[0159] like Figure 2 As shown, the first gate layer GA1 is disposed on a side of the first semiconductor layer SE away from the substrate SU. The first gate layer GA1 may include a storage capacitor Cst and a plate of the first capacitor C1 to the fourth capacitor C4 and gates of some transistors.

[0160] like Figure 2 As shown, the second gate layer GA2 is disposed on a side of the first gate layer GA1 away from the substrate SU, and includes a storage capacitor Cst and another electrode plate of the first capacitor C1 to the fourth capacitor C4.

[0161] like Figure 2 As shown, the second semiconductor layer IG may be disposed on a side of the second gate layer GA2 away from the substrate SU, and its material may be a metal oxide such as IGZO. The second semiconductor layer IG may include active portions of the first reset transistor M1 and the compensation transistor M2.

[0162] like Figure 2 As shown, the third gate layer GA3 may be disposed on a side of the second semiconductor layer IG away from the substrate SU and overlap the second semiconductor layer IG. The third gate layer GA3 may include gates of the first reset transistor M1 and the compensation transistor M2.

[0163] like Figure 2 As shown, the first source-drain layer SD1 may be disposed on a side of the third gate layer GA3 away from the substrate SU, and may be connected to some transistors and capacitors.

[0164] like Figure 2 As shown, the second source-drain layer SD2 is disposed on a side of the first source-drain layer SD1 away from the substrate SU.

[0165] In addition, if Figure 2 As shown, the driving backplane BP may further include a buffer layer BUF of an insulating material, a first gate insulating layer GI1, a second gate insulating layer GI2, a first insulating layer IL1, a third gate insulating layer GI3, a second insulating layer IL2, a first planar layer PLN1 and a second planar layer PLN2, wherein:

[0166] The buffer layer BUF may cover the light shielding layer BSM, and its material may include inorganic materials such as silicon nitride and silicon oxide. The buffer layer BUF may be a single layer or a multilayer structure, and the materials of different layers may be different. The first semiconductor layer SE is disposed on the surface of the buffer layer BUF away from the substrate SU.

[0167] The first gate insulating layer GI1 covers the first semiconductor layer SE, and its material may include inorganic materials such as silicon nitride and silicon oxide. The first gate layer GA1 is disposed on a surface of the first gate insulating layer GI1 away from the substrate SU.

[0168] The second gate insulating layer GI2 covers the first gate layer GA1, and its material may include inorganic materials such as silicon nitride and silicon oxide. The second gate layer GA2 is disposed on a surface of the second gate insulating layer GI2 away from the substrate SU.

[0169] The first insulating layer IL1 may cover the second gate layer GA2, and its material may include inorganic materials such as silicon nitride and silicon oxide. The first insulating layer IL1 may be a single layer or a multi-layer structure, and the materials of different layers may be different. The second semiconductor layer IG is disposed on the surface of the first insulating layer IL1 away from the substrate SU.

[0170] The third gate insulating layer GI3 covers the second semiconductor layer IG, and its material may include inorganic materials such as silicon nitride and silicon oxide. The third gate layer GA3 is disposed on a surface of the third gate insulating layer GI3 away from the substrate SU.

[0171] The second insulating layer IL2 may cover the third gate layer GA3, and its material may include inorganic materials such as silicon nitride and silicon oxide. The second insulating layer IL2 may be a single layer or a multi-layer structure, and the materials of different layers may be different. The first source drain layer SD1 is disposed on the surface of the second insulating layer IL2 away from the substrate SU.

[0172] The first planar layer PLN1 may cover the first source-drain layer SD1, and its material may be an organic material such as resin, and planarization may be achieved through the leveling of the organic material. The second source-drain layer SD2 may be disposed on the surface of the first planar layer PLN1 away from the substrate SU. In addition, in some embodiments, the first source-drain layer SD1 may be covered with a passivation layer, and then the passivation layer may be covered with the first planar layer PLN1.

[0173] The second planar layer PLN2 can cover the second source-drain layer SD2 and can be made of organic materials such as resin. The first electrode ANO and the pixel definition layer PDL of the light emitting device LD can be arranged on the surface of the second planar layer PLN2 away from the substrate SU.

[0174] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A shift register, characterized in that: include: an input circuit connected to the input terminal, the first clock signal terminal and the first input node, and configured to transmit an input signal provided by the input terminal to the first input node in response to a first clock signal provided by the first clock signal terminal; a voltage stabilizing circuit connected to the first voltage terminal, the first output node and the first input node, and configured to transmit a first control signal to the first output node under the control of the voltage of the first input node; a first control circuit connected to the second voltage terminal, the second clock signal terminal, the third voltage terminal, the second output node and the first input node, and configured to transmit a second control signal to the second output node under the control of a second clock signal provided by the second clock signal terminal and the voltage of the first input node; a second control circuit connected to the third voltage terminal, the first input node, the first output node, and the second output node, and configured to control the first control signal and the second control signal under the control of the voltage of the first input node and the second control signal; The output circuit is connected to the first output node, the second output node, the second voltage terminal, the third voltage terminal and the output terminal, and is configured to output the signal of the second voltage terminal or the third voltage terminal from the output terminal under the control of the first control signal and the second control signal; the voltage of the first voltage terminal can turn on the second voltage terminal and the output terminal.

2. The shift register according to claim 1, characterized in that: The first control circuit comprises: a first control subcircuit connected to the second input node, the second voltage terminal and the second clock signal terminal, and configured to be turned on or off under the control of the second clock signal; a second control subcircuit connected to the connection node, the first input node and the third voltage terminal, and configured to be turned on or off under the control of the voltage of the first input node; The third control subcircuit is connected to the second input node and the connection node, and is configured to be turned on or off under the control of the voltage of the third voltage terminal.

3. The shift register according to claim 2, characterized in that: The first control subcircuit includes a first control transistor, the second control subcircuit includes a second control transistor, and the third control subcircuit includes a third control transistor and a first capacitor; The gate of the first control transistor is connected to the second clock signal terminal, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second input node; The gate of the second control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the connection node; The gate of the third control transistor is connected to the connection node via the first capacitor, the first electrode is connected to the connection node, and the second electrode is connected to the second input node.

4. The shift register according to claim 1, wherein: The voltage stabilizing circuit includes a voltage stabilizing transistor and a second capacitor; The gate of the voltage stabilizing transistor is connected to the first input node and the second capacitor, the first electrode is connected to the first voltage terminal, and the second electrode is connected to the second capacitor and the first output node.

5. The shift register according to claim 1, characterized in that: The second control circuit includes a fourth control subcircuit and a fifth control subcircuit; The fourth control subcircuit is connected to the third voltage terminal, the first input node and the second output node, and is configured to control the second control signal under the control of the voltage of the first input node; The fifth control subcircuit is connected to the third voltage terminal, the first output node and the second output node, and is configured to control the first control signal under the control of the voltage of the second output node.

6. The shift register according to claim 5, characterized in that: The fourth control subcircuit includes a fourth control transistor; the fifth control subcircuit includes a fifth control transistor; The gate of the fourth control transistor is connected to the first input node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the second output node; The gate of the fifth control transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the first output node.

7. The shift register according to claim 1, characterized in that: The input circuit comprises an input transistor, wherein a gate of the input transistor is connected to the first clock signal terminal, a first electrode is connected to the input terminal, and a second electrode is connected to the first input node; The output circuit includes a first output transistor, a third capacitor, a second output transistor and a fourth capacitor; The gate of the first output transistor is connected to the first output node, the first electrode is connected to the second voltage terminal, the second electrode is connected to the output terminal, and the third capacitor is connected to the first output node and the second voltage terminal; The gate of the second output transistor is connected to the second output node, the first electrode is connected to the third voltage terminal, the second electrode is connected to the output terminal, and the fourth capacitor is connected to the second output node and the third voltage terminal.

8. The shift register according to claim 2, characterized in that: The shift register further includes: The first isolation circuit is connected to the first input node and the voltage stabilizing circuit.

9. The shift register according to claim 8, characterized in that: The shift register further includes: The second isolation circuit connects the connection node and the second output node.

10. The shift register according to claim 9, characterized in that: The first isolation circuit includes a first isolation transistor; the second isolation circuit includes a second isolation transistor; The gate of the first isolation transistor is connected to the second voltage terminal, the first electrode is connected to the first input node, and the second electrode is connected to the voltage stabilizing circuit; The second isolation transistor has a gate connected to the second voltage terminal, a first electrode connected to the connection node, and a second electrode connected to the second output node.

11. A driving circuit, characterized in that: It comprises a plurality of cascaded shift registers, wherein the shift register is the shift register according to any one of claims 1 to 10.

12. A display panel, characterized in that: include: A driving backplane, comprising a plurality of pixel circuits and a first driving circuit, wherein the pixel circuits are arranged in an array along a row direction and a column direction; The first driving circuit is the driving circuit according to claim 11, and an output end of the first driving circuit is connected to at least one row of pixel circuits; The light emitting devices are arranged in an array on one side of the driving backplane.

13. The display panel according to claim 12, characterized in that: The pixel circuit includes a plurality of transistors; the number of the first driving circuits is two; the display panel further includes a second driving circuit; The gates of some transistors in the same pixel circuit are connected to the output end of the first driving circuit, and the gates of another part of the transistors are connected to the output end of the second driving circuit; and the two first driving circuits are connected to the gates of different transistors in the pixel circuit.

14. The display panel according to claim 13, characterized in that: The pixel circuit includes a driving transistor, a writing transistor, a compensating transistor, a first reset transistor, a second reset transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor; the first reset transistor and the compensating transistor are N-type metal oxide transistors, and the driving transistor, the writing transistor, the second reset transistor, the first light emission control transistor and the second light emission control transistor are P-type polysilicon transistors; The first electrode of the first light-emitting control transistor is used to receive a first power supply signal, and the second electrode is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the first electrode of the second light-emitting control transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting device; the first electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the gate electrode of the driving transistor; the first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the second electrode of the compensation transistor; the first electrode of the second reset transistor is used to receive a second reset signal, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, and the second electrode is connected to the first electrode of the driving transistor; the first plate of the storage capacitor is connected to the gate electrode of the driving transistor, and the second plate is used to receive the first power supply signal; The gate of the first reset transistor and the gate of the compensation transistor are connected to an output end of the first driving circuit; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to an output end of another first driving circuit; the gate of the write transistor and the gate of the second reset transistor are connected to an output end of the second driving circuit.

15. A shift register driving method, characterized in that: The shift register is the shift register according to any one of claims 1 to 10; the driving method comprises: In the first stage, the input circuit is turned on by the first clock signal and the second clock signal, and the first control circuit is turned off; the voltage stabilizing circuit is turned on; the second voltage terminal is controlled to be turned on by the first control signal, and the third voltage terminal is controlled to be turned off by the output terminal; In the second stage, the input circuit is turned off and the first control circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned on; the second voltage terminal is controlled to be turned on and off with the output terminal by the voltage of the first voltage terminal, the first control signal and the second control signal, and the third voltage terminal is controlled to be turned on and off with the output terminal; In the third stage, the input circuit is turned on by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal is controlled to be turned on and off with the output terminal by the voltage of the first voltage terminal, the first control signal and the second control signal, and the third voltage terminal is controlled to be turned on and off with the output terminal; In the fourth stage, the input circuit is turned off by the first clock signal and the second clock signal; the voltage stabilizing circuit is turned off; the second voltage terminal and the output terminal are turned off and the third voltage terminal and the output terminal are turned on by the voltage at the third voltage terminal, the first control signal and the second control signal.

16. The driving method according to claim 15, characterized in that: An absolute value of a voltage at the first voltage terminal is greater than an absolute value of a voltage at the second voltage terminal.

17. The driving method according to claim 16, characterized in that: The absolute value of the difference between the absolute value of the voltage at the first voltage terminal and the absolute value of the voltage at the second voltage terminal is 3V.

18. The driving method according to claim 15, characterized in that: The pulse width of the input signal is n times that of the first clock signal and the second clock signal, where n is a positive integer.

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