Flash interference test method, controller and computer-readable storage medium

Abstract

An embodiment of the present application provides a flash interference test method, a controller, and a computer-readable storage medium. The flash interference test method simulates different target application scenarios such as mobile device application scenarios, automotive electronics application scenarios, or industrial equipment application scenarios, and also uses a preset interference curve to perform interference operations on the flash memory under test. During the interference test, the interference amplitude parameter changes with time. Therefore, the embodiment of the present application can set different application scenarios and varying degrees of interference to perform interference tests on flash memory products, making the interference test more suitable for complex actual usage environments. Secondly, the embodiment of the present application will also compare the read-write performance parameter curve of the flash memory under test with the standard performance parameter curve of a qualified sample flash memory to determine the anti-read-write interference ability of the flash memory under test in the target application scenario and the preset interference curve, making the anti-read-write interference ability more accurate.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly to a flash interference testing method, a controller, and a computer-readable storage medium. Background Art

[0002] In the related art, during the production and development of flash products, it is necessary to test the anti-interference ability of the products to evaluate their read / write performance and service life. However, the existing interference testing methods often perform tests in the same application scenario, and the interference level set during the test is often unchanged. Therefore, the existing interference testing means are relatively single and cannot cope with complex actual usage environments. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a flash interference testing method, a controller, and a computer-readable storage medium, aiming to perform interference testing on flash products by setting different application scenarios and varying interference levels, so that the interference testing is more suitable for complex actual usage environments.

[0004] In a first aspect, an embodiment of this application provides a flash interference testing method, including:

[0005] Obtain a preset interference curve, and perform an interference operation on the flash to be tested according to the preset interference curve, where the preset interference curve is a variation curve between an interference amplitude parameter and a time parameter;

[0006] During the interference operation on the flash to be tested in a target application scenario, perform read / write operations on each storage page of the flash to be tested in sequence, where the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario;

[0007] Obtain the read / write performance parameters of the flash to be tested during the read / write operations, and generate a read / write performance parameter curve according to the read / write performance parameters, where the read / write performance parameter curve is a variation curve between the read / write performance parameters and the time parameter;

[0008] Determine the standard performance parameter curve of a qualified sample flash in the target application scenario and under the preset interference curve;

[0009] Compare the read / write performance parameter curve with the standard performance parameter curve, and determine the anti-read / write interference ability of the flash to be tested in the target application scenario and under the preset interference curve according to the comparison result.

[0010] According to some embodiments of the present application, determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve based on the comparison result includes:

[0011] Obtaining the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval;

[0012] Determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve according to the parameter deviation value.

[0013] According to some embodiments of the present application, determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve according to the parameter deviation value includes one of the following:

[0014] When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is greater than the preset deviation value, it is determined that the anti-read / write interference ability of the flash memory under test does not meet the requirements;

[0015] When the parameter deviation value of the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval is less than or equal to the preset deviation value, it is determined that the anti-read / write interference ability of the flash memory under test meets the requirements.

[0016] According to some embodiments of the present application, determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve based on the comparison result includes:

[0017] In the case where the read / write performance parameter curve is above the standard performance parameter curve, obtaining the number of curve intersections of the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process;

[0018] Determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve according to the number of curve intersections.

[0019] According to some embodiments of the present application, determining the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve according to the number of curve intersections includes one of the following:

[0020] When the number of curve intersections of the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process is greater than the preset number, it is determined that the anti-read / write interference ability of the flash memory under test does not meet the requirements;

[0021] When the number of curve intersections between the read / write performance parameter curve and the standard performance parameter curve during the entire read / write operation process is less than or equal to a preset number, it is determined that the anti-read / write interference ability of the flash memory under test meets the requirements.

[0022] According to some embodiments of the present application, after determining that the anti-read / write interference ability of the flash memory under test meets the requirements, the method further includes:

[0023] Determine the target time interval corresponding to at least one rising curve segment in the preset interference curve;

[0024] Calculate the rising slope of the preset interference curve in the target time interval;

[0025] Calculate the falling slope of the read / write performance parameter curve in the target time interval;

[0026] Determine the anti-interference level of the flash memory under test according to the absolute value of the falling slope and the rising slope.

[0027] According to some embodiments of the present application, the determining the anti-interference level of the flash memory under test according to the absolute value of the falling slope and the rising slope includes:

[0028] Calculate the slope difference between the absolute value of the falling slope and the rising slope;

[0029] Determine the anti-interference level of the flash memory under test according to the slope difference, where there is a negative correlation between the anti-interference level and the slope difference.

[0030] According to some embodiments of the present application, the determining the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve includes:

[0031] In the case of multiple qualified sample flash memories, obtain the sample performance parameter curves of multiple qualified sample flash memories under the target application scenario and the preset interference curve, and extract the data points of multiple sample performance parameter curves;

[0032] Generate a curve fitting model, and estimate the parameters of the curve fitting model according to the target statistical method;

[0033] Input the estimated parameters and all the data points into the curve fitting model to generate a standard performance parameter curve for approximating all the data points.

[0034] In a second aspect, an embodiment of the present application provides a controller, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor runs the computer program, it executes the flash interference test method in the first aspect above.

[0035] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions for executing the flash interference test method as in the first aspect above.

[0036] In a fourth aspect, an embodiment of the present application provides a computer program product, including a computer program or computer instructions. It is characterized in that the computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device executes the flash interference test method as in the first aspect above.

[0037] According to the technical solution of the embodiment of the present application, it has at least the following beneficial effects: The embodiment of the present application simulates different target application scenarios such as mobile device application scenarios, automotive electronics application scenarios, or industrial equipment application scenarios, and also uses a preset interference curve to perform interference operations on the flash memory to be tested, and realizes that the interference amplitude parameter changes with time during the interference test. Therefore, the embodiment of the present application can set different application scenarios and changing interference degrees to perform interference tests on flash memory products, making the interference test more suitable for complex actual usage environments; Secondly, the embodiment of the present application will also compare the read-write performance parameter curve of the flash memory to be tested with the standard performance parameter curve of the qualified sample flash memory, so as to determine the anti-read-write interference ability of the flash memory to be tested under the target application scenario and the preset interference curve, making the anti-read-write interference ability more accurate.

[0038] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0039] The drawings are used to provide a further understanding of the technical solution of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

[0040] Figure 1 is a flowchart of a flash interference test method provided by an embodiment of the present application;

[0041] Figure 2 is Figure 1 a sub-step flowchart of an embodiment of step S150 in

[0042] Figure 3 is Figure 2 The sub-step flowchart of step S220 in

[0043] Figure 4 It is a schematic diagram of the parameter deviation value between the read-write performance parameter curve and the standard performance parameter curve within the same preset time interval;

[0044] Figure 5 is Figure 1 The sub-step flowchart of another embodiment of step S150 in

[0045] Figure 6 is Figure 5 The sub-step flowchart of step S520 in

[0046] Figure 7 It is a schematic diagram showing the intersection between the read-write performance parameter curve and the standard performance parameter curve;

[0047] Figure 8 It is a flowchart of an embodiment of the present application for determining the anti-interference level of a flash memory under test that meets the anti-interference requirements;

[0048] Figure 9 is Figure 8 The sub-step flowchart of step S840 in

[0049] Figure 10 is Figure 1 The sub-step flowchart of an embodiment of step S140 in

[0050] Figure 11 It is a schematic diagram of a controller for performing a flash memory interference test method provided by an embodiment of the present application. Detailed implementation manners

[0051] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application.

[0052] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

[0053] In the description of the present application, the meaning of "several" is one or more, the meaning of "multiple" is more than two, and understandings such as "greater than", "less than", "exceeding", etc. do not include the corresponding number, while understandings such as "above", "below", "within", etc. include the corresponding number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0054] In the description of the present application, unless otherwise clearly defined, terms such as "set", "installed", "connected", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0055] In some cases, during the production and development of flash memory products, it is necessary to test the anti-interference ability of the products to evaluate their read / write performance and service life. However, the existing interference test methods often perform tests in the same application scenario, and the interference degree set during the test is often unchanged. Therefore, the existing interference test means are relatively single and cannot cope with complex actual usage environments.

[0056] Based on the above situation, the embodiments of the present application propose a flash memory interference test method, a controller, and a computer-readable storage medium, aiming to perform interference tests on flash memory products by setting different application scenarios and varying interference degrees, so that the interference tests are more in line with complex actual usage environments.

[0057] The following further elaborates on each embodiment of the flash memory interference test method of the present application in conjunction with the accompanying drawings.

[0058] As Figure 1 shown, Figure 1 is a flowchart of a flash memory interference test method provided by an embodiment of the present application. The flash memory interference test method includes but is not limited to steps S110, S120, S130, S140, and S150.

[0059] Step S110: Obtain a preset interference curve, and perform an interference operation on the flash memory to be tested according to the preset interference curve, where the preset interference curve is a change curve between an interference amplitude parameter and a time parameter;

[0060] Step S120: During the interference operation on the flash memory to be tested in the target application scenario, perform read and write operations on each storage page of the flash memory to be tested in sequence, where the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario;

[0061] Step S130: Obtain the read and write performance parameters of the flash memory under test during read and write operations, and generate a read and write performance parameter curve based on the read and write performance parameters. The read and write performance parameter curve is a change curve between the read and write performance parameters and the time parameter;

[0062] Step S140: Determine the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve;

[0063] Step S150: Compare the read and write performance parameter curve with the standard performance parameter curve, and determine the anti-read and write interference ability of the flash memory under test under the target application scenario and the preset interference curve according to the comparison result.

[0064] In one embodiment, first, the embodiment of the present application will perform read and write operations and interference operations on the flash memory under test in the target application scenario and with the preset interference curve. During the read and write operations, the interference amplitude will change with time. At the same time, the embodiment of the present application will record the read and write performance parameters of the flash memory under test during the read and write operations, and respond to generate the read and write performance parameter curve of the flash memory under test. In addition, the embodiment of the present application will also obtain the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve, and then compare the read and write performance parameter curve of the flash memory under test with the standard performance parameter curve of the qualified sample flash memory, so as to determine the anti-read and write interference ability of the flash memory under test under the target application scenario and the preset interference curve.

[0065] In one embodiment, determine the read and write speed requirements and the random read and write performance requirements according to the scenario type of the target application scenario; determine the target test performance parameters according to the read and write speed requirements and the random read and write performance requirements.

[0066] In one embodiment, since the read and write speed requirements and the random read and write performance requirements corresponding to the target application scenarios of different scenario types are different, therefore, the embodiment of the present application needs to first determine the read and write speed requirements and the random read and write performance requirements according to the scenario type of the target application scenario, and then determine the target test performance parameters according to the read and write speed requirements and the random read and write performance requirements, such as read and write efficiency, error rate, etc.

[0067] It should be noted that for the mobile device test scenario, its read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0068] Read and write speed requirements: Mobile devices (such as smart phones and tablet computers) usually have relatively high requirements for the read and write speed of eMMC, especially in scenarios such as starting applications, loading games, and playing high-definition videos. The continuous read speed of the eMMC 5.1 version can reach 400MB / s, and the continuous write speed can reach 250MB / s.

[0069] Random read and write performance: In mobile devices, random read and write performance is also important, especially when dealing with a large number of small files. The random read IOPS of the eMMC 5.1 version can reach 8K, and the random write IOPS can reach 6K.

[0070] Application scenarios: Mobile devices pay more attention to the user experience, so low latency and high IOPS are key metrics.

[0071] In addition, it should be noted that for the automotive electronics test scenario, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0072] Read and write speed requirements: The automotive electronics system has relatively low requirements for the read and write speed of eMMC, but pays more attention to reliability and durability. For example, vehicle infotainment systems and dashboard systems usually do not require extremely high read and write speeds, but need to operate stably in extreme environments.

[0073] Random read and write performance: The automotive electronics system has moderate requirements for random read and write performance, mainly focusing on data integrity and reliability.

[0074] Application scenarios: The automotive electronics system pays more attention to long-term stability and safety rather than extreme performance.

[0075] In addition, it should be noted that for the industrial equipment test scenario, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0076] Read and write speed requirements: The read and write speed requirements of industrial equipment for eMMC vary depending on the specific application. Some industrial automation equipment may require higher read and write speeds to process a large amount of data, but usually not as strict as mobile devices.

[0077] Random read and write performance: Industrial equipment pays more attention to data integrity and low latency, especially in scenarios that require real-time data processing.

[0078] Application scenarios: Industrial equipment usually operates in harsh environments, so it has high requirements for the durability and reliability of eMMC.

[0079] In one embodiment, the read and write performance parameters in the read and write performance parameter curve and the standard performance parameter curve can be read and write speed, input / output operations per second, or other parameters.

[0080] In one embodiment, if the interference amplitude parameter is larger, the read and write performance parameter is lower; if the interference amplitude parameter is smaller, the read and write performance parameter is higher.

[0081] It should be noted that the embodiments of the present application simulate different target application scenarios such as mobile device application scenarios, automotive electronics application scenarios, or industrial equipment application scenarios, and also use a preset interference curve to perform interference operations on the flash memory under test. In the interference test, the interference amplitude parameter changes with time. Therefore, the embodiments of the present application can set different application scenarios and varying degrees of interference to perform interference tests on flash memory products, making the interference test more conform to complex actual usage environments. Secondly, the embodiments of the present application will also compare the read / write performance parameter curve of the flash memory under test with the standard performance parameter curve of a qualified sample flash memory, so as to determine the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve, making the anti-read / write interference ability more accurate.

[0082] In addition, as Figure 2 shown, Figure 2 is Figure 1 a sub-step flowchart of an embodiment of step S150 in

[0083] Step S210: Obtain the parameter deviation value between the read / write performance parameter curve and the standard performance parameter curve within the same preset time interval;

[0084] Step S220: Determine the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve according to the parameter deviation value.

[0085] In one embodiment, under the same target application scenario and preset interference curve, the embodiments of the present application can compare the read / write performance parameter curve of the flash memory under test with the standard performance parameter curve of a qualified sample flash memory. Specifically, a part of the read / write performance parameter curve and a part of the standard performance parameter curve within a certain preset time interval can be selected for comparison, and the difference between the part of the read / write performance parameter curve and the part of the standard performance parameter curve within the preset time interval, that is, the parameter deviation value, can be calculated. Finally, according to the magnitude of the parameter deviation value, it can be determined whether the anti-read / write interference ability of the flash memory under test in the target application scenario and the preset interference curve meets the requirements.

[0086] In addition, as Figure 3 shown, Figure 3 is Figure 2 a sub-step flowchart of step S220 in

[0087] Step S310: When the parameter deviation value between the read-write performance parameter curve and the standard performance parameter curve within the same preset time period is greater than the preset deviation value, it is determined that the anti-read-write interference ability of the flash memory under test meets the requirements;

[0088] Step S320: When the parameter deviation value between the read-write performance parameter curve and the standard performance parameter curve within the same preset time period is less than or equal to the preset deviation value, it is determined that the anti-read-write interference ability of the flash memory under test does not meet the requirements.

[0089] In one embodiment, as Figure 4 shown, Figure 4 FIG. is a schematic diagram of the parameter deviation value between the read-write performance parameter curve B and the standard performance parameter curve A within the same preset time period. It can be seen that the parameter deviation value within the preset time period T1 is H1, and H1 is a negative number. If the parameter deviation value H1 is greater than the preset deviation value, it indicates that the read-write performance parameter curve B within the preset time period does not deviate far downward from the standard performance parameter curve A. At this time, it can be confirmed that the anti-read-write interference ability of the flash memory under test meets the requirements.

[0090] In one embodiment, as Figure 4 shown, if the parameter deviation value H1 is less than or equal to the preset deviation value, it indicates that the read-write performance parameter curve within the preset time period has deviated far downward from the standard performance parameter curve. At this time, it can be confirmed that the anti-read-write interference ability of the flash memory under test does not meet the requirements.

[0091] In addition, as Figure 5 shown, Figure 5 is Figure 1 a sub-step flowchart of another embodiment of step S150 in

[0092] Step S510: When the read-write performance parameter curve is above the standard performance parameter curve, obtain the number of curve intersections between the read-write performance parameter curve and the standard performance parameter curve during the entire read-write operation process;

[0093] Step S520: Determine the anti-read-write interference ability of the flash memory under test in the target application scenario and under the preset interference curve according to the number of curve intersections.

[0094] In one embodiment, in the same target application scenario and under a preset interference curve, if all the read-write performance parameter curves are located above the standard performance parameter curve, it can be confirmed that the anti-read-write interference ability of the flash memory under test meets the requirements; if more than a preset proportion of the read-write performance parameter curves are located above the standard performance parameter curve, then it is necessary to obtain the intersection situation of the read-write performance parameter curve of the flash memory under test and the standard performance parameter curve of the qualified sample flash memory, such as the number of curve intersections, and finally determine whether the anti-read-write interference ability of the flash memory under test meets the requirements according to the number of curve intersections.

[0095] In addition, as Figure 6 shown, Figure 6 is Figure 5 the sub-step flowchart of step S520 in

[0096] Step S610: When the number of curve intersections between the read-write performance parameter curve and the standard performance parameter curve during the entire read-write operation process is greater than the preset number, it is determined that the anti-read-write interference ability of the flash memory under test does not meet the requirements;

[0097] Step S620: When the number of curve intersections between the read-write performance parameter curve and the standard performance parameter curve during the entire read-write operation process is less than or equal to the preset number, it is determined that the anti-read-write interference ability of the flash memory under test meets the requirements.

[0098] In one embodiment, as Figure 7 shown, Figure 7 is a schematic diagram of the intersection between the read-write performance parameter curve B and the standard performance parameter curve A. There are multiple curve intersection points C between the read-write performance parameter curve B and the standard performance parameter curve A. If the number of curve intersection points C, that is, the number of curve intersections, is greater than the preset number, it indicates that the read-write performance parameter curve B is less stable, that is, it indicates that the anti-read-write interference ability of the flash memory under test in the target application scenario and under the preset interference curve is less stable, and thus it can be confirmed that the anti-read-write interference ability of the flash memory under test does not meet the requirements.

[0099] In one embodiment, as Figure 7 shown, if the number of curve intersection points C, that is, the number of curve intersections, is less than or equal to the preset number, it indicates that the read-write performance parameter curve B is more stable, that is, it indicates that the anti-read-write interference ability of the flash memory under test in the target application scenario and under the preset interference curve is more stable, and thus it can be confirmed that the anti-read-write interference ability of the flash memory under test meets the requirements.

[0100] In addition, as Figure 8 shown, Figure 8It is a flowchart of an embodiment of the present application for determining the anti-interference level of a flash memory under test that meets the anti-interference requirements; the method further includes but is not limited to step S810, step S820, step S830, and step S840.

[0101] Step S810: After determining that the anti-read / write interference ability of the flash memory under test meets the requirements, determine the target time interval corresponding to at least one rising curve segment in the preset interference curve;

[0102] Step S820: Calculate the rising slope of the preset interference curve in the target time interval;

[0103] Step S830: Calculate the falling slope of the read / write performance parameter curve in the target time interval;

[0104] Step S840: Determine the anti-interference level of the flash memory under test according to the absolute value of the falling slope and the rising slope.

[0105] In one embodiment, after determining that the anti-read / write interference ability of the flash memory under test meets the requirements, the embodiment of the present application can also classify the anti-interference level of the flash memory under test that meets the requirements, specifically as follows: Select the target time interval in which the preset interference curve is in an upward trend. Among them, since the preset interference curve is in an upward trend, the read / write performance parameter curve will correspondingly be in a downward trend. Then, calculate the rising slope of the preset interference curve in the target time interval and the falling slope of the read / write performance parameter curve in the target time interval. Finally, compare the absolute value of the falling slope and the rising slope to determine the anti-interference level of the flash memory under test.

[0106] In addition, as Figure 9 shown, Figure 9 is Figure 8 a sub-step flowchart of step S840. Regarding the above step S840, it can include but is not limited to step S910 or step S920.

[0107] Step S910: Calculate the slope difference between the absolute value of the falling slope and the rising slope;

[0108] Step S920: Determine the anti-interference level of the flash memory under test according to the slope difference, where there is a negative correlation between the anti-interference level and the slope difference.

[0109] In one embodiment, the embodiment of the present application can calculate the slope difference between the absolute value of the falling slope and the rising slope, and this slope difference can characterize how much the read / write performance parameters of the flash memory under test decline during the period when the interference amplitude increases; thus, the anti-interference level of the flash memory under test can be determined according to the slope difference.

[0110] Among them, if the absolute value of the descending slope and the slope difference between the ascending slope are larger, it indicates that the degree of decline in the read / write performance parameters of the flash memory to be tested due to interference is smaller. Then, the anti-interference level of the flash memory to be tested can be set to the first anti-interference level. If the absolute value of the descending slope and the slope difference between the ascending slope are smaller, it indicates that the degree of decline in the read / write performance parameters of the flash memory to be tested due to interference is larger. Then, the anti-interference level of the flash memory to be tested can be set to the second anti-interference level. Among them, the anti-interference ability of the first anti-interference level is higher than that of the second anti-interference level.

[0111] In addition, as Figure 10 shown, Figure 10 is Figure 1 a sub-step flowchart of an embodiment of step S140 above. Regarding the determination of the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve in step S140 above, it may include but is not limited to step S1010, step S1020, and step S1030.

[0112] Step S1010: In the case of multiple qualified sample flash memories, obtain the sample performance parameter curves of the multiple qualified sample flash memories under the target application scenario and the preset interference curve, and extract the data points of the multiple sample performance parameter curves;

[0113] Step S1020: Generate a curve fitting model, and estimate the parameters of the curve fitting model according to the target statistical method;

[0114] Step S1030: Input the estimated parameters and all data points into the curve fitting model to generate a standard performance parameter curve for approximating all data points.

[0115] In one embodiment, the embodiment of the present application can generate a standard performance parameter curve through multiple steps such as data collection, selection of fitting model, parameter estimation, and curve fitting, specifically as follows:

[0116] Data collection: First, it is necessary to collect the data points of multiple curves; these data points can be experimental data, observational data, or simulation data.

[0117] Selection of fitting model: Select a suitable mathematical model according to the characteristics of the data and the purpose of fitting; common models include linear models, polynomial models, exponential models, logarithmic models, etc.

[0118] Parameter estimation: Use the least squares method, maximum likelihood estimation, or other statistical methods to estimate the parameters of the model; these parameters enable the model to best fit the data points of all curves.

[0119] Curve fitting: Substitute the estimated parameters into the model to obtain a standard curve, which should pass through or be close to all data points as much as possible.

[0120] Based on the flash interference test methods of the above various embodiments, the following respectively present various embodiments of the controller, computer-readable storage medium, and computer program product of the present application.

[0121] As Figure 11 shown, Figure 11 is a schematic diagram of a controller for executing the flash interference test method provided by an embodiment of the present application. The controller 100 implemented by the present application includes: a processor 110, a memory 120, and a computer program stored on the memory 120 and executable on the processor 110. Among them, Figure 11 one processor 110 and one memory 120 are taken as examples.

[0122] The processor 110 and the memory 120 can be connected through a bus or other means, Figure 11 Taking connection through a bus as an example.

[0123] The memory 120, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory 120 can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 120 optionally includes a memory 120 remotely set relative to the processor 110, and these remote memories 120 can be connected to the controller 100 through a network. Examples of the above network include but are not limited to the Internet, enterprise intranet, local area network, mobile communication network, and their combinations.

[0124] Those skilled in the art can understand that Figure 11 the device structure shown in

[0125] does not constitute a limitation on the controller 100, and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Figure 11 In the controller 100 shown in

[0126] It should be noted that since the controller 100 of the embodiment of the present application can execute the flash interference test method of any of the above embodiments, therefore, for the specific implementation manners and technical effects of the controller 100 of the embodiment of the present application, reference may be made to the specific implementation manners and technical effects of the flash interference test method of any of the above embodiments.

[0127] In addition, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions for executing the above flash interference test method. Exemplarily, the method steps described above are executed. Figures 1 to 3 、 Figures 5 to 6 、 Figures 8 to 10 in the method steps.

[0128] It should be noted that since the computer-readable storage medium of the embodiment of the present application can execute the flash interference test method of any of the above embodiments, therefore, for the specific implementation manners and technical effects of the computer-readable storage medium of the embodiment of the present application, reference may be made to the specific implementation manners and technical effects of the flash interference test method of any of the above embodiments.

[0129] In addition, an embodiment of the present application further provides a computer program product including a computer program or computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions to enable the computer device to execute the above flash interference test method. Exemplarily, the method steps described above are executed. Figures 1 to 3 、 Figures 5 to 6 、 Figures 8 to 10 in the method steps.

[0130] It should be noted that since the computer program product of the embodiment of the present application can execute the flash interference test method of any of the above embodiments, therefore, for the specific implementation manners and technical effects of the computer program product of the embodiment of the present application, reference may be made to the specific implementation manners and technical effects of the flash interference test method of any of the above embodiments.

[0131] Those of ordinary skill in the art will understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0132] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression refers to any combination of these items, including any combination of single item (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0133] In several embodiments provided by the present application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, indirect couplings or communication connections of apparatuses or units, and can be in electrical, mechanical, or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] It should also be understood that the various embodiments provided by the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0135] The above has made a specific description of the preferred embodiments of the present application, but the present application is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present application. These equivalent deformations or substitutions are all included within the scope defined by the claims of the present application.

Claims

1. A flash memory interference test method, characterized in that, Including: Obtain a preset interference curve, and perform an interference operation on the flash memory under test according to the preset interference curve, where the preset interference curve is a variation curve between an interference amplitude parameter and a time parameter; In a target application scenario and during the interference operation on the flash memory under test, perform read and write operations on each storage page of the flash memory under test in sequence, where the target application scenario includes a mobile device application scenario, an automotive electronics application scenario, or an industrial equipment application scenario; Obtain the read and write performance parameters of the flash memory under test during the read and write operations, and generate a read and write performance parameter curve according to the read and write performance parameters, where the read and write performance parameter curve is a variation curve between the read and write performance parameters and the time parameter; Determine the standard performance parameter curve of the qualified sample flash memory under the target application scenario and the preset interference curve; Compare the read and write performance parameter curve with the standard performance parameter curve, and determine the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the comparison result; Wherein, the determining the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the comparison result includes: In the case where the read and write performance parameter curve is above the standard performance parameter curve, obtain the number of curve intersections between the read and write performance parameter curve and the standard performance parameter curve during the entire process of the read and write operation; Determine the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the number of curve intersections; In addition, after determining that the read and write interference resistance ability of the flash memory under test meets the requirements, the method further includes: Determine the target time interval corresponding to at least one rising curve segment in the preset interference curve; Calculate the rising slope of the preset interference curve in the target time interval; Calculate the falling slope of the read and write performance parameter curve in the target time interval; Calculate the slope difference between the absolute value of the falling slope and the rising slope; Determine the anti-interference level of the flash memory under test according to the slope difference, where there is a negative correlation between the anti-interference level and the slope difference.

2. The method according to claim 1, wherein The determining the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the comparison result includes: Obtain the parameter deviation value between the read and write performance parameter curve and the standard performance parameter curve within the same preset time interval; Determine the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the parameter deviation value.

3. The method according to claim 2, characterized in that, The determining the read and write interference resistance ability of the flash memory under test under the target application scenario and the preset interference curve according to the parameter deviation value includes one of the following: When the parameter deviation value between the read and write performance parameter curve and the standard performance parameter curve within the same preset time interval is greater than the preset deviation value, determine that the read and write interference resistance ability of the flash memory under test meets the requirements; When the parameter deviation value between the read-write performance parameter curve and the standard performance parameter curve within the same preset time interval is less than or equal to the preset deviation value, it is determined that the read-write interference resistance ability of the flash memory under test does not meet the requirements.

4. The method according to claim 1, wherein The determination of the read-write interference resistance ability of the flash memory under test according to the number of curve intersections in the target application scenario and under the preset interference curve includes one of the following: When the number of curve intersections between the read-write performance parameter curve and the standard performance parameter curve during the entire read-write operation process is greater than the preset number, it is determined that the read-write interference resistance ability of the flash memory under test does not meet the requirements; When the number of curve intersections between the read-write performance parameter curve and the standard performance parameter curve during the entire read-write operation process is less than or equal to the preset number, it is determined that the read-write interference resistance ability of the flash memory under test meets the requirements.

5. The method according to claim 1, wherein The determination of the standard performance parameter curve of the qualified sample flash memory in the target application scenario and under the preset interference curve includes: In the case of multiple qualified sample flash memories, obtain the sample performance parameter curves of the multiple qualified sample flash memories in the target application scenario and under the preset interference curve, and extract the data points of the multiple sample performance parameter curves; Generate a curve fitting model and estimate the parameters of the curve fitting model according to the target statistical method; Input the estimated parameters and all the data points into the curve fitting model to generate a standard performance parameter curve for approximating all the data points.

6. A controller, characterized in that, Including: A memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor runs the computer program, it executes the flash memory interference test method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that: Stored with computer-executable instructions for executing the flash memory interference test method according to any one of claims 1 to 5.

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