Solid-state hard disk performance testing method and related equipment based on multi-interface switching

Abstract

The present invention discloses a solid-state hard disk performance test method based on multi-interface switching and related equipment, and relates to the field of data processing. The method includes determining a target interface combination according to the specification parameters of the solid-state hard disk under test and the interface types supported, and a preset interface configuration library; generating an interface switching strategy according to the target interface combination; based on the interface switching strategy, performing a first performance test through a first target interface to obtain first performance test data; based on the interface switching strategy, performing interface switching processing on the solid-state hard disk under test; performing a second performance test on the solid-state hard disk under test through a second target interface to obtain second performance test data; aligning the two performance test data to obtain protocol stack interaction feature data and physical layer signal quality data of the solid-state hard disk under test, and then determining the performance test result of the solid-state hard disk under test. The present invention can comprehensively evaluate the performance of solid-state hard disks under different interface types.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a solid state hard disk performance testing method based on multi-interface switching and related equipment. Background Art

[0002] During the testing of solid state drives (SSDs), since SSDs are widely used in various devices and scenarios, such as personal computers, servers, and embedded systems, different interface types need to be used according to different test scenarios and requirements. For example, personal computers may use SATA interfaces, while servers may use PCIe interfaces, and embedded systems may use U.2 NVMe interfaces. Different interface types have different performance characteristics and application scenarios, so comprehensive testing is required to evaluate the performance of SSDs under different interfaces.

[0003] However, most traditional testing methods use a single interface, such as testing only through a SATA interface or only through a PCIe interface. The limitation of this method is that it cannot comprehensively evaluate the performance of SSDs under different interface types. Since different interface types (such as SATA, PCIe, U.2, etc.) have different performance characteristics and application scenarios, the performance of SSDs under different interfaces may vary greatly. For example, an SSD with a SATA interface may perform well in sequential read and write speeds, but may not achieve its theoretical high bandwidth performance under a PCIe interface.

[0004] Traditional single-interface testing methods cannot reveal these differences and therefore cannot provide users with a comprehensive SSD performance assessment. Summary of the invention

[0005] In view of the above-mentioned technical problems and defects, the purpose of the present invention is to provide a solid-state hard disk performance testing method and related equipment based on multi-interface switching, which can comprehensively evaluate the performance of the solid-state hard disk under different interface types, overcoming the defect that the traditional testing method is limited to a single interface.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present invention provides a solid-state hard disk performance testing method based on multi-interface switching, comprising: determining a target interface combination according to the specification parameters of the solid-state hard disk under test and the interface types supported, and a preset interface configuration library, the target interface combination comprising a first target interface and a second target interface of different types, the interface configuration library comprising a plurality of interface types and corresponding protocol stack configuration parameters; generating an interface switching strategy according to the target interface combination, the interface switching strategy comprising a switching sequence and a residence time of the target interface; based on the interface switching strategy, performing a first performance test on the solid-state hard disk under test through the first target interface to obtain first performance test data; in the first At the end of a performance test, based on the interface switching strategy, the solid-state hard disk under test is subjected to interface switching processing to switch from the first target interface to the second target interface, and the interface switching processing includes reconfiguring the physical layer interface and reloading the protocol stack layer link parameters of the test system; a second performance test is performed on the solid-state hard disk under test through the second target interface to obtain second performance test data; the first performance test data and the second performance test data are aligned to obtain protocol stack interaction characteristic data and physical layer signal quality data of the solid-state hard disk under test; and the performance test result of the solid-state hard disk under test is determined based on the protocol stack interaction characteristic data and the physical layer signal quality data.

[0007] The present invention determines a target interface combination including different types of first target interfaces and second target interfaces according to the specification parameters of the solid-state hard disk under test and the interface types supported, combined with a preset interface configuration library. Then, an interface switching strategy including a switching order and a residence time is generated. Based on the interface switching strategy, a first performance test is first performed through the first target interface to obtain first performance test data. After the first test is completed, an interface switching process is performed, including reconfiguring the physical layer interface and reloading the protocol stack layer link parameters, switching from the first target interface to the second target interface. Then, a second performance test is performed through the second target interface to obtain second performance test data. Finally, the two performance test data are aligned, the protocol stack interaction feature data and the physical layer signal quality data are extracted, and the performance test results of the solid-state hard disk under test are determined based on these data. Through the above steps, the present invention can comprehensively evaluate the performance of the SSD under different interface types, overcoming the defect that the traditional testing method is limited to a single interface.

[0008] In combination with some embodiments of the first aspect, in some embodiments, the first performance test data and the second performance test data are aligned to obtain protocol stack interaction characteristic data and physical layer signal quality data of the solid state drive under test, including: determining a test sequence timestamp based on the operation timing of the first performance test and the second performance test; based on the test sequence timestamp, mapping the first performance test data and the second performance test data to a unified dimensional coordinate system to obtain test performance data coordinates; and aligning the first performance test data and the second performance test data based on the test sequence timestamp and the test performance data coordinates to obtain protocol stack interaction characteristic data and physical layer signal quality data of the solid state drive under test.

[0009] By adopting the technical solution of the above embodiment, the test sequence timestamp is determined according to the operation timing, and the performance test data is mapped to a unified dimensional coordinate system, so that the performance test data under different interfaces are accurately aligned. This alignment process can more accurately extract the protocol stack interaction feature data and the physical layer signal quality data, providing a reliable data basis for subsequent performance analysis. Compared with traditional methods, the alignment process of the present invention is more refined and accurate, which can effectively reduce data alignment errors and improve the credibility of performance test results. In addition, through the mapping of a unified dimensional coordinate system, the performance data under different interfaces can be intuitively compared and analyzed, which helps to discover performance bottlenecks and anomalies in the interface switching process, and provides strong support for the performance optimization of solid-state drives.

[0010] By adopting the technical solution of the above embodiment, by generating an interface compatibility matrix, the attenuation gradient of key performance indicators and firmware adaptation suggestions under different interface combinations can be intuitively displayed. This matrix-form display method provides users with comprehensive performance evaluation information, which helps users quickly understand the performance of solid-state drives under different interface combinations. Compared with traditional methods, the interface compatibility matrix of the present invention is more intuitive and comprehensive, and can effectively improve the efficiency and accuracy of performance evaluation. In addition, the firmware adaptation suggestions in the matrix provide a clear direction for the firmware optimization of the solid-state drive, which helps to improve the performance and stability of the solid-state drive. Through the interface compatibility matrix, users can better perform design optimization, quality control and application selection of solid-state drives, providing strong support for the performance improvement of solid-state drives.

[0011] In combination with some embodiments of the first aspect, in some embodiments, the performance test result of the solid state drive under test is determined based on the protocol stack interaction characteristic data and the physical layer signal quality data, including: generating an interface compatibility matrix based on the protocol stack interaction characteristic data and the physical layer signal quality data, the interface compatibility matrix being marked with key performance indicator attenuation gradients and firmware adaptation suggestions corresponding to the target interface combination; and determining the performance test result based on the interface compatibility matrix.

[0012] By adopting the technical solution of the above embodiment, by generating an interface compatibility matrix, the attenuation gradient of key performance indicators and firmware adaptation suggestions under different interface combinations can be intuitively displayed. This matrix-form display method provides users with comprehensive performance evaluation information, which helps users quickly understand the performance of solid-state drives under different interface combinations. Compared with traditional methods, the interface compatibility matrix of the present invention is more intuitive and comprehensive, and can effectively improve the efficiency and accuracy of performance evaluation. In addition, the firmware adaptation suggestions in the matrix provide a clear direction for the firmware optimization of the solid-state drive, which helps to improve the performance and stability of the solid-state drive. Through the interface compatibility matrix, users can better perform design optimization, quality control and application selection of solid-state drives, providing strong support for the performance improvement of solid-state drives.

[0013] In combination with some embodiments of the first aspect, in some embodiments, an interface compatibility matrix is ​​generated based on the protocol stack interaction characteristic data and the physical layer signal quality data, including: determining the nonlinear coupling relationship between the protocol stack interaction characteristic data and the physical layer signal quality data; calculating the standard deviation of the hard disk performance indicators corresponding to the first target interface and the second target interface under the same test load; marking the interrupt response threshold anomaly points related to the target interface combination in the firmware driver of the solid-state hard disk under test, and the interrupt response threshold anomaly points refer to the data points where the interrupt response time of the solid-state hard disk under test exceeds a preset threshold when processing an interrupt signal; and generating the interface compatibility matrix based on the nonlinear coupling relationship, the standard deviation of the hard disk performance indicators, and the interrupt response threshold anomaly points.

[0014] By adopting the technical solution of the above embodiment, by determining the nonlinear coupling relationship between the protocol stack interaction feature data and the physical layer signal quality data, calculating the standard deviation of the hard disk performance indicators of different interfaces under the same test load, and marking the interrupt response threshold anomalies, a more accurate interface compatibility matrix is ​​generated. This comprehensive analysis method can more comprehensively evaluate the performance of solid-state hard disks under different interface combinations, and provide richer data support for performance optimization. Compared with traditional methods, the interface compatibility matrix of the present invention is more accurate and reliable, and can effectively improve the accuracy and credibility of performance evaluation. In addition, by marking the interrupt response threshold anomalies, the present invention can promptly discover potential problems of solid-state hard disks during interface switching, providing strong support for fault diagnosis and performance improvement of solid-state hard disks.

[0015] In combination with some embodiments of the first aspect, in some embodiments, the interface switching strategy also includes a sequential switching mode, a random switching mode or a concurrent switching mode. The sequential switching mode is used to execute a test cycle in ascending order according to the interface bandwidth, the random switching mode is used to generate a non-fixed order switching sequence based on a Markov chain model, and the concurrent switching mode is used to synchronously activate multiple interface channels through multi-link aggregation technology.

[0016] By adopting the technical solution of the above-mentioned embodiment, by providing a sequential switching mode, a random switching mode and a concurrent switching mode, the interface switching can be flexibly performed according to different test requirements and scenarios. The sequential switching mode executes the test cycle in ascending order according to the interface bandwidth, which can effectively evaluate the performance of the solid-state hard disk under different bandwidth interfaces. The random switching mode generates a switching sequence with a non-fixed order based on the Markov chain model, which can simulate a more realistic usage scenario and improve the comprehensiveness and reliability of the test. The concurrent switching mode synchronously activates multiple interface channels through multi-link aggregation technology, which can make full use of the multi-interface capabilities of the solid-state hard disk and improve test efficiency and data throughput. Compared with traditional methods, the interface switching strategy of the present invention is more flexible and diverse, can meet different test requirements, and improve the accuracy and comprehensiveness of performance testing.

[0017] In combination with some embodiments of the first aspect, in some embodiments, the reconfiguration of the physical layer interface includes: compensating in real time, through a preset adaptive impedance matching module, for signal reflection loss generated when the first target interface is switched to the second target interface.

[0018] By adopting the technical solution of the above-mentioned embodiment, the signal reflection loss is compensated in real time during the interface switching process through a preset adaptive impedance matching module, thereby ensuring the stability and reliability of signal transmission. This real-time compensation mechanism can effectively reduce signal distortion and transmission errors during the interface switching process, and improve the accuracy and reliability of performance testing. Compared with traditional methods, the adaptive impedance matching module of the present invention is more intelligent and efficient, and can automatically adapt to the impedance characteristics of different interfaces to ensure the stability of signal transmission. In addition, by compensating for signal reflection loss in real time, the present invention can effectively improve the performance of solid-state hard disks under different interface combinations, and provide strong support for the performance optimization of solid-state hard disks.

[0019] In combination with some embodiments of the first aspect, in some embodiments, the reloading of the protocol stack layer link parameters of the test system includes: predicting the optimal link parameter combination of the communication link between the test system and the solid-state drive under test through a link parameter configuration model, and reloading the optimal link parameter combination at the protocol stack layer of the test system, wherein the link parameter configuration model is a pre-trained machine learning model.

[0020] By adopting the technical solution of the above embodiment, the optimal link parameter combination of the communication link between the test system and the solid-state hard disk is predicted through the link parameter configuration model, and these parameters are reloaded at the protocol stack layer of the test system. This link parameter optimization method based on machine learning can automatically adjust the link parameters according to different test environments and interface combinations, thereby improving the performance and stability of the communication link. Compared with the traditional method, the link parameter configuration model of the present invention is more intelligent and efficient, and can effectively improve the optimization accuracy and adaptability of the link parameters. In addition, by reloading the optimal link parameter combination, the present invention can significantly improve the performance of the solid-state hard disk under different interface combinations, providing strong support for the performance optimization of the solid-state hard disk.

[0021] In a second aspect, an embodiment of the present invention provides an electronic device, comprising: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to enable the electronic device to execute the method described in the first aspect or the second aspect, and any possible implementation method of the first aspect or the second aspect.

[0022] In a third aspect, the present invention provides a computer-readable storage medium comprising instructions, which, when executed on the electronic device, causes the electronic device to execute the method described in the first aspect or the second aspect, and any possible implementation of the first aspect or the second aspect.

[0023] In a fourth aspect, the present invention provides a computer program product comprising instructions, which, when the computer program product is run on the electronic device, enables the electronic device to execute the method described in the first aspect or the second aspect, and any possible implementation of the first aspect or the second aspect.

[0024] It is understandable that the electronic device provided in the second aspect, the storage medium provided in the third aspect, and the computer program product provided in the fourth aspect are all used to execute the method provided in the present invention. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method, which will not be repeated here.

[0025] One or more technical solutions provided by the present invention have at least the following technical effects or advantages:

[0026] 1. Comprehensive performance testing of multi-interface switching: The present invention determines the target interface combination and generates an interface switching strategy based on the specification parameters of the SSD under test and the interface types supported, thereby achieving comprehensive performance testing of SSDs under different interface types. This method breaks through the limitation of traditional testing methods that are limited to a single interface, and can more accurately evaluate the performance of SSDs in actual applications, providing more comprehensive test data support for the design optimization, quality control and application selection of SSDs.

[0027] 2. Improve the accuracy of performance test results: By aligning the performance test data after interface switching and extracting the protocol stack interaction feature data and physical layer signal quality data, the present invention can more accurately analyze the performance of the solid-state drive under different interface combinations. In addition, the interface compatibility matrix is ​​generated, and the key performance indicator attenuation gradient and firmware adaptation suggestions are marked, which further improves the accuracy and reliability of the performance test results and provides more powerful support for the performance evaluation and optimization of solid-state drives.

[0028] 3. Improve fault diagnosis and performance optimization capabilities: The present invention realizes cross-protocol stack anomaly propagation analysis by implanting probe units in each layer of the protocol stack, capturing cross-layer correlation data, and constructing an anomaly propagation model based on a Bayesian network. This enables rapid tracing and identification of cross-layer error conduction paths when anomalies occur in different interface protocol layers, establishes an anomaly correlation map of a multi-level protocol stack, and realizes root location from bit error phenomena to firmware defects. This greatly improves the fault diagnosis and performance optimization capabilities of solid-state drives, and helps to improve the reliability and stability of solid-state drives. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0030] Figure 1 is a flow chart of a solid state drive performance testing method based on multi-interface switching according to an embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of the architecture of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The terms used in the following embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to be limiting of the present invention. As used in the specification of the present invention, the singular expressions "a", "a", "above", "the" and "this" are intended to also include plural expressions, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present invention refers to any or all possible combinations comprising one or more of the listed items.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0034] It should also be noted that, unless otherwise clearly specified and limited, in the embodiments of the present invention, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components; it can be a wired communication connection or a wireless communication connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. The embodiments of the present invention are described in detail below.

[0035] The embodiment of the present invention provides a solid-state hard disk performance test method based on multi-interface switching. According to the specification parameters of the solid-state hard disk under test and the interface types supported, combined with the preset interface configuration library, a target interface combination including different types of first target interfaces and second target interfaces is determined. Then, an interface switching strategy including a switching order and a residence time is generated. Based on the interface switching strategy, a first performance test is first performed through the first target interface to obtain first performance test data. After the first test is completed, an interface switching process is performed, including reconfiguring the physical layer interface and reloading the protocol stack layer link parameters, switching from the first target interface to the second target interface. Then, a second performance test is performed through the second target interface to obtain second performance test data. Finally, the two performance test data are aligned, the protocol stack interaction feature data and the physical layer signal quality data are extracted, and the performance test results of the solid-state hard disk under test are determined based on these data. Through the above scheme, the embodiment of the present invention can comprehensively evaluate the performance of the SSD under different interface types, overcoming the defect that the traditional test method is limited to a single interface.

[0036] Combine the following Figure 1To illustrate the method of explaining this embodiment, it specifically includes the following steps:

[0037] Step 201 : determining a target interface combination according to the specification parameters and supported interface types of the solid state drive under test and a preset interface configuration library.

[0038] The target interface combination includes a first target interface and a second target interface of different types, and the interface configuration library includes a plurality of interface types and corresponding protocol stack configuration parameters.

[0039] The specification parameters of the solid-state drive include but are not limited to the capacity, flash type, performance indicators, etc. of the SSD. The interface types include but are not limited to SATA, PCIe, and U.2 NVMe interfaces. Protocol stack configuration parameters refer to the configuration parameters used by each layer of the protocol in the network protocol stack. These parameters define the format, rules, and behavior of data when it is transmitted in the network. For example, in the TCP / IP protocol stack, the TCP protocol configuration parameters of the transport layer may include port number, window size, timeout retransmission time, etc.; the IP protocol configuration parameters of the network layer may include IP address, subnet mask, default gateway, etc. These parameters jointly determine the transmission efficiency, reliability, and security of data in the network. In the test process of the solid-state drive (SSD), the correct setting of the protocol stack configuration parameters is crucial to ensure accurate data transmission and performance evaluation under different interfaces.

[0040] Specifically in this step, the test system will refer to the preset interface configuration library, which contains a variety of interface types and their corresponding protocol stack configuration parameters. Based on this information, the test system determines the target interface combination, which includes a first target interface and a second target interface of different types. For example, if the SSD supports SATA and PCIe interfaces, the test system may select SATA as the first target interface and PCIe as the second target interface. The protocol stack configuration parameters in the interface configuration library provide the necessary basis for subsequent interface switching and testing.

[0041] In this embodiment, the process of building an interface configuration library includes the following:

[0042] Collect interface types: First, determine the mainstream SSD interface types on the market, such as SATA, PCIe, and U.2 NVMe interfaces. These interface types are the basis for building an interface configuration library, and you need to have an in-depth understanding of the characteristics, application scenarios, and performance features of each interface.

[0043] Define protocol stack configuration parameters: For each interface type, define the corresponding protocol stack configuration parameters in detail. These parameters include but are not limited to data transmission rate, signal encoding method, clock synchronization mechanism, power management parameters, etc. For example, for a PCIe interface, the protocol stack configuration parameters may include data transmission rate (such as 16GT / s), signal encoding method (such as 128b / 130b encoding), clock synchronization mechanism (such as symbol-based clock data recovery), etc.

[0044] Establish parameter mapping relationship: Establish mapping relationship between each interface type and its corresponding protocol stack configuration parameters to form a clear parameter table. This parameter table will serve as the core content of the interface configuration library and guide the configuration and testing of the test system in different interface environments.

[0045] Verify parameter accuracy: Ensure that the parameters in the interface configuration library are accurate through actual testing and verification. Use professional testing equipment and tools to perform performance tests on SSDs with different interface types to verify the actual effects of protocol stack configuration parameters. If inaccurate or abnormal parameters are found, make adjustments and optimizations in a timely manner.

[0046] Continuous update and maintenance: With the continuous development of SSD technology and the emergence of new interface types, the interface configuration library needs to be continuously updated and maintained. New interface types and protocol stack configuration parameters are regularly collected and incorporated into the interface configuration library to ensure the integrity and timeliness of the interface configuration library. At the same time, the existing parameters are regularly reviewed and optimized to adapt to the ever-changing test requirements and technical environment.

[0047] Step 202: Generate an interface switching strategy according to the target interface combination, where the interface switching strategy includes a switching sequence and a residence time of the target interface.

[0048] Specifically, first, collect the basic parameters and characteristics of each interface in the target interface combination, such as bandwidth, latency, power consumption, etc. Then, determine the priority and order of interface switching based on the specifications and application scenario requirements of the solid-state drive (SSD) being tested. For example, if the SSD needs to be tested for high bandwidth and low latency performance, it can be switched to the PCIe interface first, then to the NVMe interface, and finally to the SATA interface.

[0049] Next, determine the dwell time of each interface based on the total test duration and the test requirements of each interface. The dwell time should be long enough to ensure that the performance of the SSD under the interface can be fully tested, while also considering the time efficiency of the entire test process. The generation of the interface switching strategy also needs to consider the compatibility and switching cost between interfaces to avoid affecting the accuracy and reliability of the test results due to frequent switching or unreasonable switching order.

[0050] Finally, through comprehensive analysis and optimization, a reasonable interface switching strategy is formulated to guide the subsequent multi-interface performance testing.

[0051] In some embodiments, the interface switching strategy further includes a sequential switching mode, a random switching mode, or a concurrent switching mode.

[0052] Among them, the sequential switching mode means that the interfaces are arranged in ascending order according to their bandwidth, and each interface is tested in a cycle. For example, for the SSD performance test of SATA, PCIe, and U.2 interfaces, the SATA interface is tested first, then the PCIe interface is tested, and finally the U.2 interface is tested. The sequential switching mode can evaluate the performance of different interface types in sequence, which is convenient for comparing and analyzing the performance of SSDs at different bandwidths one by one.

[0053] The random switching mode is used to generate a non-fixed order switching sequence based on the Markov chain model. Among them, the Markov chain is a random process, and its future state depends only on the current state and has nothing to do with the past state. In interface switching, the random switching mode can simulate a more realistic network environment and user behavior, because the switching order of interfaces in actual use is often unpredictable. For example, during the test, the interface may randomly switch from SATA to PCIe, then switch back to SATA, or switch to the U.2 interface, etc. Through the random switching mode, the performance and stability of the SSD under different interface switching sequences can be more comprehensively evaluated.

[0054] Concurrent switching mode is used to synchronously activate multiple interface channels through multi-link aggregation technology. Among them, multi-link aggregation technology can logically merge multiple physical interfaces into one high-speed link to improve the bandwidth and reliability of data transmission. In SSD performance testing, through concurrent switching mode, multiple interfaces can be used for data transmission at the same time, thereby improving test efficiency and data throughput. For example, when large-scale data write testing is required, SATA and PCIe interfaces can be used for data transmission at the same time through concurrent switching mode to speed up the test and fully utilize the performance potential of SSD. This mode is suitable for application scenarios that require high bandwidth and low latency, such as large data centers, high-performance computing, etc.

[0055] Step 203: Based on the interface switching strategy, a first performance test is performed on the solid state drive under test through the first target interface to obtain first performance test data.

[0056] Specifically, the test system first obtains the protocol stack configuration parameters corresponding to the first target interface type from the interface configuration library. These parameters include key information such as data transmission rate, signal encoding method, and clock synchronization mechanism. Then, the test system loads these configuration parameters into the programmable interface adapter, and the programmable interface adapter adjusts its own hardware and software resources according to these parameters to ensure seamless docking with the first target interface of the solid-state drive (SSD) under test. For example, if the first target interface is SATA, the adapter will adjust its signal transmission rate and voltage level to match the standard requirements of the SATA interface; if the first target interface is PCIe, the adapter will adjust to the configuration of the PCIe interface accordingly. Through this initialization configuration, the test system can ensure that in subsequent performance tests, data can be accurately and efficiently transmitted between the test system and the SSD, thereby laying the foundation for obtaining reliable performance test data.

[0057] Next, the test system sends test instructions, such as read and write operations, random access, etc., to the SSD through the first target interface according to the preset test process and parameters, and records the corresponding performance data, such as read and write speed, IOPS, latency, etc. These performance data constitute the first performance test data, which provides a basis for subsequent analysis and evaluation.

[0058] During this test process, the test system will follow the residence time specified in the interface switching strategy to ensure the adequacy and effectiveness of the test.

[0059] Step 204, when the first performance test ends, based on the interface switching strategy, perform interface switching processing on the solid state drive under test to switch from the first target interface to the second target interface.

[0060] The interface switching process includes reconfiguring the physical layer interface and reloading the protocol stack layer link parameters of the test system. Protocol stack layer link parameters refer to the configuration parameters used by the link layer in the network protocol stack, which define the rules and characteristics of data transmission on the physical medium. Specifically, the protocol stack layer link parameters include but are not limited to data transmission rate, signal encoding method, clock synchronization mechanism, frame format, error detection and correction algorithm, etc. For example, in the Ethernet protocol stack, the link parameters of the link layer may include data transmission rate (such as 100 Mbps, 1 Gbps, etc.), signal encoding method (such as Manchester encoding, 4B / 5B encoding, etc.), clock synchronization mechanism (such as clock signal-based synchronization or adaptive clock recovery, etc.). These parameters jointly determine the efficiency, reliability and compatibility of data transmission at the physical layer. In the test process of solid-state drives (SSDs), correctly configuring the protocol stack layer link parameters is crucial to ensure accurate data transmission and performance evaluation under different interfaces.

[0061] In this step, the test system performs interface switching on the SSD under test according to the previously set interface switching strategy. This process is specifically divided into two key steps: First, reconfigure the physical layer interface. This means adjusting the physical connection and electrical characteristics between the SSD and the test system, such as changing the signal transmission rate, voltage level, or physical connection method to ensure that the SSD can adapt to the new interface type. Second, reload the protocol stack layer link parameters of the test system. This involves updating the protocol stack configuration corresponding to the new interface type, including but not limited to data transmission rate, signal encoding method, clock synchronization mechanism, etc., to ensure that data can be transmitted stably and efficiently in the new interface environment.

[0062] Through these two steps, the test system can smoothly switch from the first target interface to the second target interface, preparing for subsequent performance testing, thereby achieving a comprehensive performance evaluation of the SSD under different interface types.

[0063] In this step, reconfiguring the physical layer interface may include: compensating in real time, through a preset adaptive impedance matching module, for a signal reflection loss generated when the first target interface is switched to the second target interface.

[0064] In this embodiment, when performing interface switching, reconfiguring the physical layer interface is a key step, which ensures the stability and reliability of signal transmission. Specifically, when switching from the first target interface to the second target interface, due to the differences in the physical characteristics of different interfaces (such as impedance, signal transmission rate, etc.), signal reflection loss may occur. In order to compensate for this loss, the test system performs real-time adjustments through a preset adaptive impedance matching module. The adaptive impedance matching module can automatically adjust its impedance value according to the characteristics of the second target interface to match the electrical characteristics of the interface.

[0065] This process involves precise control of the impedance in the signal transmission path, and dynamically adjusting the impedance matching parameters by monitoring the reflection and transmission of the signal. For example, when switching from the SATA interface to the PCIe interface, the adaptive impedance matching module will adjust its impedance value in real time according to the higher signal transmission rate and different impedance requirements of the PCIe interface to reduce signal reflection and ensure signal integrity and transmission efficiency.

[0066] Through this real-time compensation mechanism, the test system can effectively deal with signal transmission problems that may occur during interface switching, thereby ensuring the accuracy and reliability of the test.

[0067] Among them, the adaptive impedance matching module is equipped with advanced sensors and monitoring circuits, which can keenly perceive the physical characteristics of the solid-state drive (SSD) during the interface switching process. When the first target interface switches to the second target interface, the module starts working immediately, scanning the impedance change value of the SSD signal output port and the test system interface port in real time. For example, when switching to the PCIe interface, the sensor will quickly read the electrical signals emitted by the SSD, including voltage and current fluctuations, and convert these signals into digital data streams for subsequent analysis.

[0068] Based on the collected impedance data, the adaptive impedance matching module will quickly start the preset algorithm program to analyze the data. It first performs noise reduction on the data to remove error data caused by environmental interference. Then, it uses statistical methods such as linear regression to predict the ideal matching impedance value. At the same time, the influence of signal frequency is also considered, because signals of different frequencies have different requirements for impedance. For example, for high-frequency signals, lower impedance is usually required to reduce signal attenuation and distortion.

[0069] According to the calculated ideal impedance value, the adaptive impedance matching module dynamically changes the parameters of the variable resistors, capacitors, and inductors to achieve impedance matching. The adjustment of these components is done through the micro-electromechanical system (MEMS) inside the module, which can accurately adjust the physical size or connection method of the components. For example, when the impedance needs to be increased, MEMS can achieve it by increasing the dielectric thickness of the capacitor or changing the number of turns of the inductor coil. This dynamic adjustment process is completed almost instantly, and the impedance matching can be completed in advance before the signal reflection occurs, thereby effectively compensating for the signal reflection loss caused by interface switching.

[0070] During the entire impedance matching process, the adaptive impedance matching module also sets up a feedback mechanism. After adjusting the impedance element, it will monitor the signal transmission again, and evaluate the effect of impedance matching by comparing the signal quality before and after adjustment. If the effect is not ideal, such as signal reflection still exists, the module will adjust the component parameters again and perform multiple iterative optimizations until the optimal impedance matching state is achieved. At the same time, the module will also record the adjustment data for each time to form an optimization database. In future interface switching, when encountering similar impedance change trends, the module can quickly call the data in the database and pre-set the impedance matching parameters, thereby further improving the efficiency and accuracy of signal reflection compensation.

[0071] In some embodiments, reloading the protocol stack layer link parameters of the test system may include: predicting the optimal link parameter combination of the communication link between the test system and the solid-state drive under test through a link parameter configuration model, and reloading the optimal link parameter combination at the protocol stack layer of the test system, wherein the link parameter configuration model is a pre-trained machine learning model.

[0072] Specifically, this process involves using a pre-trained machine learning model, the link parameter configuration model, to predict the optimal link parameter combination. The link parameter configuration model is based on a large amount of historical data and real-time test environment information, and through complex algorithm analysis, it predicts the optimal configuration of the communication link between the test system and the SSD in the current test scenario. These parameters may include data transmission rate, signal encoding method, clock synchronization mechanism, etc., which have an important impact on the performance of the communication link.

[0073] After predicting the optimal link parameter combination, the test system will reload these parameters in its protocol stack layer to achieve the best communication effect with the SSD. For example, if the model predicts that a certain signal encoding method and data transmission rate can achieve the best communication performance under the current test environment, the test system will adjust the configuration of its protocol stack layer accordingly to match these optimal parameters.

[0074] In this way, the test system can dynamically adapt to different test requirements and environmental changes, ensuring efficient and stable communication with the SSD under various conditions, thereby improving the accuracy and reliability of the test.

[0075] The construction and training process of the link parameter configuration model in this embodiment is as follows:

[0076] (1) Data collection and preprocessing: First, a large amount of interface switching data under a real test environment needs to be collected. This data includes different interface types (such as SATA, PCIe, U.2, etc.), protocol stack parameter settings, such as data transmission rate, signal encoding method, clock synchronization mechanism, etc., as well as actual measured physical layer signal quality data, such as signal strength, noise level, bit error rate, etc., and link performance indicators such as throughput, delay, packet loss rate, etc. Data collection can be achieved through sensors and monitoring tools in the test system. The collected data needs to undergo strict preprocessing, including noise removal, missing value filling, data normalization, etc., to ensure data quality and consistency. Then add labels to these data samples. These labels usually represent the optimal link parameter combination for the communication link between the test system and the SSD under a specific test environment.

[0077] (2) Model architecture design: Select an appropriate machine learning model architecture based on the nature of the problem and the characteristics of the data. For the link parameter configuration model, traditional machine learning models such as decision trees, random forests, support vector machines (SVMs), etc., or neural network models based on deep learning may be used. Traditional machine learning models have advantages in feature engineering and can clearly understand the relationship between features and targets. They are suitable for scenarios with high feature interpretability. Deep learning models perform well in processing high-dimensional and nonlinear data, can automatically learn complex feature representations, and are suitable for large-scale and complex data sets. The design of the model architecture needs to comprehensively consider factors such as the accuracy, interpretability, and computational complexity of the model.

[0078] (3) Select model algorithm: Determine the specific model algorithm based on the model architecture. For example, if a decision tree model is selected, you can use the Splitting algorithm based on information gain or Gini index; if a neural network model is selected, you need to determine the number of network layers, the number of neurons in each layer, the activation function, the loss function, etc. The choice of algorithm needs to be weighed based on the characteristics of the experimental data and the model objectives. For example, for classification problems, you can choose algorithms such as logistic regression and support vector machines; for regression problems, you can choose algorithms such as linear regression and ridge regression.

[0079] (4) Training model: Input the preprocessed data into the model for training. During the training process, the model will automatically adjust the parameters according to the characteristics and labels of the data to minimize the loss function. The loss function defines the difference between the model's predicted value and the true value. Common loss functions include mean square error (MSE), cross entropy loss, etc. Model training usually uses iterative optimization algorithms such as gradient descent, stochastic gradient descent (SGD), Adagrad, Adam, etc. During the training process, regularization techniques (such as L1 regularization and L2 regularization) can be used to prevent model overfitting and improve the generalization ability of the model.

[0080] (5) Model evaluation and optimization: After training is completed, the performance of the model needs to be evaluated. Evaluation indicators can be selected according to the type of problem, such as accuracy, precision, recall, F1 score, etc. for classification problems; root mean square error (RMSE), mean absolute error (MAE), etc. for regression problems. In order to ensure the reliability and robustness of the model, cross-validation techniques (such as k-fold cross-validation) are usually used to evaluate the performance of the model. If the performance of the model is not ideal, it can be optimized by adjusting model parameters, increasing the amount of training data, optimizing algorithms, etc. to improve the prediction performance of the model.

[0081] Through the above process, an effective link parameter configuration model can be constructed. The model can predict the optimal link parameter combination based on the input test system and SSD related parameters, thereby achieving high-speed and stable communication link configuration and providing strong support for the performance testing of SSDs.

[0082] Step 205: Perform a second performance test on the solid state drive under test through the second target interface to obtain second performance test data.

[0083] Specifically, after completing the interface switching process, the test system performs a second performance test on the solid-state drive (SSD) under test through the second target interface. This process first involves the initialization and configuration of the second target interface to ensure that its physical layer and protocol stack layer parameters match the SSD. Then, the test system sends test instructions such as read and write operations, random access, etc. to the SSD through the second target interface according to the preset test process and parameters, and records the corresponding performance data, such as read and write speed, IOPS (input / output times per second), latency, etc. These performance data constitute the second performance test data, which provides a basis for subsequent analysis and evaluation.

[0084] During the test, the test system will follow the residence time specified in the interface switching strategy to ensure the adequacy and effectiveness of the test. Through the second performance test, the performance of the SSD under the second target interface can be fully evaluated, providing an important basis for subsequent performance analysis and optimization.

[0085] In some embodiments, after the interface switching is completed, when the second performance test is performed, the test system automatically injects a test load sequence that matches the current interface bandwidth, wherein the test load sequence includes a pre-configured read-write mix ratio and queue depth combination.

[0086] The test system will select a suitable sequence from the preset test load sequence library according to the bandwidth and characteristics of the current interface, or generate a test load that meets the current interface conditions in real time through an algorithm. For example, if the current interface is PCIe with a high bandwidth, the test system will inject a test load sequence with a high queue depth and a large read-write ratio to fully test the high bandwidth and low latency characteristics of the PCIe interface. This automatic injection mechanism ensures that the SSD can be fully and accurately tested in different interface environments, thereby obtaining reliable test results.

[0087] The test load sequence is pre-configured and contains a specific read-write mix ratio and queue depth combination. The read-write mix ratio determines the relative ratio of read operations and write operations during the test, such as 70% read operations and 30% write operations, or 50% read operations and 50% write operations. The queue depth indicates the number of read and write operations performed simultaneously, for example, a queue depth of 32 means 32 read and write operations are performed simultaneously.

[0088] By automatically injecting a test load sequence that matches the current interface bandwidth, the test system can ensure that the SSD can be fully and accurately tested under different interface environments, thereby obtaining reliable test results. This allows the performance of the SSD to be fully evaluated under various interface combinations and load conditions, providing strong support for subsequent performance analysis and optimization.

[0089] Step 206: align the first performance test data with the second performance test data to obtain protocol stack interaction feature data and physical layer signal quality data of the solid state drive under test.

[0090] Specifically, this step first involves the alignment of the time dimension, by establishing a timestamp synchronization mechanism across interfaces to ensure that the test events in the two data sets (the first performance test data and the second performance test data) can be matched in the order in which they actually occurred. For example, if a specific data packet size and transfer time are recorded in a read and write test under the first target interface (such as SATA), and a similar test is performed under the second target interface (such as PCIe), the test system will align these events based on the timestamps to compare the performance of the same or similar test operations under different interfaces.

[0091] Next, the test system will align the spatial dimensions and map the test data under different physical interfaces to a unified dimensional coordinate system by constructing a virtualized test scene space. This means that no matter whether the data is collected under the SATA interface or the PCIe interface, they will be converted to the same coordinate system for spatial comparison and analysis. Among them, the virtualized test scene space is a virtual environment created by software simulation or mathematical transformation, which is used to map the test data under different physical interfaces (i.e., the first performance test data and the second performance test data) to a unified dimensional coordinate system for spatial comparison and analysis.

[0092] Through this time-space alignment processing, the test system can extract the protocol stack interaction feature data, which includes the size of the data packet, the sending frequency, the number of retransmissions, etc. These data reflect the interaction between the protocol layers. At the same time, the test system can also extract the physical layer signal quality data, which includes the signal amplitude, frequency, noise level, etc. These data reflect the transmission quality of the physical layer signal.

[0093] By comprehensively analyzing these aligned data, the test system can obtain more accurate performance evaluation results, providing strong support for subsequent performance analysis and optimization.

[0094] Step 207: Determine the performance test result of the solid state drive under test according to the protocol stack interaction characteristic data and the physical layer signal quality data.

[0095] Specifically, based on the protocol stack interaction characteristic data and the physical layer signal quality data, the test system comprehensively evaluates the performance of the solid-state drive (SSD) under test to determine its performance test results. This process first involves the analysis of the protocol stack interaction characteristic data, such as the size of the data packet, the sending frequency, the number of retransmissions, etc., which reflect the interaction between the protocol layers. For example, a higher number of retransmissions may indicate compatibility issues in the protocol layer or unstable data transmission. Next, the test system evaluates the physical layer signal quality data, such as the signal amplitude, frequency, noise level, etc., which reflect the transmission quality of the physical layer signal. For example, a lower signal amplitude or a higher noise level may indicate that there are signal interference or transmission loss problems in the physical layer.

[0096] By comprehensively analyzing these data, the test system can determine the performance of SSDs under different interface types, such as read and write speeds, IOPS (input / output times per second), latency and other key performance indicators. Finally, the test system gives a comprehensive performance test result based on these analysis results, providing a scientific basis for SSD design optimization, quality control and application selection.

[0097] The hard disk performance test results of this embodiment cover multiple key performance indicators. First, the test results will clearly indicate the specific values ​​of the core performance indicators such as the read and write speed, IOPS (input / output times per second), and latency of the SSD under different interface combinations. These values ​​can intuitively reflect the performance differences of the SSD under various interface environments by comparing the performance under different interfaces. Secondly, the test results will also include protocol stack interaction feature data, which reveals the interaction between protocol layers, such as the size of data packets, the sending frequency, the number of retransmissions, etc., and provide an important basis for understanding the performance of the SSD at the protocol level. In addition, the physical layer signal quality data is also part of the test results, including the amplitude, frequency, noise level, etc. of the signal, which reflect the transmission quality of the physical layer signal. Finally, the test results will mark the attenuation gradient of key performance indicators and firmware adaptation suggestions through the interface compatibility matrix, providing a scientific basis for the design optimization, quality control and application selection of the SSD.

[0098] Through the above steps, this embodiment can comprehensively evaluate the performance of the SSD under different interface types, overcoming the defect that the traditional test method is limited to a single interface. By determining the target interface combination and generating an interface switching strategy, the interface switching situation in the real application scenario can be simulated, so as to more accurately evaluate the performance of the SSD. Secondly, through the precise control of the interface switching strategy, the automation and efficiency of the performance test of the SSD under different interfaces are realized. The data of the first performance test and the second performance test can be aligned to obtain the protocol stack interaction feature data and the physical layer signal quality data, which provides rich data support for in-depth analysis of the performance of the SSD. Finally, the performance test results determined according to the protocol stack interaction feature data and the physical layer signal quality data can provide a scientific basis for the design optimization, quality control and application selection of the SSD, which is helpful to improve the performance and reliability of the SSD and meet the needs of different application scenarios. This embodiment has advantages in comprehensiveness, automation, efficiency and data analysis depth, and can effectively improve the accuracy and practicality of the SSD performance test.

[0099] In one embodiment, step 206 specifically includes:

[0100] S2061, determining a test sequence timestamp according to the operation timing of the first performance test and the second performance test.

[0101] The operation timing refers to the execution order and time interval of each test operation (such as read and write operations, random access, etc.) during the performance test. The test system will accurately record the start time, end time, and duration of each test operation. This time information is crucial for determining the test sequence timestamp. For example, in the first performance test, the test system recorded the timestamps of a series of read and write operations performed under the SATA interface; in the second performance test, the timestamps of similar operations performed under the PCIe interface were recorded.

[0102] By comparing and analyzing these timestamps, the test system can determine the operation timing relationship between the two tests and provide a time reference for subsequent data alignment. Specifically, the test system will synchronize and align the timestamps of the two tests based on the operation timing to ensure that the timestamps of the same test operation under different interfaces can accurately correspond. This process needs to consider factors such as the stability of the test environment and the clock accuracy of the test equipment to ensure the accuracy and reliability of the timestamp. Accurate test sequence timestamps are the basis for data alignment and performance analysis. It can help testers better understand the time characteristics of test data and thus more accurately evaluate the performance of SSDs.

[0103] S2062: Based on the test sequence timestamp, map the first performance test data and the second performance test data to a unified dimensional coordinate system to obtain test performance data coordinates.

[0104] Specifically, based on the determined test sequence timestamp, the test system maps the first performance test data and the second performance test data to a unified dimensional coordinate system to obtain the test performance data coordinates. This process first involves extracting and analyzing the features of the two performance test data. Performance test data usually includes a variety of performance indicators, such as read and write speed, IOPS (input / output times per second), latency, etc. The test system will select a suitable dimensional coordinate system for mapping based on the characteristics of these performance indicators. For example, you can select a coordinate system with time as the horizontal axis and read and write speed as the vertical axis, and map the data points of the two tests into this coordinate system.

[0105] In this way, the performance of SSDs under different interfaces can be intuitively compared. During the mapping process, the test system will accurately place each test data point in the corresponding position in the unified dimensional coordinate system according to the test sequence timestamp. For example, a read or write operation data point under the SATA interface will be mapped to a specific position in the coordinate system according to its timestamp and read or write speed; similarly, the data point under the PCIe interface will also be mapped according to the corresponding timestamp and read or write speed.

[0106] By mapping the data of the two performance tests to a unified dimensional coordinate system, the test system can more intuitively display and compare the performance data under different interfaces, providing strong support for subsequent alignment processing and performance analysis.

[0107] S2063, aligning the first performance test data with the second performance test data according to the test sequence timestamp and the test performance data coordinates, to obtain protocol stack interaction feature data and physical layer signal quality data of the solid state drive under test.

[0108] This step involves the alignment of the two performance test data. Alignment refers to matching and aligning the data points of the two tests according to the timestamp and performance data coordinates to ensure that the data at the same time point or the same performance level can accurately correspond. For example, a certain read and write operation data point under the SATA interface will be aligned with the corresponding data point under the PCIe interface according to its timestamp and read and write speed. Through the alignment process, the test system can more accurately compare and analyze the performance data under different interfaces.

[0109] After alignment, the test system will further extract protocol stack interaction feature data and physical layer signal quality data. Protocol stack interaction feature data includes data packet size, transmission frequency, number of retransmissions, etc. These data reflect the interaction between protocol layers.

[0110] The physical layer signal quality data includes signal amplitude, frequency, noise level, etc. These data reflect the transmission quality of the physical layer signal. By extracting these data, the test system can more comprehensively evaluate the performance of the solid state drive under different interfaces, providing an important basis for subsequent performance analysis and optimization.

[0111] In some embodiments, step 207 may specifically include:

[0112] S2071: Generate an interface compatibility matrix according to the protocol stack interaction feature data and the physical layer signal quality data.

[0113] Among them, the interface compatibility matrix is ​​a tool for evaluating the performance of different interface combinations. It combines the protocol stack interaction feature data and the physical layer signal quality data, and marks the key performance indicator attenuation gradient and firmware adaptation suggestions corresponding to the target interface combination. Through the interface compatibility matrix, you can intuitively understand the performance differences and compatibility issues of different interface combinations, providing a scientific basis for the design optimization, quality control and application selection of solid-state drives.

[0114] Specifically, the protocol stack interaction feature data is first analyzed to extract key features, such as packet size, transmission frequency, number of retransmissions, etc. These features reflect the interaction between protocol layers. Next, the physical layer signal quality data is evaluated to extract key indicators, such as signal amplitude, frequency, noise level, etc. These indicators reflect the transmission quality of physical layer signals. Then, these key features and indicators are combined to evaluate the performance under different interface combinations. For example, by comparing key performance indicators such as read and write speed, IOPS (input / output times per second), and latency under different interface combinations, the attenuation gradients of these indicators under different interface combinations are determined. At the same time, based on the analysis results of the protocol stack interaction feature data and the physical layer signal quality data, firmware adaptation suggestions are proposed, such as optimizing protocol stack parameters and updating firmware versions. Finally, these evaluation results and suggestions are integrated into the interface compatibility matrix, and the key performance indicator attenuation gradients and firmware adaptation suggestions corresponding to the target interface combination are marked.

[0115] In this way, the interface compatibility matrix can intuitively display the performance differences and compatibility issues of different interface combinations, providing a scientific basis for SSD design optimization, quality control, and application selection.

[0116] In some embodiments, this step may specifically include the following:

[0117] (1) Determine the nonlinear coupling relationship between the protocol stack interaction characteristic data and the physical layer signal quality data.

[0118] In this embodiment, by collecting protocol stack interaction feature data and physical layer signal quality data, mathematical methods and algorithms such as correlation analysis and regression analysis are used to study the nonlinear coupling phenomenon between the two, and establish a mathematical model or function that can describe this complex relationship, thereby revealing the specific impact of protocol stack parameter changes on the physical layer signal quality. The degree and degree of influence.

[0119] Specifically, first collect a large amount of protocol stack interaction feature data and physical layer signal quality data, which should cover different interface types, different test loads and different working conditions. Then, use mathematical and statistical methods, such as correlation analysis, regression analysis, principal component analysis, etc., to process and analyze these data to reveal the intrinsic connection between the two. For example, a multivariate linear regression model can be used to fit the relationship between the protocol stack interaction feature data and the physical layer signal quality data, and the coefficients and significance tests of the model can be used to determine whether there is a nonlinear coupling relationship.

[0120] In addition, machine learning algorithms, such as neural networks and support vector machines, can be used to train and model data to more accurately capture nonlinear coupling relationships. In the modeling process, data preprocessing, such as normalization and denoising, is required to improve the accuracy and generalization ability of the model.

[0121] Through these steps, the nonlinear coupling relationship between the protocol stack interaction feature data and the physical layer signal quality data can be determined, providing a basis for subsequent performance evaluation and optimization.

[0122] (2) Calculate the standard deviation of the hard disk performance indicators corresponding to the first target interface and the second target interface under the same test load.

[0123] Specifically, under the same test load conditions, multiple performance tests are performed on the first target interface and the second target interface, and various performance indicators (such as read and write speed, IOPS, latency, etc.) are recorded. Then, these data are statistically analyzed to calculate the average and standard deviation of each interface performance indicator. The standard deviation reflects the fluctuation of the performance indicator. The larger the standard deviation, the worse the stability of the hard disk performance indicator and the more obvious the performance difference between different interfaces.

[0124] (3) Mark the interrupt response threshold abnormal points related to the target interface combination in the firmware driver of the solid-state drive under test.

[0125] The interrupt response threshold abnormal point refers to a data point at which the interrupt response time of the solid state drive under test exceeds a preset threshold when processing an interrupt signal.

[0126] During the test, the interrupt response time of the SSD under test is monitored and compared with the preset interrupt response threshold. When the interrupt response time is found to exceed the threshold, the specific information of these abnormal points (such as the time of occurrence, the test phase, the related interface and workload, etc.) is recorded. These abnormal data points may be caused by interface compatibility issues, insufficient firmware driver optimization, hardware failure, etc., and require further analysis and diagnosis.

[0127] Specifically, it is necessary to first determine the preset threshold of the interrupt response time, and then during the test, by monitoring the interrupt response time, when it is found that the interrupt response time exceeds the threshold, record the specific information of these abnormal points, including the time of occurrence, the test stage, the related interface and workload, etc. These abnormal points may be caused by interface compatibility issues, insufficient firmware driver optimization, hardware failure, etc., and require further analysis and diagnosis.

[0128] (4) Generate the interface compatibility matrix according to the nonlinear coupling relationship, the standard deviation of the hard disk performance indicator, and the interrupt response threshold abnormal point.

[0129] First, extract the key parameters and indicators in the nonlinear coupling relationship, which reflect the complex relationship between the protocol stack interaction feature data and the physical layer signal quality data. Then, compare and analyze the standard deviation of the hard disk performance indicators corresponding to the first target interface and the second target interface under the same test load to determine the fluctuation range and stability of the performance indicators. Next, integrate the anomaly point information of the marked interrupt response threshold, including the time, frequency, related interfaces, and workload of the anomaly point. By comprehensively analyzing this information, construct an interface compatibility matrix containing multiple interface combinations.

[0130] In the interface compatibility matrix, the performance differences between different interface combinations are represented by the attenuation gradient of key performance indicators, including read and write speed, IOPS (input / output times per second), latency, etc. At the same time, the interface compatibility matrix also marks the location and frequency of abnormal points of interrupt response thresholds, as well as the degree of impact of nonlinear coupling relationships on performance.

[0131] In addition, based on these analysis results, firmware adaptation suggestions are put forward, such as optimizing protocol stack parameters, updating firmware versions, etc., to improve interface compatibility and performance.

[0132] In this way, the interface compatibility matrix can intuitively display the performance differences and compatibility issues of different interface combinations, providing a scientific basis for SSD design optimization, quality control, and application selection.

[0133] S2072: Determine the performance test result according to the interface compatibility matrix.

[0134] Specifically, first, a comprehensive evaluation is performed on the key performance indicator attenuation gradients and firmware adaptation recommendations marked in the interface compatibility matrix. The key performance indicator attenuation gradient reflects the changes in performance indicators under different interface combinations. For example, if the read and write speeds are significantly improved and the latency is significantly reduced when switching from the SATA interface to the PCIe interface, this indicates that the PCIe interface has better performance in this scenario. The firmware adaptation recommendations provide optimization directions for different interface combinations. For example, if under a certain interface combination, the firmware adaptation recommendations propose to optimize the protocol stack parameters or update the firmware version, the test system will make corresponding adjustments and optimizations based on these recommendations.

[0135] By comprehensively evaluating this information, the test system can determine the performance of the SSD under different interface combinations and obtain performance test results. The performance test results will provide users with a comprehensive performance evaluation, helping users understand the performance advantages and disadvantages of the SSD under different interface combinations, so as to better select and apply the SSD.

[0136] The embodiment of the present invention provides a solid-state hard disk performance test method based on multi-interface switching, which realizes a comprehensive performance evaluation of the solid-state hard disk under different interface types by determining the target interface combination, generating an interface switching strategy, performing performance testing, aligning and processing test data, and generating an interface compatibility matrix. This method can effectively solve the problem that traditional testing methods are limited to a single interface and cannot comprehensively evaluate SSD performance, thereby improving the accuracy and reliability of the test. Through the analysis of spatiotemporal alignment processing and protocol stack interaction feature data and physical layer signal quality data, a deeper understanding of the performance of the SSD under different interfaces can be achieved, providing strong support for the design optimization, quality control and application selection of the SSD. In addition, the generated interface compatibility matrix marks the attenuation gradient of key performance indicators and firmware adaptation suggestions, providing a scientific basis for the performance improvement and application optimization of solid-state hard disks.

[0137] In some embodiments, the present embodiment also notes that the existing test load injection does not match the interface characteristics sufficiently, and cannot simulate the synergistic effect of interface switching and load fluctuations in real scenarios. In traditional testing methods, the injection of test loads is usually based on fixed patterns and parameters, and lacks dynamic association with the characteristics of the interface. This results in the inability to accurately simulate the dynamic changes in load when the interface is switched in real scenarios during the test process, thereby affecting the accuracy and reliability of the test results. For example, in actual applications, when the interface switches from low bandwidth to high bandwidth, the queue depth and read-write ratio of the load may change significantly, and traditional testing methods cannot capture these changes, resulting in deviations between the test results and actual performance.

[0138] Therefore, this embodiment embeds a load prediction model, such as a long short-term memory network (LSTM) neural network, in the interface switching process. The model can dynamically generate a load waveform based on the historical interface negotiation rate, so that the queue depth change of the test load forms a nonlinear coupling with the interface bandwidth fluctuation. By monitoring the negotiation rate and bandwidth changes of the interface in real time, the LSTM model can predict a load waveform that matches the current interface characteristics, thereby achieving dynamic matching of the test load and the interface characteristics.

[0139] The Q-learning algorithm is used to establish a mapping relationship between the interface state matrix and the optimal load mode, automatically optimizing the read-write ratio and pressure intensity. The generator can dynamically adjust the read-write ratio and queue depth of the test load according to the current interface state to simulate load fluctuations in real scenarios. The Q-learning algorithm finds the optimal load mode under different interface states through continuous trial and error and learning, thereby improving the matching degree between the test load and the interface characteristics.

[0140] This embodiment dynamically associates the interface physical layer state with the logical layer load, breaking through the limitation of the separation of load mode and interface characteristics in traditional testing. By embedding the load prediction model and the load strategy generator based on reinforcement learning, real-time dynamic matching of test load and interface characteristics is achieved, which can accurately simulate the synergistic effect of interface switching and load fluctuation in real scenarios. This dynamic load coupling technology not only improves the accuracy and reliability of test results, but also provides more powerful support for performance optimization and application selection of solid-state drives.

[0141] On the other hand, in step 206, during the process of aligning the first performance test data with the second performance test data, this embodiment also takes into account the problem that it is difficult to trace the anomalies of different interface protocol layers and it is impossible to identify the cross-layer error conduction path. In a complex storage system, the protocol stack usually includes multiple layers, such as the physical layer, link layer, and transport layer. When an abnormality occurs in the system, the anomaly may propagate between different layers, making it difficult to determine the root cause of the anomaly. For example, signal distortion at the physical layer may cause a CRC error at the link layer, which in turn causes a timeout retransmission at the transport layer. However, traditional methods can often only detect anomalies in a single layer and cannot effectively identify the cross-layer abnormal propagation path, thereby affecting the system's fault diagnosis and performance optimization.

[0142] In response to the above problems, this embodiment implants probe units in each layer of the protocol stack (physical layer, link layer, and transport layer), and these probe units can capture key cross-layer correlation data. For example, the probe of the physical layer can capture signal quality indicators, such as signal amplitude, frequency, noise level, etc.; the probe of the link layer can capture data such as CRC error counter and TLP retransmission times; the probe of the transport layer can capture data such as protocol state machine value and timeout retransmission times. Through these probe units, the operating status of each layer of the protocol stack can be fully monitored, providing rich data support for abnormal propagation analysis.

[0143] At the same time, the Bayesian network is used to build an abnormal propagation model, and the abnormal propagation path is identified through conditional probability calculation. Bayesian network is a probabilistic graph model that can represent the conditional dependency between variables. In this scheme, the abnormal events of each layer of the protocol stack can be used as nodes, and the conditional probability relationship between them can be represented by the Bayesian network. For example, signal distortion at the physical layer may cause CRC errors at the link layer, and CRC errors at the link layer may cause timeout retransmission at the transport layer. By calculating these conditional probabilities, the path of abnormal propagation can be identified, thereby realizing the identification of the conduction chain from physical layer signal distortion to upper layer protocol timeout.

[0144] Based on the above scheme, this embodiment establishes an abnormal correlation map of a multi-level protocol stack, and realizes the root cause location from bit error phenomenon to firmware defects. By implanting probe units in each layer of the protocol stack, capturing cross-layer correlation data, and using the Bayesian network to build an abnormal propagation model, the cross-layer abnormal propagation path can be effectively identified. This breaks through the limitation of traditional methods that can only detect single-layer anomalies, and provides strong support for fault diagnosis and performance optimization of complex storage systems. Through this solution, the root cause of the anomaly can be located more accurately, improving the reliability and stability of the system.

[0145] The method of this embodiment is executed by a test system, and the test system includes an electronic device. The electronic device in the embodiment of the present invention is described below from the perspective of hardware processing. Figure 2 , is a schematic diagram of a physical device structure of an electronic device in an embodiment of the present invention.

[0146] It should be noted that Figure 2 The structure of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0147] like Figure 2 As shown, the electronic device includes a central processing unit (CPU) 401, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 402 or the program loaded from the storage part 408 to the random access memory (RAM) 403, such as executing the method described in the above embodiment. In the random access memory (RAM) 403, various programs and data required for system operation are also stored. The central processing unit (CPU) 401, the read-only memory (ROM) 402 and the random access memory (RAM) 403 are connected to each other through a bus 404. The input / output (I / O) interface 405 is also connected to the bus 404.

[0148] The following components are connected to the input / output (I / O) interface 405: an input section 406 including an audio input device, a button switch, etc.; an output section 407 including a display and an audio output device, an indicator light, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the input / output (I / O) interface 405 as needed. A removable medium 411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 410 as needed so that a computer program read therefrom is installed into the storage section 408 as needed.

[0149] In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 409, and / or installed from a removable medium 411. When the computer program is executed by the central processing unit (CPU) 401, various functions defined in the present invention are performed.

[0150] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that may be used by or in combination with an instruction execution system, apparatus, or device.

[0151] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. Each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings.

[0152] Specifically, the electronic device of this embodiment includes a processor and a memory, the memory is coupled to one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and one or more processors call the computer instructions to enable the electronic device to execute the method provided by the above embodiment.

[0153] As another aspect, the present invention further provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above storage medium carries one or more computer programs, and when the above one or more computer programs are executed by a processor of the electronic device, the electronic device implements the method provided in the above embodiment.

[0154] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

[0155] As used in the above embodiments, the term "when..." may be interpreted to mean "if..." or "after..." or "in response to determining..." or "in response to detecting...", depending on the context. Similarly, the phrases "upon determining..." or "if (the stated condition or event) is detected" may be interpreted to mean "if determining..." or "in response to determining..." or "upon detecting (the stated condition or event)" or "in response to detecting (the stated condition or event)", depending on the context.

[0156] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

Claims

1. A solid state drive performance testing method based on multi-interface switching, characterized in that: include: Determine a target interface combination according to the specification parameters and supported interface types of the solid state drive under test and a preset interface configuration library, wherein the target interface combination includes a first target interface and a second target interface of different types, and the interface configuration library includes multiple interface types and corresponding protocol stack configuration parameters; Generating an interface switching strategy according to the target interface combination, wherein the interface switching strategy includes a switching sequence and a residence time of the target interface; Based on the interface switching strategy, performing a first performance test on the solid state drive under test through the first target interface to obtain first performance test data; At the end of the first performance test, based on the interface switching strategy, performing interface switching processing on the solid state drive under test to switch from the first target interface to the second target interface, the interface switching processing including reconfiguring the physical layer interface and reloading the protocol stack layer link parameters of the test system; Performing a second performance test on the solid state drive under test through the second target interface to obtain second performance test data; Aligning the first performance test data with the second performance test data to obtain protocol stack interaction feature data and physical layer signal quality data of the solid state drive under test, specifically including: determining a test sequence timestamp according to the operation timing of the first performance test and the second performance test; Based on the test sequence timestamp, the first performance test data and the second performance test data are mapped to a unified dimensional coordinate system to obtain test performance data coordinates; according to the test sequence timestamp and the test performance data coordinates, the first performance test data and the second performance test data are aligned to obtain protocol stack interaction feature data and physical layer signal quality data of the solid state drive under test; A performance test result of the solid state drive under test is determined according to the protocol stack interaction characteristic data and the physical layer signal quality data.

2. The method according to claim 1, characterized in that: The step of determining the performance test result of the solid state drive under test according to the protocol stack interaction characteristic data and the physical layer signal quality data includes: Generate an interface compatibility matrix according to the protocol stack interaction feature data and the physical layer signal quality data, wherein the interface compatibility matrix is ​​annotated with a key performance indicator attenuation gradient and a firmware adaptation suggestion corresponding to the target interface combination; The performance test result is determined according to the interface compatibility matrix.

3. The method according to claim 2, characterized in that Generating an interface compatibility matrix according to the protocol stack interaction characteristic data and the physical layer signal quality data, including: Determining a nonlinear coupling relationship between the protocol stack interaction characteristic data and the physical layer signal quality data; Calculate the standard deviation of hard disk performance indicators corresponding to the first target interface and the second target interface under the same test load; Marking the interrupt response threshold abnormal point related to the target interface combination in the firmware driver of the solid state drive under test, wherein the interrupt response threshold abnormal point refers to a data point at which the interrupt response time of the solid state drive under test exceeds a preset threshold when processing an interrupt signal; The interface compatibility matrix is ​​generated according to the nonlinear coupling relationship, the hard disk performance indicator standard deviation, and the interrupt response threshold abnormal point.

4. The method according to claim 1, characterized in that: The interface switching strategy also includes a sequential switching mode, a random switching mode or a concurrent switching mode. The sequential switching mode is used to execute a test cycle in ascending order according to the interface bandwidth. The random switching mode is used to generate a switching sequence in a non-fixed order based on a Markov chain model. The concurrent switching mode is used to synchronously activate multiple interface channels through multi-link aggregation technology.

5. The method according to any one of claims 1 to 4, characterized in that: The reconfiguring of the physical layer interface includes: compensating in real time, through a preset adaptive impedance matching module, for a signal reflection loss generated when the first target interface is switched to the second target interface.

6. The method according to claim 5, characterized in that The reloading of the protocol stack layer link parameters of the test system includes: predicting the optimal link parameter combination of the communication link between the test system and the solid-state drive under test through a link parameter configuration model, and reloading the optimal link parameter combination at the protocol stack layer of the test system, wherein the link parameter configuration model is a pre-trained machine learning model.

7. An electronic device, characterized in that: including one or more processors and memory; The memory is coupled to the one or more processors, and the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and the one or more processors call the computer instructions to enable the electronic device to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed on an electronic device, the electronic device is caused to execute the method as claimed in any one of claims 1 to 6.

9. A computer program product, characterized in that When the computer program product is executed on an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 6.

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