Wafer preparation processing method, wafer, chip and electronic equipment

Abstract

The invention belongs to the technical field of semiconductor materials, and provides a wafer preparation processing method, a wafer, a chip and electronic equipment, and the method comprises the steps: carrying out the thinning operation of structural layers of at least two initial wafers, and obtaining at least two thinned wafers; performing wafer bonding processing on the at least two wafers according to the structure layers of the at least two wafers after the thinning processing to obtain wafers after the bonding processing; and packaging the bonded wafer to obtain a synthetic wafer. The technical problem that the actual utilization rate of the wafer is low due to the fact that the preparation process of the wafer is poor in the related technology is solved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor material technology, and more specifically, relates to a wafer preparation and processing method, a wafer, a chip and an electronic device. Background Art

[0002] With the continuous development of semiconductor materials and advanced packaging technologies, as well as changes in consumer groups and emerging market demands, semiconductor products have penetrated into all walks of life. For example, consumer electronics chips and automotive electronics chips have appeared and are active in the market.

[0003] In addition, users have increasingly wider requirements for the compatibility of semiconductor products, and expect the same electronic chip to realize multiple functions according to different customer needs, so as to maximize the resource utilization of electronic chips. However, due to the current semiconductor materials (chip manufacturing materials), that is, the poor preparation process of wafers and the low actual utilization rate of wafers, the resource utilization needs of chip production cannot be met. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a wafer preparation and processing method, a wafer, a chip and an electronic device, aiming to solve the technical problem in the related art that the wafer preparation process is poor, resulting in low actual utilization rate of the wafer.

[0005] To achieve the above object, according to a first aspect of the present application, a method for preparing a wafer is provided, the method comprising:

[0006] Performing a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process;

[0007] According to the structural layers of the at least two wafers after the thinning process, performing wafer bonding process on the at least two wafers to obtain wafers after the bonding process;

[0008] The wafer after the bonding process is packaged to obtain a composite wafer.

[0009] Optionally, in a possible implementation manner of the first aspect, performing a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process includes:

[0010] Acquire structural layer data of at least two of the initial wafers, wherein the structural layers of the initial wafers include: a silicon layer, an aluminum layer, and a functional layer, and the functional designs of the functional layers of different initial wafers are different;

[0011] Determining a corresponding predetermined thinning ratio according to the structural layer data;

[0012] Based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer and / or the aluminum layer of at least two of the initial wafers respectively to obtain the at least two wafers after the thinning process.

[0013] Optionally, in a possible implementation manner of the first aspect, based on the predetermined thinning ratio, performing thinning operations on the silicon layer and / or the aluminum layer of at least two of the initial wafers respectively to obtain the at least two wafers after the thinning process includes:

[0014] In the case where the number of the initial wafers is two, based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer of the first wafer to obtain a first wafer after thinning;

[0015] Based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer and the aluminum layer of the second wafer to obtain the second wafer after the thinning process.

[0016] Optionally, in a possible implementation manner of the first aspect, performing wafer bonding on the at least two wafers according to the structural layers of the at least two wafers after the thinning process to obtain the wafers after the bonding process includes:

[0017] Bonding the silicon layer of the first wafer after the thinning process with the aluminum layer of the second wafer after the thinning process to obtain a new synthetic layer;

[0018] The first wafer after the thinning process and the second wafer after the thinning process are connected through the synthetic layer to obtain the bonding wafer.

[0019] Optionally, in a possible implementation manner of the first aspect, before packaging the wafer after the bonding process to obtain a composite wafer, the method further includes:

[0020] reallocating the positions of the connecting leads in the wafer after the bonding process;

[0021] The layout of the pads in the wafer after the bonding process is redesigned.

[0022] Optionally, in a possible implementation manner of the first aspect, the reallocating positions of the connecting leads in the wafer after the bonding process includes one of the following:

[0023] By means of the redistribution layer in the wafer after the bonding process, the connecting lead at a first position in the first coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a second position in the first coordinate axis direction or the second coordinate axis direction;

[0024] By means of the redistribution layer in the wafer after the bonding process, the connecting lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a fourth position in the first coordinate axis direction or the second coordinate axis direction;

[0025] Through the through silicon vias in the wafer after the bonding process, the connecting leads of any layer in the wafer after the bonding process are extended to another layer of the wafer after the bonding process along the third coordinate axis direction of the three-dimensional space.

[0026] Optionally, in a possible implementation manner of the first aspect, redesigning the layout of the pads in the wafer after the bonding process includes:

[0027] A metal ball implantation operation is performed on the aluminum layer surface of the wafer after the bonding process to layout bumps on the aluminum layer surface to replace the pads of the initial wafer, wherein the bumps are used to directly connect with corresponding pads during packaging.

[0028] According to a second aspect of the present application, a wafer preparation device is provided, the device comprising:

[0029] A thinning processing unit, used for performing a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process;

[0030] A bonding processing unit, used for performing wafer bonding processing on the at least two wafers after the thinning processing according to the structural layers of the at least two wafers, so as to obtain wafers after the bonding processing;

[0031] The packaging processing unit is used to perform packaging processing on the wafer after the bonding process to obtain a composite wafer.

[0032] Optionally, in a possible implementation manner of the first aspect, the thinning processing unit includes:

[0033] An acquisition subunit is used to acquire structural layer data of at least two of the initial wafers, wherein the structural layers of the initial wafers include: a silicon layer, an aluminum layer, and a functional layer, and the functional designs of the functional layers of different initial wafers are different;

[0034] A determination subunit, configured to determine a corresponding predetermined thinning ratio according to the structural layer data;

[0035] The thinning subunit is used to perform thinning operations on the silicon layer and / or aluminum layer of at least two of the initial wafers based on the predetermined thinning ratio to obtain the at least two wafers after the thinning process.

[0036] Optionally, in a possible implementation manner of the first aspect, the thinning subunit is specifically used to:

[0037] In the case where the number of the initial wafers is two, based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer of the first wafer to obtain a first wafer after thinning;

[0038] Based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer and the aluminum layer of the second wafer to obtain the second wafer after the thinning process.

[0039] Optionally, in a possible implementation manner of the first aspect, the bonding processing unit includes:

[0040] Bonding the silicon layer of the first wafer after the thinning process with the aluminum layer of the second wafer after the thinning process to obtain a new synthetic layer;

[0041] The first wafer after the thinning process and the second wafer after the thinning process are connected through the synthetic layer to obtain the bonding wafer.

[0042] Optionally, in a possible implementation manner of the first aspect, the device further includes:

[0043] A lead allocating unit, used for reallocating the positions of the connecting leads in the wafer after the bonding process;

[0044] The pad layout unit is used to redesign the layout of the pads in the wafer after the bonding process.

[0045] Optionally, in a possible implementation manner of the first aspect, the lead distribution unit is specifically used to implement one of the following:

[0046] By means of the redistribution layer in the wafer after the bonding process, the connecting lead at a first position in the first coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a second position in the first coordinate axis direction or the second coordinate axis direction;

[0047] By means of the redistribution layer in the wafer after the bonding process, the connecting lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a fourth position in the first coordinate axis direction or the second coordinate axis direction;

[0048] Through the through silicon vias in the wafer after the bonding process, the connecting leads of any layer in the wafer after the bonding process are extended to another layer of the wafer after the bonding process along the third coordinate axis direction of the three-dimensional space.

[0049] Optionally, in a possible implementation manner of the first aspect, redesigning the layout of the pads in the wafer after the bonding process includes:

[0050] A metal ball implantation operation is performed on the aluminum layer surface of the wafer after the bonding process to layout bumps on the aluminum layer surface to replace the pads of the initial wafer, wherein the bumps are used to directly connect with corresponding pads during packaging.

[0051] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0052] According to the third aspect of the present application, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the electronic device implements any one of the methods described in one embodiment.

[0053] According to a fourth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of the above is implemented.

[0054] According to a fifth aspect of the present application, an embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes any one of the methods described in the first aspect above.

[0055] According to a sixth aspect of the present application, a wafer is provided, which is prepared by any of the methods described above.

[0056] According to a seventh aspect of the present application, there is provided an electronic chip, which is manufactured using the wafer.

[0057] It can be understood that the beneficial effects of the second to seventh aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0058] The present application provides a wafer preparation and processing method, a wafer, a chip and an electronic device. The method performs a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after thinning; performs wafer bonding processing on at least two wafers according to the structural layers of the at least two wafers after thinning to obtain bonded wafers; and performs packaging processing on the bonded wafers to obtain a composite wafer.

[0059] By thinning, bonding and splicing at least two initial wafers, the functions of multiple single wafers are combined to form a multifunctional wafer, which reduces the materials required to make multiple wafers separately, and can achieve more functions or produce more qualified chips on a limited wafer area, thereby improving the actual utilization rate of the wafer. The technical problem of poor wafer preparation process in related technologies, which leads to low actual utilization rate of wafers, is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] Figure 1 It is a schematic diagram of a front view of an existing wafer;

[0062] Figure 2 It is a schematic flow chart of a wafer preparation and processing method provided in an embodiment of the present application;

[0063] Figure 3 It is a schematic flow chart of an optional wafer preparation and processing method provided in an embodiment of the present application;

[0064] Figure 4 This is a schematic diagram of the structural layers of an optional initial wafer provided in an embodiment of the present application;

[0065] Figure 5 A schematic flow chart of a wafer preparation and processing method provided by the present application is shown;

[0066] Figure 6 A schematic diagram of a wafer after bonding process provided by the present application is shown;

[0067] Figure 7 A schematic diagram of performing RDL and TSV processing on a wafer after bonding processing provided by the present application is shown;

[0068] Figure 8 A schematic diagram of a front view of a composite wafer provided by the present application is shown;

[0069] Fig. 9 It is a structural schematic diagram of a wafer preparation device provided in an embodiment of the present application;

[0070] Fig.10 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0072] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0073] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0074] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0075] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0076] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0077] First, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0078] An integrated circuit (IC) is a miniature electronic device or component that uses a certain process to interconnect the transistors, resistors, capacitors, inductors and other components and wiring required in a circuit. It is made on a small piece or several small pieces of semiconductor chips or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function.

[0079] The redistribution layer (RDL), also known as the redistribution layer, is an important structure in the integrated circuit manufacturing process, mainly used to redistribute the electrical connections on the chip to achieve better electrical performance and packaging feasibility.

[0080] Through Silicon Via (TSV) is a key technology in three-dimensional integrated circuits (3D ICs). It is a tiny through hole that vertically penetrates the silicon wafer and is used to achieve electrical connections between chips or between different layers within a chip.

[0081] In the semiconductor field, a single wafer refers to a circular thin sheet of material used to manufacture semiconductor devices.

[0082] A chip (die) refers to an independent chip formed on a wafer through a series of semiconductor manufacturing processes. There can be multiple dies on a single wafer. Each die can become an independent semiconductor chip product, such as a processor chip, memory chip, etc., after subsequent processes such as cutting and packaging.

[0083] The above is a brief introduction to the nouns involved in the embodiments of the present application, which will not be repeated below.

[0084] In the traditional wafer preparation and chip manufacturing process, the available area and resources of the wafer are not fully utilized, and it is impossible to achieve more functions or produce more qualified chips on the limited wafer area, resulting in a waste of wafer resources.

[0085] In addition, if Figure 1 As shown is a schematic diagram of the main view of an existing wafer, the existing wafer is affected by the wire bonding process of the packaging process, and the wires can only be laid out around the wafer when the pad layout is allocated, resulting in most of the middle area of ​​a single chip being wasted, and resources and functions are limited. In addition, it is difficult to expand the utilization rate of the wafer under the existing technology, and it is difficult to take into account various needs.

[0086] To solve the above problems, this application example provides an example of a wafer preparation method, please refer to Figure 2 As shown, Figure 2A schematic flow chart of a wafer preparation method provided by the present application is shown. As an example but not a limitation, the method can be applied to or run in any wafer preparation equipment. The method includes:

[0087] S101, performing a thinning operation on structural layers of at least two initial wafers to obtain at least two wafers after the thinning process.

[0088] S102, performing wafer bonding processing on at least two wafers according to the structural layers of at least two wafers after the thinning processing to obtain wafers after the bonding processing.

[0089] S103, packaging the wafer after bonding to obtain a composite wafer.

[0090] In this application example, first, a suitable initial wafer is selected according to the specific needs and application scenarios of the electronic chip product. For example, if wafers for high-performance computing chips are to be prepared, silicon wafers with high crystal structure integrity and extremely low impurity content may be preferred to ensure that the chip has the basic conditions for high-speed computing and stable performance.

[0091] In addition, professional thinning operation equipment can be controlled or equipped to perform thinning operations on the structural layers of at least two initial wafers, such as chemical mechanical polishers (CMP), etching equipment, etc. For chemical mechanical polishers, it is necessary to ensure that the flatness of the polishing head, the rotation speed and other parameters can be accurately controlled; for etching equipment, it is necessary to ensure that the flow rate of etching gas, the pressure of the etching chamber, etc. can be accurately controlled.

[0092] One thinning method is to use chemical mechanical polishing (CMP) technology to perform a thinning operation on the structural layers of at least two initial wafers, for example, by fixing each initial wafer on the workbench of a polishing machine and applying a polishing liquid containing abrasives to the surface of the wafer. The abrasive in the polishing liquid will chemically react with the surface material of the wafer to soften the surface material, and then the softened material will be removed by the mechanical friction between the polishing head and the wafer surface, thereby achieving thinning of the wafer surface. It should be understood that in this process, it is necessary to accurately control parameters such as the pressure of the polishing head, the flow rate of the polishing liquid, and the polishing time to ensure the uniformity of the thinning and achieve the desired thinning thickness. For example, if a silicon wafer with an initial thickness of 500 microns is to be thinned to 100 microns, it is necessary to accurately adjust parameters such as the pressure of the polishing head (generally between a few grams per square centimeter and tens of grams per square centimeter), the flow rate of the polishing liquid (usually between tens of milliliters per minute and hundreds of milliliters per minute), and the polishing time (which may vary from a few minutes to tens of minutes) based on factors such as the material properties of the wafer and the target thickness, so as to ensure the uniformity of the thinning and achieve the expected thinning thickness.

[0093] Another thinning method is etching thinning, which can be done using chemical etching or plasma etching technology. Taking chemical etching as an example, the initial wafer is immersed in a specific etching solution, and the chemical substances in the solution will react chemically with specific components on the surface of the wafer, thereby selectively removing the material on the surface of the wafer to achieve thinning. When performing etching thinning, the concentration, temperature, etching time and other parameters of the etching solution must also be strictly controlled to ensure the consistency and accuracy of the thinning effect.

[0094] Furthermore, before performing wafer bonding on at least two wafers, it is necessary to perform a detailed analysis of the wafer structure layers after thinning to understand the structural layer composition of each wafer, such as the specific conditions of the silicon layer, functional layer, aluminum layer, etc., including: thickness, surface flatness, electrical properties, etc., in order to determine the most suitable bonding method and process parameters.

[0095] If the surface flatness of each wafer reaches the atomic level after thinning and can meet the conditions for direct bonding in an ultra-high vacuum or clean environment, direct bonding can be selected. The specific operation is to directly bond two wafers that have undergone ultra-precision surface treatment (such as chemical mechanical polishing, etc.) to make their surfaces atomically flat together under certain temperature and pressure conditions. For example, for two silicon wafers, while ensuring that their surfaces are extremely clean and flat, set the temperature and air pressure values, and at the same time ensure the ultra-high vacuum or extremely high cleanliness of the bonding environment to ensure that atoms can form stable chemical bonds between the wafer surfaces.

[0096] In another implementation, when it is necessary to achieve bonding between wafers through an intermediate dielectric layer, a dielectric bonding method can be used. First, a dielectric material such as silicon dioxide, silicon nitride, etc. is coated on the surface of the wafer as an intermediate layer, and then the wafers with dielectric layers are bonded to each other through heating, pressurization and other process steps. For example, after a 100-nanometer-thick silicon dioxide dielectric layer is coated on the surface of a wafer, it is bonded to another wafer with the same dielectric layer at appropriate temperature and pressure, and electrical isolation and tight bonding between the two are achieved through the dielectric layer.

[0097] In another implementation, if a metal material is required as a bonding medium, metal bonding can be used. For example, a metal film (such as gold, copper, etc.) is deposited on the surface of the wafer, and then the wafers with the metal film are bonded to each other through processes such as hot pressing and ultrasound. For example, a gold film with a thickness of 50 nanometers is deposited on the surfaces of two wafers, and then they are bonded to each other under a certain temperature and pressure through a hot pressing process, and the good electrical conductivity and thermal conductivity of the gold film are used to achieve tight electrical connection and thermal management.

[0098] Finally, when packaging the wafer after bonding, first conduct a comprehensive inspection and analysis of the wafer after bonding, mainly to check the quality of its bonding, including whether there are problems such as loose bonding and abnormal electrical performance. Electrical testing instruments (such as multimeters, oscilloscopes, etc.) can be used to detect the electrical properties of the wafer, and the bonding interface can be observed through a microscope to determine whether there are gaps, defects, and other factors that affect the bonding quality.

[0099] In addition, it is also necessary to prepare the materials required for packaging, such as packaging substrates, lead frames, packaging resins, etc. For packaging substrates, the appropriate type should be selected according to the characteristics of the wafer after bonding (such as electrical performance, size, etc.). For example, for wafers of high-speed computing chips, it may be necessary to select packaging substrates with good electrical and heat dissipation properties.

[0100] Specifically, the packaging process of the wafer after bonding is to accurately place the wafer after bonding on the packaging substrate, usually by pasting or welding to ensure a firm connection between the wafer and the substrate. Then, an electrical connection is established between the wafer and the packaging substrate, and the signal transmission is achieved by connecting one end of a metal lead (such as a gold wire) to a pad on the wafer and the other end to a corresponding pin on the packaging substrate.

[0101] For example, if the pasting method is used, silver glue is used to paste the wafer to the substrate. During the pasting process, it is necessary to ensure that the silver glue is evenly applied to avoid bubbles and other factors that affect the pasting quality. The wafer is gently placed on the substrate coated with silver glue, and then cured according to the specified process conditions (such as temperature, pressure, etc.) to fully cure the silver glue and ensure a firm connection between the wafer and the substrate. For another example, if the welding method is used, the wafer is generally connected to the solder joints on the substrate through welding processes such as reflow soldering. During the welding process, it is necessary to ensure accurate control of parameters such as welding temperature and welding time to avoid problems such as cold soldering and over-soldering, and to ensure a firm connection between the wafer and the substrate.

[0102] In addition, in another embodiment, when performing wire bonding, it is necessary to ensure that the length, shape, connection accuracy, etc. of the wire meet the design requirements to ensure the quality of the electrical connection. The wire bonding equipment can be used to perform the operation, and the parameters such as the length and curvature of the wire can be set on the equipment, and then the wire bonding operation can be performed according to the prescribed procedures.

[0103] Through the wafer preparation method provided by the example of this application, at least two initial wafers are combined into one, thereby avoiding the waste of wafer materials. By performing a series of operations such as thinning, bonding and splicing at least two initial wafers, the functions of multiple single wafers are combined to form a multifunctional wafer, which reduces the materials required for making multiple wafers separately, and can achieve more functions or produce more qualified chips on a limited wafer area, thereby improving the actual utilization rate of the wafer.

[0104] For a possible implementation, please refer to Figure 3 As shown, Figure 3 A schematic flow chart of a wafer preparation method provided by the present application is shown, wherein a thinning operation is performed on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process, including:

[0105] S201, obtaining structural layer data of at least two initial wafers.

[0106] S202: Determine a corresponding predetermined thinning ratio according to the structural layer data.

[0107] S203, based on a predetermined thinning ratio, performing thinning operations on the silicon layer and / or the aluminum layer of at least two initial wafers respectively to obtain at least two wafers after thinning processing.

[0108] Before thinning the initial wafer, the structural layer data of each initial wafer is obtained first, for example, which structural layers are included, the thickness data of each structural layer, etc., to provide a basis for subsequently determining the appropriate thinning ratio and ensuring the accuracy of the thinning operation, thereby ensuring the effectiveness of the entire wafer preparation method.

[0109] like Figure 4 As shown, the structural layers of each initial wafer include: a silicon layer (thickness of about 550 microns), an aluminum layer (thickness of about 150 microns), and a functional layer (thickness of about 150 microns). The functional designs of the functional layers of different initial wafers are different. For example, the functional layers of different initial wafers are designed to realize different types of circuit functions such as digital circuit functions and analog circuit functions.

[0110] In the example of the present application, the corresponding predetermined thinning ratio is determined according to the structural layer data. For example, based on the overall thickness data of each initial wafer and the thickness data of each structural layer, if a layer (such as a silicon layer) has a thicker initial thickness and its thickness requirements in subsequent processes are relatively flexible, a relatively large thinning ratio can be considered to be set without affecting the overall performance.

[0111] At the same time, the characteristics of each structural layer and the compatibility of the wafer after the thinning operation in subsequent processes (such as wafer bonding, packaging, etc.) must also be considered. For example, if the functional design of the functional layer is relatively complex and involves many precise circuit components and connections, there is no need to thin the functional layer, or the functional layer should be thinned more carefully, and the thinning ratio may be relatively small to avoid damaging the circuit structure of the functional layer and affecting the function. For example, if a wafer bonding operation is to be performed later and a direct bonding method is used, the surface flatness requirements of each layer are extremely high. At this time, when determining the thinning ratio, it is necessary to consider how to use the thinning operation to make each layer reach the target thickness while improving the surface flatness as much as possible to meet the conditions for direct bonding.

[0112] Since the chip has high requirements for thinness, assuming there are two initial wafers, the initial thickness of the silicon layer of the first wafer is about 550 microns. At the same time, considering that the wafer bonding in the subsequent process adopts a dielectric bonding method, the requirements for the surface flatness of the silicon layer are relatively not particularly high. Combining these factors, based on experience and relevant process standards, the thickness of the silicon layer of the first wafer needs to be reduced to about 50 microns, and the predetermined thinning ratio of the silicon layer of the first wafer is determined to be 91%.

[0113] The aluminum layer of the second wafer is thinned in order to bond it with the silicon layer of the first wafer. The initial thickness of the aluminum layer of the second wafer is about 150 microns, and the thickness of the aluminum layer of the second wafer finally needs to be reduced to about 50 microns. Therefore, the predetermined thinning ratio of the aluminum layer of the second wafer is determined to be 67%.

[0114] The silicon layer of the second wafer is thinned to ensure that the thickness of the final composite wafer is within the specification requirements and does not affect its functional realization. The initial thickness of the silicon layer of the second wafer is about 550 microns, and the silicon layer of the second wafer finally needs to be reduced to about 300 microns. Therefore, the predetermined thinning ratio of the silicon layer of the second wafer is determined to be 45%.

[0115] Furthermore, based on a predetermined thinning ratio, the thinning operation on the silicon layer and / or the aluminum layer of at least two initial wafers can be precisely controlled to obtain at least two wafers after thinning.

[0116] Through the above method steps, the appropriate thinning ratio can be determined based on the structural layer data of the initial wafer, and the thinning operation can be accurately performed to obtain a thinned wafer that meets the requirements, so as to facilitate subsequent wafer bonding, packaging and other processes.

[0117] As an optional embodiment, in addition to determining the predetermined thinning ratio based on the structural layer data, multiple other factors can also be comprehensively considered, such as the product target of the final prepared wafer and the requirements of the wafer for heat dissipation. These factors are closely related to the acquired structural layer data. For example, if it is a wafer used to manufacture high-performance smartphone chips, it is necessary to reduce the thickness of the wafer as much as possible to meet the needs of thin and light mobile phones while ensuring chip performance. In this case, it may be inclined to set a relatively large thinning ratio, but at the same time, it is also necessary to ensure that the function and reliability of the chip will not be affected by excessive thinning. For example, for some wafers of industrial control chips that have high heat dissipation requirements, it is necessary to retain a certain thickness during the thinning process to ensure good heat dissipation performance. At this time, the thinning ratio needs to be reasonably adjusted according to the heat dissipation requirements.

[0118] In a possible implementation, based on a predetermined thinning ratio, thinning operations are performed on silicon layers and / or aluminum layers of at least two initial wafers respectively to obtain at least two wafers after thinning, including:

[0119] In the case that the number of initial wafers is two, a thinning operation is performed on the silicon layer of the first wafer based on a predetermined thinning ratio to obtain a first wafer after thinning.

[0120] Based on a predetermined thinning ratio, a thinning operation is performed on the silicon layer and the aluminum layer of the second wafer to obtain a second wafer after thinning.

[0121] In one example, the silicon layer of the first wafer can be thinned in the following manner: fix the first wafer on the workbench of the chemical mechanical polisher, ensure that the wafer fits tightly to the workbench and is placed horizontally, and avoid shaking or tilting during the polishing process, which affects the thinning effect. Start the chemical mechanical polisher according to the debugged equipment parameters. At this time, the polishing head starts to rotate at a set rotation speed and applies a set pressure to the wafer surface. At the same time, the polishing liquid supply system sprays the polishing liquid evenly on the wafer surface at a set flow rate.

[0122] During the polishing process, the thickness change of the silicon layer is monitored in real time. The current thickness of the silicon layer can be accurately measured at regular intervals (such as every few seconds) through online thickness monitoring equipment (such as a laser thickness meter). Afterwards, the parameters of the chemical mechanical polisher are adjusted in a timely manner according to the measured current thickness and the target thinning thickness. For example, if it is found that the current thickness thinning speed is too fast and is about to fall below the target thinning thickness, the pressure of the polishing head or the flow rate of the polishing liquid can be appropriately reduced; conversely, if the current thickness thinning speed is too slow, the relevant parameters can be appropriately increased to ensure that the target thinning thickness can be accurately reached in the end.

[0123] When the thickness of the silicon layer reaches the target thinning thickness, the operation of the chemical mechanical polisher is stopped by the online thickness monitoring equipment. Subsequently, the first wafer after thinning is preliminarily inspected. The flatness and roughness of the silicon layer surface can be checked using equipment such as an optical microscope or an electron microscope to ensure that the surface quality meets the requirements of processes such as wafer bonding. At the same time, the thickness of the silicon layer is measured again to verify whether the target thinning thickness has been achieved. If there is a deviation, the cause is analyzed and handled accordingly.

[0124] Based on the predetermined thinning ratio, the silicon layer and aluminum layer of the second wafer are thinned: the second wafer is fixed on the workbench of the chemical mechanical polisher according to the similar operation process as the thinning of the silicon layer of the first wafer, the polisher is started and polished according to the set parameters. During the polishing process, the thickness changes of the silicon layer and the aluminum layer are monitored in real time through the online thickness monitoring equipment, and the parameters of the polisher are adjusted in time according to the measurement results to ensure that the target thinning thickness is finally achieved.

[0125] When the thickness of the silicon layer or the aluminum layer reaches the target thinning thickness, the polishing machine is stopped. Then the silicon layer and the aluminum layer of the second wafer after thinning are inspected to check whether their surface flatness, roughness and thickness meet the requirements. For example, optical microscopes or electron microscopes can be used to check to ensure that the surface quality of the aluminum layer meets the requirements of subsequent processes.

[0126] Through the above detailed operation steps, the silicon layer of the first wafer and the silicon layer and aluminum layer of the second wafer are thinned according to a predetermined thinning ratio, and finally the first wafer and the second wafer after thinning are obtained.

[0127] For a possible implementation, please refer to Figure 5 As shown, Figure 5 A schematic flow chart of a wafer preparation method provided by the present application is shown, wherein at least two wafers are subjected to wafer bonding according to the structural layers of at least two wafers after thinning to obtain a wafer after bonding, including:

[0128] S401, bonding the silicon layer of the first wafer after the thinning process and the aluminum layer of the second wafer after the thinning process to obtain a new composite layer.

[0129] S402, establishing a connection between the first wafer after thinning and the second wafer after thinning through a composite layer to obtain a bonded wafer.

[0130] In the example of this application, before the bonding process, it is necessary to analyze the characteristics of the silicon layer of the first wafer and the aluminum layer of the second wafer after the thinning process. For example, measure the thickness, surface flatness, and electrical properties. Accurately measure the thickness through high-precision instruments such as optical microscopes or electron microscopes to ensure that the silicon layer of the first wafer and the aluminum layer of the second wafer meet the expected thickness requirements after thinning. Using equipment such as atomic force microscopes, the microscopic fluctuations of the silicon layer of the first wafer and the aluminum layer of the second wafer are detected. Generally, it is required to achieve atomic-level flatness or near-atomic-level flatness to meet the conditions for high-quality bonding. In terms of electrical characteristics, for example, parameters such as the resistivity of the silicon layer and the conductivity of the aluminum layer are measured to ensure that the electrical performance of the entire wafer meets expectations after bonding.

[0131] According to the results of the analysis of the characteristics of the silicon layer and the aluminum layer, a suitable bonding method is selected, such as direct bonding, dielectric bonding, and metal bonding. In this example, direct bonding is used as an example (of course, the actual situation needs to determine the most suitable bonding method based on the specific characteristics).

[0132] For example, for direct bonding, it is usually required that the two surfaces to be bonded (i.e., the silicon layer surface of the first wafer and the aluminum layer surface of the second wafer) are atomically flat and bonded in an ultra-high vacuum or clean environment. If the surface flatness does not meet the requirements, further surface treatment may be required, such as polishing the relevant surfaces again using methods such as chemical mechanical polishing to improve the surface flatness to meet the conditions for direct bonding.

[0133] Specifically, in the example of this application, the first wafer and the second wafer after thinning are placed on the corresponding positions of a special direct bonding device, respectively, to ensure that the surfaces to be bonded (silicon layer and aluminum layer) of the two wafers can be accurately aligned and in close contact. During the placement process, special attention should be paid to avoid scratches or contamination on the surface of the wafer. Suitable fixtures or operating tools can be used to assist in the placement operation to ensure that the position of the wafer in the bonding device is stable. The bonding equipment directly bonds the silicon layer of the first wafer and the aluminum layer of the second wafer together in an ultra-high vacuum or clean environment according to the set temperature and pressure conditions. During the bonding process, chemical bonds will gradually form between atoms, so that the silicon layer and aluminum layer of the two wafers are tightly combined to form a new synthetic layer. Continuously monitor the operating status of the bonding equipment to ensure the stability of parameters such as temperature and pressure to ensure the bonding quality.

[0134] After the silicon layer and the aluminum layer are bonded to form a new composite layer, the physical connection between the two wafers through the composite layer can be checked first. For example, the interface of the composite layer can be observed under a microscope to see if there are gaps, holes or other obvious physical defects. If such problems are found, it may be necessary to re-evaluate the bonding process, check whether the bonding equipment parameters are set correctly, whether the environment meets the requirements, etc., and make corresponding adjustments or re-bond operations according to the situation.

[0135] In addition to checking the physical connection, the electrical performance of the two wafers connected through the synthesis layer can also be tested. For example, use electrical test instruments (such as multimeters, oscilloscopes, etc.) to set test points at different parts of the two wafers, measure electrical parameters such as current and voltage, to verify whether normal electrical conduction can be achieved after the connection through the synthesis layer, and whether the electrical performance meets expectations. If the electrical performance is abnormal, such as excessive resistance, unstable signal transmission, etc., it is also necessary to re-test the bonding process and related parameters, and make necessary adjustments or re-bond operations.

[0136] After confirming the quality of the composite layer (including physical connection and electrical performance), the integrity of the entire wafer after bonding should be checked. Check whether the shape of the wafer is complete and whether there is any damage or deformation. At the same time, measure the key dimensions of the wafer (such as diameter, thickness, etc.) again to ensure that it meets the requirements of subsequent processes (such as packaging, etc.).

[0137] Through the above detailed steps, the silicon layer of the first wafer after thinning is bonded with the aluminum layer of the second wafer after thinning to obtain a new synthetic layer, and the connection between the two wafers is established through the synthetic layer, and finally the following is obtained: Figure 6 The wafer after bonding process is shown (five layers, overall thickness is about 850 microns).

[0138] In a possible implementation, before packaging the wafer after bonding to obtain a composite wafer, the method further includes:

[0139] Reassign the positions of the connecting leads in the wafer after the bonding process.

[0140] Redesign the layout of pads in the wafer after the bonding process.

[0141] Before packaging the bonding wafer to obtain a composite wafer, the two operations of reallocating the connection lead positions and redesigning the pad layout are performed to further optimize the electrical connection performance of the wafer, improve the convenience of packaging, and better adapt to subsequent application requirements, thereby improving the overall quality and performance of the final composite wafer.

[0142] In a possible implementation, the positions of the connecting leads in the wafer after the bonding process are reallocated, including one of the following:

[0143] S501, adjusting the connecting lead at the first position in the first coordinate axis direction in the three-dimensional space in the wafer after the bonding process to the second position in the first coordinate axis direction or the second coordinate axis direction through the redistribution layer in the wafer after the bonding process.

[0144] Optionally, in the present application example, the redistribution layer RDL is a metal structure located on the chip surface or between the chip and the package substrate, and its main function is to re-plan and distribute the original electrical connections inside the chip. In the present application example, the redistribution layer can be used in the plane direction (i.e., the first coordinate axis direction and the second coordinate axis direction, which can usually be understood as the horizontal direction in the wafer plane, such as Figure 7 The position of the connecting lead is adjusted in the X and Y coordinate axis directions shown.

[0145] For example, as an optional specific adjustment process: first, determine the connection leads that need to be adjusted. These leads are originally in the first position in the first coordinate axis direction (assuming the X coordinate axis direction) in the three-dimensional space in the wafer after bonding. Then, according to the overall design requirements of the chip and the requirements of subsequent packaging and application, use micro-machining processes such as photolithography and etching to make new metal circuit patterns on the rewiring layer, and connect the connection leads in the first position to the second position in the first coordinate axis direction (X coordinate axis direction) or the second coordinate axis direction (Y coordinate axis direction) through these new lines. For example, if a connection lead that was originally close to the edge of the wafer in the X coordinate axis direction may be adjusted to a suitable position closer to the center of the wafer in the X coordinate axis direction or in the Y coordinate axis direction after rewiring, this can optimize the distribution of the leads, reduce interference in signal transmission, and improve the efficiency of electrical connection.

[0146] S502, adjusting the connecting lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process to the fourth position in the first coordinate axis direction or the second coordinate axis direction through the redistribution layer in the wafer after the bonding process.

[0147] In addition, through the rewiring layer in the wafer after the bonding process, the connecting lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to the fourth position in the first coordinate axis direction or the second coordinate axis direction. The adjustment is made for the connecting lead at the third position in the second coordinate axis direction (assuming the Y coordinate axis direction) in the three-dimensional space. Similarly, using the micromachining process of the rewiring layer, a new metal circuit pattern is made according to specific needs, and the connecting lead is reconnected from the original third position in the Y coordinate axis direction to the fourth position in the first coordinate axis direction (X coordinate axis direction) or the second coordinate axis direction (Y coordinate axis direction). For example, a connecting lead originally in the middle area of ​​the Y coordinate axis direction may be adjusted to a specific position in the X coordinate axis direction after rewiring to better match the layout of other circuit components or meet the requirements of pin arrangement during packaging.

[0148] S503, extending the connection leads of any layer of the wafer after the bonding process along the third coordinate axis direction of the three-dimensional space to another layer of the wafer after the bonding process through the through silicon via in the wafer after the bonding process.

[0149] In this application example, TSV is a tiny through hole that runs vertically through the silicon wafer and is used to achieve electrical connection between chips or between different layers within a chip. In this application example, it is used to connect the silicon wafer in the vertical direction (i.e., the third coordinate axis direction of the three-dimensional space, which can usually be understood as the direction perpendicular to the wafer plane, such as Figure 7 The connecting lead is extended in the Z coordinate axis direction (as shown).

[0150] As an optional specific extension process: First, determine the layer where the connecting lead that needs to be vertically extended is located and the target layer. For example, suppose that a connecting lead on a layer (such as a functional layer) in the wafer after bonding is to be extended along the Z coordinate axis to another layer (such as an aluminum layer). Then, a vertical silicon via is drilled on the silicon wafer through processes such as photolithography and etching, and then a conductive material (such as copper, etc.) is filled in the hole, so that the connecting lead can be extended from the original layer along the Z coordinate axis to the target layer through the silicon via, thereby realizing a vertical electrical connection between different layers. It should be understood that this vertical connection is of great significance for constructing complex multi-layer circuit structures, optimizing electrical connection paths, and improving chip integration.

[0151] In a possible implementation, redesigning the layout of pads in the wafer after bonding process includes:

[0152] After the bonding process, a metal ball implantation operation is performed on the aluminum layer surface of the wafer to layout bumps on the aluminum layer surface to replace the pads of the initial wafer, wherein the bumps are used to directly connect with corresponding pad points during packaging.

[0153] Specifically, in the example of this application, a metal ball implantation operation is used to implement a metal bump (or metal bump) layout instead of welding. It should be understood that the metal ball implantation operation refers to the process of depositing metal balls on the aluminum layer surface of the wafer after the bonding process. For example, through electroplating, chemical plating and other methods, metal bumps are formed on the surface of the aluminum layer according to a certain layout rule.

[0154] During packaging, metal bumps can be directly connected to corresponding pads (such as pads on the packaging substrate). Compared with the traditional pad layout method, it has the following advantages: on the one hand, the layout of the bumps can be more flexible and can be optimized and adjusted according to the packaging requirements and the overall chip design; on the other hand, the bumps may have better performance in electrical connection, such as lower contact resistance, etc., thereby improving the quality of electrical connection during the packaging process, and helping to reduce the packaging volume and improve packaging efficiency.

[0155] By performing the above operations of reallocating the connection lead positions and redesigning the pad layout on the wafer after the bonding process before the packaging process, the resulting composite wafer (such as Figure 8 The front view of the composite wafer shown in the figure has been significantly improved in terms of electrical performance and packaging convenience, better meeting the requirements of modern electronic devices for high performance and miniaturization of chips.

[0156] According to the example of the present application, a wafer example is also provided, which is prepared using any of the above methods.

[0157] First, a thinning operation is performed on the structural layers of at least two initial wafers. This involves obtaining the structural layer data of the initial wafer, including information on each layer such as the silicon layer, the aluminum layer, and the functional layer, and the functional design of the functional layers of different initial wafers is different. Then, the corresponding predetermined thinning ratio is determined based on these structural layer data, and finally, based on the predetermined thinning ratio, the silicon layer and / or aluminum layer of at least two initial wafers are thinned respectively to obtain at least two wafers after thinning. For example, when the number of initial wafers is two, the silicon layer of the first wafer is thinned based on the predetermined thinning ratio, and the silicon layer and aluminum layer of the second wafer are thinned.

[0158] Next, the silicon layer of the first wafer after thinning is bonded to the aluminum layer of the second wafer after thinning to obtain a new synthetic layer. In this process, it is necessary to first analyze the structural layer characteristics of the thinned wafer, select a suitable bonding method (such as direct bonding, etc.) and prepare relevant conditions. Then, through the synthetic layer, the connection between the first wafer after thinning and the second wafer after thinning is established to obtain a bonded wafer.

[0159] Before packaging the bonded wafer, the following two important operations are required:

[0160] To relocate a connection lead:

[0161] Through the redistribution layer (RDL) in the wafer after bonding processing, the position of the connecting leads can be adjusted in the planar direction (such as adjusting the connecting lead at the first position in the direction of the first coordinate axis in the three-dimensional space to the second position in the direction of the first coordinate axis or the second coordinate axis; or adjusting the connecting lead at the third position in the direction of the second coordinate axis in the three-dimensional space to the fourth position in the direction of the first coordinate axis or the second coordinate axis) to optimize the electrical connection.

[0162] Through the through silicon via (TSV) in the wafer after bonding, the connecting leads of any layer can be extended along the third coordinate axis of the three-dimensional space to another layer of the wafer after bonding, thereby realizing vertical electrical connection between different layers.

[0163] Redesign the layout of the pads:

[0164] After bonding, metal ball implantation is performed on the aluminum surface of the wafer to lay out bumps on the aluminum surface to replace the pads of the initial wafer. These bumps can be directly connected to the corresponding pads during packaging, which helps to improve the electrical connection quality and packaging efficiency during the packaging process.

[0165] Finally, the wafer after bonding process after the above series of processes is packaged to obtain the final composite wafer, that is, the wafer prepared by the wafer preparation method provided in the example of this application.

[0166] Due to multiple processes such as fine thinning, bonding, rewiring and redesign of pad layout, this wafer has many advantages in structure and performance.

[0167] For example, through reasonable thinning operations, the overall thickness of the wafer and the thickness of each structural layer can be adjusted according to specific needs, which can not only meet the product's requirements for lightness and thinness (such as in the consumer electronics field), but also ensure normal functions in some application scenarios that have requirements for heat dissipation and other performance (such as in the automotive electronics field).

[0168] For another example, reallocating the position of the connection leads makes the electrical connection more reasonable and efficient. The optimized wiring of RDL in the plane direction and the vertical electrical connection achieved by TSV reduce the interference and loss of signal transmission, improve the speed and accuracy of signal transmission, and thus improve the electrical performance of the entire wafer.

[0169] For another example, redesigning the layout of the pads and using the bumps formed by metal ball implantation to replace the traditional pads may not only have advantages such as lower contact resistance in terms of electrical connection, but also can be flexibly arranged according to packaging requirements, further optimizing the electrical connection effect. The bumps formed by metal ball implantation can be directly connected to the corresponding pad points during packaging. This direct connection method is simpler and faster than the traditional pad connection method, reducing the process complexity during the packaging process and improving packaging efficiency.

[0170] After the rewiring and redesign of the pad layout, the electrical connection of the wafer has been optimized according to the packaging requirements, making it easier to accurately match and connect with the packaging substrate and other components during packaging, reducing the difficulty of packaging. Due to the optimization of electrical connections, various problems caused by poor electrical connections, such as short circuits and cold solder joints, can be reduced during the packaging process, thereby improving the packaging quality and reducing the defective rate of products. The optimized pad layout and connection lead position enable the wafer to better adapt to the requirements of the packaging process during the packaging process, ensuring that the wafer can operate stably after packaging and extending the service life of the product.

[0171] In summary, the wafer prepared by the wafer preparation method provided in the example of this application has obvious advantages in structure, performance, packaging convenience and quality, etc., and can maximize the resource utilization of electronic chips and better meet the diverse needs of modern electronic devices for chips.

[0172] According to an example of the present application, an example of an electronic chip is provided, which is prepared using the wafer provided in the above example.

[0173] Since the wafer used in the electronic chip has undergone multiple fine processing steps, the electronic chip also benefits from this refinement in structure. For example, the wafer is thinned so that each structural layer (such as silicon layer, aluminum layer, functional layer, etc.) reaches a suitable thickness. After the electronic chip inherits this optimized structure, its internal circuit layout and component distribution can be more compact and reasonable, which helps to improve the chip's integration and realize more complex circuit functions in a smaller chip area.

[0174] Moreover, during the wafer preparation process, the reallocation of the connection lead positions (through technologies such as redistribution layer RDL and through silicon via TSV) and the redesign of the pad layout (through metal ball implantation to form bumps instead of traditional pads) optimize the electrical connection structure of the electronic chip at the microscopic level. This optimization can maximize the resource utilization of the electronic chip.

[0175] This electronic chip inherits the advantages of the wafer in improving electrical performance, and the electronic chip also exhibits better electrical characteristics. By optimizing the wiring in the planar direction through RDL and realizing vertical electrical connection through TSV, the signal transmission speed inside the chip is significantly improved, and it can quickly and accurately process various input signals and output corresponding results. At the same time, the redesigned pad layout uses bumps formed by metal ball planting, which has electrical advantages such as lower contact resistance, further improving the electrical performance of the chip when connected to the external circuit, so that the chip can play a more efficient role in the circuit system of the entire electronic device, reducing performance degradation or failure problems that may be caused by poor electrical connections.

[0176] The wafer used in this electronic chip has undergone a series of optimization operations for packaging convenience before packaging, such as the bumps formed by metal ball planting can be directly connected to the corresponding pads. This feature is also reflected in the packaging process of the electronic chip. This direct connection method greatly simplifies the process flow of chip packaging, reduces the process complexity and operation difficulty that may occur in the packaging link, and enables the chip to complete the packaging process more quickly and smoothly.

[0177] Moreover, after rewiring and redesigning the pad layout, the electrical connection of the wafer has been optimized according to the packaging requirements. The electronic chip can be better matched and connected with the packaging substrate and other components during packaging, which improves the compatibility of the chip and the packaging structure and ensures that the chip can be stably embedded in the circuit system of various electronic devices after packaging.

[0178] The electronic chip prepared by using the above-mentioned wafer provided in the example of this application has significant application advantages in various electronic devices:

[0179] For example, in high-performance computing scenarios, consumer electronic devices such as smartphones, tablets, and laptops have high requirements for chip computing speed, processing power, and energy efficiency. With its excellent electrical properties, this electronic chip can quickly process large amounts of data and complex computing tasks, while keeping power consumption within a reasonable range, meeting the needs of these devices for high-performance computing and providing users with a smooth operating experience.

[0180] For another example, in the scenario of miniaturization and integration requirements, as electronic devices continue to develop in the direction of miniaturization and integration, such as wearable devices and IoT devices, the requirements for chip integration are getting higher and higher. This type of electronic chip, because it inherits the fine structural hierarchy of the wafer and the optimized electrical connection structure, can realize more complex circuit functions in a smaller chip area, and is very suitable for use in these electronic devices with strict requirements on space and integration, which will help promote the further miniaturization and integration of these devices.

[0181] For another example, in high reliability demand scenarios, the reliability of electronic equipment is crucial in the fields of automotive electronics, industrial control, aerospace, etc. The electronic chip can work stably under harsh environmental conditions (such as high temperature, high humidity, vibration, etc.) through the improvement of its packaging quality and reliability, reducing equipment failures or safety accidents that may be caused by chip failures, and providing solid protection for electronic equipment in these fields.

[0182] In summary, the electronic chip prepared using the wafer provided in the example of this application, by inheriting the advantages of the wafer and its own characteristics in electrical performance, packaging, etc., exhibits excellent application advantages in various electronic devices and can better meet the diverse needs of modern electronic devices for chips.

[0183] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0184] Corresponding to the wafer preparation method of the above embodiment, Fig. 9 is a schematic diagram of the structure of a wafer preparation device provided in an embodiment of the present application. The device can be implemented as part or all of a computer device by software, hardware, or a combination of both. The computer device can be Fig.10 Electronic equipment shown.

[0185] Reference Fig. 9 , the wafer preparation device comprises:

[0186] A thinning processing unit 601 is used to perform a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process;

[0187] The bonding processing unit 602 is used to perform wafer bonding processing on at least two wafers according to the structural layers of the at least two wafers after the thinning processing to obtain wafers after the bonding processing;

[0188] The packaging processing unit 603 is used to package the wafer after the bonding process to obtain a composite wafer.

[0189] Further, based on any of the above embodiments, as an example of the present application, the thinning processing unit includes:

[0190] An acquisition subunit is used to acquire structural layer data of at least two initial wafers, wherein the structural layers of the initial wafers include: a silicon layer, an aluminum layer, and a functional layer, and the functional designs of the functional layers of different initial wafers are different;

[0191] A determination subunit is used to determine a corresponding predetermined thinning ratio according to the structural layer data;

[0192] The thinning subunit is used to perform thinning operations on the silicon layer and / or the aluminum layer of at least two initial wafers based on a predetermined thinning ratio to obtain at least two wafers after thinning.

[0193] Further, based on any of the above embodiments, as an example of the present application, the thinning subunit is specifically used for:

[0194] When the number of initial wafers is two, a thinning operation is performed on the silicon layer of the first wafer based on a predetermined thinning ratio to obtain a first wafer after thinning;

[0195] Based on a predetermined thinning ratio, a thinning operation is performed on the silicon layer and the aluminum layer of the second wafer to obtain a second wafer after thinning.

[0196] Further, based on any of the above embodiments, as an example of the present application, the bonding processing unit includes:

[0197] Bonding the silicon layer of the first wafer after thinning with the aluminum layer of the second wafer after thinning to obtain a new composite layer;

[0198] The first wafer after thinning is connected to the second wafer after thinning by the synthesis layer to obtain a bonding wafer.

[0199] Further, based on any of the above embodiments, as an example of the present application, the device further includes:

[0200] A lead distribution unit, used for redistributing the positions of the connecting leads in the wafer after the bonding process;

[0201] The pad layout unit is used to redesign the layout of pads in the wafer after the bonding process.

[0202] Further, based on any of the above embodiments, as an example of the present application, the lead distribution unit is specifically used to implement one of the following:

[0203] Adjusting the connecting lead at a first position in the first coordinate axis direction in the three-dimensional space in the wafer after the bonding process to a second position in the first coordinate axis direction or the second coordinate axis direction through the redistribution layer in the wafer after the bonding process;

[0204] Adjusting the connection lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process to a fourth position in the first coordinate axis direction or the second coordinate axis direction through the redistribution layer in the wafer after the bonding process;

[0205] Through the through silicon vias in the wafer after bonding, the connecting leads of any layer in the wafer after bonding are extended to another layer of the wafer after bonding along the third coordinate axis direction of the three-dimensional space.

[0206] Further, based on any of the above embodiments, as an example of the present application, the layout of the pads in the wafer after the bonding process is redesigned, including:

[0207] After the bonding process, a metal ball implantation operation is performed on the aluminum layer surface of the wafer to layout bumps on the aluminum layer surface to replace the pads of the initial wafer, wherein the bumps are used to directly connect with corresponding pad points during packaging.

[0208] It should be noted that the wafer preparation device provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0209] The functional units and modules in the above embodiments may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit, and the above integrated units may be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present application.

[0210] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0211] An embodiment of the present application further provides an electronic device, the electronic device comprising one or more processors and a memory;

[0212] The memory is coupled to one or more processors, and the memory is used to store computer program codes, the computer program codes include computer instructions, and one or more processors call the computer instructions to enable the electronic device to execute the wafer preparation and processing method shown above.

[0213] Fig.10The schematic diagram of the structure of an electronic device provided in the embodiment of the present application, the electronic device 700 can be a mobile phone, a smart screen, a tablet computer, a wearable electronic device, an in-vehicle electronic device, an augmented reality (AR) device, a virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a projector, or a communication device such as a server, a storage device, a base station, or a smart car, etc. The embodiment of the present application does not impose any restrictions on the specific type of the electronic device.

[0214] The memory 701 can be used to store computer software programs 702 and modules, and the processor 703 executes various functional applications and data processing of the electronic device by running the software programs and modules stored in the memory 701. The memory 701 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, a phone book, etc.), etc. In addition, the memory 701 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0215] Among them, the processor 703 may include one or more processors such as a central processing unit, an application processor (AP), a baseband processor, etc. The processor may be the nerve center and command center of the wireless router. The processor 703 may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions. The memory 701 may be used to store computer executable program codes, and the executable program codes include instructions. The processor 703 executes various functional applications and data processing of the network device by running the instructions stored in the memory. The memory 701 may include a program storage area and a data storage area, such as storing data of a sound signal to be played. For example, the memory may be a double rate synchronous dynamic random access memory DDR or a flash memory Flash.

[0216] An embodiment of the present application also provides a computer-readable storage medium, in which computer instructions are stored; when the computer-readable storage medium is run on an electronic device, the electronic device executes the wafer preparation and processing method shown above.

[0217] The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0218] The embodiment of the present application also provides a computer program product including computer instructions. When the computer program product is run on an electronic device, the electronic device can execute the wafer preparation and processing method shown above.

[0219] The computer storage medium and computer program product provided in the above-mentioned embodiments of the present application are used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the method provided above, and will not be repeated here.

[0220] In the above embodiments, it can also be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (such as: coaxial cable, optical fiber, data subscriber line (Digital Subscriber Line, DSL)) or wireless (such as: infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital versatile disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)).

[0221] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0222] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments applied for herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0223] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0224] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0225] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for preparing a wafer, characterized in that: include: Performing a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after the thinning process; According to the structural layers of the at least two wafers after the thinning process, performing wafer bonding process on the at least two wafers to obtain wafers after the bonding process; The wafer after the bonding process is packaged to obtain a composite wafer.

2. The method according to claim 1, characterized in that The step of performing a thinning operation on the structural layers of at least two initial wafers to obtain at least two wafers after thinning includes: Acquire structural layer data of at least two of the initial wafers, wherein the structural layers of the initial wafers include: a silicon layer, an aluminum layer, and a functional layer, and the functional designs of the functional layers of different initial wafers are different; Determining a corresponding predetermined thinning ratio according to the structural layer data; Based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer and / or the aluminum layer of at least two of the initial wafers respectively to obtain the at least two wafers after the thinning process.

3. The method according to claim 2, characterized in that The method of performing thinning operations on the silicon layer and / or the aluminum layer of at least two of the initial wafers based on the predetermined thinning ratio to obtain the at least two wafers after the thinning process comprises: In the case where the number of the initial wafers is two, based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer of the first wafer to obtain a first wafer after thinning; Based on the predetermined thinning ratio, a thinning operation is performed on the silicon layer and the aluminum layer of the second wafer to obtain the second wafer after the thinning process.

4. The method according to claim 3, characterized in that The method of performing wafer bonding on the at least two wafers according to the structural layers of the at least two wafers after the thinning process to obtain wafers after the bonding process comprises: Bonding the silicon layer of the first wafer after the thinning process with the aluminum layer of the second wafer after the thinning process to obtain a new synthetic layer; The first wafer after the thinning process and the second wafer after the thinning process are connected through the synthetic layer to obtain the bonding wafer.

5. The method according to claim 1, characterized in that Before packaging the wafer after the bonding process to obtain a composite wafer, the method further includes: reallocating the positions of the connecting leads in the wafer after the bonding process; The layout of the pads in the wafer after the bonding process is redesigned.

6. The method according to claim 5, characterized in that The reallocation of the positions of the connecting leads in the wafer after the bonding process comprises one of the following: By means of the redistribution layer in the wafer after the bonding process, the connecting lead at a first position in the first coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a second position in the first coordinate axis direction or the second coordinate axis direction; By means of the redistribution layer in the wafer after the bonding process, the connecting lead at the third position in the second coordinate axis direction in the three-dimensional space in the wafer after the bonding process is adjusted to a fourth position in the first coordinate axis direction or the second coordinate axis direction; Through the through silicon vias in the wafer after the bonding process, the connecting leads of any layer in the wafer after the bonding process are extended to another layer of the wafer after the bonding process along the third coordinate axis direction of the three-dimensional space.

7. The method according to claim 5, characterized in that The redesigning of the layout of the pads in the wafer after the bonding process comprises: A metal ball implantation operation is performed on the aluminum layer surface of the wafer after the bonding process to layout bumps on the aluminum layer surface to replace the pads of the initial wafer, wherein the bumps are used to directly connect with corresponding pads during packaging.

8. A wafer, characterized in that: The method is prepared by the method according to any one of claims 1 to 7.

9. An electronic chip, characterized in that: The method is prepared using the wafer as claimed in claim 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the electronic device implements the method according to any one of claims 1 to 7.

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