Semiconductor element

Abstract

A semiconductor device is provided, including a substrate, a first device structure layer, an interconnect structure layer, a second device structure layer, a pattern structure, a first guard ring and a second guard ring. The first device structure layer is disposed on the substrate. The interconnect structure layer is disposed on the first device structure layer and electrically connected to the first device structure layer. The interconnect structure layer includes a plurality of first pads located at a surface of the interconnect structure layer. The second element structure layer is disposed on the interconnect structure layer. The second element structure layer includes a plurality of second pads located at a surface of the second element structure layer. The pattern structure is disposed at a first interface between the interconnect structure layer and the second device structure layer. The first guard ring is disposed on the surface of the interconnect structure layer and surrounds the pattern structure. The second guard ring is disposed on the surface of the second device structure layer and surrounds the pattern structure. Each first connecting pad is connected with the corresponding second connecting pad, and the first protection ring is connected with the second protection ring.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a hybrid bonding structure. Background Art

[0002] In a general hybrid bonding process, two chips are bonded together with their active surfaces facing each other to form a bonding structure, wherein a dielectric layer of one chip is bonded to a dielectric layer of another chip, and a pad of one chip is bonded to a pad of another chip.

[0003] However, in addition to the pads, there are usually larger components, such as various mark structures, on the surface of the wafer. After the two wafers are bonded, when the bonded structure is subjected to high temperature or external force, the film peeling is likely to occur around the larger components at the bonding interface, and the film peeling may even extend to the entire wafer, causing damage to the wafer. Summary of the invention

[0004] The present invention provides a semiconductor element having a hybrid bonding structure, wherein a pattern structure having a larger width at a bonding interface is surrounded by a seal ring.

[0005] The semiconductor element of the present invention comprises a substrate, a first element structure layer, an internal connection structure layer, a second element structure layer, a pattern structure, a first guard ring and a second guard ring. The first element structure layer is arranged on the substrate. The internal connection structure layer is arranged on the first element structure layer and is electrically connected to the first element structure layer. The internal connection structure layer includes a plurality of first pads located at the surface of the internal connection structure layer. The second element structure layer is arranged on the internal connection structure layer. The second element structure layer includes a plurality of second pads located at the surface of the second element structure layer. The pattern structure is arranged at a first interface between the internal connection structure layer and the second element structure layer. The first guard ring is arranged at the surface of the internal connection structure layer and surrounds the pattern structure. The second guard ring is arranged at the surface of the second element structure layer and surrounds the pattern structure. Each of the first pads is connected to the corresponding second pad, and the first guard ring is connected to the second guard ring.

[0006] In an embodiment of the semiconductor device of the present invention, the width of the pattern structure is greater than the width of the first pad, and greater than the width of the second pad.

[0007] In an embodiment of the semiconductor device of the present invention, the width of the first guard ring is greater than or equal to half of the width of the first pad and less than or equal to three times the width of the first pad.

[0008] In an embodiment of the semiconductor device of the present invention, the width of the second guard ring is greater than or equal to half of the width of the second pad and less than or equal to three times the width of the second pad.

[0009] In an embodiment of the semiconductor device of the present invention, the width of the pattern structure is greater than or equal to 4 times the width of the first pad, and greater than or equal to 4 times the width of the second pad.

[0010] In an embodiment of the semiconductor device of the present invention, the pattern structure is not electrically connected to the interconnect structure layer, and is not electrically connected to the second device structure layer.

[0011] In an embodiment of the semiconductor device of the present invention, the pattern structure includes a marking mark or an alignment mark.

[0012] In an embodiment of the semiconductor device of the present invention, the pattern structure is located in the interconnect structure layer.

[0013] In an embodiment of the semiconductor device of the present invention, the distance between the first guard ring and the pattern structure is greater than or equal to twice the width of the first pad.

[0014] In an embodiment of the semiconductor device of the present invention, the pattern structure is located in the second device structure layer.

[0015] In an embodiment of the semiconductor device of the present invention, the distance between the second guard ring and the pattern structure is greater than or equal to twice the width of the second pad.

[0016] In one embodiment of the semiconductor element of the present invention, the multiple first pads include at least one first electrical connection pad and at least one first dummy pad, the multiple second pads include at least one second electrical connection pad and at least one second dummy pad, each of the first electrical connection pads is connected to the corresponding second electrical connection pad, and each of the first dummy pads is connected to the corresponding second dummy pad.

[0017] In an embodiment of the semiconductor device of the present invention, the first electrical connection pad is electrically connected to the first device structure layer.

[0018] In an embodiment of the semiconductor device of the present invention, the second electrical connection pad is electrically connected to the second device structure layer.

[0019] In an embodiment of the semiconductor device of the present invention, there is no first pad between the first guard ring and the pattern structure, and there is no second pad between the second guard ring and the pattern structure.

[0020] In an embodiment of the semiconductor device of the present invention, a width of the first guard ring is the same as a width of the second guard ring.

[0021] In an embodiment of the semiconductor device of the present invention, a width of the first guard ring is different from a width of the second guard ring.

[0022] In an embodiment of the semiconductor device of the present invention, a second interface is defined between the first pad and the second pad.

[0023] In an embodiment of the semiconductor device of the present invention, the second device structure layer includes a memory structure layer.

[0024] In an embodiment of the semiconductor device of the present invention, the memory structure layer includes a three-dimensional flash memory structure.

[0025] Based on the above, in the semiconductor device of the present invention, the first guard ring and the second guard ring surround the pattern structure. Therefore, when the semiconductor device is subjected to high temperature or external force in subsequent processes, the first guard ring and the second guard ring can effectively limit the area where film separation occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0027] Figure 2A for Figure 1 Schematic diagram of the top view of the internal connection structure layer in .

[0028] Figure 2B for Figure 1 Schematic top view of the second component structure layer in FIG.

[0029] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0030] Figure 4A for Figure 3 Schematic diagram of the top view of the internal connection structure layer in .

[0031] Figure 4B for Figure 3 Schematic top view of the second component structure layer in FIG.

[0032] Description of Reference Numerals

[0033] 10, 20: Semiconductor components

[0034] 100: First base

[0035] 102: Second base

[0036] 104: First component structure layer

[0037] 106: Internal connection structure layer

[0038] 108: First pad

[0039] 108a: first electrical connection pad

[0040] 108b: first dummy pad

[0041] 110: Pattern structure

[0042] 112: First protection ring

[0043] 114: Second component structure layer

[0044] 116: Second pad

[0045] 116a: second electrical connection pad

[0046] 116b: second dummy pad

[0047] 118: Second protection ring

[0048] CP1: First chip

[0049] CP2: Second chip DETAILED DESCRIPTION

[0050] The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same elements will be described with the same symbols in the following description.

[0051] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0052] When the terms "first", "second", etc. are used to describe elements, they are only used to distinguish these elements from each other, and do not limit the order or importance of these elements. Therefore, in some cases, the first element can also be called the second element, and the second element can also be called the first element, and this does not deviate from the scope of the present invention.

[0053] In addition, the directional terms mentioned herein, such as "upper", "lower", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

[0054] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.

[0055] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention.

[0056] Please refer to Figure 1 The semiconductor device 10 of the present embodiment includes a first substrate 100, a second substrate 102, a first device structure layer 104, an inner wiring structure layer 106, a pattern structure 110, a first protection ring 112, a second device structure layer 114, and a second protection ring 118. Depending on the types of the first device structure layer 104 and the second device structure layer 114, the semiconductor device 10 can be applied to various semiconductor devices, and the present invention is not limited to this. For example, the semiconductor device 10 can be applied to a three-dimensional NAND flash memory with high capacity and high performance. The semiconductor device 10 applied to a three-dimensional flash memory will be used as an example for description.

[0057] In this embodiment, the second substrate 102 is disposed on the first substrate 100. In this embodiment, the active surface of the first substrate 100 and the active surface of the second substrate 102 are opposite to each other. The first substrate 100 and the second substrate 102 can each be a silicon substrate or a silicon on insulator (SOI) substrate.

[0058] The first device structure layer 104 is disposed on the active surface of the first substrate 100 and is located between the first substrate 100 and the second substrate 102. In this embodiment, the first device structure layer 104 may include transistors, device isolation structures, contacts, a dielectric layer covering the above devices, etc., but the present invention is not limited thereto. Figure 1 , the first device structure layer 104 is simply illustrated as an example. The detailed structure of the first device structure layer 104 is well known to those skilled in the art and will not be further described herein.

[0059] The interconnect structure layer 106 is disposed on the first device structure layer 104 and is located between the first device structure layer 104 and the second substrate 102. The interconnect structure layer 106 is electrically connected to the first device structure layer 104. In the present embodiment, the interconnect structure layer 106 may include a plurality of circuit layers, a plurality of vias, a dielectric layer covering the above-mentioned devices, etc. In the interconnect structure layer 106, the bottommost circuit layer may be connected to the contact window in the first device structure layer 104, and the via may connect two adjacent circuit layers. Figure 1 , the interconnect structure layer 106 is simply illustrated as an example. The detailed structure of the interconnect structure layer 106 is well known to those skilled in the art, and thus will not be described separately.

[0060] In addition, the interconnect structure layer 106 includes a plurality of first pads 108. The first pads 108 are disposed on the surface of the interconnect structure layer 106. Specifically, in this embodiment, the first pads 108 are embedded in the interconnect structure layer 106 and include first electrical connection pads 108a and first dummy pads 108b. Figure 1 In the figure, the number of the first electrical connection pads 108a and the first dummy pads 108b is only used as an example, and the present invention is not limited thereto. The first electrical connection pads 108a can be electrically connected to the topmost circuit layer in the interconnect structure layer 106 to provide a function of electrical signal transmission and a bonding function. The first dummy pads 108b are not electrically connected to the components in the interconnect structure layer 106, and only provide a bonding function.

[0061] The pattern structure 110 and the first guard ring 112 are disposed on the surface of the interconnect structure layer 106. Specifically, in the present embodiment, the pattern structure 110 and the first guard ring 112 are embedded in the interconnect structure layer 106, and the first guard ring 112 surrounds the pattern structure 110. The pattern structure 110 and the first guard ring 112 are not electrically connected to the interconnect structure layer 106. The pattern structure 110 may be a marking mark, an alignment mark, or any other mark, and the present invention is not limited thereto.

[0062] Figure 2A FIG. 1 is a schematic top view of the interconnect structure layer 106. Figure 2A As shown, in this embodiment, the first pad 108 is disposed on the surface of the interconnect structure layer 106 and arranged in an array, but the present invention is not limited thereto. In addition, the pattern structure 110 and the first guard ring 112 are located outside the array area. The first guard ring 112 surrounds the pattern structure 110 and is not connected to the pattern structure 110. In this embodiment, the distance between the first guard ring 112 and the pattern structure 110 is, for example, greater than or equal to twice the width of the first pad 108. There is no first pad 108 between the first guard ring 112 and the pattern structure 110.

[0063] Compared to the first pad 108, the pattern structure 110 has a larger size. Since the pattern structure 110 has a larger size, a depression will be generated on the surface of the pattern structure 110 during the process of forming the pattern structure 110. In this embodiment, the width of the pattern structure 110 is greater than the width of the first pad 108. For example, the width of the pattern structure 110 may be greater than or equal to 4 times the width of the first pad 108. In addition, the width of the first guard ring 112 is greater than or equal to half the width of the first pad 108 and less than or equal to 3 times the width of the first pad 108. Figure 2A In the figure, the shapes of the first pad 108, the pattern structure 110 and the first guard ring 112 are only examples, and the present invention is not limited thereto.

[0064] The first substrate 100, the first device structure layer 104, the interconnect structure layer 106, the first pad 108, the pattern structure 110 and the first guard ring 112 can constitute the first chip CP1 in this embodiment. In other words, Figure 2A It can be regarded as a schematic top view of the first chip CP1.

[0065] Please continue to refer to Figure 1 , the second device structure layer 114 is disposed on the active surface of the second substrate 102 and is located between the interconnect structure layer 106 and the second substrate 102. In this embodiment, when the semiconductor device 10 is applied to a three-dimensional NAND flash memory, the second device structure layer 114 is a memory structure layer, which may at least include a stacked structure consisting of multiple insulating layers and multiple conductive layers, a vertical channel (VC) structure penetrating the stacked structure, a contact window, a dielectric layer covering the above-mentioned device, etc., but the present invention is not limited thereto. Figure 1 In the figure, the second device structure layer 114 is simply illustrated as an example. The detailed structure of the second device structure layer 114 is well known to those skilled in the art and will not be further described herein.

[0066] In other embodiments, when the semiconductor device 10 is applied to other semiconductor devices, the second device structure layer 114 may have a desired structure. For example, the second device structure layer may include structures similar to the first device structure layer 104 and the interconnect structure layer 106, which is not limited in the present invention.

[0067] In addition, the second device structure layer 114 includes a plurality of second pads 116. The second pads 116 are disposed on the surface of the second device structure layer 114. Specifically, in the present embodiment, the second pads 116 are embedded in the second device structure layer 114 and include second electrical connection pads 116a and second dummy pads 116b. The second electrical connection pads 116a can be electrically connected to the contact window or the conductive layer in the second device structure layer 114 to provide a function of transmitting electrical signals and a bonding function. The second dummy pads 116b are not electrically connected to the device in the second device structure layer 114 and only provide a bonding function.

[0068] The position and quantity of the second electrical connection pad 116a correspond to the position and quantity of the first electrical connection pad 108a, and the position and quantity of the second dummy pad 116b correspond to the position and quantity of the first dummy pad 108b. The second electrical connection pad 116a is connected to the corresponding first electrical connection pad 108a and has an interface therebetween, and the second dummy pad 116b is connected to the corresponding second dummy pad 108b and has an interface therebetween. In the present embodiment, the second electrical connection pad 116a is aligned with the corresponding first electrical connection pad 108a, and the second dummy pad 116b is aligned with the corresponding second dummy pad 108b, but the present invention is not limited thereto. In other embodiments, there may be an alignment offset between the second electrical connection pad 116a and the corresponding first electrical connection pad 108a, and there may be an alignment offset between the second dummy pad 116b and the corresponding second dummy pad 108b.

[0069] The second guard ring 118 is disposed at the surface of the second element structure layer 114. In detail, in the present embodiment, the second guard ring 118 is embedded in the second element structure layer 114. The second guard ring 118 is connected to the first guard ring 112, and there is an interface between the two. In addition, the position of the second guard ring 118 corresponds to the position of the first guard ring 112 to surround the pattern structure 110. The second guard ring 118 is not electrically connected to the second element structure layer 114. In the present embodiment, the second guard ring 118 is aligned with the first guard ring 112, but the present invention is not limited thereto. In other embodiments, there may be an alignment offset between the second guard ring 118 and the first guard ring 112.

[0070] Figure 2B FIG. 1 is a schematic top view of the interconnect structure layer 106. Figure 2B As shown, in this embodiment, the second pads 116 are disposed on the surface of the second device structure layer 114 and are arranged in an array manner corresponding to the first pads 116. In addition, the second guard ring 112 is located outside the array region corresponding to the first guard ring 112. The region surrounded by the second guard ring 118 does not have the second pads 116.

[0071] In this embodiment, the width of the second guard ring 112 is the same as the width of the first guard ring 112, but the present invention is not limited thereto. In other embodiments, the width of the second guard ring 112 may be different from the width of the first guard ring 112. In addition, the width of the second guard ring 112 is greater than or equal to half the width of the second pad 116 and less than or equal to 3 times the width of the second pad 116. Figure 2B The shapes of the second pad 116 and the second guard ring 118 are only examples, and the present invention is not limited thereto. The shapes of the second pad 116 and the second guard ring 118 may be the same as or different from the shapes of the first pad 108 and the first guard ring 112, and the present invention is not limited thereto.

[0072] The second substrate 102, the second device structure layer 114, the second pad 116 and the second protection ring 118 can constitute the second chip CP2 in this embodiment. Figure 2B It can be regarded as a top view of the second chip CP2.

[0073] As can be seen from the above, the semiconductor element 10 of the present embodiment includes a hybrid bonding structure formed by bonding the first chip CP1 and the second chip CP2 by hybrid bonding, and therefore there is an interface between the internal connection structure layer 106 of the first chip CP1 and the second element structure layer 114 of the second chip CP2, and the pattern structure 110 is located at the interface. In the present embodiment, the active surface of the first substrate 100 in the first chip CP1 and the active surface of the second substrate 102 in the second chip CP2 are opposite to each other, so the process of bonding the chips in the present embodiment is a face-to-face bonding process.

[0074] After the above-mentioned bonding process, the second substrate 102 in the second wafer CP2 may be processed. In one embodiment, the second substrate 102 may be thinned by grinding, polishing or etching from the back side of the second substrate 102 to form a thin film such as Figure 1 In another embodiment, the second substrate 102 in the second chip CP2 can be completely removed. In other words, in this case, in the semiconductor device 10, the second chip CP2 bonded to the interconnect structure layer 106 in the first chip CP1 only includes the second device structure layer 114.

[0075] In the semiconductor element 10, the first guard ring 112 surrounds the pattern structure 110, and the second guard ring 118 also surrounds the pattern structure 110. Therefore, when the semiconductor element 10 is subjected to high temperature or external force in the subsequent process, since the pattern structure 110 is surrounded by the first guard ring 112 and the second guard ring 118, even if film separation occurs around the air pocket AG, the film separation phenomenon will only be limited to the area surrounded by the first guard ring 112 and the area surrounded by the second guard ring 118, and will not affect the area outside the first guard ring 112 and the area outside the second guard ring 118. That is to say, in this embodiment, by providing the first guard ring 112 and the second guard ring 118, the influence of the air pocket AG on the element can be greatly reduced or even avoided.

[0076] Particularly, in the present embodiment, the width of the first guard ring 112 is greater than or equal to half of the width of the first pad 108 and less than or equal to three times the width of the first pad 108, and the width of the second guard ring 118 is greater than or equal to half of the width of the second pad 116 and less than or equal to three times the width of the second pad 116. Therefore, the first guard ring 112 and the second guard ring 118 can effectively reduce or even avoid the influence of air pockets AG on the device.

[0077] When the width of the first guard ring 112 is less than half the width of the first pad 108, the first guard ring 112 cannot be effectively connected to the second guard ring 118, and the phenomenon of film separation cannot be effectively limited to the area surrounded by the first guard ring 112. When the width of the second guard ring 118 is less than half the width of the second pad 116, the second guard ring 118 cannot be effectively connected to the first guard ring 112, and the phenomenon of film separation cannot be effectively limited to the area surrounded by the second guard ring 118.

[0078] In addition, when the width of the first guard ring 112 is greater than 3 times the width of the first pad 108, the first guard ring 112 may have a depression on the surface like the pattern structure 110, resulting in air pockets in the semiconductor device 10. When the width of the second guard ring 118 is greater than 3 times the width of the second pad 116, the second guard ring 118 may have a depression on the surface like the pattern structure 110, resulting in air pockets in the semiconductor device 10.

[0079] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention. Figure 4A for Figure 3 Schematic diagram of the top view of the internal connection structure layer in . Figure 4B for Figure 3In this embodiment, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described again.

[0080] Please also refer to Figure 3 , Figure 4A and Figure 4B The difference between the semiconductor element 20 of this embodiment and the semiconductor element 10 of the first embodiment is that: in the semiconductor element 20, the pattern structure 110 is located at the interface between the internal connection structure layer 106 of the first chip CP1 and the second element structure layer 114 of the second chip CP2, and is located on the surface of the second element structure layer 114.

[0081] In detail, in the present embodiment, the pattern structure 110 is embedded in the second device structure layer 114, and the second guard ring 118 surrounds the pattern structure 110. The pattern structure 110 is not electrically connected to the second device structure layer 114. The distance between the second guard ring 118 and the pattern structure 110 is, for example, greater than or equal to twice the width of the second pad 116. There is no second pad 116 between the second guard ring 118 and the pattern structure 110.

[0082] Compared to the second pad 116, the pattern structure 110 has a larger size. In the present embodiment, the width of the pattern structure 110 is greater than the width of the second pad 116. For example, the width of the pattern structure 110 may be greater than or equal to 4 times the width of the second pad 116. In addition, the width of the first guard ring 112 is greater than or equal to half the width of the first pad 108 and less than or equal to 3 times the width of the first pad 108, and the width of the second guard ring 118 is greater than or equal to half the width of the second pad 116 and less than or equal to 3 times the width of the second pad 116.

[0083] In this way, when the semiconductor element 20 is subjected to high temperature or external force in subsequent processes, since the pattern structure 110 is surrounded by the first guard ring 112 and the second guard ring 118, even if film separation occurs around the air cavity AG, the film separation phenomenon will only be limited to the area surrounded by the first guard ring 112 and the area surrounded by the second guard ring 118, and will not affect the area outside the first guard ring 112 and the area outside the second guard ring 118.

[0084] Although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the attached claims.

Claims

1. A semiconductor element, characterized in that: include: substrate; A first element structure layer is disposed on the substrate; An inner connection structure layer is disposed on the first element structure layer and is electrically connected to the first element structure layer, wherein the inner connection structure layer includes a plurality of first pads located on a surface of the inner connection structure layer; A second device structure layer is disposed on the inner connection structure layer, wherein the second device structure layer includes a plurality of second pads located on a surface of the second device structure layer; A pattern structure is disposed at a first interface between the inner connection structure layer and the second element structure layer; A first guard ring is disposed on the surface of the inner connection structure layer and surrounds the pattern structure; as well as A second guard ring is disposed on the surface of the second element structure layer and surrounds the pattern structure. Each of the first pads is connected to the corresponding second pad, and the first guard ring is connected to the second guard ring. 2 . The semiconductor device as claimed in claim 1 , wherein a width of the pattern structure is greater than a width of the first pad, and greater than a width of the second pad. 3 . The semiconductor device as claimed in claim 1 , wherein a width of the first guard ring is greater than or equal to half of a width of the first pad and less than or equal to three times of a width of the first pad. 4 . The semiconductor device as claimed in claim 1 , wherein a width of the second guard ring is greater than or equal to half of a width of the second pad and less than or equal to three times of a width of the second pad. 5 . The semiconductor device as claimed in claim 1 , wherein a width of the pattern structure is greater than or equal to 4 times a width of the first pad, and greater than or equal to 4 times a width of the second pad. 6 . The semiconductor device as claimed in claim 1 , wherein the pattern structure is not electrically connected to the interconnect structure layer, and is not electrically connected to the second device structure layer. 7 . The semiconductor device according to claim 6 , wherein the pattern structure comprises a marking mark or an alignment mark. 8 . The semiconductor device as claimed in claim 1 , wherein the pattern structure is located in the interconnect structure layer. 9 . The semiconductor device according to claim 8 , wherein a distance between the first guard ring and the pattern structure is greater than or equal to twice a width of the first pad. 10 . The semiconductor device according to claim 1 , wherein the pattern structure is located in the second device structure layer. 11 . The semiconductor device as claimed in claim 10 , wherein a distance between the second guard ring and the pattern structure is greater than or equal to twice a width of the second pad.

12. The semiconductor element according to claim 1, wherein the plurality of first pads include at least one first electrical connection pad and at least one first dummy pad, the plurality of second pads include at least one second electrical connection pad and at least one second dummy pad, each of the first electrical connection pads is connected to the corresponding second electrical connection pad, and each of the first dummy pads is connected to the corresponding second dummy pad. 13 . The semiconductor device as claimed in claim 12 , wherein the first electrical connection pad is electrically connected to the first device structure layer. 14 . The semiconductor device as claimed in claim 12 , wherein the second electrical connection pad is electrically connected to the second device structure layer. 15 . The semiconductor device as claimed in claim 1 , wherein there is no first pad between the first guard ring and the pattern structure, and there is no second pad between the second guard ring and the pattern structure. 16 . The semiconductor device according to claim 1 , wherein a width of the first guard ring is the same as a width of the second guard ring. 17 . The semiconductor device according to claim 1 , wherein a width of the first guard ring is different from a width of the second guard ring. 18 . The semiconductor device as claimed in claim 1 , wherein a second interface is defined between the first pad and the second pad.

19. The semiconductor device according to claim 1, wherein the second device structure layer comprises a memory structure layer.

20. The semiconductor device of claim 19, wherein the memory structure layer comprises a three-dimensional flash memory structure.

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