Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof. The packaging structure comprises a packaging carrier plate; the dielectric layer is located at the top of the packaging carrier plate; the one or more stacked re-wiring layers are located in the dielectric layer, and the top re-wiring layer is exposed out of the top surface of the dielectric layer; the plurality of adjacent chips are arranged at the top of the rewiring layer, and the sizes of the plurality of chips are not uniform; the anti-extrusion stress layer is located above the rewiring layer at the corner formed by the adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chips at the corner; and the plastic packaging layer is located at the top of the dielectric layer and the rewiring layer and covers the plurality of chips and the side wall of the anti-extrusion stress layer. In the thinning processing process, the anti-extrusion stress layer can effectively resist the extrusion force of chips accumulated at the corners enclosed by the adjacent chips towards the chip direction, so that the risk of cracks of the chips due to the extrusion force in the thinning processing process can be reduced, and the reliability of the packaging structure is further improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a method for forming the same. Background Art

[0002] As the demand for smaller size, more functions, high reliability and low cost increases, innovation in semiconductor advanced packaging technology becomes particularly important. Chiplet technology can integrate multiple chips into one packaging unit, realize functional modularization, improve the overall performance of the system, and save space and power consumption.

[0003] The number of chips integrated in the fan-out package structure unit is increasing, and the sizes of chips with different performances in the package structure unit are different. In the existing fan-out package (FOP) structure unit, because the difficulty of cutting each material (such as silicon, epoxy molding compound (EMC), underfill) is different, the material removal rate of each area inside the FOP is different when thinning. Specifically, multiple chips (such as SoC (system-on-chip), HBM chip (broadband memory), etc.) are located in the same FOP unit and mounted on the surface of the RDL layer (rewiring layer). Smaller chips will leave more vacant areas above the RDL layer, which are filled with EMC. During the thinning process, since EMC is easier to be removed than chips, the corner vacant area surrounded by adjacent chips is prone to generate steps with the surface of adjacent chips. The debris generated during the thinning process gathers in the corner vacant area and squeezes toward the higher step (i.e., the adjacent chip), causing the chip edge to bear huge extrusion stress and cracks.

[0004] Currently, the reliability of the packaging structure needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a method for forming the same, thereby improving the reliability of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, comprising: a packaging carrier; a dielectric layer, located on the top of the packaging carrier; one or more stacked rewiring layers, located in the dielectric layer, and the topmost rewiring layer exposes the top surface of the dielectric layer; a plurality of adjacent chips, arranged on the top of the rewiring layer, and the sizes of the plurality of chips are uneven; an anti-extrusion stress layer, located above the dielectric layer at a corner surrounded by adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chip located at the corner; and a plastic encapsulation layer, located on the top of the dielectric layer and the rewiring layer, and covering the side walls of the plurality of chips and the anti-extrusion stress layer.

[0007] Optionally, the packaging structure further includes: a first conductive bump, located on the bottom surface of the chip and electrically connected to the redistribution layer.

[0008] Optionally, the packaging structure further includes: an adhesive layer located on the top of the dielectric layer at a corner surrounded by adjacent chips; and the anti-extrusion stress layer covers the top surface of the adhesive layer.

[0009] Optionally, the material of the adhesive layer includes one or both of a resin adhesive and a double-sided adhesive film.

[0010] Optionally, the packaging structure further includes: a first bottom filling layer, located between the chip and the redistribution layer, and between the chip and the dielectric layer.

[0011] Optionally, the material of the anti-extrusion stress layer includes one or more of an inorganic non-metallic material, an organic resin polymer, and a composite material of an organic resin polymer.

[0012] Optionally, the packaging structure also includes: a second conductive bump, located on the bottom surface of the dielectric layer, and the top of the second conductive bump is electrically connected to the bottom layer of the rewiring layer, and the bottom of the second conductive bump is electrically connected to the packaging carrier; a second bottom filling layer, located between the dielectric layer and the packaging carrier, and between the bottom layer of the rewiring layer and the packaging carrier, and the second bottom filling layer covers the side walls of the second conductive bump.

[0013] Correspondingly, an embodiment of the present invention also provides a method for forming a packaging structure, comprising: providing a packaging carrier, a dielectric layer is formed on the top of the packaging carrier, one or more stacked rewiring layers are formed in the dielectric layer, and the topmost rewiring layer exposes the top surface of the dielectric layer; arranging a plurality of adjacent chips of uneven sizes on the top of the rewiring layer; forming an anti-extrusion stress layer above the dielectric layer at a corner surrounded by adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chip located at the corner; forming a plastic encapsulation layer covering the plurality of chips, the anti-extrusion stress layer, the dielectric layer and the rewiring layer; and thinning the plastic encapsulation layer, the anti-extrusion stress layer and the chip.

[0014] Optionally, the step of arranging a plurality of adjacent chips of non-uniform sizes on the top of the rewiring layer includes: providing a plurality of chips, each having a plurality of first conductive bumps formed on its bottom surface; sequentially welding the first conductive bumps of the plurality of chips to the rewiring layer through a welding process, and the first conductive bumps are electrically connected to the rewiring layer.

[0015] Optionally, the welding process includes a high temperature reflow process, a hot pressing welding process or a laser assisted bonding process.

[0016] Optionally, after arranging a plurality of the chips and before forming the anti-extrusion stress layer, the method for forming the packaging structure further includes: forming an adhesive layer on top of the dielectric layer at the corners surrounded by adjacent chips; and in the process of forming the anti-extrusion stress layer, the anti-extrusion stress layer covers the top surface of the adhesive layer.

[0017] Optionally, the material of the adhesive layer includes one or both of a resin adhesive and a double-sided adhesive film.

[0018] Optionally, the process of forming an adhesive layer on the top of the dielectric layer at the corners surrounded by adjacent chips includes a glue dispensing process or a film pasting process.

[0019] Optionally, after setting up a plurality of the chips and before forming the adhesive layer, the method for forming the packaging structure also includes: forming a first bottom filling layer between the chip and the topmost rewiring layer, and between the chip and the dielectric layer; in the process of forming the adhesive layer, the side wall of the adhesive layer contacts the side wall of the first bottom filling layer.

[0020] Optionally, in the step of forming the anti-extrusion stress layer, the top of the anti-extrusion stress layer is not lower than the top of the chip.

[0021] Optionally, the process of forming the anti-extrusion stress layer includes a mounting process.

[0022] Optionally, the material of the anti-extrusion stress layer includes one or more of a non-metallic material, an organic resin polymer, and an organic resin polymer composite material.

[0023] Optionally, in the step of providing a packaging carrier, a plurality of second conductive bumps are formed on the bottom surface of the dielectric layer, the tops of the second conductive bumps are electrically connected to the bottommost rewiring layer, the bottoms of the second conductive bumps are electrically connected to the packaging carrier, a second bottom filling layer is formed between the dielectric layer and the packaging carrier, and between the bottommost rewiring layer and the packaging carrier, and the second bottom filling layer covers the side walls of the second conductive bumps.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] In the packaging structure provided by the embodiment of the present invention, multiple adjacent chips are arranged on the top of the rewiring layer, and the sizes of the multiple chips are uneven. The anti-extrusion stress layer is located above the dielectric layer at the corner surrounded by the adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chip at the corner. The plastic encapsulation layer is located on the top of the dielectric layer and the rewiring layer, and covers the side walls of the multiple chips and the anti-extrusion stress layer. During the formation of the packaging structure, it is necessary to thin the multiple chips. By setting the anti-extrusion stress layer, during the thinning process, the anti-extrusion stress layer can effectively resist the extrusion force of debris accumulated at the corner surrounded by adjacent chips toward the chip, thereby reducing the risk of cracks in the chip due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0026] In the method for forming a packaging structure provided by an embodiment of the present invention, a plurality of adjacent chips of uneven size are arranged on the top of the rewiring layer, an anti-extrusion stress layer is formed above the dielectric layer at the corners surrounded by the adjacent chips, and the anti-extrusion stress layer surrounds the boundaries of the chips at the corners to form a plastic encapsulation layer covering the plurality of chips, the anti-extrusion stress layer, the dielectric layer and the rewiring layer, and the plastic encapsulation layer, the anti-extrusion stress layer and the chips are thinned. In the embodiment of the present invention, an anti-extrusion stress layer is formed above the dielectric layer at the corners surrounded by the adjacent chips. In the subsequent thinning process, the anti-extrusion stress layer can effectively resist the extrusion force of debris accumulated at the corners surrounded by the adjacent chips toward the chip, thereby reducing the risk of cracks in the chip due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 to Figure 2 A structural schematic diagram corresponding to a packaging structure is shown;

[0028] Figure 3 to Figure 4 is a schematic diagram of the structure corresponding to an embodiment of a packaging structure of the present invention;

[0029] Figures 5 to 14 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a packaging structure of the present invention. DETAILED DESCRIPTION

[0030] At present, the reliability of the packaging structure still needs to be improved. Now, the reasons why its performance still needs to be improved are analyzed in combination with a packaging structure.

[0031] Figure 1 to Figure 2 A structural schematic diagram corresponding to a packaging structure is shown.

[0032] refer to Figure 1 to Figure 2 ,in, Figure 1 It is a top view. Figure 2 yes Figure 1 In the cross-sectional view along the aa direction, the packaging structure includes: a packaging carrier 20; a dielectric layer 22, located on the top of the packaging carrier 20; one or more stacked rewiring layers 25, located in the dielectric layer 22, and the topmost rewiring layer 25 exposes the top surface of the dielectric layer 22; a plurality of adjacent chips 21, arranged on the top of the rewiring layer 25, and the sizes of the plurality of chips 21 are uneven; a plastic encapsulation layer 28, located on the top of the dielectric layer 22 and the rewiring layer 25, and covering the side walls of the plurality of chips 21.

[0033] Research has found that in the process of thinning the multiple chips 21 of the packaging structure, the plastic layer 28 is easier to be removed than the chip 21. Therefore, the debris generated during the thinning process is easy to accumulate at the corner 10A surrounded by adjacent chips 21. Long-term accumulation can easily cause the debris accumulated at the corner 10A surrounded by adjacent chips 21 to generate an extrusion pressure toward the inside of the chip 21, thereby increasing the risk of cracks in the chip 21 due to the extrusion pressure during the thinning process, thereby affecting the reliability of the packaging structure.

[0034] In order to solve the above technical problems, an embodiment of the present invention provides a packaging structure, including: a packaging carrier; a dielectric layer, located on the top of the packaging carrier; one or more stacked rewiring layers, located in the dielectric layer, and the topmost rewiring layer exposes the top surface of the dielectric layer; a plurality of adjacent chips, arranged on the top of the rewiring layer, and the sizes of the plurality of chips are uneven; an anti-extrusion stress layer, located above the dielectric layer at a corner surrounded by adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chip located at the corner; a plastic encapsulation layer, located on the top of the dielectric layer and the rewiring layer, and covering the side walls of the plurality of chips and the anti-extrusion stress layer.

[0035] In the packaging structure provided by the embodiment of the present invention, multiple adjacent chips are arranged on the top of the rewiring layer, and the sizes of the multiple chips are uneven. The anti-extrusion stress layer is located above the dielectric layer at the corner surrounded by the adjacent chips, and the anti-extrusion stress layer surrounds the boundary of the chip at the corner. The plastic encapsulation layer is located on the top of the dielectric layer and the rewiring layer, and covers the side walls of the multiple chips and the anti-extrusion stress layer. During the formation of the packaging structure, it is necessary to thin the multiple chips. By setting the anti-extrusion stress layer, during the thinning process, the anti-extrusion stress layer can effectively resist the extrusion force of debris accumulated at the corner surrounded by adjacent chips toward the chip, thereby reducing the risk of cracks in the chip due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0036] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figure 3 to Figure 4 : is a schematic diagram of the structure corresponding to an embodiment of the packaging structure of the present invention. Figure 3 It is a top view. Figure 4 yes Figure 3 Cross-sectional view along the AA direction.

[0038] The packaging structure includes: a packaging carrier 200; a dielectric layer 202, located on the top of the packaging carrier 200; one or more stacked rewiring layers 205, located in the dielectric layer 202, and the topmost rewiring layer 205 exposes the top surface of the dielectric layer 202; a plurality of adjacent chips 210, arranged on the top of the rewiring layer 205, and the sizes of the plurality of chips 210 are uneven; an anti-compression stress layer 226, located above the dielectric layer 202 at a corner 200A surrounded by adjacent chips 210, and the anti-compression stress layer 226 surrounds the boundary of the chip 210 located at the corner 200A; a plastic encapsulation layer 228, located on the top of the dielectric layer 202 and the rewiring layer 205, and covering the side walls of the plurality of chips 210 and the anti-compression stress layer 226.

[0039] It should be noted that multiple adjacent chips 210 are arranged on the top of the rewiring layer 205, and the sizes of the multiple chips 210 are uneven. The anti-extrusion stress layer 226 is located above the dielectric layer 202 at the corner 200A surrounded by the adjacent chips 210, and the anti-extrusion stress layer 226 surrounds the boundary of the chip 210 located at the corner 200A. The plastic encapsulation layer 228 is located on the top of the dielectric layer 202 and the rewiring layer 205, and covers the side walls of the multiple chips 210 and the anti-extrusion stress layer 226. During the formation of the packaging structure, the multiple chips 210 need to be thinned. By setting the anti-extrusion stress layer 226, during the thinning process, the anti-extrusion stress layer 226 can effectively resist the extrusion force of debris accumulated at the corner 200A surrounded by the adjacent chips 210 toward the chip 210, thereby reducing the risk of cracks in the chip 210 due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0040] Specifically, the packaging substrate 200 has a conductive circuit, which is used to supply power to the chip 210 or transmit electrical signals, thereby realizing the packaging and circuit integration of the chip 210. In addition, multiple chips 210 are integrated on the packaging substrate 200, which reduces the process difficulty of arranging the conductive circuit on the packaging substrate 200 and reduces the process cost.

[0041] In this embodiment, the package carrier 200 includes an organic substrate or a glass substrate having a circuit.

[0042] It should be noted that the dielectric layer 202 serves to electrically isolate the rewiring layers 205 , thereby reducing the risk of electrical leakage between adjacent rewiring layers 205 .

[0043] As an example, the material of the dielectric layer 202 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0044] It should be noted that the rewiring layer 205 is used to electrically connect to multiple chips 210. By setting up the rewiring layer 205, the input ports and output ports on the multiple chips 210 can be reallocated, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0045] As an example, the material of the redistribution layer 205 includes one or more of copper, aluminum and silver.

[0046] Specifically, the topmost rewiring layer 205 exposes the top surface of the dielectric layer 202 , which facilitates the electrical connection between the topmost rewiring layer 205 and the chip 210 , thereby enabling the chip 210 to be electrically connected to the package carrier 200 through the rewiring layer 205 .

[0047] In this embodiment, an interconnection through-hole structure 206 is provided in the dielectric layer 202 between adjacent rewiring layers 205 , and adjacent rewiring layers 205 are electrically connected via the interconnection through-hole structure 206 .

[0048] As an example, the material of the interconnect via structure 206 includes one or more of copper, tungsten, and cobalt.

[0049] In this embodiment, the packaging structure also includes: a second conductive bump 203, located on the bottom surface of the dielectric layer 202, and the top of the second conductive bump 203 is electrically connected to the bottom layer of the redistribution layer 205, and the bottom of the second conductive bump 203 is electrically connected to the packaging carrier 200.

[0050] It should be noted that the second conductive bump 203 is used to realize setting the rewiring layer 205 in the dielectric layer 202 on the packaging carrier 200, thereby reducing the risk of the packaging carrier 200 and the rewiring layer 205 in the dielectric layer 202 being separated from each other. At the same time, the second conductive bump 203 is also used to realize electrical connection between the rewiring layer 205 and the packaging carrier 200.

[0051] Specifically, during the formation of the packaging structure, the second conductive bump 203 is formed by an electroplating process, so that the second conductive bump 203 can be formed at a specified position on the bottom surface of the dielectric layer 202. At the same time, the second conductive bump 203 formed by the electroplating process has the characteristics of high connection reliability, which can reduce the risk of the second conductive bump 203 and the packaging carrier 200 falling off.

[0052] As an example, the material of the second conductive bump 203 includes one or more of gold, lead tin, silver tin, gold tin and copper tin.

[0053] In this embodiment, the packaging structure further includes: a second bottom filling layer 201 located between the dielectric layer 202 and the packaging carrier 200 , and between the bottommost redistribution layer 205 and the packaging carrier 200 , and the second bottom filling layer 201 covers the sidewalls of the second conductive bump 203 .

[0054] It should be noted that the second bottom filling layer 201 is used to adhere the bottommost rewiring layer 205 and the dielectric layer 202 to the packaging carrier 200, to prevent the risk of loosening or falling off between the rewiring layer 205 and the packaging carrier 200, and to improve the reliability of the packaging structure. At the same time, the second bottom filling layer 201 also protects the rewiring layer 205 and the packaging carrier 200, to prevent dust or moisture in the external environment from damaging the packaging structure.

[0055] As an example, the material of the second underfill layer 201 includes epoxy resin.

[0056] Specifically, a plurality of chips 210 are disposed on the top of the rewiring layer 205 to form a fan-out package (Fan Out Package, FOP) structure.

[0057] It should be noted that, specifically, the chip 210 is a chip with a specific function. Specifically, the type of the chip 210 is determined according to the actual functional requirements or application scenarios. For example, the chip 210 includes one or more of a system-on-chip (SoC), a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0058] It should also be noted that the sizes of chips with specific functions are not uniform in order to meet customer and process requirements.

[0059] In this embodiment, the packaging structure further includes: a first conductive bump 212 , which is located on the bottom surface of the chip 210 and electrically connected to the redistribution layer 205 .

[0060] It should be noted that the first conductive bump 212 is used to electrically lead out the chip 210, and the first conductive bump 212 is used to realize setting the chip 210 on the top-level rewiring layer 205, thereby reducing the risk of the chip 210 and the rewiring layer 205 being separated from each other. At the same time, the first conductive bump 212 is also used to realize the electrical connection between the chip 210 and the rewiring layer 205, so that the chip 210 can be electrically connected to the packaging carrier 200 through the first conductive bump 212.

[0061] Specifically, during the formation of the packaging structure, the first conductive bump 212 is formed by an electroplating process, so that the first conductive bump 212 can be formed at a specified position on the bottom surface of the chip 210. At the same time, the first conductive bump 212 formed by the electroplating process has the characteristics of high connection reliability, which can reduce the risk of the first conductive bump 212 and the top-layer rewiring layer 205 falling off.

[0062] As an example, the material of the first conductive bump 212 includes one or more of gold, lead tin, silver tin, gold tin, and copper tin.

[0063] In this embodiment, the packaging structure further includes: a first bottom filling layer 220 , which is located between the chip 210 and the topmost rewiring layer 205 , and between the chip 210 and the dielectric layer 202 .

[0064] It should be noted that the first bottom filling layer 220 is used to adhere the chip 210 to the topmost rewiring layer 205 to prevent the risk of loosening or falling off between the chip 210 and the rewiring layer 205, thereby improving the reliability of the packaging structure. At the same time, the first bottom filling layer 220 also protects the chip 210 and the rewiring layer 205, as well as the chip 210 and the dielectric layer 202, to prevent dust or moisture in the external environment from damaging the packaging structure.

[0065] As an example, the material of the first underfill layer 220 includes epoxy resin.

[0066] In this embodiment, the packaging structure further includes: an adhesive layer 221 located on the top of the interposer 202 at the corner 200A surrounded by the adjacent chips 210 .

[0067] It should be noted that the adhesive layer 221 is used to bond the anti-extrusion stress layer 226, so that the anti-extrusion stress layer 226 can be firmly adhered to the top of the dielectric layer 202 at the corner 200A surrounded by the adjacent chips 210. Accordingly, during the thinning process, the anti-extrusion stress layer 226 can effectively resist the extrusion force of debris accumulated at the corner 200A surrounded by the adjacent chips 210 toward the chip 210, so that the anti-extrusion stress layer 226 will not fall off due to the extrusion force, thereby reducing the risk of cracks in the chip 210 due to the extrusion force during the thinning process.

[0068] In this embodiment, the material of the adhesive layer 221 includes one or both of a resin adhesive and a double-sided adhesive film.

[0069] As an example, the side wall of the adhesive layer 221 contacts the side wall of the first bottom filling layer 220 , thereby preventing debris accumulation at the corner 200A formed by the chip 210 during the thinning process of the chip 210 and enabling the anti-extrusion stress layer 226 to provide maximum anti-extrusion stress protection for the chip 210 .

[0070] Specifically, in the method for forming the packaging structure, multiple chips 210 need to be thinned. By setting an anti-extrusion stress layer 226, during the thinning process, the anti-extrusion stress layer 226 can effectively resist the extrusion pressure of debris accumulated at the corner 200A surrounded by adjacent chips 210 toward the chip 210, thereby reducing the risk of cracks in the chip 210 due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0071] In this embodiment, the anti-extrusion stress layer 226 covers the top surface of the adhesive layer 221 .

[0072] Specifically, the anti-extrusion stress layer 226 covers the top surface of the adhesive layer 221, and the adhesive layer 221 plays a bonding role on the anti-extrusion stress layer 226, so that the anti-extrusion stress layer 226 can be firmly set on the top of the dielectric layer 202 at the corner 200A surrounded by the adjacent chips 210. Accordingly, during the thinning process, the anti-extrusion stress layer 226 can effectively resist the extrusion force of debris accumulated at the corner 200A surrounded by the adjacent chips 210 toward the chip 210, so that the anti-extrusion stress layer 226 will not be at risk of falling off due to the extrusion force.

[0073] In this embodiment, the material of the anti-extrusion stress layer 226 includes one or more of an inorganic non-metallic material, an organic resin polymer, and a composite material of an organic resin polymer.

[0074] It should be noted that the plastic encapsulation layer 228 protects the chip 210, the redistribution layer 205 and the packaging substrate 200, and can also reduce the probability of the chip 210 being damaged and contaminated. At the same time, the chip 210 and the packaging substrate 200 encapsulated by the plastic encapsulation layer 228 are also convenient for installation and transportation.

[0075] It should be noted that the plastic encapsulation layer 228 protects the chip 210, the redistribution layer 205 and the packaging carrier 200, prevents the chips 210 from being cross-wired with each other, and reduces the probability of the chip 210 being damaged and contaminated. At the same time, the chip 210 and the packaging carrier 200 encapsulated by the plastic encapsulation layer 228 are also convenient for installation and transportation.

[0076] In this embodiment, the material of the plastic encapsulation layer 228 includes a plastic encapsulation material. Specifically, the material of the plastic encapsulation material includes epoxy resin, which has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. It should be noted that the material of the plastic encapsulation material may also include one or more of a hardener, a catalyst, and a filler.

[0077] It should be noted that in the method of forming the packaging structure, the plastic layer 228 needs to be cured and baked to make the molecular chains in the plastic layer 228 cross-react more fully, so that it has more stable physical and chemical properties and releases the internal stress in the plastic layer 228.

[0078] Accordingly, an embodiment of the present invention further provides a method for forming a packaging structure. Figures 5 to 14 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a packaging structure of the present invention.

[0079] refer to Figure 5 , providing a packaging carrier 100, wherein a dielectric layer 102 is formed on the top of the packaging carrier 100, wherein one or more stacked redistribution layers 105 are formed in the dielectric layer 102, and the topmost redistribution layer 105 exposes the top surface of the dielectric layer 102.

[0080] Specifically, the packaging substrate 100 has a conductive circuit, which is used to supply power to the chip or transmit electrical signals, thereby realizing chip packaging and circuit integration. In addition, multiple chips are integrated on the packaging substrate 100, which reduces the process difficulty of arranging the conductive circuit on the packaging substrate 100 and reduces the process cost.

[0081] In this embodiment, the package carrier 100 includes an organic substrate or a glass substrate having a circuit.

[0082] It should be noted that the dielectric layer 102 serves to electrically isolate the rewiring layers 105 , thereby reducing the risk of electrical leakage between adjacent rewiring layers 105 .

[0083] As an example, the material of the dielectric layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

[0084] It should be noted that the rewiring layer 105 is used to electrically connect with multiple chips that are subsequently set up. By setting the rewiring layer 105, the input ports and output ports on multiple chips can be reallocated, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0085] As an example, the material of the redistribution layer 105 includes one or more of copper, aluminum and silver.

[0086] Specifically, the topmost rewiring layer 105 exposes the top surface of the dielectric layer 102 , which facilitates the subsequent electrical connection between the topmost rewiring layer 105 and the chip, so that the chip can be electrically connected to the package carrier 100 through the rewiring layer 105 .

[0087] In this embodiment, an interconnection via structure 106 is formed in the dielectric layer 102 between adjacent rewiring layers 105 , and adjacent rewiring layers 105 are electrically connected via the interconnection via structure 106 .

[0088] As an example, the material of the interconnect via structure 106 includes one or more of copper, tungsten, and cobalt.

[0089] In the present embodiment, in the step of providing the packaging carrier 100, a plurality of second conductive bumps 103 are formed on the bottom surface of the dielectric layer 102, the top of the second conductive bump 103 is electrically connected to the bottommost rewiring layer 105, the bottom of the second conductive bump 103 is electrically connected to the packaging carrier 100, and a second bottom filling layer 101 is formed between the dielectric layer 102 and the packaging carrier 100, and between the bottommost rewiring layer 105 and the packaging carrier 100, and the second bottom filling layer 101 covers the side walls of the second conductive bump 103.

[0090] It should be noted that the second conductive bump 103 is used to realize setting the bottom-level rewiring layer 105 in the dielectric layer 102 on the packaging carrier 100, thereby reducing the risk of the packaging carrier 100 and the bottom-level rewiring layer 105 in the dielectric layer 102 being separated from each other. At the same time, the second conductive bump 103 is also used to realize electrical connection between the rewiring layer 105 and the packaging carrier 100.

[0091] In this embodiment, the process of forming the plurality of second conductive bumps 103 on the bottom surface of the dielectric layer 102 includes an electroplating process.

[0092] Specifically, the second conductive bump 103 is formed by the electroplating process, so that the second conductive bump 103 can be formed at a specified position on the bottom surface of the dielectric layer 102. At the same time, the second conductive bump 103 formed by the electroplating process has the characteristics of high connection reliability, which can reduce the risk of the second conductive bump 103 and the packaging carrier 100 falling off.

[0093] As an example, the material of the second conductive bump 103 includes one or more of gold, lead tin, silver tin, gold tin and copper tin.

[0094] It should be noted that the second bottom filling layer 101 is used to adhere the bottommost rewiring layer 105 and the dielectric layer 102 to the packaging carrier 100, to prevent the risk of loosening or falling off between the rewiring layer 105 and the packaging carrier 100, and to improve the reliability of the packaging structure. At the same time, the second bottom filling layer 101 also protects the rewiring layer 105 and the packaging carrier 100, to prevent dust or moisture in the external environment from damaging the packaging structure.

[0095] As an example, the material of the second underfill layer 101 includes epoxy resin.

[0096] refer to Figure 6 to Figure 7 ,in, Figure 6 It is a top view. Figure 7 yes Figure 6 In the cross-sectional view along the AA direction, a plurality of adjacent chips 110 of non-uniform sizes are arranged on the top of the rewiring layer 105 .

[0097] Specifically, a plurality of chips 110 are disposed on the top of the rewiring layer 105 to form a fan-out package (Fan Out Package, FOP) structure.

[0098] It should be noted that, specifically, the chip 110 is a chip with a specific function. Specifically, the type of the chip 110 is determined according to the actual functional requirements or application scenarios. For example, the chip 110 includes one or more of a system-on-chip (SoC), a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0099] It should also be noted that the sizes of chips with specific functions are not uniform in order to meet customer and process requirements.

[0100] In this embodiment, the step of arranging a plurality of adjacent chips 110 of non-uniform sizes on the top of the rewiring layer 105 includes: providing a plurality of chips 110, wherein a plurality of first conductive bumps 112 are formed on the bottom surface of the chips 110; sequentially soldering the first conductive bumps 112 of the plurality of chips 110 to the rewiring layer 105 through a soldering process, and the first conductive bumps 112 are electrically connected to the rewiring layer 105.

[0101] It should be noted that the first conductive bump 112 is used to electrically lead out the chip 110, and the first conductive bump 112 is used to realize setting the chip 110 on the rewiring layer 105 to reduce the risk of the chip 110 and the rewiring layer 105 being separated from each other. At the same time, the first conductive bump 112 is also used to realize the electrical connection between the chip 110 and the rewiring layer 105, so that the chip 110 can be electrically connected to the packaging carrier 100 through the first conductive bump 112.

[0102] In this embodiment, the process of forming the plurality of first conductive bumps 112 on the bottom surface of the chip 110 includes an electroplating process.

[0103] Specifically, the first conductive bump 112 is formed by an electroplating process, so that the first conductive bump 112 can be formed at a specified position on the bottom surface of the chip 110, thereby facilitating the first conductive bump 112 to fit with the rewiring layer 105. At the same time, the first conductive bump 112 formed by the electroplating process has the characteristics of high connection reliability, which can reduce the risk of the first conductive bump 112 and the rewiring layer 105 falling off.

[0104] As an example, the material of the first conductive bump 112 includes one or more of gold, lead tin, silver tin, gold tin and copper tin.

[0105] In this embodiment, the welding process includes a high temperature reflow process, a hot pressing welding process or a laser assisted bonding process.

[0106] refer to Figure 8 After arranging a plurality of the chips 110 and before subsequently forming an adhesive layer, the method for forming a packaging structure further includes: forming a first bottom filling layer 120 between the chip 110 and the bottommost rewiring layer 105 and between the chip 110 and the dielectric layer 102 .

[0107] It should be noted that the first bottom filling layer 120 is used to adhere the chip 110 to the rewiring layer 105 to prevent the risk of loosening or falling off between the chip 110 and the rewiring layer 105, thereby improving the reliability of the packaging structure. At the same time, the first bottom filling layer 120 also protects the chip 110 and the rewiring layer 105, as well as the chip 110 and the dielectric layer 102, to prevent dust or moisture in the external environment from damaging the packaging structure.

[0108] As an example, the material of the first underfill layer 120 includes epoxy resin.

[0109] refer to Fig. 9 After arranging a plurality of the chips 110 and before subsequently forming an anti-extrusion stress layer, the method for forming a packaging structure further includes: forming an adhesive layer 121 on top of the dielectric layer 102 at a corner 100A surrounded by adjacent chips 110 .

[0110] It should be noted that the adhesive layer 121 is used to bond the subsequently formed anti-extrusion stress layer, so that the subsequently formed anti-extrusion stress layer can be firmly adhered to the top of the dielectric layer 102 at the corner 100A surrounded by the adjacent chips 110. Accordingly, in the subsequent thinning process, the anti-extrusion stress layer can effectively resist the extrusion pressure of debris accumulated at the corner 100A surrounded by the adjacent chips 110 toward the chip 110, so that the anti-extrusion stress layer will not fall off due to the extrusion pressure, thereby reducing the risk of cracks in the chip 110 due to the extrusion pressure during the thinning process.

[0111] In this embodiment, the material of the adhesive layer 121 includes one or both of a resin adhesive and a double-sided adhesive film.

[0112] In this embodiment, the process of forming the adhesive layer 121 on the top of the dielectric layer 102 at the corner 100A surrounded by the adjacent chips 110 includes a dispensing process or a film pasting process.

[0113] As an example, during the process of forming the adhesive layer 121 , a sidewall of the adhesive layer 121 contacts a sidewall of the first bottom filling layer 120 .

[0114] Specifically, the sidewalls of the adhesive layer 121 are in contact with the sidewalls of the first bottom filling layer 120 , thereby preventing debris accumulation at the corners 100A formed by the chip 110 during the thinning process of the chip 110 and enabling the subsequently formed anti-extrusion stress layer to provide maximum anti-extrusion stress protection for the chip 110 .

[0115] refer to Figure 10 to Figure 11 ,in, Fig.10 It is a top view. Fig.11 yes Fig.10In the cross-sectional view along the AA direction, an anti-compression stress layer 126 is formed above the dielectric layer 102 at the corner 100A surrounded by the adjacent chips 110 , and the anti-compression stress layer 126 surrounds the boundary of the chip 110 at the corner 100A.

[0116] Specifically, in the subsequent method for forming the packaging structure, it is necessary to perform a thinning process on multiple chips 110. By setting an anti-extrusion stress layer 126, during the thinning process, the anti-extrusion stress layer 126 can effectively resist the extrusion pressure of debris accumulated at the corner 100A surrounded by adjacent chips 110 toward the chip 110, thereby reducing the risk of cracks in the chip 110 due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0117] In this embodiment, during the process of forming the anti-extrusion stress layer 126 , the anti-extrusion stress layer 126 covers the top surface of the adhesive layer 121 .

[0118] Specifically, the anti-extrusion stress layer 126 covers the top surface of the adhesive layer 121, and the adhesive layer 121 plays a bonding role on the anti-extrusion stress layer 126, so that the anti-extrusion stress layer 126 can be firmly set on the top of the dielectric layer 102 at the corner 100A surrounded by the adjacent chips 110. Accordingly, in the subsequent thinning process, the anti-extrusion stress layer 126 can effectively resist the extrusion force of debris accumulated at the corner 100A surrounded by the adjacent chips 110 toward the chip 110, so that the anti-extrusion stress layer 126 will not be at risk of falling off due to the extrusion force.

[0119] In this embodiment, in the step of forming the anti-extrusion stress layer 126 , the top of the anti-extrusion stress layer 126 is not lower than the top of the chip 110 .

[0120] It should be noted that the top of the anti-extrusion stress layer 126 is not lower than the top of the chip 110, which means that the top of the anti-extrusion stress layer 126 is higher than or flush with the top of the chip 110. In the subsequent thinning process of multiple chips 110, the corner 100A surrounded by adjacent chips 110 can always have an anti-extrusion stress layer 126 to offset the extrusion force of debris toward the chip 110, thereby further reducing the risk of cracks in the chip 110 due to the extrusion force.

[0121] In this embodiment, the process of forming the anti-extrusion stress layer 126 includes a mounting process.

[0122] In this embodiment, the material of the anti-extrusion stress layer 126 includes one or more of an inorganic non-metallic material, an organic resin polymer, and a composite material of an organic resin polymer.

[0123] refer to Fig.12 , forming a plastic packaging layer 128 covering the plurality of chips 110 , the anti-extrusion stress layer 126 , the dielectric layer 102 and the rewiring layer 105 .

[0124] It should be noted that the plastic encapsulation layer 128 protects the chip 110, the redistribution layer 105 and the packaging substrate 100, and can also reduce the probability of the chip 110 being damaged and contaminated. At the same time, the chip 110 and the packaging substrate 100 encapsulated by the plastic encapsulation layer 128 are also convenient for installation and transportation.

[0125] In this embodiment, the material of the plastic encapsulation layer 128 includes a plastic encapsulation material. Specifically, the material of the plastic encapsulation material includes epoxy resin, which has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. It should be noted that the material of the plastic encapsulation material may also include one or more of a hardener, a catalyst and a filler.

[0126] It should be noted that in the method of forming the packaging structure, the plastic layer 128 needs to be cured and baked to make the molecular chains in the plastic layer 128 cross-react more fully, so that it has more stable physical and chemical properties and releases the internal stress in the plastic layer 128.

[0127] In this embodiment, the process of forming the plastic encapsulation layer 128 includes a molding process.

[0128] refer to Figure 13 to Figure 14 ,in, Fig.13 It is a top view. Fig.14 yes Fig.13 In the cross-sectional view along the AA direction, the plastic encapsulation layer 128 , the anti-extrusion stress layer 126 and the chip 110 are thinned.

[0129] Specifically, the plastic encapsulation layer 128, the anti-extrusion stress layer 126 and the chip 110 are thinned, and the thinned packaging unit can reduce the packaging size and help improve the heat dissipation efficiency of the packaging structure.

[0130] It should be noted that during the thinning process, the plastic layer 128 is easier to be removed than the chip 110. Therefore, the debris generated during the thinning process is easy to accumulate at the corner 100A surrounded by adjacent chips 110. The anti-extrusion stress layer 126 can effectively resist the extrusion pressure of the debris accumulated at the corner 100A surrounded by adjacent chips 110 in the direction of the chip 110, thereby reducing the risk of cracks in the chip 110 due to the extrusion force during the thinning process, thereby improving the reliability of the packaging structure.

[0131] In this embodiment, the plastic encapsulation layer 128, the anti-extrusion stress layer 126 and the chip 110 can be thinned by first rough grinding and then fine grinding. The rough grinding is performed quickly by a rough grinding machine, and the fine grinding is performed by, for example, a chemical mechanical grinding process.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: Package carrier board; A dielectric layer, located on the top of the packaging substrate; One or more stacked redistribution layers are located in the dielectric layer, and the topmost redistribution layer is exposed from the top surface of the dielectric layer; A plurality of adjacent chips are arranged on the top of the rewiring layer, and the sizes of the plurality of chips are non-uniform; an anti-compression stress layer, located above the dielectric layer at a corner formed by adjacent chips, and the anti-compression stress layer surrounds the boundary of the chip located at the corner; The plastic packaging layer is located on the top of the dielectric layer and the rewiring layer and covers the side walls of the plurality of chips and the anti-extrusion stress layer.

2. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first conductive bump located on the bottom surface of the chip and electrically connected to the redistribution layer.

3. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: an adhesive layer located on the top of the dielectric layer at the corners surrounded by the adjacent chips; The anti-extrusion stress layer covers the top surface of the adhesive layer.

4. The packaging structure according to claim 3, characterized in that: The material of the adhesive layer includes one or both of a resin adhesive and a double-sided adhesive film.

5. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first bottom filling layer, which is located between the chip and the topmost rewiring layer, and between the chip and the dielectric layer.

6. The packaging structure according to claim 1, characterized in that: The material of the anti-extrusion stress layer includes one or more of an inorganic non-metallic material, an organic resin polymer, and a composite material of an organic resin polymer.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a second conductive bump, located on the bottom surface of the dielectric layer, and the top of the second conductive bump is electrically connected to the bottommost rewiring layer, and the bottom of the second conductive bump is electrically connected to the packaging carrier; The second bottom filling layer is located between the dielectric layer and the package carrier, and between the bottommost redistribution layer and the package carrier, and the second bottom filling layer covers the sidewalls of the second conductive bumps.

8. A method for forming a packaging structure, characterized in that: include: Providing a packaging carrier, wherein a dielectric layer is formed on the top of the packaging carrier, one or more stacked rewiring layers are formed in the dielectric layer, and the topmost rewiring layer exposes the top surface of the dielectric layer; Arranging a plurality of adjacent chips of non-uniform size on top of the rewiring layer; forming an anti-extrusion stress layer above the dielectric layer at a corner surrounded by adjacent chips, wherein the anti-extrusion stress layer surrounds the boundary of the chip located at the corner; Forming a plastic encapsulation layer covering the plurality of chips, the anti-extrusion stress layer, the dielectric layer and the rewiring layer; The plastic sealing layer, the anti-extrusion stress layer and the chip are thinned.

9. The method for forming a package structure according to claim 8, wherein: The step of arranging a plurality of adjacent chips of uneven sizes on the top of the rewiring layer includes: providing a plurality of chips, wherein a plurality of first conductive bumps are formed on the bottom surface of the chips; sequentially welding the first conductive bumps of the plurality of chips to the rewiring layer through a welding process, and the first conductive bumps are electrically connected to the rewiring layer.

10. The method for forming a package structure according to claim 9, wherein: The welding process includes a high temperature reflow process, a hot pressing welding process or a laser assisted bonding process.

11. The method for forming a package structure according to claim 8, wherein: After arranging a plurality of the chips and before forming the anti-extrusion stress layer, the method for forming the packaging structure further comprises: forming an adhesive layer on the top of the dielectric layer at the corners surrounded by the adjacent chips; In the process of forming the anti-extrusion stress layer, the anti-extrusion stress layer covers the top surface of the adhesive layer.

12. The method for forming a package structure according to claim 11, wherein: The material of the adhesive layer includes one or both of a resin adhesive and a double-sided adhesive film.

13. The method for forming a package structure according to claim 11, wherein: The process of forming an adhesive layer on the top of the rewiring layer at the corners surrounded by the adjacent chips includes a glue dispensing process or a film pasting process.

14. The method for forming a package structure according to claim 11, wherein: After arranging a plurality of the chips and before forming the adhesive layer, the method for forming a packaging structure further comprises: forming a first bottom filling layer between the chip and the topmost rewiring layer and between the chip and the dielectric layer; During the process of forming the adhesive layer, a sidewall of the adhesive layer contacts a sidewall of the first underfill layer.

15. The method for forming a package structure according to claim 8, wherein: In the step of forming the anti-extrusion stress layer, the top of the anti-extrusion stress layer is not lower than the top of the chip.

16. The method for forming a package structure according to claim 8, wherein: The process of forming the anti-extrusion stress layer includes a mounting process.

17. The method for forming a package structure according to claim 8, wherein: The material of the anti-extrusion stress layer includes one or more of an inorganic non-metallic material, an organic resin polymer, and a composite material of an organic resin polymer.

18. The method for forming a package structure according to claim 8, wherein: In the step of providing a packaging carrier, a plurality of second conductive bumps are formed on the bottom surface of the dielectric layer, the tops of the second conductive bumps are electrically connected to the bottommost rewiring layer, the bottoms of the second conductive bumps are electrically connected to the packaging carrier, a second bottom filling layer is formed between the dielectric layer and the packaging carrier, and between the bottommost rewiring layer and the packaging carrier, and the second bottom filling layer covers the side walls of the second conductive bumps.

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