Wafer-scale system-in-package structure and forming method thereof

Abstract

The invention discloses a wafer-scale system-level packaging structure and a forming method thereof. The packaging structure comprises a silicon substrate and a plurality of functional sub-modules which are mounted on the upper surface of the silicon substrate, are arranged in an array and are electrically connected with the silicon substrate, the first bridging structure is attached to the upper surface of the silicon substrate at the edge of the functional sub-modules and is used for interconnecting the adjacent functional sub-modules; the second bridging structure is attached to the upper surface of the silicon substrate of the corner head of the functional sub-module and is used for interconnecting the adjacent functional sub-modules around the corner head; and the first plastic packaging layer is positioned on the upper surface of the silicon substrate and wraps the functional sub-module, the first bridging structure and the second bridging structure. According to the invention, the interconnection channel in the vertical direction is expanded, and the bandwidth of the wafer-scale system-in-package structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a wafer-scale system-level packaging structure and a method for forming the same. Background Art

[0002] System in Package (SiP) integrates chips with various functions such as optoelectronics, digital / logic, radio frequency, storage, etc. into a package in the form of chip stacking or package stacking, thereby realizing a system that can realize the above multiple functions.

[0003] The demand for data computing in today's emerging fields (mobile devices, artificial intelligence, automotive electronics, data storage, etc.) is growing exponentially. In order to meet the needs of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, the existing system-level packaging is expanding towards wafer scale, that is, integrating multiple chip sub-modules arranged in rows and columns on a silicon wafer to form a wafer-scale system-level packaging structure.

[0004] However, the interconnection channels and bandwidth (band-width) of the sub-modules of the existing wafer-scale system-level packaging structure are limited to interconnection through two-dimensional plane RDL rewiring, which still needs to be improved. Summary of the invention

[0005] The problem to be solved by the present application is to provide a wafer-scale system-level packaging structure and a method for forming the same, which expands the interconnection channels in the vertical direction and realizes three-dimensional interconnection to improve the bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0006] To solve the above problems, the present application first provides a wafer-scale system-level packaging structure, including: a silicon substrate comprising an upper surface and a lower surface opposite to each other; A plurality of functional submodules arranged in an array and mounted on the upper surface of the silicon substrate, each of the functional submodules comprising four corners and an edge between adjacent corners, the functional submodules being electrically connected to the silicon substrate; A first bridge structure mounted on the upper surface of the silicon substrate at the edge of the functional submodule, wherein the first bridge structure is used to interconnect adjacent functional submodules; A second bridge structure mounted on the upper surface of the silicon substrate of the corner head of the functional submodule, wherein the second bridge structure is used to interconnect the adjacent functional submodules around the corner head; The interconnection is located on the upper surface of the silicon substrate, and the first plastic sealing layer covers the functional sub-module, the first bridge structure and the second bridge structure, and the first plastic sealing layer exposes the upper surface of the functional sub-module, the first bridge structure and the second bridge structure.

[0007] In an optional embodiment, each of the functional sub-modules has the same structure, and the functional sub-modules include at least two semiconductor chips, which are mounted on the upper surface of the silicon substrate in a flip-chip manner; each functional sub-module also includes a bottom filling layer filled between the lower surface of the semiconductor chip in each functional sub-module and the upper surface of the silicon substrate and covering the side surfaces of the semiconductor chip.

[0008] In an optional embodiment, it also includes: edge dummy devices of different sizes mounted on the upper surface of the edge area of ​​the silicon substrate outside the functional sub-module array, the first plastic packaging layer also covers the edge dummy devices and exposes the upper surface of the edge dummy devices; the edge dummy devices are one or more of passive devices, heat dissipation discrete parts or dummy films.

[0009] In an optional embodiment, the first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, when the first bridging structure is mounted on the upper surface of the silicon substrate, the first welding protrusion is electrically connected to the silicon substrate, and the first bridging structure together with the silicon substrate interconnects adjacent functional sub-modules.

[0010] In an optional embodiment, the first supporting layer of the first bridging structure is a single-layer or multi-layer stacked structure.

[0011] In an optional embodiment, the material of the first supporting layer of the first bridging structure is one or more of silicon, silicon germanium, silicon carbide, glass, resin, and PCB core board.

[0012] In an optional embodiment, the number of first bridging structures surface-mounted on the silicon substrate at each edge of the functional submodule is at least two, and the plurality of first bridging structures are arranged in a direction parallel to the edge of the functional submodule.

[0013] In an optional embodiment, the second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, when the second bridging structure is mounted on the upper surface of the silicon substrate, the second welding protrusion is electrically connected to the silicon substrate, and the second bridging structure together with the silicon substrate interconnects the adjacent functional sub-modules around the corner head.

[0014] In an optional embodiment, the second supporting layer is a flexible structure, and the rigidity of the second supporting layer is less than the rigidity of the first plastic packaging layer.

[0015] In an optional embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the core layer has a blind hole, the blind hole is a cavity, or the blind hole is filled with filling material, the second buffer layer closes the opening of the blind hole, and the first plastic sealing layer exposes the upper surface of the second buffer layer; the side wall surface of the blind hole also has a metal layer.

[0016] In an optional embodiment, it also includes: a heat dissipation cover, the heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surface of the second buffer layer of the first plastic sealing layer, the functional sub-module, the first bridging structure and the second bridging structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0017] In an optional embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer, and the first plastic packaging layer exposes the blind holes; the side wall surface of the blind hole also has a metal layer.

[0018] In an optional embodiment, it also includes: a heat dissipation cover, the heat dissipation cover including a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the first plastic sealing layer, the functional sub-module, the first bridging structure and the second bridging structure, the anchoring protrusions are mounted in the corresponding blind holes by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0019] In an optional embodiment, the silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body, and the silicon wafer body has a silicon through-hole, and the silicon through-hole electrically connects the first redistribution layer and the second redistribution layer.

[0020] In an optional embodiment, the functional sub-modules, the first bridging structure and the second bridging structure are respectively electrically connected to different parts of the first redistribution layer, and adjacent functional sub-modules are interconnected through the first bridging structure and / or the second bridging structure and through part of the first redistribution layer in the silicon substrate.

[0021] In an optional embodiment, it also includes: a bridge chip mounted on the lower surface of the silicon substrate, the bridge chip is electrically connected to a portion of the second redistribution layer, and the bridge chip interconnects the adjacent functional sub-modules above the bridge chip through a portion of the second redistribution layer, the through silicon via and a portion of the first redistribution layer.

[0022] In an optional embodiment, it also includes: a metal bump protruding from the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, the lower surface of the metal bump being no lower than the lower surface of the bridge chip; edge dummy devices of different sizes mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; and a second plastic encapsulation layer located on the lower surface of the silicon substrate and covering the bridge chip, the metal bump and the edge dummy device, the second plastic encapsulation layer exposing the lower surface of the bridge chip, the metal bump and the edge dummy device.

[0023] In an optional embodiment, it also includes: a power supply module mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bump, the power supply module supplies power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

[0024] In an optional embodiment, it also includes: a bonding material for fixing the four corners of the power supply module to the corresponding lower surface of the second plastic packaging layer.

[0025] In an optional embodiment, it also includes: a metal bump protruding from the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, the lower surface of the metal bump being no lower than the lower surface of the bridge chip; a power supply module mounted on the lower surface of the metal bump; edge dummy devices of different sizes mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; and a second plastic packaging layer located on the lower surface of the silicon substrate and covering the bridge chip, the metal bump, the power supply module and the edge dummy device, the second plastic packaging layer exposing the lower surfaces of the power supply module and the edge dummy device.

[0026] The present application also provides a method for forming a wafer-scale system-level packaging structure, comprising: Providing a silicon substrate, the silicon substrate comprising an upper surface and a lower surface opposite to each other; Mounting a plurality of functional submodules arranged in an array on the surface of the silicon substrate, each of the functional submodules comprising four corners and an edge between adjacent corners, the functional submodules being electrically connected to the silicon substrate; A first bridge structure is mounted on the surface of the silicon substrate at the edge of the functional submodule, wherein the first bridge structure is used to interconnect adjacent functional submodules; A second bridge structure is mounted on the surface of the silicon substrate of the corner head of the functional submodule, and the second bridge structure is used to interconnect the adjacent functional submodules around the corner head; A first plastic encapsulation layer covering the functional submodule, the first bridge structure and the second bridge structure is formed on the upper surface of the silicon substrate, and the first plastic encapsulation layer exposes the upper surfaces of the functional submodule, the first bridge structure and the second bridge structure.

[0027] In an optional embodiment, edge dummy devices of different sizes are mounted on the upper surface of the edge area of ​​the silicon substrate outside the functional sub-module array, and the first plastic packaging layer also covers the edge dummy devices and exposes the upper surface of the edge dummy devices; the edge dummy devices are one or more of passive devices, heat dissipation discrete parts or dummy films.

[0028] In an optional embodiment, the first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, and the first welding protrusion is electrically connected to the silicon substrate.

[0029] In an optional embodiment, the second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, and the second welding protrusion is electrically connected to the silicon substrate.

[0030] In an optional embodiment, the second supporting layer is a flexible structure, and the rigidity of the second supporting layer is less than the rigidity of the first plastic packaging layer.

[0031] In an optional embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes that penetrate the second buffer layer and the core layer, and the first plastic sealing layer exposes the blind holes; and also includes: a heat dissipation cover, the heat dissipation cover includes a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the first plastic sealing layer, the functional sub-module and the first bridging structure, the anchoring protrusions are mounted in the corresponding blind holes by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0032] In an optional embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the core layer has a blind hole, the blind hole is a cavity, or the blind hole is filled with filling material, the second buffer layer closes the opening of the blind hole, the first plastic sealing layer exposes the upper surface of the second buffer layer, and the side wall surface of the blind hole also has a metal layer; it also includes: a heat dissipation cover is mounted, the heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the second buffer layer of the first plastic sealing layer, the functional sub-module, the first bridging structure and the second bridging structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0033] In an optional embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer, the first plastic sealing layer exposes the blind holes, and the side wall surface of the blind hole also has a metal layer; it also includes: a heat dissipation cover, the heat dissipation cover includes a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the first plastic sealing layer, the functional sub-module, the first bridging structure and the second bridging structure, the anchoring protrusions are mounted in the corresponding blind holes by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0034] In an optional embodiment, the silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body, the silicon wafer body has a through silicon via, and the through silicon via electrically connects the first redistribution layer and the second redistribution layer; the functional sub-modules, the first bridging structure and the second bridging structure are respectively electrically connected to different parts of the first redistribution layer, and adjacent functional sub-modules are interconnected through the first bridging structure and / or the second bridging structure and through part of the first redistribution layer in the silicon substrate.

[0035] In an optional embodiment, it also includes: mounting a bridge chip on the lower surface of the silicon substrate, the bridge chip is electrically connected to a portion of the second redistribution layer, and the bridge chip interconnects the adjacent functional sub-modules above the bridge chip through a portion of the second redistribution layer, the through silicon via and a portion of the first wiring layer.

[0036] In an optional embodiment, it also includes: forming a raised metal bump on the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, the lower surface of the metal bump is not lower than the lower surface of the bridge chip; mounting edge dummy devices of different sizes on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; forming a second plastic encapsulation layer on the lower surface of the silicon substrate to cover the bridge chip, the edge dummy device and the metal bump, the second plastic encapsulation layer exposing the lower surface of the bridge chip, the metal bump and the edge dummy device.

[0037] In an optional embodiment, a power supply module is mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bump, and the power supply module is used to supply power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

[0038] In an optional embodiment, a bonding material is formed to fix four corners of the power supply module to the corresponding lower surface of the second plastic packaging layer.

[0039] In an optional embodiment, a raised metal bump connected to a portion of the second redistribution layer is formed on the lower surface of the silicon substrate, and the lower surface of the metal bump is not lower than the lower surface of the bridge chip; a power supply module is mounted on the lower surface of the metal bump; edge dummy devices of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; and a second plastic packaging layer covering the bridge chip, the metal bump, the power supply module and the edge dummy device is formed on the lower surface of the silicon substrate, and the second plastic packaging layer exposes the lower surfaces of the power supply module and the edge dummy device.

[0040] The advantages of the technical solution of this application are: The wafer-scale system-level packaging structure and its formation method in the aforementioned embodiments of the present application, in one embodiment, the packaging structure includes a silicon substrate, the silicon substrate includes relative upper and lower surfaces; a plurality of functional sub-modules arranged in an array and mounted on the upper surface of the silicon substrate, and each of the functional sub-modules includes four corner heads and an edge located between adjacent corner heads, and the functional sub-modules are electrically connected to the silicon substrate; a first bridging structure mounted on the upper surface of the silicon substrate at the edge of the functional sub-module, the first bridging structure is used to interconnect adjacent functional sub-modules; a second bridging structure mounted on the upper surface of the silicon substrate at the corner head of the functional sub-module, the second bridging structure is used to interconnect adjacent functional sub-modules around the corner head; a first plastic sealing layer located on the upper surface of the silicon substrate covering the functional sub-module, the first bridging structure and the second bridging structure, the first plastic sealing layer exposing the upper surfaces of the functional sub-module, the first bridging structure and the second bridging structure. In the present application, in addition to being electrically connected to the silicon substrate wiring, adjacent functional sub-modules can also be interconnected through the first bridge structure and the second bridge structure, so that the channels for interconnection between adjacent functional sub-modules are increased, thereby improving the bandwidth (band-width) between adjacent functional sub-modules, and further improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0041] Furthermore, in one embodiment, the wafer-scale system-level packaging structure also includes: a bridge chip mounted on the lower surface of the silicon substrate, the bridge chip being electrically connected to a portion of the second redistribution layer, the bridge chip being used to interconnect the adjacent functional sub-modules above the bridge chip through a portion of the second redistribution layer, the through silicon vias and a portion of the first redistribution layer, thereby achieving diversity in interconnection between adjacent functional sub-modules, further increasing the bandwidth (band-width) between adjacent functional sub-modules, and thereby increasing the overall bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0042] Further, in one embodiment, the second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, and the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer. On the one hand, the second supporting layer of the second bridging structure of the structure has a smaller rigidity, thereby more effectively buffering and balancing the larger stress existing at and near the corners of adjacent functional submodules. On the other hand, when mounting the heat dissipation cover, the second supporting layer provides support for the corresponding lower surface of the horizontal cover top of the heat dissipation cover. The support and buffer pads provide a mounting interface for the anchoring protrusions on the lower surface of the heat dissipation cover. At the same time, when the heat dissipation cover is mounted, the anchoring protrusions on the lower surface of the heat dissipation cover are correspondingly mounted in the corresponding blind holes, that is, the blind holes also provide limiting space for the anchoring protrusions on the lower surface of the heat dissipation cover, thereby improving the alignment accuracy when mounting the heat dissipation cover, and limiting the mounting accuracy of the heat dissipation cover during the mounting process and the bonding process of the heat dissipation cover. When the anchoring protrusions on the corresponding lower surface of the horizontal cover top of the heat dissipation cover are correspondingly mounted in the corresponding blind holes, the anchoring protrusions are locked in the blind holes, thereby improving the firmness of the mounting of the heat dissipation cover.

[0043] Furthermore, in one embodiment, a plurality of edge dummy devices of different sizes are mounted on the upper surface of the edge region of the silicon substrate, so that the amount of the first plastic encapsulation layer on the upper surface of the edge region of the silicon substrate is reduced, thereby increasing the Si / EMC ratio (EMC is a plastic encapsulation material) of the edge region, thereby reducing the difference between the Si / EMC ratio of the edge region and the Si / EMC ratio of the middle region, thereby preventing the warping problem of the wafer-scale system-level packaging structure caused by the large difference in the Si / EMC ratio between the edge region and the middle region. In one embodiment, a plurality of edge dummy devices of different sizes are mounted on the lower surface of the edge region of the silicon substrate, so that the amount of the second plastic encapsulation layer on the lower surface of the edge region of the silicon substrate is reduced, thereby increasing the Si / EMC ratio (EMC is a plastic encapsulation material) of the edge region, thereby reducing the difference between the Si / EMC ratio of the edge region and the Si / EMC ratio of the middle region, thereby preventing the warping problem of the wafer-scale system-level packaging structure caused by the large difference in the Si / EMC ratio between the edge region and the middle region. Through the application of the above edge dummy devices, the warping of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature is effectively regulated. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of a top view of a wafer-scale system-level packaging structure in an embodiment of the present application; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1; Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line BB1; Figure 4 This is a schematic structural diagram of a second bridging structure in an embodiment of the present application; Figure 5 This is a structural schematic diagram of a second bridging structure in another embodiment of the present application; Figure 6 It is a schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 7 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 8 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Fig. 9 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Fig.10 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Fig.11 It is a structural schematic diagram of a wafer-scale system-level packaging structure in another embodiment of the present application. DETAILED DESCRIPTION

[0045] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0046] An embodiment of the present application first provides a system-level packaging structure. Figure 1-Figure 3 ,in Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 The schematic diagram of the cross-sectional structure along the cutting line BB1 ​​includes: A silicon substrate 103, wherein the silicon substrate 103 includes an upper surface and a lower surface opposite to each other; A plurality of functional submodules 20 arranged in an array and mounted on the upper surface of the silicon substrate 103, wherein each of the functional submodules 20 includes four corners and an edge between adjacent corners, and the functional submodules 20 are electrically connected to the silicon substrate 103; A first bridge structure 421 mounted on the upper surface of the silicon substrate 103 at the edge of the functional sub-module 20, wherein the first bridge structure 421 is used to interconnect adjacent functional sub-modules 20; A second bridge structure 422 mounted on the upper surface of the silicon substrate 103 of the corner of the functional submodule 20, wherein the second bridge structure 422 is used to interconnect the adjacent functional submodules 20 around the corner; The first plastic encapsulation layer 111 covering the functional submodule 20 , the first bridge structure 421 and the second bridge structure 422 is located on the upper surface of the silicon substrate 103 , and the first plastic encapsulation layer 111 exposes the upper surfaces of the functional submodule 20 , the first bridge structure 421 and the second bridge structure 422 .

[0047] Specifically, the silicon substrate 103 includes a silicon wafer body 100 , a first redistribution layer 101 located on an upper surface of the silicon wafer body 100 , and a second redistribution layer 102 located on a lower surface of the silicon wafer body 100 .

[0048] The first redistribution layer 101 is located on the upper surface of the silicon wafer body 100, and the functional submodule 20, the first bridge structure 421 and the second bridge structure 422 are respectively electrically connected to different parts of the first redistribution layer 101. The electrical connection between the functional submodule 20 and the silicon substrate 103 includes: the plurality of functional submodules 20 are electrically connected to a part of the first redistribution layer 101 in the silicon substrate 103, and may also include: adjacent functional submodules 20 are interconnected through the first bridge structure 421 and / or the second bridge structure 422 and through a part of the first redistribution layer 101 in the silicon substrate 103, so that the interconnection channels between adjacent functional submodules 20 are increased (in addition to the wiring in the silicon substrate 103, the first bridge structure 421 and / or the second bridge structure 422 are also included), so that the bandwidth (band-width) between adjacent functional submodules 20 is increased, thereby improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure. The material of the silicon wafer body 100 is silicon, and the silicon wafer body 100 can be round or square, and the shape of the silicon substrate 103 is also round or square accordingly. In this embodiment, the packaging structure is a wafer-scale system-level packaging structure. The size of the wafer-scale system-level packaging structure is relatively large, and the corresponding sizes of the silicon wafer body 100 and the silicon substrate 103 are also relatively large. In a specific embodiment, when the silicon wafer body 100 and the silicon substrate 103 are round, the diameter size of the silicon wafer body 100 and the silicon substrate 103 can be 300mm, 450±5mm, and when the silicon wafer body 100 and the silicon substrate 103 are square, the diagonal size of the silicon wafer body 100 and the silicon substrate 103 can be 300mm, 450±10mm.

[0049] In one embodiment, the silicon wafer body 100 has a through silicon via 104 and a micro device (not shown in the figure), and the through silicon via 104 is electrically connected to the first redistribution layer 101 and the second redistribution layer 102. In a specific embodiment, the through silicon via 104 is located in the silicon wafer body, and the through silicon via 104 passes through the upper surface and the lower surface of the silicon wafer body 100, the upper end of the through silicon via 104 is electrically connected to the first redistribution layer 101, and the lower end of the through silicon via 104 is electrically connected to the second redistribution layer 102. The material of the through silicon via 104 is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The micro-device can be electrically connected to the first redistribution layer 101, and the micro-device and the first redistribution layer 101 (and the second redistribution layer 102) can cooperate to form a circuit with a specific function, and the specific function can be one or more of signal decoupling and voltage stabilization, anti-static and overvoltage protection or signal filtering, and the specific function can also include other suitable functions. The micro-device can be formed inside the silicon wafer body 100 and / or on the upper surface of the silicon wafer body 100 through a semiconductor integrated manufacturing process. In one embodiment, the micro-device is one or more of a deep trench silicon capacitor (Deep Trench Capacitor, DTC), a protective diode, and a grounding inductor. The high-density trench silicon capacitor can be used for decoupling and voltage stabilization, the protective diode can be used for anti-static and overvoltage protection, and the grounding inductor can be used for signal filtering or isolation.

[0050] In a specific embodiment, the first rewiring layer 101 includes a first passivation layer 106 located on the upper surface of the silicon wafer body 100 and a first wiring 105 located in the first passivation layer 106. When the through silicon via 104 is electrically connected to the first rewiring layer 101 and the functional submodule 20 is electrically connected to the first rewiring layer 101, the through silicon via 104 is electrically connected to the corresponding part of the first wiring 105 in the first rewiring layer 101. In an embodiment, the first passivation layer 106 can be a single-layer or multi-layer stacked structure, and the corresponding first wiring 105 can also be a single-layer or multi-layer circuit structure. The material of the first passivation layer 106 can be an inorganic material or an organic material. The inorganic material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The organic material can be a polymer resin material, which can specifically include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the first wiring 105 is metal, specifically, one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In a specific embodiment, the first passivation layer 106 is a double-layer stacked structure, including an inorganic material passivation layer located on the upper surface of the silicon wafer body 100 and an organic material passivation layer located on the upper surface of the inorganic material passivation layer.

[0051] The second redistribution layer 102 is located on the lower surface of the silicon wafer body 100. In one embodiment, the second redistribution layer 102 includes a second passivation layer 108 located on the lower surface of the silicon wafer body 100 and a second wiring 107 located in the second passivation layer 108. When the through silicon via 104 is electrically connected to the second redistribution layer 102, the through silicon via 104 is electrically connected to the corresponding part of the second wiring 107 in the second redistribution layer 102. In a specific embodiment, the second passivation layer 108 can be a single-layer or multi-layer stacked structure, and the corresponding second wiring 107 can also be a single-layer or multi-layer circuit structure. The material of the second passivation layer 108 can be an inorganic material or an organic material. The inorganic material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The organic material can be a polymer resin material, which can specifically include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The material of the second wiring 107 is metal, specifically, one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. In a specific embodiment, the second passivation layer 108 is a double-layer stacked structure, including an inorganic material passivation layer located on the lower surface of the silicon wafer body 100 and an organic material passivation layer located on the lower surface of the inorganic material passivation layer.

[0052] In one embodiment, the silicon substrate 103 may include a middle region 11 and an edge region 12 surrounding the middle region 11 , and the functional sub-modules 20 , the first bridge structure 421 and the second bridge structure 422 are mounted on the upper surface of the middle region 11 .

[0053] The functional submodules 20 are chip modules with specific functions. Several functional submodules 20 are arranged in an array and mounted on the upper surface of the silicon substrate 103. The number of the functional submodules 20 is at least 2, and can be 2, 4, 9, 16, 25 or more (for example, N 2 , N is greater than 5), several functional sub-modules 20 can be arranged in AXB arrays such as 1X1, 2X2, 3X3, 4X4, 5X5 (A does not have to be equal to B) or more arrays and mounted on the upper surface of the silicon substrate 103. Figure 1 As shown, nine functional sub-modules 20 are arranged in a 3×3 array and mounted on the upper surface of the silicon substrate 103 as an example.

[0054] In one embodiment, each of the functional submodules 20 has the same structure and function. The plane layout of each of the functional submodules 20 may be a cuboid or a cube. Each of the functional submodules 20 includes four corners and edges between adjacent corners, that is, four corners and four edges. In other embodiments, the plane layout of the functional submodule 20 may be in other shapes, such as a cuboid, a cube, a parallelogram or other regular three-dimensional shapes. In one embodiment, each of the submodules 20 includes at least two semiconductor chips 201. In a specific embodiment, when each of the submodules 20 includes at least two semiconductor chips 201, the sizes and / or functions of the at least two semiconductor chips 201 are different. In another specific embodiment, when each of the submodules 20 includes at least two semiconductor chips 201, the sizes and / or functions of some of the semiconductor chips 201 may be the same, and the sizes and / or functions of some of the semiconductor chips 201 may be different. In one embodiment, the semiconductor chips 201 include but are not limited to signal processing chips, logic control chips, storage chips, sensor chips, power chips or radio frequency chips.

[0055] The functional submodule 20 is mounted on the upper surface of the silicon substrate 103, including: the semiconductor chip 201 in each functional submodule 20 is mounted on the upper surface of the silicon substrate 103 by flip-chip method. In one embodiment, the semiconductor chip 201 includes an active surface and a back surface opposite to each other, and the active surface has a welding protrusion 203. An integrated circuit (not shown in the figure) with a specific function is formed in the semiconductor chip 201, and the welding protrusion 203 is electrically connected to the integrated circuit. When the semiconductor chip 201 in the functional submodule 20 is mounted on the upper surface of the silicon substrate 103 by flip-chip method, the active surface of the semiconductor chip 201 faces downward, and the welding protrusion 203 on the active surface is welded together with the corresponding first wiring 105 in the first redistribution layer 101 of the silicon substrate 103. In one embodiment, the welding protrusion 203 may include a welding pad and a solder layer located on the surface of the welding pad. In another embodiment, the welding protrusion 203 may also include a welding pad, a metal column located on the surface of the welding pad, and a solder layer located on the top surface of the metal column. The material of the pad and the metal column is metal, which can be one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the solder layer is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0056] In one embodiment, each functional submodule 20 further includes an underfill layer 205 filled between the lower surface (active surface) of the semiconductor chip 201 in each functional submodule 20 and the upper surface of the silicon substrate 103 and covering the side surface of the semiconductor chip 201. In one embodiment, the underfill layer 205 may cover part or all of the sidewalls of the semiconductor chip 201. In one embodiment, the underfill layer 205 on the sidewall surface of the semiconductor chip 201 has an inclined sidewall. The edge region 12 of the silicon substrate 103 is too narrow to mount the functional submodule 20. When the upper surface of the edge region 12 is completely covered by the first plastic encapsulation layer 111, there is no silicon material on the upper surface of the edge region 12, and the Si / EMC ratio is small (Si is silicon, EMC is plastic encapsulation material), while the upper surface of the middle region 11 is mounted with a functional submodule, that is, most of the middle region is silicon material, a small part is the first plastic encapsulation layer material, and the Si / EMC ratio of the middle region 11 is large, which will cause a large difference in the Si / EMC ratio of the edge region 12 and the middle region 11, resulting in the formation of warpage in the wafer-scale system-level packaging structure. Therefore, in one embodiment, a number of edge dummy devices 301 of different sizes can be mounted on the upper surface of the edge region 12 to increase the Si / EMC ratio of the edge region 12, thereby reducing the difference between the Si / EMC ratio of the edge region 12 and the Si / EMC ratio of the middle region 11, thereby effectively regulating the warpage of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature.

[0057] In one embodiment, the edge dummy device 301 may be one or more of a passive device, a heat dissipation discrete component or a dummy piece. In a specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a passive device, the passive device may be electrically connected to the silicon substrate 103, and the passive device may be one or more of a resistor, a capacitor, and an inductor. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a heat dissipation discrete component, such as a heat dissipation metal block, the lower surface of the heat dissipation discrete component is adhered to the upper surface of the edge region 12 of the silicon substrate 103 by a heat dissipation adhesive, the heat dissipation discrete component may be used for heat dissipation of the packaging structure, and the material of the heat dissipation discrete component is a metal material for heat dissipation. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the silicon substrate 103 is a dummy piece, the lower surface of the dummy piece is adhered to the upper surface of the edge region 12 of the silicon substrate 103 by an adhesive, and the dummy piece is a silicon particle without a circuit.

[0058] In one embodiment, the size of the edge dummy device 301 away from the middle area 11 is smaller than the size of the edge dummy device 301 close to the middle area 11, so that the upper surface of the edge area 12 is fully mounted on the edge dummy device 301, thereby further improving the Si / EMC ratio of the edge area 12 of the wafer-scale system-level packaging structure, thereby further reducing the difference between the Si / EMC ratio of the edge area 12 and the Si / EMC ratio of the middle area 11, which is conducive to better suppressing the warping of the wafer-scale system-level packaging structure.

[0059] In one embodiment, the edge dummy device 301 mounted on the upper surface of the edge region 12 close to the middle region 11 is a passive device, and the edge dummy device 301 mounted on the upper surface of the edge region 12 away from the middle region 11 is a heat dissipation discrete component or a dummy piece. The mounting method of the passive device (edge ​​dummy device 301) close to the middle region 11 can be the same as the mounting method of the functional submodule 20 to maintain the consistency of the mounting method and the packaging structure to improve production capacity. In one embodiment, the edge dummy devices can be arranged in rows or columns.

[0060] In one embodiment, reference Figure 2 or Figure 3 The first bridge structure 421 includes a first circuit layer 401 and a first support layer 402 located on the upper surface of the first circuit layer 401. The first circuit layer 401 includes a first dielectric layer, a first circuit (not shown in the figure) located in the first dielectric layer, and a first welding protrusion 401a protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit. When the first bridge structure 421 is mounted on the upper surface of the silicon substrate 103, the first welding protrusion 401a is electrically connected to a part of the first redistribution layer 101 (or a part of the first wiring 105) in the silicon substrate 103. The first bridge structure 421, together with a part of the first redistribution layer 101 in the silicon substrate 103, interconnects the adjacent functional submodules 20.

[0061] In one embodiment, the first supporting layer 402 is a single-layer or multi-layer stacked structure, and the material of the first supporting layer 402 is one or more of silicon, silicon germanium, silicon carbide, glass, resin, and PCB core board.

[0062] The first dielectric layer in the first circuit layer 401 is used for isolation between the first circuits. The first dielectric layer can be a single-layer or multi-layer stacked structure. The material of the first dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The first circuit can also be a single-layer or multi-layer circuit structure. The material of the first circuit is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0063] In one embodiment, the first bridging structure 421 located on the upper surface of the silicon substrate 103 may be connected to a device mounted on the lower surface of the silicon substrate 103 through a circuit in the silicon substrate 103 in addition to being connected to the corresponding functional sub-module 20 .

[0064] In one embodiment, the number of first bridging structures 421 surface-mounted on the silicon substrate 103 at each edge of the functional submodule 20 is at least two, and the plurality of first bridging structures 421 are arranged in a direction parallel to the edge of the functional submodule 20 .

[0065] In one embodiment, the first bridge structure 421 is manufactured by an integrated manufacturing process to improve the production capacity of the first bridge structure 421. In a specific embodiment, the manufacturing process of the first bridge structure 421 may include: providing a support carrier, which is subsequently used to form a first support layer; forming an initial circuit layer on the upper surface of the support carrier, wherein the initial circuit layer includes a plurality of discrete first circuit layers 401; after optional thinning, the initial circuit layer and the support carrier are cut to form a plurality of discrete first bridge structures 421, each of which includes a first support layer 402 and a first circuit layer 401 located on the first support layer 402. The thickness of the first circuit layer 401 is usually very thin and cannot be processed as a separate device, so the first support layer 402 provides physical support for the first circuit layer 401 and protects the first circuit layer 401 from failure such as disconnection due to warping.

[0066] In one embodiment, reference Figure 1 and Figure 3The second bridging structure 422 includes a second circuit layer 403 and a second supporting layer 404 located on the upper surface of the second circuit layer 403. The second circuit layer 403 includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion 403a protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit. When the second bridging structure 422 is mounted on the upper surface of the silicon substrate, the second welding protrusion 403a is electrically connected to a portion of the first redistribution layer 101 in the silicon substrate 103. The second bridging structure 422 together with a portion of the first redistribution layer 101 in the silicon substrate interconnects the adjacent functional sub-modules 20 around the corner head.

[0067] In one embodiment, reference Figure 3 The second supporting layer 404 is a flexible structure, and the rigidity of the second supporting layer 404 is less than the rigidity of the first plastic packaging layer 111, so that the second supporting layer 404 can effectively buffer and balance the large stress existing at and near the corners of adjacent functional sub-modules 20, thereby effectively reducing the warping of the wafer-scale system-level packaging structure caused by the stress at the corners of the functional sub-modules 20.

[0068] The second dielectric layer in the second circuit layer 403 is used for isolation between the second circuits. The second dielectric layer can be a single layer or a multi-layer stacked structure. The material of the second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The second circuit can also be a single layer or a multi-layer circuit structure. The material of the second circuit is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0069] In one embodiment, the second bridging structure 422 located on the upper surface of the silicon substrate 103 can be connected to the corresponding functional sub-module 20 and can also be connected to the device mounted on the lower surface of the silicon substrate 103 through the circuit in the silicon substrate 103 .

[0070] In one embodiment, a second bridge structure 422 is mounted on the upper surface of the silicon substrate 103 at each corner of the functional submodule 20 .

[0071] In one embodiment, the second bridge structure 422 is manufactured using an integrated manufacturing process to improve the production capacity of the second bridge structure 422. In a specific embodiment, the manufacturing process of the second bridge structure 422 may include: providing a support carrier, which is subsequently used to form a second support layer; an initial circuit layer on the upper surface of the support carrier, wherein the initial circuit layer includes a plurality of discrete second circuit layers 403; the initial circuit layer and the initial support carrier are cut after optional thinning to form a plurality of discrete second bridge structures 422, each of which includes a second support layer 404 and a second circuit layer 403 located on the second support layer 404. The thickness of the second circuit layer 403 is usually very thin and cannot be processed as a separate device, so the second support layer 404 provides physical support for the second circuit layer 403 and protects the second circuit layer 403 from failure such as disconnection due to warping.

[0072] continue Figure 3 The second supporting layer 404 is a flexible structure, and the rigidity of the second supporting layer 404 is less than the rigidity of the first plastic packaging layer 111, so that the second supporting layer 404 can effectively buffer and balance the large stress existing at and near the corners of adjacent functional sub-modules 20, thereby effectively reducing the warping of the wafer-scale system-level packaging structure caused by the large stress at the corners of the functional sub-modules 20.

[0073] In one embodiment, reference Figure 3 and Figure 4 The second supporting layer 404 of the flexible structure 422 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408. The core layer 408 has a blind hole 409. The blind hole 409 is a cavity, or the blind hole 409 is filled with a filling material 411 (refer to Figure 4 ), and then mount the heat dissipation cover 601 (reference Figure 6 ), part of the lower surface of the horizontal cover top of the heat dissipation cover 601 is attached to the upper surface of the second buffer layer 407 in the second support layer 404. In addition to being able to more effectively buffer and balance the greater stress existing at and near the corners of the adjacent functional submodules 20, the flexible structure 422 also provides support and buffering pads for the corresponding lower surface of the horizontal cover top of the heat dissipation cover 601.

[0074] In another embodiment, reference Figure 5The second supporting layer 404 of the flexible structure 422 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408. The second buffer layer 407 and the core layer 408 have blind holes 409 penetrating the second buffer layer 407 and the core layer 408. On the one hand, the rigidity of the second bridging structure 422 of the structure is relatively small, so as to more effectively buffer and balance the large stress existing at and near the corners of the adjacent functional submodules 20. On the other hand, the subsequent mounting of the heat dissipation cover 601 (reference Figure 7 ), the second bridging structure 422 provides support and cushioning pads for the corresponding lower surface of the horizontal cover top of the heat dissipation cover 601, and provides a mounting interface for the anchoring protrusions 606 on the corresponding lower surface of the horizontal cover top of the heat dissipation cover 601. At the same time, when the heat dissipation cover 601 is mounted, the anchoring protrusions 606 on the lower surface of the heat dissipation cover 601 are correspondingly mounted in the corresponding blind holes 409, that is, the blind holes 409 also provide limiting spaces for the anchoring protrusions 606 on the lower surface of the heat dissipation cover 601, thereby improving the alignment accuracy of the heat dissipation cover 601 during mounting, and limiting the mounting accuracy of the heat dissipation cover 601 during the mounting process and the bonding process of the heat dissipation cover 601. When the anchoring protrusions 606 on the corresponding lower surface of the horizontal cover top of the heat dissipation cover 601 are correspondingly mounted in the corresponding blind holes 409, the anchoring protrusions 606 are locked in the blind holes, thereby improving the mounting firmness of the heat dissipation cover 601.

[0075] In one embodiment, the first buffer layer 406 and the second buffer layer 407 are used for stress buffering between the upper and lower surfaces of the second support layer 404 and other structures. The materials of the first buffer layer 406 and the second buffer layer 407 are organic or inorganic buffer materials, and the material of the core layer 408 is PCB or substrate material.

[0076] In one embodiment, reference Figure 4 or Figure 5 , the sidewall surface of the blind hole 409 also has a metal layer 410. In one embodiment, reference Figure 4 When the blind hole 409 is filled with a filling material 411 , in addition to the metal layer 410 on the sidewall surface of the blind hole 409 , there are also metal layers above and below the filling material 409 .

[0077] In one embodiment, reference Figure 1-3The material of the first plastic encapsulation layer 111 may be a filler-containing epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin; or may be a filler-containing polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. In some embodiments, the filler may be an inorganic filler or an organic filler. In some embodiments, the process for forming the first plastic encapsulation layer 111 includes a compression molding process or a transfer molding process.

[0078] In one embodiment, reference Figure 6 or Figure 7 The packaging structure also includes: a heat dissipation cover 601 mounted on the upper surfaces of the first plastic packaging layer 111, the functional sub-module 20, the first bridge structure 421 and the second bridge structure 422, and the outer side surfaces of the first plastic packaging layer 111 and the silicon substrate 103, and the heat dissipation cover 601 is used to dissipate heat for the wafer-scale system-level packaging structure.

[0079] In one embodiment, reference Figure 6 The heat dissipation cover 601 includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top. The lower surface of the horizontal cover top of the heat dissipation cover 601 is mounted on the upper surfaces of the first plastic sealing layer 111, the functional submodule 20, the first bridge structure 421 and the second bridge structure 422, and the inner side wall surface of the cover edge of the heat dissipation cover 601 is mounted on the outer side surface of the first plastic sealing layer 111 and the silicon substrate 103.

[0080] In another specific embodiment, referring to Figure 7 The heat dissipation cover 601 includes a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downwardly protruding anchoring protrusions 606 protruding from the lower surface of the horizontal cover top. The lower surface of the horizontal cover top of the heat dissipation cover 601 is mounted on the upper surfaces of the first plastic sealing layer 111, the functional sub-module 20 and the first bridging structure 421. The anchoring protrusions 606 are mounted in the corresponding blind holes 409 through adhesive 603. The inner side wall surface of the cover edge of the heat dissipation cover 601 is mounted on the outer side surfaces of the first plastic sealing layer 111 and the silicon substrate 103.

[0081] In one embodiment, the heat dissipation cover 601 is made of a material with high thermal conductivity including metal (such as copper, aluminum, gold, nickel, steel or stainless steel) or a carbon-containing material (such as graphite, graphene or carbon nanotubes).

[0082] In one embodiment, reference Figure 8The packaging structure also includes: a bridge chip 423 mounted on the lower surface of the silicon substrate 103, the bridge chip 423 is electrically connected to a portion of the second redistribution layer 102, and the bridge chip 423 is used to interconnect the adjacent functional sub-modules 20 above the bridge chip 423 through a portion of the second redistribution layer 102, the silicon through-via 104 and a portion of the first redistribution layer 101, thereby achieving diversity in interconnection between adjacent functional sub-modules 20, further improving the bandwidth (band-width) between adjacent functional sub-modules 20, and thereby improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0083] In one embodiment, the bridge chip 423 includes a third wire and a third welding protrusion 413 connected to the third wire. The electrical connection between the bridge chip 423 and part of the second redistribution layer 102 includes: welding the welding protrusion 413 on the bridge chip 423 and part of the second wiring 107 in the second redistribution layer 102 of the silicon substrate 103 together.

[0084] In one embodiment, reference Fig. 9 The packaging structure further includes: a metal bump 113 protruding from the lower surface of the silicon substrate 103 and connected to part of the second redistribution layer 102, the lower surface of the metal bump 113 is not lower than the lower surface of the bridge chip 423, specifically, the lower surface of the metal bump 113 can be flush with the lower surface of the bridge chip 423, or higher than the lower surface of the bridge chip 423. The metal bump 113 is used to electrically connect the wafer-scale system-level packaging structure with other external packaging structures or external devices, specifically, one end of the metal bump 113 can be electrically connected to part of the second wiring 107 in the second redistribution layer 102, and the material of the metal bump 113 is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The second plastic layer 112 located on the lower surface of the silicon substrate 103 covers the bridge chip 423 and the metal bump 113 , and the second plastic layer 112 exposes the metal bump 113 and the lower surface of the bridge chip 423 , or the second plastic layer 112 exposes only the metal bump 113 .

[0085] In one embodiment, continue to refer to Fig. 9, further comprising: edge dummy devices 301 of different sizes mounted on the lower surface of the edge region of the silicon substrate 103 outside the functional submodule array 20, the second plastic encapsulation layer 112 also covering the edge dummy devices 301 and exposing the lower surface of the edge dummy devices 301. The edge dummy devices 301 of different sizes mounted on the lower surface of the edge region of the silicon substrate 103 outside the functional submodule array 20 can further balance the Si / EMC ratio, so as to further balance the warpage of the upper and lower surfaces of the silicon substrate 103, and thus regulate the overall warpage of the system packaging structure of the wafer-level super-large core module.

[0086] The second plastic encapsulation layer 112 is used to protect the circuits and devices on the lower surface of the silicon substrate 112. The properties of the second plastic encapsulation layer 112 may be the same as or different from the properties of the first plastic encapsulation layer 111. In one embodiment, the properties of the second plastic encapsulation layer 112 are different from those of the first plastic encapsulation layer 111. Specifically, the thickness of the second plastic encapsulation layer 112 is less than the thickness of the first plastic encapsulation layer 111 and is at least 15 um. The thermal expansion coefficient and / or Young's modulus of the second plastic encapsulation layer 112 are equal to or higher than the thermal expansion coefficient and / or Young's modulus of the first plastic encapsulation layer 111. The second plastic encapsulation layer 112 with specific properties (including: specific thickness and specific thermal expansion coefficient and / or Young's modulus) is used to balance or reduce the difference in thermal expansion coefficient and / or Young's modulus of the unbalanced structure and material on the upper surface and the lower surface of the silicon substrate 103, thereby preventing the wafer-scale system-level packaging structure from warping due to the large difference in thermal expansion coefficient and / or Young's modulus of the unbalanced structure and material on the upper surface and the lower surface of the silicon substrate 103, thereby effectively regulating the warping of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature.

[0087] In one embodiment, the thermal expansion coefficient and / or Young's modulus of the second plastic sealing layer 112 is equal to or higher than the thermal expansion coefficient and / or Young's modulus of the first plastic sealing layer 111, which is divided into multiple situations, wherein the first situation is: the thermal expansion coefficient of the second plastic sealing layer 112 is equal to or higher than the thermal expansion coefficient of the first plastic sealing layer 111; the second situation is: the Young's modulus of the second plastic sealing layer 112 is equal to or higher than the Young's modulus of the first plastic sealing layer 111; the third situation is: the thermal expansion coefficient and Young's modulus of the second plastic sealing layer 112 are both equal to or higher than the thermal expansion coefficient and Young's modulus of the first plastic sealing layer 111. It should be noted that, in the present application, "equal to" is divided into two situations. One situation is that the two are completely equal in value, for example, the value of the thermal expansion coefficient of the second plastic sealing layer 112 is completely equal to the value of the thermal expansion coefficient of the first plastic sealing layer 111; the other situation is that the two are also regarded as "equal" within the numerical deviation range of ±20%. For example, when the value of the thermal expansion coefficient of the second plastic sealing layer 112 is greater than or less than the value of the thermal expansion coefficient of the first plastic sealing layer 111 within the range of ±20%, the two are regarded as "equal". For example, when the value of the curing shrinkage rate of the second plastic sealing layer 112 is greater than or less than the value of the curing shrinkage rate of the first plastic sealing layer 111 within the range of ±20%, the two are regarded as "equal". In this application, "higher than" means that the difference between the two is greater than 20%. For example, the thermal expansion coefficient of the second plastic sealing layer 112 is higher than the thermal expansion coefficient of the first plastic sealing layer 111, which means that the thermal expansion coefficient of the second plastic sealing layer 112 is greater than the thermal expansion coefficient of the first plastic sealing layer 111 by more than 20%. For another example, the curing shrinkage rate of the second plastic sealing layer 112 is also higher than the curing shrinkage rate of the first plastic sealing layer 111, which means that the curing shrinkage rate of the second plastic sealing layer 112 is greater than the curing shrinkage rate of the first plastic sealing layer 111 by more than 20%.

[0088] In one embodiment, reference Fig.10 The packaging structure further includes: a power supply module 501 mounted on the lower surface of the second plastic packaging layer 112 and electrically connected to the metal bump 113, the power supply module 501 is used to supply power to at least two adjacent functional sub-modules 20 on the upper surface of the silicon substrate 103. The power supply module 501 can convert an external input voltage into a voltage of a specific magnitude and a specific power and supply it to the corresponding functional sub-module 20.

[0089] In one embodiment, the number of the power supply modules 501 may be one or more. When the number of the power supply modules 501 is one, one power supply module 501 supplies power to all the functional sub-modules 20 on the upper surface of the silicon substrate 103. When the number of the power supply modules 501 is multiple, each power supply module 501 supplies power to multiple (specifically, 2-4) adjacent functional sub-modules 20 on the upper surface of the silicon substrate 103.

[0090] In one embodiment, the power supply module 501 may include a substrate 505, which may be a PCB substrate, with dielectric layers 505 on the upper and lower surfaces of the substrate 505, with connecting lines 504 in the substrate 505 and the dielectric layer 505, with a plurality of pads 502 in the dielectric layer 505 on the upper surface of the PCB substrate, with the pads 502 being electrically connected to the connecting lines 504, and the pads 502 being soldered together with corresponding metal bumps 113 on the lower surface of the silicon substrate 103 through solder. In one embodiment, the power supply module 501 further includes: a semiconductor chip (and passive devices) mounted on the lower surface of the substrate 505 or embedded in the substrate 505 (not shown in the figure), the semiconductor chip may be a power supply control chip, and the semiconductor chip is electrically connected to the connecting lines 504.

[0091] In one embodiment, continue to refer to Fig.10 , further comprising: bonding materials 503 for fixing the four corners of the power supply module 501 to the corresponding lower surface of the second plastic packaging layer 112. The four corners of the power supply module 501 are further fixed to the second plastic packaging layer 112 by the bonding materials 503, so as to improve the mounting firmness of the larger power supply module 501 and suppress the warping of the wafer-scale system-level packaging structure caused by the power supply module 501.

[0092] In another embodiment, the structure of the second plastic encapsulation layer 112 in the packaging structure is different from that in the above-mentioned embodiment. Fig.11 The second plastic packaging layer 112 covers the bridge chip 423 , the metal bumps 113 , the power supply module 501 and the edge dummy device 301 located on the lower surface of the silicon substrate 103 , and the second plastic packaging layer 112 exposes the lower surfaces of the power supply module 501 and the edge dummy device 301 .

[0093] Another embodiment of the present application further provides a method for forming a wafer-scale system-level packaging structure, which is described below in conjunction with the accompanying drawings (it should be noted that the same or similar parts of this embodiment (the method for forming a wafer-scale system-level packaging structure) and the aforementioned embodiment (the wafer-scale system-level packaging structure) are not repeated in this embodiment, and please refer to the definitions or descriptions of the corresponding parts in the aforementioned embodiment for details).

[0094] Combined with reference Figure 1-Figure 3 , providing a silicon substrate 103, wherein the silicon substrate 103 includes an upper surface and a lower surface opposite to each other; A plurality of functional submodules 20 arranged in an array are mounted on the surface of the silicon substrate 103, and each of the functional submodules 20 includes four corners and an edge between adjacent corners, and the functional submodules 20 are electrically connected to the silicon substrate 103; A first bridge structure 421 is mounted on the surface of the silicon substrate 103 at the edge of the functional submodule 20, and the first bridge structure 421 is used to interconnect adjacent functional submodules 20; A second bridge structure 422 is mounted on the surface of the silicon substrate 103 of the corner head of the functional submodule 20, and the second bridge structure 422 is used to interconnect the adjacent functional submodules 20 around the corner head; A first plastic encapsulation layer 111 covering the functional submodule 20 , the first bridge structure 421 and the second bridge structure 422 is formed on the upper surface of the silicon substrate 103 , and the first plastic encapsulation layer 111 exposes the upper surfaces of the functional submodule 20 , the first bridge structure 421 and the second bridge structure 422 .

[0095] In one embodiment, it further includes: mounting edge dummy devices 301 of different sizes on the upper surface of the edge region of the silicon substrate 103 outside the array of the functional submodules 20. The first plastic encapsulation layer 111 also covers the edge dummy devices 301 and exposes the upper surface of the edge dummy devices 301; the edge dummy devices 301 are one or more of passive devices, heat dissipation discrete parts or dummy chips.

[0096] In one embodiment, the first bridging structure 421 includes a first circuit layer 401 and a first supporting layer 402 located on the upper surface of the first circuit layer 401, the first circuit layer 401 includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion 401a protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, and the first welding protrusion 401a is welded to the silicon substrate 103.

[0097] In one embodiment, at least two first bridging structures 421 are surface mounted on the silicon substrate 103 at each edge of the functional submodule 20 , and the first bridging structures 421 are arranged in a direction parallel to the edge of the functional submodule 20 .

[0098] In one embodiment, the second bridging structure 422 includes a second circuit layer 403 and a second supporting layer 404 located on the upper surface of the second circuit layer 403, the second circuit layer 403 includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion 403a protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, and the second welding protrusion 403a is welded to the silicon substrate 103.

[0099] In a specific embodiment, in conjunction with reference Figure 4 and Figure 6 The second supporting layer 404 of the flexible structure 422 includes a first buffer layer 406, a core layer 408 located on the surface of the first buffer layer 406, and a second buffer layer 407 located on the surface of the core layer 408. The core layer 408 has a blind hole 409, and the blind hole 409 is a cavity, or the blind hole 409 is filled with a filling material. The second buffer layer 407 closes the opening of the blind hole 409, and the first plastic sealing layer 111 exposes the upper surface of the second buffer layer 407. The side wall surface of the blind hole also has a metal layer; it also includes: a heat dissipation cover 601 is mounted, the heat dissipation cover 601 includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover 601 is mounted on the upper surface of the second buffer layer 407 of the first plastic sealing layer 111, the functional sub-module 20, the first bridging structure 421 and the second bridging structure 422, and the inner side wall surface of the cover edge of the heat dissipation cover 601 is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

[0100] In a specific embodiment, in conjunction with reference Figure 5 and Figure 7The second supporting layer 404 of the flexible structure 422 includes a first buffer layer 406, a core layer 408 located on the upper surface of the first buffer layer 406, and a second buffer layer 407 located on the upper surface of the core layer 408, wherein the second buffer layer 407 and the core layer 408 have blind holes 409, the blind holes 409 penetrate the second buffer layer 407 and the core layer 408, the first plastic sealing layer 111 exposes the blind holes 409, and the side wall surface of the blind holes also has a metal layer; further comprising: a heat dissipation cover 601, wherein the heat dissipation cover 601 includes A horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions 606 protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover 601 is mounted on the upper surfaces of the first plastic sealing layer 111, the functional sub-module 20, the first bridging structure 421 and the second bridging structure 422, the anchoring protrusions 606 are mounted in the corresponding blind holes 409 by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover 604 is mounted on the outer side surface of the first plastic sealing layer 111 and the silicon substrate 103.

[0101] In one embodiment, the silicon substrate 103 includes a silicon wafer body 100, a first redistribution layer 101 located on the upper surface of the silicon wafer body 100, and a second redistribution layer 102 located on the lower surface of the silicon wafer body 100, the silicon wafer body 100 has a through silicon via 104, and the through silicon via 104 electrically connects the first redistribution layer 101 and the second redistribution layer 102; the functional sub-module 20, the first bridging structure 421, and the second bridging structure 422 are respectively electrically connected to different parts of the first redistribution layer 101, and adjacent functional sub-modules 20 are interconnected through the first bridging structure 421 and / or the second bridging structure 422 and through part of the first redistribution layer 101 in the silicon substrate 103.

[0102] In one embodiment, reference Figure 8 , further comprising: mounting a bridge chip 423 on the lower surface of the silicon substrate 103, the bridge chip 423 being electrically connected to a portion of the second redistribution layer 102, the bridge chip 423 interconnecting the adjacent functional sub-modules 20 above the bridge chip 423 through a portion of the second redistribution layer 102, the through silicon via 104 and a portion of the first wiring layer 101.

[0103] In one embodiment, reference Fig. 9, further comprising: forming a raised metal bump 113 on the lower surface of the silicon substrate 103 and connected to a portion of the second redistribution layer 102, wherein the lower surface of the metal bump 113 is not lower than the lower surface of the bridge chip 423; mounting edge dummy devices 301 of different sizes on the lower surface of the edge area of ​​the silicon substrate 103 outside the functional sub-module array; forming a second plastic encapsulation layer 112 on the lower surface of the silicon substrate 103 to cover the bridge chip 423, the edge dummy device 301 and the metal bump 113, wherein the second plastic encapsulation layer 112 exposes the lower surfaces of the bridge chip 423, the edge dummy device 301 and the metal bump 113.

[0104] In one embodiment, reference Fig.10 A power supply module 501 is mounted on the lower surface of the second plastic packaging layer 112 and electrically connected to the metal bump 113 , and the power supply module 501 is used to supply power to at least two adjacent functional sub-modules 20 on the upper surface of the silicon substrate 103 .

[0105] In one embodiment, continue to refer to Fig.10 , forming a bonding material 503 for fixing the four corners of the power supply module 501 to the corresponding lower surface of the second plastic packaging layer 112.

[0106] In one embodiment, reference Fig.11 , a raised metal bump 113 connected to a portion of the second redistribution layer 102 is formed on the lower surface of the silicon substrate 103, and the lower surface of the metal bump 113 is not lower than the lower surface of the bridge chip 423; a power supply module 501 is mounted on the lower surface of the metal bump 113; edge dummy devices 301 of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate 103 outside the array of functional sub-modules 20; a second plastic packaging layer 112 covering the bridge chip 423, the metal bump 113, the power supply module 501 and the edge dummy device 301 is formed on the lower surface of the silicon substrate 103, and the second plastic packaging layer 112 exposes the lower surfaces of the power supply module 501 and the edge dummy device 301.

[0107] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A wafer-scale system-level packaging structure, characterized in that: include: a silicon substrate comprising an upper surface and a lower surface opposite to each other; A plurality of functional submodules arranged in an array and mounted on the upper surface of the silicon substrate, each of the functional submodules comprising four corners and an edge between adjacent corners, the functional submodules being electrically connected to the silicon substrate; A first bridge structure mounted on the upper surface of the silicon substrate at the edge of the functional submodule, wherein the first bridge structure is used to interconnect adjacent functional submodules; A second bridge structure mounted on the upper surface of the silicon substrate of the corner head of the functional submodule, wherein the second bridge structure is used to interconnect the adjacent functional submodules around the corner head; A first plastic sealing layer is located on the upper surface of the silicon substrate and covers the functional submodule, the first bridge structure and the second bridge structure, and the first plastic sealing layer exposes the upper surfaces of the functional submodule, the first bridge structure and the second bridge structure.

2. The wafer-scale system-in-package structure according to claim 1, wherein: Each of the functional submodules has the same structure, and the functional submodule comprises at least two semiconductor chips, and the at least two semiconductor chips are mounted on the upper surface of the silicon substrate in a flip-chip manner; Each functional submodule further includes an underfill layer which is filled between the lower surface of the semiconductor chip in each functional submodule and the upper surface of the silicon substrate and covers the side surfaces of the semiconductor chip.

3. The wafer-scale system-in-package structure according to claim 1, wherein: Also includes: Edge dummy devices of different sizes are mounted on the upper surface of the edge area of ​​the silicon substrate outside the functional sub-module array, the first plastic packaging layer also covers the edge dummy devices and exposes the upper surface of the edge dummy devices; the edge dummy devices are one or more of passive devices, heat dissipation discrete parts or dummy films.

4. The wafer-scale system-in-package structure according to claim 1, wherein: The first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, when the first bridging structure is mounted on the upper surface of the silicon substrate, the first welding protrusion is electrically connected to the silicon substrate, and the first bridging structure together with the silicon substrate interconnects the adjacent functional sub-modules.

5. The wafer-scale system-in-package structure according to claim 4, characterized in that: The first supporting layer of the first bridging structure is a single-layer or multi-layer stacking structure.

6. The wafer-scale system-in-package structure according to claim 5, wherein: The material of the first supporting layer of the first bridge structure is one or more of silicon, silicon germanium, silicon carbide, glass, resin, and PCB core board.

7. The wafer-scale system-in-package structure according to claim 4, wherein: The number of first bridging structures surface-mounted on the silicon substrate at each edge of the functional submodule is at least two, and the plurality of first bridging structures are arranged in a direction parallel to the edge of the functional submodule.

8. The wafer-scale system-in-package structure according to claim 1, wherein: The second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, when the second bridging structure is mounted on the upper surface of the silicon substrate, the second welding protrusion is electrically connected to the silicon substrate, and the second bridging structure together with the silicon substrate interconnects the adjacent functional sub-modules around the corner head.

9. The wafer-scale system-in-package structure according to claim 8, wherein: The second supporting layer is a flexible structure, and the rigidity of the second supporting layer is less than the rigidity of the first plastic packaging layer.

10. The wafer-scale system-in-package structure according to claim 9, wherein: The second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the core layer has a blind hole, the blind hole is a cavity, or the blind hole is filled with filling material, the second buffer layer closes the opening of the blind hole, the first plastic sealing layer exposes the upper surface of the second buffer layer; the side wall surface of the blind hole also has a metal layer.

11. The wafer-scale system-in-package structure according to claim 10, wherein: Also includes: A heat dissipation cover, the heat dissipation cover comprises a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surface of the first plastic sealing layer, the functional sub-module, the first bridge structure and the second buffer layer of the second bridge structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

12. The wafer-scale system-in-package structure according to claim 9, wherein: The second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer. The second buffer layer and the core layer have blind holes that penetrate the second buffer layer and the core layer, and the first plastic packaging layer exposes the blind holes. The side wall surface of the blind hole also has a metal layer.

13. The wafer-scale system-in-package structure of claim 12, further comprising: A heat dissipation cover, the heat dissipation cover comprising a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the first plastic sealing layer, the functional submodule, the first bridge structure and the second bridge structure, the anchoring protrusions are mounted in the corresponding blind holes by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

14. The wafer-scale system-in-package structure according to claim 1, wherein: The silicon substrate includes a silicon wafer body, a first redistribution layer located on the upper surface of the silicon wafer body, and a second redistribution layer located on the lower surface of the silicon wafer body. The silicon wafer body has a silicon through hole, and the silicon through hole electrically connects the first redistribution layer and the second redistribution layer.

15. The wafer-scale system-in-package structure according to claim 14, wherein: The functional sub-modules, the first bridge structure and the second bridge structure are electrically connected to different parts of the first redistribution layer respectively, and adjacent functional sub-modules are interconnected through the first bridge structure and / or the second bridge structure and through part of the first redistribution layer in the silicon substrate.

16. The wafer-scale system-in-package structure according to claim 14 or 15, characterized in that: Also includes: A bridge chip mounted on the lower surface of the silicon substrate, the bridge chip is electrically connected to a portion of the second redistribution layer, and the bridge chip interconnects the adjacent functional sub-modules above the bridge chip through a portion of the second redistribution layer, the through silicon via and a portion of the first redistribution layer.

17. The wafer-scale system-in-package structure according to claim 16, wherein: Also includes: A metal bump protruding from the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, wherein the lower surface of the metal bump is not lower than the lower surface of the bridge chip; Edge dummy devices of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; a second plastic packaging layer located on the lower surface of the silicon substrate and covering the bridge chip, the metal bumps and the edge dummy devices, the second plastic packaging layer exposing the lower surface of the bridge chip, the metal bumps and the edge dummy devices.

18. The wafer-scale system-in-package structure according to claim 17, wherein: Also includes: A power supply module is mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bump, and the power supply module supplies power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

19. The wafer-scale system-in-package structure according to claim 18, wherein: Also includes: A bonding material is used to fix the four corners of the power supply module to the corresponding lower surface of the second plastic packaging layer.

20. The wafer-scale system-in-package structure according to claim 16, wherein: Also includes: A metal bump protruding from the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, wherein the lower surface of the metal bump is not lower than the lower surface of the bridge chip; A power supply module mounted on the lower surface of the metal bump; Edge dummy devices of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; a second plastic packaging layer located on the lower surface of the silicon substrate and covering the bridge chip, metal bumps, power supply module and edge dummy devices, and the second plastic packaging layer exposes the lower surface of the power supply module and the edge dummy devices.

21. A method for forming a wafer-scale system-level packaging structure, characterized in that: include: Providing a silicon substrate, the silicon substrate comprising an upper surface and a lower surface opposite to each other; Mounting a plurality of functional submodules arranged in an array on the surface of the silicon substrate, each of the functional submodules comprising four corners and an edge between adjacent corners, the functional submodules being electrically connected to the silicon substrate; A first bridge structure is mounted on the surface of the silicon substrate at the edge of the functional submodule, wherein the first bridge structure is used to interconnect adjacent functional submodules; A second bridge structure is mounted on the surface of the silicon substrate of the corner head of the functional submodule, and the second bridge structure is used to interconnect the adjacent functional submodules around the corner head; A first plastic encapsulation layer covering the functional submodule, the first bridge structure and the second bridge structure is formed on the upper surface of the silicon substrate, and the first plastic encapsulation layer exposes the upper surfaces of the functional submodule, the first bridge structure and the second bridge structure.

22. The method for forming a wafer-scale system-in-package structure according to claim 21, wherein: Edge dummy devices of different sizes are mounted on the upper surface of the edge area of ​​the silicon substrate outside the functional sub-module array, and the first plastic packaging layer also covers the edge dummy devices and exposes the upper surface of the edge dummy devices; the edge dummy devices are one or more of passive devices, heat dissipation discrete parts or dummy chips.

23. The method for forming a wafer-scale system-in-package structure according to claim 21, wherein: The first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, and the first welding protrusion is electrically connected to the silicon substrate.

24. The method for forming a wafer-scale system-in-package structure according to claim 23, wherein: The second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, and the second welding protrusion is electrically connected to the silicon substrate.

25. The method for forming a wafer-scale system-in-package structure according to claim 24, wherein: The second supporting layer is a flexible structure, and the rigidity of the second supporting layer is less than the rigidity of the first plastic packaging layer.

26. The method for forming a wafer-scale system-in-package structure according to claim 25, wherein: The second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, wherein the core layer has a blind hole, wherein the blind hole is a cavity, or wherein the blind hole is filled with a filling material, wherein the second buffer layer closes the opening of the blind hole, wherein the first plastic sealing layer exposes the upper surface of the second buffer layer, and wherein the side wall surface of the blind hole also has a metal layer; further comprising: a heat dissipation cover mounted thereon, wherein the heat dissipation cover includes a horizontal cover top and a cover edge protruding from the lower surface of the edge of the horizontal cover top, wherein the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the second buffer layers of the first plastic sealing layer, the functional submodule, the first bridging structure, and the second bridging structure, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

27. The method for forming a wafer-scale system-in-package structure according to claim 25, wherein: The second supporting layer of the flexible structure includes a first buffer layer, a core layer located on the upper surface of the first buffer layer, and a second buffer layer located on the upper surface of the core layer, the second buffer layer and the core layer have blind holes penetrating the second buffer layer and the core layer, the first plastic sealing layer exposes the blind holes, and the side wall surface of the blind hole also has a metal layer; it also includes: a heat dissipation cover is mounted, the heat dissipation cover includes a horizontal cover top, a cover edge protruding from the lower surface of the edge of the horizontal cover top, and a plurality of downward anchoring protrusions protruding from the lower surface of the horizontal cover top, the lower surface of the horizontal cover top of the heat dissipation cover is mounted on the upper surfaces of the first plastic sealing layer, the functional sub-module, the first bridging structure and the second bridging structure, the anchoring protrusions are mounted in the corresponding blind holes by adhesive, and the inner side wall surface of the cover edge of the heat dissipation cover is mounted on the outer side surface of the first plastic sealing layer and the silicon substrate.

28. The method for forming a wafer-scale system-in-package structure according to claim 21, wherein: The silicon substrate comprises a silicon wafer body, a first redistribution layer located on an upper surface of the silicon wafer body, and a second redistribution layer located on a lower surface of the silicon wafer body, wherein the silicon wafer body has a through silicon via, and the through silicon via electrically connects the first redistribution layer and the second redistribution layer; The functional sub-modules, the first bridge structure and the second bridge structure are electrically connected to different parts of the first redistribution layer respectively, and adjacent functional sub-modules are interconnected through the first bridge structure and / or the second bridge structure and through part of the first redistribution layer in the silicon substrate.

29. The method for forming a wafer-scale system-in-package structure according to claim 28, wherein: Also includes: A bridge chip is mounted on the lower surface of the silicon substrate, the bridge chip is electrically connected to a portion of the second redistribution layer, and the bridge chip interconnects the adjacent functional sub-modules above the bridge chip through a portion of the second redistribution layer, the through silicon via and a portion of the first wiring layer.

30. The method for forming a wafer-scale system-in-package structure according to claim 29, wherein: Also includes: Forming a raised metal bump on the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, wherein the lower surface of the metal bump is not lower than the lower surface of the bridge chip; Edge dummy devices of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; a second plastic packaging layer covering the bridge chip, the edge dummy devices and the metal bumps is formed on the lower surface of the silicon substrate, and the second plastic packaging layer exposes the lower surfaces of the bridge chip, the metal bumps and the edge dummy devices; a power supply module is mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bumps, and the power supply module is used to supply power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

31. The method for forming a wafer-scale system-in-package structure according to claim 30, wherein: A bonding material is formed to fix the four corners of the power supply module to the corresponding lower surface of the second plastic packaging layer.

32. The method for forming a wafer-scale system-in-package structure as claimed in claim 29, wherein: Forming a raised metal bump on the lower surface of the silicon substrate and connected to a portion of the second redistribution layer, wherein the lower surface of the metal bump is not lower than the lower surface of the bridge chip; mounting a power supply module on the lower surface of the metal bump; Edge dummy devices of different sizes are mounted on the lower surface of the edge area of ​​the silicon substrate outside the functional sub-module array; a second plastic packaging layer covering the bridge chip, metal bumps, power supply module and edge dummy devices is formed on the lower surface of the silicon substrate, and the second plastic packaging layer exposes the lower surfaces of the power supply module and the edge dummy devices.

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