Semiconductor device and forming method thereof
By forming an h-BN heat dissipation layer on the substrate of the semiconductor device and filling the h-BN heat dissipation layer in the dummy hole, the problem of insufficient heat dissipation capability of the semiconductor device is solved, and efficient heat dissipation and performance improvement is achieved.
Patent Information
- Application Number
- CN202411804336.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-28
AI Technical Summary
In advanced integrated packaging, the heat dissipation ability of semiconductor devices such as intermediary substrates is insufficient, resulting in temperature gradient and thermal stress problems, affecting structural stability and chip performance.
Both include hexagonal boron nitride (h-BN) with high thermal conductivity to improve the heat dissipation performance of the semiconductor device by forming a first heat dissipation layer on the substrate and filling the second heat dissipation layer in the dummy holes in the substrate.
It realizes excellent heat dissipation performance of semiconductor devices, can timely dissipate heat generated during work, improve device performance and reduce thermal stress.
Smart Images
Figure CN119725262A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art
[0002] With the development of technology, the market demand for advanced chips has increased, which has also promoted the development of advanced integrated packaging. For example, through advanced integrated packaging, different chips can be interconnected with high density through 2D, 2.5D or 3D packaging architectures, thereby achieving improved system-level chip performance.
[0003] The development of advanced integrated packaging has also put forward higher requirements for heat dissipation conditions. For example, in the 2.5D packaging architecture, different chips are bonded on the surface of the same interposer to form a system-level chip. However, the power consumption of different chips may be different, which can easily form a temperature accumulation zone on the surface of the interposer, resulting in a relatively high temperature gradient on the interposer, which in turn generates relatively large thermal stress, affecting the stability of the structure and chip performance.
[0004] Therefore, how to improve the heat dissipation capability of semiconductor devices such as interposers remains an important issue in the development of advanced integrated packaging. Summary of the invention
[0005] In order to improve the heat dissipation capability of a semiconductor device, the present invention provides a semiconductor device and a method for forming the semiconductor device.
[0006] In one aspect, the present invention provides a method for forming a semiconductor device, comprising:
[0007] forming a first heat dissipation layer on the substrate, wherein the first heat dissipation layer comprises h-BN; and
[0008] A dummy hole is formed in the substrate, and a second heat dissipation layer is filled in the dummy hole, wherein the second heat dissipation layer includes h-BN.
[0009] Optionally, after forming the second heat dissipation layer, the forming method further includes:
[0010] forming a conductive column penetrating the first heat dissipation layer and a portion of the substrate; and
[0011] A metal interconnection structure electrically connected to the conductive pillar is formed on the conductive pillar.
[0012] Optionally, forming the conductive pillar includes:
[0013] forming an opening penetrating the first heat dissipation layer and a portion of the substrate;
[0014] forming an isolation layer on the inner wall of the substrate exposed by the opening; and
[0015] A metal layer is filled in the opening.
[0016] Optionally, a planarization process is performed to make the metal layer flush with the upper surface of the first heat dissipation layer.
[0017] Optionally, the isolation layer comprises h-BN.
[0018] Optionally, forming the metal interconnect structure includes:
[0019] forming an interlayer dielectric layer on the first heat dissipation layer, and forming a groove penetrating the interlayer dielectric layer and exposing the conductive pillar; and
[0020] A metal material is filled in the trench to form a first metal interconnection layer embedded in the interlayer dielectric layer.
[0021] Optionally, the interlayer dielectric layer includes a third heat dissipation layer, and the third heat dissipation layer includes h-BN.
[0022] On the other hand, the present invention provides a semiconductor device, which includes a substrate and a first heat dissipation layer formed on the substrate, a dummy hole is formed in the substrate, the dummy hole is filled with a second heat dissipation layer, and the first heat dissipation layer and the second heat dissipation layer include h-BN.
[0023] Optionally, the semiconductor device further includes:
[0024] A conductive column penetrating the first heat dissipation layer and at least a portion of the substrate;
[0025] an interlayer dielectric layer, formed on the first heat dissipation layer;
[0026] A first metal interconnection layer is embedded in the interlayer dielectric layer and electrically connected to the conductive pillars, wherein the interlayer dielectric layer includes a third heat dissipation layer, and the third heat dissipation layer includes h-BN.
[0027] Optionally, both the conductive column and the dummy hole penetrate the substrate.
[0028] Optionally, the semiconductor device is an interposer substrate, and at least one chip is bonded to a side of the interposer substrate where the first heat dissipation layer is formed.
[0029] The semiconductor device formation method and the semiconductor device provided by the present invention have the following technical effects: by forming a first heat dissipation layer on a substrate and forming a second heat dissipation layer in a dummy hole in the substrate, the first heat dissipation layer and the second heat dissipation layer both include h-BN (hexagonal boron nitride), and the thermal conductivity of h-BN is high, so that the first heat dissipation layer and the second heat dissipation layer have excellent heat dissipation performance, which is convenient for timely dissipation of heat generated during operation of the semiconductor device, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention.
[0031] FIG. 2A to FIG. 2J FIG. 4 is a cross-sectional view of a method for forming a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0032] The semiconductor device and the method for forming the same of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.
[0033] First, the method for forming a semiconductor device of the present invention will be described below by way of an embodiment.
[0034] Reference Figure 1 and Figure 2A In an embodiment of the present invention, a method for forming a semiconductor device includes step S1: forming a first heat dissipation layer 110 on a substrate 100, wherein the first heat dissipation layer 110 includes h-BN.
[0035] The substrate 100 may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, etc., or may also include other materials. In the following embodiments, the substrate 100 is, for example, a silicon substrate.
[0036] In order to enhance the heat dissipation capability of the semiconductor device to be formed, a first heat dissipation layer 110 is formed on the substrate 100. As an example, the first heat dissipation layer 110 is directly formed on the surface of the substrate 100 (e.g., the substrate 100 is used to form the front surface of the semiconductor device). In other embodiments, according to the needs of the semiconductor device, other dielectric layers or electrical components may be formed between the first heat dissipation layer 110 and the surface of the substrate 100, and semiconductor devices (such as MOS devices, sensor devices, memory devices or passive devices, etc.) may also be formed on the surface of the substrate. As an example, the semiconductor device to be formed is an interposer, which is used to bond with at least two chips for integrated packaging.
[0037] h-BN (hexagonal boron nitride) has excellent thermal conductivity, and its thermal conductivity is 390W / m·K, which is much higher than the thermal conductivity of silicon oxide (1.4W / m·K) under the same conditions. In this embodiment, the first heat dissipation layer includes h-BN, so that the first heat dissipation layer 110 has excellent heat dissipation performance. The first heat dissipation layer 110 may also include materials other than h-BN, or the first heat dissipation layer 110 may only include h-BN. The first heat dissipation layer 110 may be a single-layer or multi-layer structure. As an example, Figure 2A As shown, the first heat dissipation layer 110 is a single-layer structure, such as an h-BN material film layer.
[0038] Reference Figure 1 , Figure 2B and Figure 2C According to an embodiment of the present invention, in step S2, a dummy hole 10 is formed in the substrate 100, and a second heat dissipation layer 120 is filled in the dummy hole 10, and the second heat dissipation layer 120 includes h-BN. The second heat dissipation layer 120 may also include materials other than h-BN, or the second heat dissipation layer 120 only includes h-BN.
[0039] In some embodiments, Figure 2A As shown, firstly, a first heat dissipation layer 110 is formed on the surface of the substrate 100 by step S1, and then Figure 2B and Figure 2C As shown, step S2 is performed to form at least one dummy via 10 in the substrate 100 and fill the second heat dissipation layer 120. However, the present invention is not limited thereto. In other embodiments, step S2 may be performed first to form the dummy via 10 in the substrate 100 and fill the second heat dissipation layer 120, and then step S1 may be performed to form the above-mentioned first heat dissipation layer 110 on the substrate 100.
[0040] As an example, step S2 includes the following process:
[0041] First, refer to Figure 2BA mask layer (such as a photoresist layer, not shown) for defining the position of the dummy hole 10 is first formed on the substrate 100, and then the first heat dissipation layer 110 and the substrate 100 are etched to form a dummy hole 10 extending from the surface of the substrate 100 to the inside of the substrate 110, such as Figure 2B As shown, after forming the dummy hole 10, a heat dissipation film 101 may be formed on the inner wall of the dummy hole 10, and the heat dissipation film 101 may include h-BN or other materials with good thermal conductivity;
[0042] Afterwards, refer to Figure 2C , deposit the heat dissipation material to cover the heat dissipation film 101 and the first heat dissipation layer 110 outside the dummy hole 10, and the dummy hole is gradually filled with the heat dissipation material. After that, a planarization process (such as CMP) is performed to make the heat dissipation material on the substrate 100 flat. For example, the heat dissipation material located above the first heat dissipation layer 110 can be removed through the planarization process, and the heat dissipation film 101 in the dummy hole 10 and the heat dissipation material 102 form a second heat dissipation layer 120.
[0043] In this embodiment, the dummy hole 10 is not used for circuit connection, but for heat dissipation, relative to the conductive column (TSV, Through Silicon Via) used for circuit connection in the substrate 100, so the number and position of the dummy hole 10 can be arranged according to the heat dissipation needs. In other embodiments, the dummy hole 10 can be connected to the circuit in the substrate 100 as needed. The second heat dissipation layer 120 filled in the dummy hole 10 can be made of various heat dissipation materials. In this embodiment, h-BN can be filled in the dummy hole 10 because of its excellent thermal conductivity. The second heat dissipation layer 120 includes h-BN, for example, the second heat dissipation layer 120 is, for example, a h-BN material film layer.
[0044] As required, the conductive pillar (TSV) may be formed before or after forming the first heat dissipation layer 110, or before or after forming the second heat dissipation layer 120. As an example, after forming the second heat dissipation layer 120 in the dummy hole 10, the conductive pillar is formed, for example, including the following process:
[0045] First, if Figure 2D As shown, a mask layer 200 for defining the position of the conductive pillar is formed on the substrate 100, and the mask layer 200 is, for example, a photoresist layer;
[0046] Afterwards, if Figure 2EAs shown, a dry or wet etching process is performed to etch the first heat dissipation layer 110 and the substrate 100 corresponding to the opening in the mask 200 to form an opening 20 penetrating the first heat dissipation layer 110 and a portion of the substrate 100, and then the mask layer 200 is removed. Further, an isolation layer 130 may be formed on the inner wall of the substrate 100 exposed in the opening 20 to isolate the metal material to be filled in the opening 20 from the substrate 100. Optionally, in order to enhance the heat dissipation in the area of the opening 20, the isolation layer 130 may be formed using a material with good heat dissipation. As an example, the isolation layer 130 includes h-BN, and the isolation layer 130 may also include a material other than h-BN, or the isolation layer 130 only includes h-BN.
[0047] Then, if Figure 2F As shown, a metal layer 140 (such as copper) can be grown in the opening 20 and on the substrate 100 of the opening 20 by using other suitable processes such as electroplating, so that the upper surface of the metal layer 140 is higher than the first heat dissipation layer 110;
[0048] Afterwards, if Figure 2G As shown, a CMP process is performed to expose the upper surface of the first heat dissipation layer 110, and then a thermal annealing is performed to eliminate defects and improve the compactness of the metal layer 140. After the thermal annealing, the top of the metal layer 140 in the opening 20 protrudes from the upper surface of the first heat dissipation layer 110;
[0049] Then, if Figure 2H As shown, the CMP process is performed again to make the upper surface of the metal layer 140 flush with the upper surface of the first heat dissipation layer 110, and the metal layer 140 filled in the opening 20 forms a conductive column TSV.
[0050] The depths of the dummy holes 10 and the conductive pillars TSV in the substrate 100 can be set as needed. In some embodiments, the depth of the dummy holes 10 in the substrate 100 is greater than or equal to the depth of the conductive pillars TSV in the substrate 100, so that when the substrate 100 is subsequently thinned from the back side to expose the conductive pillars TSV, the second heat dissipation layer 120 in the dummy holes 10 can also be exposed from the back side of the substrate 100, so that heat can be dissipated from the back side of the substrate 100, and the second heat dissipation layer 120 can be connected to other heat dissipation structures on the back side of the substrate 100.
[0051] After forming the conductive pillar, a metal interconnect structure electrically connected to the conductive pillar TSV may be further formed on the substrate 100. The metal interconnect structure may include a plurality of metal interconnect layers on the substrate 100 and a conductive channel between adjacent metal interconnect layers. As an example, forming the metal interconnect structure may include the following process:
[0052] First, if Fig.2I As shown, an interlayer dielectric layer 150 is formed on the first heat dissipation layer 110;
[0053] Afterwards, if Figure 2J As shown, a groove 30 is formed that penetrates the interlayer dielectric layer 150 and exposes the conductive pillar TSV, and then electroplating or other suitable processes are used to deposit metal material, so that the metal material is deposited in the groove 30 and on the interlayer dielectric layer 150 outside the groove 30. Thereafter, a CMP process is performed to expose the upper surface of the interlayer dielectric layer 150, and the remaining metal material is filled in the groove 30 to form a first metal interconnection layer M1, which is embedded in the interlayer dielectric layer 150.
[0054] The first metal interconnection layer M1 is the metal interconnection layer closest to the substrate 100 in the metal interconnection structure. As required, other metal interconnection layers such as the second metal interconnection layer M2, the third metal interconnection layer M3, and the fourth metal interconnection layer M4 may be further formed on the first metal interconnection layer M1 to electrically connect adjacent metal interconnection layers.
[0055] The interlayer dielectric layer 150 may be a single layer or at least a two-layer structure. In this embodiment, in order to enhance heat dissipation, the interlayer dielectric layer 150 includes a third heat dissipation layer, and the third heat dissipation layer uses a heat dissipation material, such as h-BN. As an example, the interlayer dielectric layer 150 is a h-BN material film layer. In one embodiment, the interlayer dielectric layer where the first metal interconnection layer M1 is located is the first interlayer dielectric layer, the interlayer dielectric layer where the second metal interconnection layer M2 is located is the second interlayer dielectric layer, the interlayer dielectric layer where the third metal interconnection layer M3 is located is the third interlayer dielectric layer, and the interlayer dielectric layer where the fourth metal interconnection layer M4 is located is the fourth interlayer dielectric layer, and so on. The interlayer dielectric layer closest to the substrate 100, that is, the first interlayer dielectric layer includes h-BN, and may also include materials other than h-BN, or only include h-BN, and other interlayer dielectric layers other than the interlayer dielectric layer closest to the substrate 100 may include h-BN and at least one of dielectric materials other than h-BN (such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc.), or only include h-BN, or include dielectric materials other than h-BN.
[0056] Using the method for forming a semiconductor device described in the above embodiment, a first heat dissipation layer 110 is formed on a substrate 100 and a second heat dissipation layer 120 is formed in a dummy hole 10 in the substrate 100. The first heat dissipation layer 110 and the second heat dissipation layer 120 both include h-BN (hexagonal boron nitride). The thermal conductivity of h-BN is high, so that the first heat dissipation layer 110 and the second heat dissipation layer 120 have excellent heat dissipation performance, which helps to dissipate the heat generated during the operation of the semiconductor device in a timely manner and improve the performance of the semiconductor device.
[0057] The embodiment of the present invention includes a semiconductor device, and the semiconductor device can be manufactured using the method for forming the semiconductor device described in the above embodiment. Figure 2J In an embodiment of the present invention, the semiconductor device includes a substrate 100 and a first heat dissipation layer 110 formed on the substrate 100 (such as the front side of the substrate 100), a dummy hole 10 is formed in the substrate, and the dummy hole 10 is filled with a second heat dissipation layer 120, and the first heat dissipation layer 110 and the second heat dissipation layer 120 include h-BN.
[0058] like Figure 2J As shown, in some embodiments, the semiconductor device further includes a conductive pillar TSV, an interlayer dielectric layer 150, and a first metal interconnection layer M1; wherein the conductive pillar TSV penetrates the first heat dissipation layer 110 and at least a portion of the substrate 100, the interlayer dielectric layer 150 is formed on the first heat dissipation layer 110, and the first metal interconnection layer M1 is embedded in the interlayer dielectric layer 150 and electrically connected to the conductive pillar TSV. Optionally, in order to enhance heat dissipation, the interlayer dielectric layer 150 includes a third heat dissipation layer, and the third heat dissipation layer includes h-BN.
[0059] In some embodiments, the conductive pillar TSV and the dummy hole 10 both penetrate the substrate 100. The conductive pillar TSV can be connected to other electrical components from the side of the substrate 100 away from the first metal interconnection layer M1 (such as the back side of the substrate 100). The dummy hole 10 can be connected to other heat dissipation structures from the side of the substrate 100 away from the first metal interconnection layer M1.
[0060] In some embodiments, the semiconductor device is an interposer, and at least one chip may be bonded to the surface of the interposer. The interposer includes the substrate 100, and the first heat dissipation layer 110 may be formed on at least one side of the substrate 100 to facilitate heat dissipation. Optionally, at least one chip is bonded to the side of the interposer where the first heat dissipation layer 110 is formed. By bonding at least one chip to the interposer, the at least one chip may be interconnected through the circuit in the interposer to form a system-level chip. By forming the first heat dissipation layer and forming the second heat dissipation layer 120 in the substrate, the heat generated by the at least one chip during operation can be dissipated in a timely manner to avoid affecting the chip performance.
[0061] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The relevant parts can be understood by reference.
[0062] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: include: forming a first heat dissipation layer on the substrate, wherein the first heat dissipation layer comprises h-BN; as well as A dummy hole is formed in the substrate, and a second heat dissipation layer is filled in the dummy hole, wherein the second heat dissipation layer includes h-BN.
2. The forming method according to claim 1, characterized in that: After forming the second heat dissipation layer, the method further includes: forming a conductive column penetrating the first heat dissipation layer and a portion of the substrate; and A metal interconnection structure electrically connected to the conductive pillar is formed on the conductive pillar.
3. The forming method according to claim 2, characterized in that: Forming the conductive pillar comprises: forming an opening penetrating the first heat dissipation layer and a portion of the substrate; forming an isolation layer on the inner wall of the substrate exposed by the opening; and A metal layer is filled in the opening.
4. The forming method according to claim 3, characterized in that: A planarization process is performed to make the metal layer flush with the upper surface of the first heat dissipation layer.
5. The forming method according to claim 3, characterized in that: The isolation layer includes h-BN.
6. The forming method according to claim 2, characterized in that: Forming the metal interconnect structure includes: forming an interlayer dielectric layer on the first heat dissipation layer, and forming a groove penetrating the interlayer dielectric layer and exposing the conductive pillar; and A metal material is filled in the trench to form a first metal interconnection layer embedded in the interlayer dielectric layer.
7. The forming method according to claim 6, characterized in that: The interlayer dielectric layer includes a third heat dissipation layer, and the third heat dissipation layer includes h-BN.
8. A semiconductor device, characterized in that: The semiconductor device includes a substrate and a first heat dissipation layer formed on the substrate. A dummy hole is formed in the substrate. The dummy hole is filled with a second heat dissipation layer. The first heat dissipation layer and the second heat dissipation layer include h-BN.
9. The semiconductor device according to claim 8, wherein: Also includes: A conductive column penetrating the first heat dissipation layer and at least a portion of the substrate; an interlayer dielectric layer, formed on the first heat dissipation layer; as well as A first metal interconnection layer is embedded in the interlayer dielectric layer and electrically connected to the conductive pillars, wherein the interlayer dielectric layer includes a third heat dissipation layer, and the third heat dissipation layer includes h-BN.
10. The semiconductor device according to claim 9, wherein: The conductive column and the dummy hole both penetrate the substrate.
11. The semiconductor device according to claim 8, wherein The semiconductor device is an interposer substrate, and at least one chip is bonded to the interposer substrate on a side where the first heat dissipation layer is formed.